LTC1878EMS8

LTC1878 High Efficiency Monolithic Synchronous Step-Down Regulator U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC ®1878 is a high efficiency monolithic synchronous buck regulator using a constant frequency, current mode architecture. Supply current during operation is only 10µA and drops to < 1µA in shutdown. The 2.65V to 6V input voltage range makes the LTC1878 ideally suited for single Li-Ion battery-powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. High Efficiency: Up to 95% Very Low Quiescent Current: Only 10µA During Operation 600mA Output Current at VIN = 3.3V 2.65V to 6V Input Voltage Range 550kHz Constant Frequency Operation Synchronizable from 400kHz to 700kHz Selectable Burst ModeTM Operation or Pulse Skipping Mode No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle 0.8V Reference Allows Low Output Voltages Shutdown Mode Draws < 1µA Supply Current ±2% Output Voltage Accuracy Current Mode Control for Excellent Line and Load Transient Response Overcurrent and Overtemperature Protected Available in 8-Lead MSOP Package Switching frequency is internally set at 550kHz, allowing the use of small surface mount inductors and capacitors. For noise sensitive applications the LTC1878 can be externally synchronized from 400kHz to 700kHz. Burst Mode operation is inhibited during synchronization or when the SYNC/MODE pin is pulled low, preventing low frequency ripple from interfering with audio circuitry. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. Low output voltages are easily supported with the 0.8V feedback reference voltage. The LTC1878 is available in a space saving 8-lead MSOP package. U APPLICATIO S ■ ■ ■ ■ ■ ■ Cellular Telephones Wireless Modems Personal Information Appliances Portable Instruments Distributed Power Systems Battery-Powered Equipment For higher input voltage (11V abs max) applications, refer to the LTC1877 data sheet. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a trademark of Linear Technology Corporation. U Efficiency vs Output Load Current TYPICAL APPLICATIO 100 95 VIN 2.65V TO 6V 22µF** CER 7 6 1 2 220pF SW SYNC VIN 5 + LTC1878 GND VFB VOUT† 3.3V 20pF 47µF*** RUN ITH 10µH* 3 4 887k 280k EFFICIENCY (%) High Efficiency Step-Down Converter 90 VIN = 4.2V 85 VIN = 6V 80 75 1878 TA01 *TOKO D62CB A920CY-100M **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***SANYO POSCAP 6TPA47M † VOUT CONNECTED TO VIN FOR 2.65V < VIN < 3.3V VIN = 3.6V 70 0.1 Burst Mode OPERATION VOUT = 3.3V L = 10µH 1 10 100 OUTPUT CURRENT (mA) 1000 1878 TA02 1 LTC1878 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage (VIN)...........................– 0.3V to 7V ITH, PLL LPF Voltage ................................– 0.3V to 2.7V RUN, VFB Voltages ...................................... – 0.3V to VIN SYNC/MODE Voltage .................................. – 0.3V to VIN SW Voltage ................................... – 0.3V to (VIN + 0.3V) P-Channel MOSFET Source Current (DC) ........... 800mA N-Channel MOSFET Sink Current (DC) ............... 800mA Peak SW Sink and Source Current ........................ 1.5A Operating Ambient Temperature Range (Note 2) .................................................. – 40°C to 85°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW RUN ITH VFB GND 1 2 3 4 8 7 6 5 PLL LPF SYNC/MODE VIN SW MS8 PACKAGE 8-LEAD PLASTIC MSOP LTC1878EMS8 MS8 PART MARKING TJMAX = 125°C, θJA = 150°C/ W LTNX Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. V IN = 3.6V unless otherwise specified. SYMBOL PARAMETER CONDITIONS IVFB Feedback Current (Note 4) ● VFB Regulated Output Voltage (Note 4) 0°C ≤ TA ≤ 85°C (Note 4) – 40°C ≤ TA ≤ 85°C ● 0.784 0.74 ● 20 ∆VOVL Output Overvoltage Lockout ∆VOVL = VOVL – VFB ∆VFB Reference Voltage Line Regulation VIN = 2.65V to 6V (Note 4) VLOADREG Output Voltage Load Regulation Measured in Servo Loop; VITH = 0.9V to 1.2V Measured in Servo Loop; VITH = 1.6V to 1.2V VIN Input Voltage Range IQ Input DC Bias Current Pulse Skipping Mode Burst Mode Operation Shutdown (Note 5) 2.65V < VIN < 6V, VSYNC/MODE = 0V, IOUT = 0A VSYNC/MODE = VIN, IOUT = 0A VRUN = 0V, VIN = 6V fOSC Oscillator Frequency VFB = 0.8V VFB = 0V fSYNC SYNC Capture Range IPLL LPF Phase Detector Output Current Sinking Capability Sourcing Capability fPLLIN < fOSC fPLLIN > fOSC RPFET RDS(ON) of P-Channel MOSFET RNFET RDS(ON) of N-Channel MOSFET 2 MIN TYP MAX 4 30 UNITS nA 0.8 0.8 0.816 0.84 V V 50 110 mV 0.05 0.2 %/V 0.1 – 0.1 0.5 – 0.5 % % 6 V 230 10 0 350 15 1 µA µA µA 550 80 605 kHz kHz 700 kHz 10 –10 20 –20 µA µA ISW = 100mA 0.5 0.7 Ω ISW = –100mA 0.6 0.8 Ω ● ● ● 2.65 495 400 ● ● 3 –3 LTC1878 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. V IN = 3.6V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IPK Peak Inductor Current VIN = 3.3V, VFB = 0.7V, Duty Cycle < 35% 0.8 1.0 1.25 A ILSW SW Leakage ±0.01 ±1 µA 1.0 1.5 V ±0.01 ±1 µA 0.7 1.5 V ±0.01 ±1 µA VRUN = 0V, VSW = 0V or 6V, VIN = 6V VSYNC/MODE SYNC/MODE Threshold VSYNC/MODE Rising ISYNC/MODE SYNC/MODE Leakage Current VRUN RUN Threshold IRUN RUN Input Current 0.3 ● VRUN Rising 0.3 ● Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC1878E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC1878EMS8: TJ = TA + (PD)(150°C/W) Note 4: The LTC1878 is tested in a feedback loop which servos VFB to the balance point for the error amplifier (VITH = 1.2V). Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Input Voltage Efficiency vs Output Current ILOAD = 100mA 90 ILOAD = 10mA 80 85 90 VIN = 4.2V ILOAD = 300mA ILOAD = 1mA 80 ILOAD = 0.1mA 75 60 50 40 VIN = 3.6V VIN = 4.2V 30 70 Burst Mode OPERATION 65 VOUT = 2.5V L = 10µH 60 3 4 6 2 5 INPUT VOLTAGE (V) 20 10 7 8 1878 G01 0 0.1 L = 15µH 85 70 EFFICIENCY (%) EFFICIENCY (%) 90 VIN = 3.6V EFFICIENCY (%) 95 Efficiency vs Output Current 95 100 100 PULSE SKIPPING MODE Burst Mode OPERATION VOUT = 1.8V L = 10µH 1 10 100 OUTPUT CURRENT (mA) 1000 1878 G02 L = 10µH 80 75 70 65 60 55 Burst Mode OPERATION VIN = 6V VOUT = 2.5V 50 0.1 1 10 100 OUTPUT CURRENT (mA) 1000 1878 G03 3 LTC1878 U W TYPICAL PERFOR A CE CHARACTERISTICS Reference Voltage vs Temperature Efficiency vs Output Current 95 0.814 VIN = 3V VIN = 3.6V VIN = 4.2V 80 VIN = 6V 75 585 0.804 0.799 0.794 10 100 1 OUTPUT CURRENT (mA) 1000 50 25 75 0 TEMPERATURE (°C) 100 –25 25 50 75 0 TEMPERATURE (°C) Output Voltage vs Load Current RDS(ON) vs Input Voltage 0.8 SYNCHRONOUS SWITCH 0.7 565 555 545 535 525 515 4 6 1.80 1.79 8 SUPPLY VOLTAGE (V) 250 0.9 VIN = 3V 0.8 0.7 VIN = 5V 0.6 0.5 100 125 1878 G10 1 2 3 5 6 4 INPUT VOLTAGE (V) PULSE SKIPPING MODE 200 100 50 1 4 3 2 5 INPUT VOLTAGE (V) 8 VIN = 3.6V 250 150 0 7 1878 G09 300 PULSE SKIPPING MODE 200 150 100 50 0 0 25 50 75 TEMPERATURE (°C) 0 DC Supply Current vs Temperature Burst Mode OPERATION –25 0 VOUT = 1.8V 0.4 0.3 –50 0.2 0.1 SUPPLY CURRENT (µA) DC SUPPLY CURRENT (µA) SYNCHRONOUS SWITCH MAIN SWITCH 1.0 MAIN SWITCH 0.4 DC Supply Current vs Input Voltage RDS(ON) vs Temperature 1.1 0.5 1878 G08 1878 G07 1.2 0.6 0.3 1.78 PULSE SKIPPING MODE VIN = 3.6V L = 10µH 1.77 0 100 200 300 400 500 600 700 800 900 LOAD CURRENT (mA) 505 2 1.81 RDS(ON) (Ω) OUTPUT VOLTAGE (V) 575 125 0.9 1.82 585 0 100 1878 G06 595 OSCILLATOR FREQUENCY (kHz) 535 495 –50 125 1.83 605 RDS(ON) (Ω) 545 1878 G05 Oscillator Frequency vs Supply Voltage 4 555 505 0.784 –50 –25 1878 G04 495 565 515 VOUT = 1.8V L = 10µH 65 0.1 575 525 0.789 70 VIN = 3.6V 595 FREQUENCY (kHz) 85 605 VIN = 3.6V 0.809 REFERENCE VOLTAGE (V) EFFICIENCY (%) 90 Oscillator Frequency vs Temperature 6 7 1878 G11 0 –50 Burst Mode OPERATION –25 50 25 75 0 TEMPERATURE (°C) 100 125 1878 G12 LTC1878 U W TYPICAL PERFOR A CE CHARACTERISTICS Switch Leakage vs Temperature 2.5 Switch Leakage vs Input Voltage 1.2 VIN = 7V RUN = 0V RUN = 0V SW 5V/DIV 1.0 SWITCH LEAKAGE (nA) 2.0 SWITCH LEAKAGE (µA) Burst Mode Operation 1.5 MAIN SWITCH 1.0 SYNCHRONOUS SWITCH 0.5 0 – 50 – 25 SYNCHRONOUS SWITCH 0.8 VOUT 50mV/DIV AC COUPLED 0.6 0.4 MAIN SWITCH 0.2 0 75 50 25 TEMPERATURE (°C) 0 100 125 0 1 2 IL 200mA/DIV 5 6 3 4 INPUT VOLTAGE (V) 7 8 1878 G20 1878 G13 Pulse Skipping Mode Operation Start-Up from Shutdown VOUT 50mV/DIV AC COUPLED VOUT 1V/DIV VOUT 20mV/DIV AC COUPLED 1878 G14 Load Step Response RUN 2V/DIV SW 5V/DIV 10µs/DIV VIN = 4.2V CIN = 22µF VOUT = 1.5V COUT = 47µF L = 10µH ILOAD = 50mA IL 500mA/DIV IL 500mA/DIV IL 200mA/DIV ITH 1V/DIV 1µs/DIV VIN = 4.2V CIN = 22µF VOUT = 1.5V COUT = 47µF L = 10µH ILOAD = 50mA 1878 G15 40µs/DIV CIN = 22µF VIN = 3.6V VOUT = 1.5V COUT = 47µF L = 10µH ILOAD = 500mA 1878 G16 Load Step Response 40µs/DIV VIN = 3.6V CIN = 22µF VOUT = 1.5V COUT = 47µF L = 10µH ILOAD = 200mA TO 500mA PULSE SKIPPING MODE 1878 G17 Load Step Response VOUT 100mV/DIV AC COUPLED VOUT 100mV/DIV AC COUPLED IL 500mA/DIV IL 500mA/DIV ITH 1V/DIV ITH 1V/DIV 40µs/DIV VIN = 3.6V CIN = 22µF VOUT = 1.5V COUT = 47µF L = 10µH ILOAD = 50mA TO 500mA PULSE SKIPPING MODE 1878 G18 40µs/DIV VIN = 3.6V CIN = 22µF VOUT = 1.5V COUT = 47µF L = 10µH ILOAD = 50mA TO 500mA Burst Mode OPERATION 1878 G19 5 LTC1878 U U U PI FU CTIO S RUN (Pin 1): Run Control Input. Forcing this pin below 0.4V shuts down the LTC1878. In shutdown all functions are disabled drawing < 1µA supply current. Forcing this pin above 1.2V enables the LTC1878. Do not leave RUN floating. ITH (Pin 2): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is from 0.5V to 1.9V. VFB (Pin 3): Feedback Pin. Receives the feedback voltage from an external resistive divider across the output. GND (Pin 4): Ground Pin. SW (Pin 5): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. VIN (Pin 6): Main Supply Pin. Must be closely decoupled to GND, Pin 4. SYNC/MODE (Pin 7): External Clock Synchronization and Mode Select Input. To synchronize with an external clock, apply a clock with a frequency between 400kHz and 700kHz. To select Burst Mode operation, tie to VIN. Grounding this pin selects pulse skipping mode. Do not leave this pin floating. PLL LPF (Pin 8): Output of the Phase Detector and Control Input of Oscillator. Connect a series RC lowpass network from this pin to ground if externally synchronized. If unused, this pin may be left open. W FU CTIO AL DIAGRA U U VIN BURST DEFEAT PLL LPF Y Y = “0” ONLY WHEN X IS A CONSTANT “1” X 8 SLOPE COMP SYNC/MODE 7 0.8V VCO OSC 0.6V 3 VFB – 6 VIN FREQ SHIFT + – + 0.55V – EA gm = 0.5m Ω 0.8V REF EN SLEEP – + VIN S Q R Q RS LATCH 6Ω + ICOMP BURST VIN SLEEP 2 ITH VIN RUN 1 – + VREF 0.8V SWITCHING LOGIC AND BLANKING CIRCUIT ANTISHOOTTHRU 5 SW – OVDET SHUTDOWN + + 0.85V IRCMP 4 GND – 1878 BD 6 LTC1878 U OPERATIO Main Control Loop The LTC1878 uses a constant frequency, current mode step-down architecture. Both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches are internal. During normal operation, the internal top power MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of error amplifier EA. The VFB pin, described in the Pin Functions section, allows EA to receive an output feedback voltage from an external resistive divider. When the load current increases, it causes a slight decrease in the feedback voltage relative to the 0.8V reference, which in turn, causes the ITH voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse as indicated by the current reversal comparator IRCMP, or the beginning of the next clock cycle. Comparator OVDET guards against transient overshoots >6.25% by turning the main switch off and keeping it off until the fault is removed. Burst Mode Operation The LTC1878 is capable of Burst Mode operation in which the internal power MOSFETs operate intermittently based on load demand. To enable Burst Mode operation, simply tie the SYNC/MODE pin to VIN or connect it to a logic high (VSYNC/MODE > 1.5V). To disable Burst Mode operation and enable PWM pulse skipping mode, connect the SYNC/ MODE pin to GND. In this mode, the efficiency is lower at light loads, but becomes comparable to Burst Mode operation when the output load exceeds 50mA. The advantage of pulse skipping mode is lower output ripple and less interference to audio circuitry. When the converter is in Burst Mode operation, the peak current of the inductor is set to approximately 250mA, even though the voltage at the ITH pin indicates a lower value. The voltage at the ITH pin drops when the inductor’s average current is greater than the load requirement. As the ITH voltage drops below approximately 0.55V, the BURST comparator trips, causing the internal sleep line to go high and forces off both power MOSFETs. The ITH pin is then disconnected from the output of the EA amplifier and parked a diode voltage above ground. In sleep mode, both power MOSFETs are held off and a majority of the internal circuitry is partially turned off, reducing the quiescent current to 10µA. The load current is now being supplied solely from the output capacitor. When the output voltage drops, the ITH pin reconnects to the output of the EA amplifier and the top MOSFET is again turned on and this process repeats. Short-Circuit Protection When the output is shorted to ground, the frequency of the oscillator is reduced to about 80kHz, 1/7 the nominal frequency. This frequency foldback ensures that the inductor current has ample time to decay, thereby preventing runaway. The oscillator’s frequency will progressively increase to 550kHz (or the synchronized frequency) when VFB rises above 0.3V. Frequency Synchronization A phase-locked loop (PLL) is available on the LTC1878 to allow the internal oscillator to be synchronized to an external source connected to the SYNC/MODE pin. The output of the phase detector at the PLL LPF pin operates over a 0V to 2.4V range corresponding to 400kHz to 700kHz. When locked, the PLL aligns the turn-on of the top MOSFET to the rising edge of the synchronizing signal. When the LTC1878 is clocked by an external source, Burst Mode operation is disabled; the LTC1878 then operates in PWM pulse skipping mode. In this mode, when the output load is very low, current comparator ICOMP may remain tripped for several cycles and force the main switch to stay off for the same number of cycles. Increasing the output load slightly allows constant frequency PWM operation to resume. This mode exhibits low output ripple as well as low audio noise and reduced RF interference while providing reasonable low current efficiency. Frequency synchronization is inhibited when the feedback voltage VFB is below 0.6V. This prevents the external clock from interfering with the frequency foldback for shortcircuit protection. 7 LTC1878 U OPERATIO Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-channel MOSFET and the inductor. Low Supply Operation The LTC1878 is designed to operate down to an input supply voltage of 2.65V although the maximum allowable output current is reduced at this low voltage. Figure 1 shows the reduction in the maximum output current as a function of input voltage for various output voltages. L = 10µH MAX OUTPUT CURRENT (mA) 1000 VOUT = 1.5V 800 VOUT = 3.3V 600 VOUT = 2.5V 400 200 0 2.5 3.5 Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. As a result, the maximum inductor peak current is reduced for duty cycles > 40%. This is shown in the decrease of the inductor peak current as a function of duty cycle graph in Figure 2. MAXIMUM INDUCTOR PEAK CURRENT (mA) 1200 Another important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases. Therefore, the user should calculate the power dissipation when the LTC1878 is used at 100% duty cycle with a low input voltage (see Thermal Considerations in the Applications Information section). 4.5 5.5 6.5 INPUT VOLTAGE (V) 1100 VIN = 3.3V 1000 900 800 700 600 7.5 0 1878 F01 20 60 40 DUTY CYCLE (%) 80 100 1878 F02 Figure 1. Maximum Output Current vs Input Voltage Figure 2. Maximum Inductor Peak Current vs Duty Cycle U W U U APPLICATIO S I FOR ATIO The basic LTC1878 application circuit is shown on the first page. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Value Calculation The inductor selection will depend on the operating frequency of the LTC1878. The internal nominal frequency is 550kHz, but can be externally synchronized from 400kHz to 700kHz. 8 The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. However, operating at a higher frequency generally results in lower efficiency because of increased internal gate charge losses. The inductor value has a direct effect on ripple current. The ripple current ∆IL decreases with higher inductance or frequency and increases with higher VIN or VOUT. LTC1878 U W U U APPLICATIO S I FOR ATIO ∆IL =  V  1 VOUT  1 − OUT  ( f)(L)  VIN  (1) Accepting larger values of ∆IL allows the use of low inductance, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆IL = 0.4(IMAX). The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 250mA. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Kool Mµ (from Magnetics, Inc.) is a very good, low loss core material for toroids with a “soft” saturation characteristic. Molypermalloy is slightly more efficient at high (>200kHz) switching frequencies but quite a bit more expensive. Toroids are very space efficient, especially when you can use several layers of wire, while inductors wound on bobbins are generally easier to surface mount. New designs for surface mount inductors are available from Coiltronics, Coilcraft, Dale and Sumida. CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: CIN required IRMS ≅ IOMAX [VOUT (VIN − VOUT )]1/ 2 VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple ∆VOUT is determined by:  1  ∆VOUT ≅ ∆IL  ESR +  8 fCOUT   where f = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. For the LTC1878, the general rule for proper operation is: COUT required ESR < 0.25Ω The choice of using a smaller output capacitance increases the output ripple voltage due to the frequency dependent term but can be compensated for by using capacitor(s) of very low ESR to maintain low ripple voltage. The ITH pin compensation components can be Kool Mµ is a registered trademark of Magnetics, Inc. 9 LTC1878 U W U U APPLICATIO S I FOR ATIO ESR is a direct function of the volume of the capacitor. Manufacturers such as Taiyo-Yuden, AVX, Kemet, Sprague and Sanyo should be considered for high performance capacitors. The POSCAP solid electrolytic chip capacitor available from Sanyo is an excellent choice for output bulk capacitors due to its low ESR/size ratio. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. When using tantalum capacitors, it is critical that they are surge tested for use in switching power supplies. A good choice is the AVX TPS series of surface mount tantalum, available in case heights ranging from 2mm to 4mm. Other capacitor types include KEMET T510 and T495 series and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Output Voltage Programming external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range ∆fH is equal to the capture range, ∆fH = ∆fC = ±150kHz. The output of the phase detector is a pair of complementary current sources charging or discharging the external filter network on the PLL LPF pin. The relationship between the voltage on the PLL LPF pin and operating frequency is shown in Figure 4. A simplified block diagram is shown in Figure 5. 800 OSCILLATOR FREQUENCY (kHz) optimized to provide stable high performance transient response regardless of the output capacitor selected. 700 600 500 400 The output voltage is set by a resistive divider according to the following formula:  R2  VOUT = 0.8V  1 +   R1 300 0 0.8 1.2 VPLL LPF (V) 0.4 2.0 1878 F04 (2) Figure 4. Relationship Between Oscillator Frequency and Voltage at PLL LPF Pin The external resistive divider is connected to the output, allowing remote voltage sensing as shown in Figure 3. RLP PHASE DETECTOR 0.8V ≤ VOUT ≤ 6V 2.4V CLP PLL LPF R2 SYNC/ MODE VFB LTC1878 1.6 R1 GND DIGITAL PHASE/ FREQUENCY DETECTOR VCO 1878 F03 Figure 3. Setting the LTC1878 Output Voltage Phase-Locked Loop and Frequency Synchronization The LTC1878 has an internal voltage-controlled oscillator and phase detector comprising a phase-locked loop. This allows the top MOSFET turn-on to be locked to the rising edge of an external frequency source. The frequency range of the voltage-controlled oscillator is 400kHz to 700kHz. The phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the 10 1878 F05 Figure 5. Phase-Locked Loop Block Diagram If the external frequency (VSYNC/MODE) is greater than 550kHz, the center frequency, current is sourced continuously, pulling up the PLL LPF pin. When the external frequency is less than 550kHz, current is sunk continuously, pulling down the PLL LPF pin. If the LTC1878 U W U U APPLICATIO S I FOR ATIO The loop filter components CLP and RLP smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter component’s CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01µF. When not synchronized to an external clock, the internal connection to the VCO is disconnected. This disallows setting the internal oscillator frequency by a DC voltage on the VPLL LPF pin. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC1878 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 6. 1. The VIN quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the 1 0.1 POWER LOST (W) external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLL LPF pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is high impedance and the filter capacitor CLP holds the voltage. 0.01 VIN = 4.2V L = 10µH VOUT = 1.5V VOUT = 2.5V VOUT = 3.3V Burst Mode OPERATION 0.001 0.0001 0.00001 0.1 1 10 100 LOAD CURRENT (mA) 1000 1878 F06 Figure 6. Power Lost vs Load Current internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Charateristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss. 11 LTC1878 U W U U APPLICATIO S I FOR ATIO Thermal Considerations P-channel switch at 70°C is approximately 0.7Ω. Therefore, power dissipated by the part is: In most applications the LTC1878 does not dissipate much heat due to its high efficiency. But, in applications where the LTC1878 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. PD = ILOAD2 • RDS(ON) = 0.175W For the MSOP package, the θJA is 150°C/ W. Thus, the junction temperature of the regulator is: TJ = 70°C + (0.175)(150) = 96°C which is below the maximum junction temperature of 125°C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). To avoid the LTC1878 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD • ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steadystate value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The internal compensation provides adequate compensation for most applications. But if additional compensation is required, the ITH pin can be used for external compensation using RC, CC1 as shown in Figure 7. (The 220pF capacitor, CC2, is typically needed for noise decoupling.) TR = (PD)(θJA) where PD is the power dissipated by the regulator and qJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: T J = TA + TR where TA is the ambient temperature. As an example, consider the LTC1878 in dropout at an input voltage of 3V, a load current of 500mA, and an ambient temperature of 70°C. From the typical performance graph of switch resistance, the RDS(ON) of the CC2 LTC1878 OPTIONAL RC 1 CC1 2 3 4 R1 R2 RUN ITH PLL LPF SYNC/MODE VFB GND VIN SW 8 7 BOLD LINES INDICATE HIGH CURRENT PATHS 6 5 + L1 + + CIN + COUT VOUT VIN – – 1878 F07 Figure 7. LTC1878 Layout Diagram 12 LTC1878 U W U U APPLICATIO S I FOR ATIO A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a 250µs rise time, limiting the charging current to about 130mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1878. These items are also illustrated graphically in the layout diagram of Figure 7. Check the following in your layout: 1. Are the signal and power grounds segregated? The LTC1878 signal ground consists of the resistive divider, the optional compensation network (RC and CC1) and CC2. The power ground consists of the (–) plate of CIN, the (–) plate of COUT and Pin 4 of the LTC1878. The power ground traces should be kept short, direct and wide. The signal ground and power ground should converge to a common node in a starground configuration. 2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1/R2 must be connected between the (+) plate of COUT and signal ground. 3. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 4. Keep the switching node SW away from sensitive small signal nodes. Design Example As a design example, assume the LTC1878 is used in a single lithium-ion battery-powered cellular phone application. The input voltage will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 0.3A but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 2.5V. With this information we can calculate L using equation (1), L=  V  1 VOUT  1 − OUT  ( f)(∆IL )  VIN  (3) Substituting VOUT = 2.5V, VIN = 4.2V, ∆IL=120mA and f = 550kHz in equation (3) gives: L=  2.5V  2.5V 1 −  = 15.3µH 550kHz(120mA)  4.2V  A 15µH inductor works well for this application. For best efficiency choose a 1A inductor with less than 0.25Ω series resistance. CIN will require an RMS current rating of at least 0.15A at temperature and COUT will require an ESR of less than 0.25Ω. In most applications, the requirements for these capacitors are fairly similar. For the feedback resistors, choose R1 = 412k. R2 can then be calculated from equation (2) to be: V  R2 =  OUT − 1 R1 = 875.5k ; use 887k  0.8  Figure 8 shows the complete circuit along with its efficiency curve. 13 LTC1878 U W U U APPLICATIO S I FOR ATIO 95 VIN = 3V VIN 2.65V TO 4.2V LTC1878 2 3 4 RUN PLL LPF ITH SYNC/MODE VFB VIN GND SW VIN = 3.6V 22µF** CER 8 EFFICIENCY (%) 220pF 1 90 7 6 15µH* 5 VOUT 2.5V + 80 VOUT = 2.5V L = 15µH 70 0.1 1 10 100 OUTPUT CURRENT (mA) 887k 1878 F08a 20pF VIN = 4.2V 75 47µF*** 412k 85 *SUMIDA CD54-150 **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***SANYO POSCAP 6TPA47M 1878 F08b Figure 8. Single Lithium-Ion to 2.5V/0.3A Regulator from Design Example U TYPICAL APPLICATIO S Single Li-Ion to 2.5V/0.6A Regulator Using All Ceramic Capacitors LTC1878 1 2 220pF 3 4 RUN PLL LPF ITH SYNC/MODE VFB VIN GND SW 8 7 6 5 10µH* 20pF *TOKO D62CB A920CY-100M **TAIYO-YUDEN CERAMIC JMK325BJ226MM 887k VOUT 2.5V COUT** 0.6A 22µF CER CIN** 22µF CER VIN 3V TO 4.2V 412k 1878 TA03 3- to 4-Cell NiCd/NiMH to 1.8V/0.5A Regulator Using All Ceramic Capacitors LTC1878 1 2 220pF 3 4 RUN PLL LPF ITH SYNC/MODE VFB VIN GND SW 8 7 6 5 10µH* 20pF *TOKO D62CB A920CY-100M **TAIYO-YUDEN CERAMIC JMK325BJ226MM 887k 698k 1878 TA04 14 1000 COUT** 22µF CER VOUT 1.8V 0.5A CIN** 22µF CER VIN 2.7V TO 6V LTC1878 U TYPICAL APPLICATIO S Externally Synchronized 2.5V/0.6A Regulator Using All Ceramic Capacitors LTC1878 1 RUN 2 220pF ITH 3 0.01µF PLL LPF SYNC/MODE VFB 4 VIN GND SW 10k 8 7 EXT CLOCK 700kHz 6 10µH* 5 20pF *TOKO D62CB A920CY-100M **TAIYO-YUDEN CERAMIC JMK325BJ226MM VOUT 2.5V COUT** 0.6A 22µF CER CIN** 22µF CER VOUT 2.5V COUT*** 0.3A 47µF 6.3V CIN** 22µF CER 887k VIN 3V TO 6V 412k 1878 TA04 Low Noise 2.5V/0.3A Regulator LTC1878 1 2 220pF 3 4 RUN PLL LPF ITH SYNC/MODE VFB VIN GND SW 8 7 6 5 15µH* + 20pF 887k VIN 2.65V TO 6V 412k *SUMIDA CD54-150 **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***SANYO POSCAP CTPA47M 1878 TA06 3- to 4-Cell NiCd/NiMH to 3.3V/0.5A Regulator Using All Ceramic Capacitors LTC1878 1 2 220pF 3 4 RUN PLL LPF ITH SYNC/MODE VFB VIN GND SW 8 7 6 5 10µH* 20pF *TOKO D62CB A920CY-100M **TAIYO-YUDEN CERAMIC JMK325BJ226MM † VOUT CONNECTED TO VIN FOR 2.7V < VIN < 3.3V 887k VOUT† 3.3V COUT** 0.5A 22µF CER CIN** 22µF CER VIN 2.7V TO 6V 280k 1878 TA06 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1878 U TYPICAL APPLICATIO Single Li-Ion to 2.5V/0.5A Regulator with Precision 2.7V Undervoltage Lockout 0.1µF LTC1540 1.58M 1% 1 2 3 4 1.18M 1% GND V– IN+ IN – OUT V+ REF HYS 10k 8 7 2 220pF 6 5 LTC1878 1 44.2k 1% 3 0.01µF 4 RUN PLL LPF ITH SYNC/MODE VFB VIN GND SW 8 7 6 5 10µH* 20pF 2.37M 1% 887k COUT** 22µF CER VOUT 2.5V 0.6A CIN** 22µF CER VIN 2.7V TO 4.2V 412k *TOKO D62CB A920CY-100M **TAIYO-YUDEN CERAMIC JMK325BJ226MM 1878 TA08 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.040 ± 0.006 (1.02 ± 0.15) 0.007 (0.18) 0.034 ± 0.004 (0.86 ± 0.102) 0.118 ± 0.004* (3.00 ± 0.102) 8 7 6 5 0° – 6° TYP 0.021 ± 0.006 (0.53 ± 0.015) SEATING PLANE 0.012 (0.30) 0.0256 REF (0.65) BSC 0.006 ± 0.004 (0.15 ± 0.102) 0.118 ± 0.004** (3.00 ± 0.102) 0.193 ± 0.006 (4.90 ± 0.15) MSOP (MS8) 1098 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE 1 2 3 4 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1174/LTC1174-3.3 LTC1174-5 High Efficiency Step-Down and Inverting DC/DC Converters Monolithic Switching Regulators, I OUT to 450mA, Burst Mode Operation LTC1265 1.2A, High Efficiency Step-Down DC/DC Converter Constant Off-Time, Monolithic, Burst Mode Operation LTC1474/LTC1475 Low Quiescent Current Step-Down DC/DC Converters Monolithic, IOUT to 250mA, IQ = 10µA, 8-Pin MSOP LTC1504A Monolithic Synchronous Step-Down Switching Regulator Low Cost, Voltage Mode IOUT to 500mA, VIN from 4V to 10V LTC1622 Low Input Voltage Current Mode Step-Down DC/DC Controller High Frequency, High Efficiency, 8-Pin MSOP LTC1626 Low Voltage, High Efficiency Step-Down DC/DC Converter Monolithic, Constant Off-Time, IOUT to 600mA, Low Supply Voltage Range: 2.5V to 6V LTC1627 Monolithic Synchronous Step-Down Switching Regulator Constant Frequency, IOUT to 500mA, Secondary Winding Regulation, VIN from 2.65V to 8.5V LTC1701 Monolithic Current Mode Step-Down Switching Regulator Constant Off-Time, IOUT to 500mA, 1MHz Operation, VIN from 2.5V to 5.5V LTC1707 Monolithic Synchronous Step-Down Switching Regulator 1.19V VREF Pin, Constant Frequency, I OUT to 600mA, VIN from 2.65V to 8.5V LTC1772 Low Input Voltage Current Mode Step-Down DC/DC Controller 550kHz, 6-Pin SOT-23, IOUT Up to 5A, VIN from 2.2V to 10V LTC1877 High Efficiency Monolithic Step-Down Regulator 550kHz, MS8, VIN Up to 10V, IQ = 10µA, IOUT to 600mA 16 Linear Technology Corporation 1878f LT/TP 1000 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com  LINEAR TECHNOLOGY CORPORATION 2000