LTC2182/LTC2181/LTC2180
16-Bit, 65Msps/
40Msps/25Msps Low Power
Dual ADCs
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
n
Two-Channel Simultaneously Sampling ADC
77dB SNR
90dB SFDR
Low Power: 160mW/115mW/78mW Total
80mW/58mW/39mW per Channel
Single 1.8V Supply
CMOS, DDR CMOS, or DDR LVDS Outputs
Selectable Input Ranges: 1VP-P to 2VP-P
550MHz Full Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
64-Pin (9mm × 9mm) QFN Package
The LTC®2182/LTC2181/LTC2180 are two-channel simultaneous sampling 16-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 77dB SNR and 90dB
spurious free dynamic range (SFDR). Ultralow jitter of
0.07psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.3LSBRMS.
The digital outputs can be either full rate CMOS, Double
Data Rate CMOS, or Double Data Rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
APPLICATIONS
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of
clock duty cycles.
Communications
n Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multi-Channel Data Acquisition
n Nondestructive Testing
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
VDD
2-Tone FFT, fIN = 70MHz and 69MHz
1.8V
OVDD
0
–10
CH 2
ANALOG
INPUT
–20
D1_15
•
•
•
D1_0
16-BIT
ADC CORE
S/H
16-BIT
ADC CORE
S/H
OUTPUT
DRIVERS
D2_15
•
•
•
D2_0
–30
CMOS,
DDR CMOS
OR DDR LVDS
OUTPUTS
AMPLITUDE (dBFS)
CH 1
ANALOG
INPUT
–40
–50
–60
–70
–80
–90
–100
–110
–120
65MHz
CLOCK
CLOCK
CONTROL
0
20
10
FREQUENCY (MHz)
30
218210 TA01b
218210 TA01a
GND
OGND
218210f
1
LTC2182/LTC2181/LTC2180
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages (VDD, OVDD)........................ –0.3V to 2V
Analog Input Voltage (AIN+, AIN –,
PAR/SER, SENSE) (Note 3)........... –0.3V to (VDD + 0.2V)
Digital Input Voltage (ENC+, ENC–, CS,
SDI, SCK) (Note 4)..................................... –0.3V to 3.9V
SDO (Note 4).............................................. –0.3V to 3.9V
Digital Output Voltage................. –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2182C, LTC2181C, LTC2180C.............. 0°C to 70°C
LTC2182I, LTC2181I, LTC2180I.............–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATIONS
FULL-RATE CMOS OUTPUT MODE
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
64 VDD
63 SENSE
62 VREF
61 SDO
60 OF1
59 OF2
58 D1_15
57 D1_14
56 D1_13
55 D1_12
54 D1_11
53 D1_10
52 D1_9
51 D1_8
50 D1_7
49 D1_6
64 VDD
63 SENSE
62 VREF
61 SDO
60 OF2_1
59 DNC
58 D1_14_15
57 DNC
56 D1_12_13
55 DNC
54 D1_10_11
53 DNC
52 D1_8_9
51 DNC
50 D1_6_7
49 DNC
TOP VIEW
VDD 1
VCM1 2
GND 3
AIN1+ 4
AIN1– 5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
AIN2+ 12
AIN2– 13
GND 14
VCM2 15
VDD 16
65
GND
48 D1_4_5
47 DNC
46 D1_2_3
45 DNC
44 D1_0_1
43 DNC
42 OVDD
41 OGND
40 CLKOUT+
39 CLKOUT–
38 D2_14_15
37 DNC
36 D2_12_13
35 DNC
34 D2_10_11
33 DNC
VDD 17
ENC+ 18
ENC– 19
CS 20
SCK 21
SDI 22
DNC 23
D2_0_1 24
DNC 25
D2_2_3 26
DNC 27
D2_4_5 28
DNC 29
D2_6_7 30
DNC 31
D2_8_9 32
65
GND
48 D1_5
47 D1_4
46 D1_3
45 D1_2
44 D1_1
43 D1_0
42 OVDD
41 OGND
40 CLKOUT+
39 CLKOUT–
38 D2_15
37 D2_14
36 D2_13
35 D2_12
34 D2_11
33 D2_10
VDD 17
ENC+ 18
ENC– 19
CS 20
SCK 21
SDI 22
D2_0 23
D2_1 24
D2_2 25
D2_3 26
D2_4 27
D2_5 28
D2_6 29
D2_7 30
D2_8 31
D2_9 32
VDD 1
VCM1 2
GND 3
AIN1+ 4
AIN1– 5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
AIN2+ 12
AIN2– 13
GND 14
VCM2 15
VDD 16
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 28°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 28°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
218210f
2
LTC2182/LTC2181/LTC2180
PIN CONFIGURATIONS
DOUBLE DATA RATE LVDS OUTPUT MODE
64 VDD
63 SENSE
62 VREF
61 SDO
60 OF2_1+
59 OF2_1–
58 D1_14_15+
57 D1_14_15–
56 D1_12_13+
55 D1_12_13–
54 D1_10_11+
53 D1_10_11–
52 D1_8_9+
51 D1_8_9–
50 D1_6_7+
49 D1_6_7–
TOP VIEW
VDD 1
VCM1 2
GND 3
AIN1+ 4
AIN1– 5
GND 6
REFH 7
REFL 8
REFH 9
REFL 10
PAR/SER 11
AIN2+ 12
AIN2– 13
GND 14
VCM2 15
VDD 16
48 D1_4_5+
47 D1_4_5–
46 D1_2_3+
45 D1_2_3–
44 D1_0_1+
43 D1_0_1–
42 OVDD
41 OGND
40 CLKOUT+
39 CLKOUT–
38 D2_14_15+
37 D2_14_15–
36 D2_12_13+
35 D2_12_13–
34 D2_10_11+
33 D2_10_11–
VDD 17
ENC+ 18
ENC– 19
CS 20
SCK 21
SDI 22
D2_0_1– 23
D2_0_1+ 24
D2_2_3– 25
D2_2_3+ 26
D2_4_5– 27
D2_4_5+ 28
D2_6_7– 29
D2_6_7+ 30
D2_8_9– 31
D2_8_9+ 32
65
GND
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 28°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2182CUP#PBF
LTC2182CUP#TRPBF
LTC2182UP
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2182IUP#PBF
LTC2182IUP#TRPBF
LTC2182UP
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
LTC2181CUP#PBF
LTC2181CUP#TRPBF
LTC2181UP
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2181IUP#PBF
LTC2181IUP#TRPBF
LTC2181UP
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
LTC2180CUP#PBF
LTC2180CUP#TRPBF
LTC2180UP
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2180IUP#PBF
LTC2180IUP#TRPBF
LTC2180UP
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
218210f
3
LTC2182/LTC2181/LTC2180
CONVERTER
CHARACTERISTICS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2182
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
MIN
LTC2181
TYP
MAX
MIN
LTC2180
TYP
MAX
MIN
MAX
UNITS
l
16
Integral Linearity Error
Differential Analog Input (Note 6) l
–6
±2
6
–6
±2
6
–6
±2
6
LSB
Differential Linearity Error
Differential Analog Input
l
–0.9
±0.5
0.9
–0.9
±0.5
0.9
–0.9
±0.5
0.9
LSB
Offset Error
(Note 7)
l
–7
±1.5
7
–7
±1.5
7
–7
±1.5
7
mV
Gain Error
Internal Reference
External Reference
–1.8
±1.5
–0.5
–1.8
±1.5
–0.5
–1.8
±1.5
–0.5
0.8
%FS
%FS
l
Offset Drift
16
TYP
0.8
16
0.8
Bits
±10
±10
±10
µV/°C
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
Gain Matching
±0.3
±0.3
±0.3
%FS
Offset Matching
±1.5
±1.5
±1.5
mV
Transition Noise
3.3
3.3
3.2
LSBRMS
Full-Scale Drift
Internal Reference
External Reference
ANALOG
INPUT
The
l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN
Analog Input Range (AIN+ – AIN–)
1.7V < VDD < 1.9V
l
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Analog Input (Note 8)
l
0.7
VCM
1.25
V
VSENSE
External Voltage Reference Applied to SENSE External Reference Mode
l
0.625
1.250
1.300
V
IINCM
Analog Input Common Mode Current
Per Pin, 65Msps
Per Pin, 40Msps
Per Pin, 25Msps
IIN1
Analog Input Leakage Current (No Encode)
0 < AIN+, AIN– < VDD
l
–1
1
µA
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–3
3
µA
IIN3
SENSE Input Leakage Current
0.625 < SENSE < 1.3V
l
–6
6
µA
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Jitter
CMRR
Analog Input Common Mode Rejection Ratio
BW-3B
Full-Power Bandwidth
1 to 2
104
64
40
0
Single-Ended Encode
Differential Encode
Figure 6 Test Circuit
VP-P
0.07
0.09
µA
µA
µA
ns
psRMS
psRMS
80
dB
550
MHz
218210f
4
LTC2182/LTC2181/LTC2180
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2182
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
30MHz Input
70MHz Input
140MHz Input
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd Harmonic
30MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
3rd Harmonic
30MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
30MHz Input
70MHz Input
140MHz Input
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
30MHz Input
70MHz Input
140MHz Input
Crosstalk
10MHz Input
MIN
l
75.6
l
82
l
83
l
89
l
74.9
TYP
LTC2181
MAX
77
76.9
76.8
76.3
MIN
75.4
90
90
89
84
84
90
90
89
84
84
95
95
95
95
89
76.8
76.7
76.4
76.3
74.9
–110
TYP
LTC2180
MAX
76.9
76.8
76.7
76.2
MIN
75.5
90
90
89
84
85
90
90
89
84
85
95
95
95
95
89
76.7
76.6
76.3
75.2
74.9
–110
TYP
MAX
UNITS
77.1
77
76.9
76.4
dBFS
dBFS
dBFS
dBFS
90
90
89
84
dBFS
dBFS
dBFS
dBFS
90
90
89
84
dBFS
dBFS
dBFS
dBFS
95
95
95
95
dBFS
dBFS
dBFS
dBFS
76.9
76.8
76.5
76.4
dBFS
dBFS
dBFS
dBFS
–110
dBc
INTERNAL
REFERENCE CHARACTERISTICS l denotes the specifications which apply over the
The
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.5 • VDD – 25mV
0.5 • VDD
0.5 • VDD + 25mV
VCM Output Temperature Drift
±25
VCM Output Resistance
–600µA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
VREF Output Temperature Drift
1.250
±25
VREF Output Resistance
–400µA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
7
0.6
V
ppm/°C
4
1.225
UNITS
Ω
1.275
V
ppm/°C
Ω
mV/V
218210f
5
LTC2182/LTC2181/LTC2180
DIGITAL
INPUTS AND OUTPUTS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC– )
Differential Encode Mode (ENC– Not Tied to GND)
VID
Differential Input Voltage
(Note 8)
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
l
0.2
l
0.2
V
1.2
1.6
V
V
3.6
V
VIN
Input Voltage Range
ENC+, ENC– to GND
RIN
Input Resistance
(See Figure 10)
10
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
Single-Ended Encode Mode (ENC– Tied to GND)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
1.2
V
VIN
Input Voltage Range
ENC+ to GND
l
RIN
Input Resistance
(See Figure 11)
30
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
0
0.6
V
3.6
V
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH
High Level Input Voltage
VDD = 1.8V
l
VIL
Low Level Input Voltage
VDD = 1.8V
l
IIN
Input Current
VIN = 0V to 3.6V
l
CIN
Input Capacitance
(Note 8)
1.3
V
–10
0.6
V
10
µA
3
pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
ROL
Logic Low Output Resistance to GND
VDD = 1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
(Note 8)
200
l
–10
Ω
10
3
µA
pF
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OVDD = 1.8V
VOH
High Level Output Voltage
IO = –500µA
l
VOL
Low Level Output Voltage
IO = 500µA
l
1.750
1.790
0.010
V
0.050
V
OVDD = 1.5V
VOH
High Level Output Voltage
IO = –500µA
1.488
V
VOL
Low Level Output Voltage
IO = 500µA
0.010
V
OVDD = 1.2V
VOH
High Level Output Voltage
IO = –500µA
1.185
V
VOL
Low Level Output Voltage
IO = 500µA
0.010
V
DIGITAL DATA OUTPUTS (LVDS MODE)
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
247
350
175
454
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
1.125
1.250
1.250
1.375
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100
mV
mV
V
V
Ω
218210f
6
LTC2182/LTC2181/LTC2180
POWER
REQUIREMENTS l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2182
SYMBOL PARAMETER
CONDITIONS
LTC2181
LTC2180
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
1.8
1.9
1.8
1.9
V
43.5
44.5
50
mA
mA
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
OVDD
Output Supply Voltage
(Note 10)
l
1.1
1.8
1.9
1.1
1.8
1.9
1.1
IVDD
Analog Supply Current
DC Input
Sine Wave Input
l
89
91
99
64
66
72
IOVDD
Digital Supply Current
Sine Wave Input, OVDD = 1.2V
PDISS
Power Dissipation
l
DC Input
Sine Wave Input, OVDD = 1.2V
5
3
160
170
179
2
115
122
130
V
mA
78.3
82.5
90
mW
mW
LVDS Output Mode
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
IVDD
Analog Supply Current
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
93
95
106
68
70
77
46.5
48.5
54
mA
mA
Digital Supply Current
(0VDD = 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
39
74
83
38
74
83
38
74
83
mA
mA
Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
237
304
341
191
259
288
152
221
247
mW
mW
IOVDD
PDISS
All Output Modes
PSLEEP
Sleep Mode Power
1
1
1
mW
PNAP
Nap Mode Power
10
10
10
mW
PDIFFCLK
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
20
20
20
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2182
SYMBOL
PARAMETER
CONDITIONS
fS
Sampling Frequency
(Note 10)
l
MIN
1
tL
ENC Low Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2
tH
ENC High Time (Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2
tAP
Sample-and-Hold
Acquisition Delay Time
SYMBOL
PARAMETER
TYP
LTC2181
MAX
MIN
65
1
7.69
7.69
500
500
11.88
2
7.69
7.69
500
500
11.88
2
0
TYP
LTC2180
MAX
MIN
40
1
12.5
12.5
500
500
19
2
12.5
12.5
500
500
19
2
0
CONDITIONS
TYP
MAX
UNITS
25
MHz
20
20
500
500
ns
ns
20
20
500
500
ns
ns
0
ns
MIN
TYP
MAX
UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.7
3.1
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.4
2.6
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
Pipeline Latency
Full Data Rate Mode
Double Data Rate Mode
6
6.5
ns
Cycles
Cycles
218210f
7
LTC2182/LTC2181/LTC2180
TIMING
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Data Outputs (LVDS Mode)
tD
ENC to Data Delay
CL = 5pF (Note 8)
l
1.1
1.8
3.2
ns
tC
ENC to CLKOUT Delay
CL = 5pF (Note 8)
l
1
1.5
2.7
ns
tSKEW
DATA to CLKOUT Skew
tD – tC (Note 8)
l
0
0.3
0.6
ns
Pipeline Latency
6.5
Cycles
SPI Port Timing (Note 8)
tSCK
SCK Period
tS
Write Mode
Readback Mode, CSDO = 20pF, RPULLUP = 2k
l
l
40
250
ns
ns
CS to SCK Setup Time
l
5
ns
tH
SCK to CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
ns
tDO
SCK Falling to SDO Valid
Readback Mode, CSDO = 20pF, RPULLUP = 2k
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2182), 40MHz
(LTC2181), or 25MHz (LTC2180), LVDS outputs, differential ENC+/ENC– =
2VP-P sine wave, input range = 2VP-P with differential drive, unless
otherwise noted.
l
125
ns
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = 1.8V, fSAMPLE = 65MHz (LTC2182), 40MHz (LTC2181), or
25MHz (LTC2180), CMOS outputs, ENC+ = single-ended 1.8V square
wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on
each digital output unless otherwise noted. The supply current and power
dissipation specifications are totals for the entire IC, not per channel.
Note 10: Recommended operating conditions.
218210f
8
LTC2182/LTC2181/LTC2180
TIMING DIAGRAMS
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
CH 1
ANALOG
INPUT
A+4
A+2
A
A+3
tAP
CH 2
ANALOG
INPUT
A+1
B+4
B+2
B
B+3
tH
tL
B+1
ENC–
ENC+
tD
D1_0 - D1_15, OF1
A–6
A–5
A–4
A–3
A–2
D2_0 - D2_15, OF2
B–6
B–5
B–4
B–3
B–2
tC
CLKOUT +
CLKOUT –
218210 TD01
Double Data Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
CH 1
ANALOG
INPUT
A+3
tAP
CH 2
ANALOG
INPUT
A+4
A+2
A
A+1
B+4
B+2
B
B+3
tH
tL
B+1
ENC–
ENC+
tD
tD
BIT 0
A-6
BIT 1
A-6
BIT 0
A-5
BIT 1
A-5
BIT 0
A-4
BIT 1
A-4
BIT 0
A-3
BIT 1
A-3
BIT 0
A-2
D1_14_15
BIT 14
A-6
BIT 15
A-6
BIT 14
A-5
BIT 15
A-5
BIT 14
A-4
BIT 15
A-4
BIT 14
A-3
BIT 15
A-3
BIT 14
A-2
D2_0_1
BIT 0
B-6
BIT 1
B-6
BIT 0
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
BIT 14
B-6
BIT 15
B-6
BIT 14
B-5
BIT 15
B-5
BIT 14
B-4
BIT 15
B-4
BIT 14
B-3
BIT 15
B-3
BIT 14
B-2
OF
B-6
OF
A-6
OF
B-5
OF
A-5
OF
B-4
OF
A-4
OF
B-3
OF
A-3
OF
B-2
D1_0_1
••
•
••
•
D2_14_15
OF2_1
CLKOUT+
CLKOUT –
tC
tC
218210 TD02
218210f
9
LTC2182/LTC2181/LTC2180
TIMING DIAGRAMS
Double Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
tAP
CH 1
ANALOG
INPUT
A+4
A+2
A
A+3
tAP
CH 2
ANALOG
INPUT
A+1
B+4
B+2
B
B+3
tH
B+1
tL
ENC–
ENC+
tD
D1_0_1+
D1_0_1–
••
•
D1_14_15+
D1_14_15–
D2_0_1+
D2_0_1–
••
•
D2_14_15+
D2_14_15–
OF2_1+
OF2_1–
tD
BIT 0
A-6
BIT 1
A-6
BIT 0
A-5
BIT 1
A-5
BIT 0
A-4
BIT 1
A-4
BIT 0
A-3
BIT 1
A-3
BIT 0
A-2
BIT 14
A-6
BIT 15
A-6
BIT 14
A-5
BIT 15
A-5
BIT 14
A-4
BIT 15
A-4
BIT 14
A-3
BIT 15
A-3
BIT 14
A-2
BIT 0
B-6
BIT 1
B-6
BIT 0
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
BIT 14
B-6
BIT 15
B-6
BIT 14
B-5
BIT 15
B-5
BIT 14
B-4
BIT 15
B-4
BIT 14
B-3
BIT 15
B-3
BIT 14
B-2
OF
B-6
OF
A-6
OF
B-5
OF
A-5
OF
B-4
OF
A-4
OF
B-3
OF
A-3
OF
B-2
tC
tC
CLKOUT+
CLKOUT –
218210 TD03
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
SDO
R/W
HIGH IMPEDANCE
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
218210 TD04
218210f
10
LTC2182/LTC2181/LTC2180
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2182: Integral
Non-Linearity (INL)
LTC2182: Differential
Non-Linearity (DNL)
4.0
1.0
0
3.0
0.8
–10
1.0
0
–1.0
–2.0
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
INL ERROR (LSB)
–20
0.6
2.0
0.2
0
–0.2
–0.4
–0.8
–4.0
–1.0
0
16384
32768
49152
OUTPUT CODE
65536
–40
–50
–60
–70
–80
–90
–100
–0.6
–3.0
0
16384
32768
49152
OUTPUT CODE
218210 G01
65536
–110
–120
0
–10
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–60
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
20
10
FREQUENCY (MHz)
30
0
20
10
FREQUENCY (MHz)
218210 G04
LTC2182: 64k Point 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
65Msps
LTC2182: SNR vs Input Frequency,
–1dB, 65Msps, 2V Range
78
77
8000
–80
5000
4000
3000
–90
–100
–110
–120
6000
SNR (dBFS)
COUNT
–70
30
218210 G07
0
32831
74
DIFFERENTIAL
ENCODE
73
71
1000
20
10
FREQUENCY (MHz)
75
72
2000
0
SINGLE-ENDED
ENCODE
76
7000
–60
30
LTC2182: Shorted Input Histogram
9000
–40
20
10
FREQUENCY (MHz)
218210 G06
10000
–30
0
218210 G05
0
–20
AMPLITUDE (dBFS)
30
–10
–50
30
LTC2182: 64k Point FFT,
fIN = 140MHz, –1dBFS, 65Msps
–10
–50
20
10
FREQUENCY (MHz)
218210 G03
LTC2182: 64k Point FFT,
fIN = 70MHz, –1dBFS, 65Msps
–40
0
218210 G02
LTC2182: 64k Point FFT,
fIN = 30MHz, –1dBFS, 65Msps
AMPLITUDE (dBFS)
LTC2182: 64k Point FFT, fIN = 5MHz
–1dBFS, 65Msps
32837
32843
32849
OUTPUT CODE
32855
218210 G08
70
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
218210 G09
218210f
11
LTC2182/LTC2181/LTC2180
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2182: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 65Msps,
1V Range
100
95
95
3RD
85
80
2ND
75
70
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
120
85
2ND
80
75
IVDD (mA)
IOVDD (mA)
3.5mA LVDS OUTPUTS
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
218210 G12
77
60
76
50
1.75mA LVDS
30
0
60
LTC2182: SNR vs SENSE,
fIN = 5MHz, –1dBFS
70
40
74
73
71
1.8V CMOS
20
40
SAMPLE RATE (Msps)
75
72
1.2V CMOS
0
70
60
1.0
0
3.0
0.8
–10
–4.0
0.2
0
–0.2
–0.4
–0.8
0
16384
32768
49152
OUTPUT CODE
65536
218210 G16
–1.0
1.3
–40
–50
–60
–70
–80
–90
–100
–0.6
–3.0
1.2
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
–2.0
0.9
1
1.1
SENSE PIN (V)
–20
0.6
2.0
–1.0
0.8
LTC2181: 64k Point FFT,
fIN = 5MHz, –1dBFS, 40Msps
4.0
0
0.7
218210 G15
LTC2181: Differential
Non-Linearity (DNL)
1.0
0.6
218210 G14
LTC2181: Integral
Non-Linearity (INL)
0
78
218210 G13
INL ERROR (LSB)
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
300
3.5mA LVDS
10
20
40
SAMPLE RATE (Msps)
50
30
20
0
60
40
80
70
60
dBc
70
LTC2182: IOVDD vs Sample Rate,
5MHz, –1dBFS, Sine Wave Input
on Each Channel
100
CMOS OUTPUTS
90
80
218210 G11
LTC2182: IVDD vs Sample Rate,
5MHz, –1dBFS, Sine Wave Input
on Each Channel
80
100
70
218210 G10
90
dBFS
110
3RD
90
65
300
130
SNR (dBFS)
90
LTC2182: SFDR vs Input Level,
fIN = 70MHz, 65Msps, 2V Range
SFDR (dBc AND dBFS)
100
2ND AND 3RD HARMONIC (dBFS)
2ND AND 3RD HARMONIC (dBFS)
LTC2182: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 65Msps,
2V Range
0
16384
32768
49152
OUTPUT CODE
65536
218210 G17
–110
–120
0
5
10
15
FREQUENCY (MHz)
20
218210 G18
218210f
12
LTC2182/LTC2181/LTC2180
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–10
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–10
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
5
10
15
FREQUENCY (MHz)
20
0
5
10
15
FREQUENCY (MHz)
218210 G19
LTC2181: 64k Point 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
40Msps
77
8000
5000
4000
3000
–90
–100
5
10
15
FREQUENCY (MHz)
0
32823
20
32829
32835 32841
OUTPUT CODE
95
95
2ND AND 3RD HARMONIC (dBFS)
100
80
2ND
75
70
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
218210 G25
50
100
150
200
250
INPUT FREQUENCY (MHz)
120
dBFS
110
3RD
85
2ND
80
75
100
90
80
dBc
70
60
50
40
70
65
LTC2181: SFDR vs Input Level,
fIN = 70MHz, 40Msps, 2V Range
130
90
300
218210 G24
LTC2181: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 40Msps,
1V Range
100
85
0
218210 G23
LTC2181: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 40Msps,
2V Range
3RD
73
70
32847
218210 G22
90
DIFFERENTIAL
ENCODE
74
71
1000
0
75
72
2000
SFDR (dBc AND dBFS)
–110
–120
6000
SNR (dBFS)
COUNT
–80
SINGLE-ENDED
ENCODE
76
7000
–70
20
LTC2181: SNR vs Input Frequency,
–1dBFS, 40Msps, 2V Range
78
–60
10
15
FREQUENCY (MHz)
LTC2181: Shorted Input Histogram
9000
–50
5
218210 G21
10000
–40
0
218210 G20
0
–30
AMPLITUDE (dBFS)
20
–10
–20
2ND AND 3RD HARMONIC (dBFS)
LTC2181: 64k Point FFT,
fIN = 140MHz, –1dBFS, 40Msps
LTC2181: 64k Point FFT,
fIN = 70MHz, –1dBFS, 40Msps
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
LTC2181: 64k Point FFT,
fIN = 30MHz, –1dBFS, 40Msps
30
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
218210 G26
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
218210 G27
218210f
13
LTC2182/LTC2181/LTC2180
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2181: IVDD vs Sample Rate,
5MHz, –1dBFS, Sine Wave Input
on Each Channel
LTC2181: IOVDD vs Sample Rate,
5MHz, –1dBFS, Sine Wave Input
on Each Channel
80
80
3.5mA LVDS OUTPUTS
CMOS OUTPUTS
70
77
60
76
1.75mA LVDS
40
30
50
0
10
20
30
SAMPLE RATE (Msps)
0
40
73
0
10
20
30
SAMPLE RATE (Msps)
70
40
1.0
0
3.0
0.8
–10
–4.0
0.2
0
–0.2
–0.4
–0.8
0
16384
32768
49152
OUTPUT CODE
65536
–1.0
0
16384
32768
49152
OUTPUT CODE
–40
–50
–60
–70
–80
65536
–110
–120
LTC2180: 64k Point FFT,
fIN = 70MHz, –1dBFS, 25Msps
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–10
–60
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
5
FREQUENCY (MHz)
10
218210 G34
10
LTC2180: 64k Point FFT,
fIN = 140MHz, –1dBFS, 25Msps
0
–50
5
FREQUENCY (MHz)
218210 G33
–10
–40
0
218210 G32
218210 G31
LTC2180: 64k Point FFT,
fIN = 30MHz, –1dBFS, 25Msps
1.3
–90
–100
–0.6
–3.0
1.2
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
–2.0
0.9
1
1.1
SENSE PIN (V)
–20
0.6
2.0
–1.0
0.8
LTC2180: 64k Point FFT,
fIN = 5MHz, –1dBFS, 25Msps
4.0
0
0.7
218210 G30
LTC2180: Differential
Non-Linearity (DNL)
1.0
0.6
218210 G29
LTC2180: Integral
Non-Linearity (INL)
INL ERROR (LSB)
74
71
1.8V CMOS
218210 G28
AMPLITUDE (dBFS)
75
72
20
10
40
SNR (dBFS)
60
78
3.5mA LVDS
50
IOVDD (mA)
IVDD (mA)
70
LTC2181: SNR vs SENSE,
fIN = 5MHz, –1dBFS
0
5
FREQUENCY (MHz)
10
218210 G35
0
5
FREQUENCY (MHz)
10
218210 G36
218210f
14
LTC2182/LTC2181/LTC2180
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2180: 64k Point 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
25Msps
LTC2180: Shorted Input
Histogram
0
10000
78
–10
9000
–20
77
8000
–30
–60
–70
6000
5000
4000
–80
3000
–90
–100
2000
0
32836
10
32842
32848
32854
OUTPUT CODE
100
100
95
95
3RD
80
2ND
75
70
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
2ND
80
75
IOVDD (mA)
IVDD (mA)
45
35
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
50
LTC2180: SNR vs SENSE,
fIN = 5MHz, –1dBFS
78
70
77
60
76
50
1.75mA LVDS
40
25
30
218210 G43
0
0
218210 G42
3.5mA LVDS
75
74
73
72
10
10
15
20
SAMPLE RATE (Msps)
60
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
300
20
5
dBc
70
30
80
0
90
80
LTC2180: IOVDD vs Sample Rate,
5MHz, –1dBFS, Sine Wave Input
on Each Channel
3.5mA LVDS OUTPUTS
dBFS
100
40
70
218210 G41
50
30
LTC2180: SFDR vs Input Level,
fIN = 70MHz, 25Msps, 2V Range
110
3RD
85
LTC2180: IVDD vs Sample Rate,
5MHz, –1dBFS, Sine Wave Input
on Each Channel
300
120
90
65
300
CMOS OUTPUTS
100
150
200
250
INPUT FREQUENCY (MHz)
130
218210 G40
40
50
218210 G39
LTC2180: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 25Msps,
1V Range
2ND AND 3RD HARMONIC (dBFS)
2ND AND 3RD HARMONIC (dBFS)
LTC2180: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 25Msps,
2V Range
85
0
218210 G38
218210 G37
90
DIFFERENTIAL
ENCODE
73
70
32860
SFDR (dBc AND dBFS)
5
FREQUENCY (MHz)
74
71
1000
0
75
72
SNR (dBFS)
–110
–120
SNR (dBFS)
–50
SINGLE-ENDED
ENCODE
76
7000
–40
COUNT
AMPLITUDE (dBFS)
LTC2180: SNR vs Input Frequency,
–1dBFS, 25Msps, 2V Range
71
1.8V CMOS
0
5
10
15
20
SAMPLE RATE (Msps)
25
218210 G44
70
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
1.2
1.3
218210 G45
218210f
15
LTC2182/LTC2181/LTC2180
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL
OUTPUT MODES
VDD (Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to
1.9V. Bypass to ground with 0.1µF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
VCM1 (Pin 2): Common Mode Bias Output, nominally equal
to VDD/2. VCM1 should be used to bias the common mode
of the analog inputs to channel 1. Bypass to ground with
a 0.1µF ceramic capacitor.
GND (Pins 3, 6, 14): ADC Power Ground.
AIN1+ (Pin 4): Channel 1 Positive Differential Analog
Input.
AIN1– (Pin 5): Channel 1 Negative Differential Analog
Input.
REFH (Pins 7, 9): ADC High Reference. See the Applications Information section for recommended bypassing
circuits for REFH and REFL.
REFL (Pins 8, 10): ADC Low Reference. See the Applications Information section for recommended bypassing
circuits for REFH and REFL.
PAR/SER (Pin 11): Programming mode selection pin. Connect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or VDD and not be driven by a logic signal.
AIN2+ (Pin 12): Channel 2 Positive Differential Analog
Input.
AIN2– (Pin 13): Channel 2 Negative Differential Analog
Input.
VCM2 (Pin 15): Common Mode Bias Output, nominally
equal to VDD/2. VCM2 should be used to bias the common
mode of the analog inputs to channel 2. Bypass to ground
with a 0.1µF ceramic capacitor.
ENC+ (Pin 18): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 19): Encode Complement Input. Conversion
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 20): In serial programming mode, (PAR/SER =
0V), CS is the Serial Interface Chip Select Input. When CS
is low, SCK is enabled for shifting data on SDI into the
mode control registers. In the parallel programming mode
(PAR/SER = VDD), CS controls the clock duty cycle stabilizer
(See Table 2). CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 21): In serial programming mode, (PAR/SER =
0V), SCK is the Serial Interface Clock Input. In the parallel
programming mode (PAR/SER = VDD), SCK controls the
digital output mode. (See Table 2). SCK can be driven with
1.8V to 3.3V logic.
SDI (Pin 22): In serial programming mode, (PAR/SER =
0V), SDI is the Serial Interface Data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In the parallel programming mode (PAR/
SER = VDD), SDI can be used together with SDO to power
down the part (see Table 2). SDI can be driven with 1.8V
to 3.3V logic.
OGND (Pin 41): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OVDD (Pin 42): Output Driver Supply. Bypass to ground
with a 0.1µF ceramic capacitor.
SDO (Pin 61): In serial programming mode, (PAR/SER
= 0V), SDO is the optional Serial Interface Data Output.
Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V – 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = VDD), SDO can
be used together with SDI to power down the part (see
Table 2). When used as an input, SDO can be driven with
1.8V to 3.3V logic through a 1k series resistor.
VREF (Pin 62): Reference Voltage Output. Bypass to
ground with a 2.2µF ceramic capacitor. The output voltage
is nominally 1.25V.
218210f
16
LTC2182/LTC2181/LTC2180
PIN FUNCTIONS
SENSE (Pin 63): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9,
D11, D13, D15) appear when CLKOUT+ is high.
Ground (Exposed Pad Pin 65): The exposed pad must be
soldered to the PCB ground.
CLKOUT+ (Pin 40): Data Output Clock. The digital outputs
normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels
(OGND to OVDD)
D2_0 to D2_15 (Pins 23, 24, 25, 26, 27, 28, 29, 30, 31,
32, 33, 34, 35, 36, 37, 38): Channel 2 Digital Outputs.
D2_15 is the MSB.
CLKOUT– (Pin 39): Inverted version of CLKOUT+.
CLKOUT+ (Pin 40): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
D1_0 to D1_15 (Pins 43, 44, 45, 46, 47, 48, 49, 50, 51,
52, 53, 54, 55, 56, 57, 58): Channel 1 Digital Outputs.
D1_15 is the MSB.
OF2 (Pin 59): Channel 2 Over/Under Flow Digital Output.
OF2 is high when an overflow or underflow has occurred.
OF1 (Pin 60): Channel 1 Over/Under Flow Digital Output.
OF1 is high when an overflow or underflow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels
(OGND to OVDD)
D2_0_1 to D2_14_15 (Pins 24, 26, 28, 30, 32, 34, 36,
38): Channel 2 Double Data Rate Digital Outputs. Two data
bits are multiplexed onto each output pin. The even data
bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when
DNC (Pins 23, 25, 27, 29, 31, 33, 35, 37, 43, 45, 47,
49, 51, 53, 55, 57, 59): Do not connect these pins.
CLKOUT– (Pin 39): Inverted version of CLKOUT+.
D1_0_1 to D1_14_15 (Pins 44, 46, 48, 50, 52, 54, 56,
58): Channel 1 Double Data Rate Digital Outputs. Two data
bits are multiplexed onto each output pin. The even data
bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when
CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9,
D11, D13, D15) appear when CLKOUT+ is high.
OF2_1 (Pin 60): Over/Under Flow Digital Output. OF2_1
is high when an overflow or underflow has occurred. The
over/under flow for both channels are multiplexed onto
this pin. Channel 2 appears when CLKOUT+ is low, and
Channel 1 appears when CLKOUT+ is high.
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level Is Programmable. There Is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
D2_0_1–/D2_0_1+ to D2_14_15–/D2_14_15+ (Pins 23/24,
25/26, 27/28, 29/30, 31/32, 33/34, 35/36, 37/38): Channel 2 Double Data Rate Digital Outputs. Two data bits are
multiplexed onto each differential output pair. The even data
bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when
CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9,
D11, D13, D15) appear when CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 39/40): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
218210f
17
LTC2182/LTC2181/LTC2180
PIN FUNCTIONS
D1_0_1–/D1_0_1+ to D1_14_15–/D1_14_15+ (Pins 43/44,
45/46, 47/48, 49/50, 51/52, 53/54, 55/56, 57/58): Channel 2 Double Data Rate Digital Outputs. Two data bits are
multiplexed onto each differential output pair. The even data
bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when
CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9,
D11, D13, D15) appear when CLKOUT+ is high.
OF2_1–/OF2_1+ (Pins 59/60): Over/Under Flow Digital
Output. OF2_1+ is high when an overflow or underflow
has occurred. The over/under flow for both channels
are multiplexed onto this pin. Channel 2 appears when
CLKOUT+ is low, and Channel 1 appears when CLKOUT+
is high.
FUNCTIONAL BLOCK DIAGRAM
OVDD
CH 1
ANALOG
INPUT
OF1
16-BIT
ADC CORE
S/H
OF2
CORRECTION
LOGIC
CH 2
ANALOG
INPUT
16-BIT
ADC CORE
S/H
D1_15
•
•
•
D1_0
OUTPUT
DRIVERS
CLKOUT +
CLKOUT –
VREF
2.2µF
D2_15
•
•
•
D2_0
1.25V
REFERENCE
RANGE
SELECT
SENSE
VCM1
0.1µF
OGND
REFH
REF
BUF
VDD/2
REFL
INTERNAL CLOCK SIGNALS
VDD
DIFF
REF
AMP
CLOCK/DUTY
CYCLE
CONTROL
MODE
CONTROL
REGISTERS
VCM2
0.1µF
GND
REFH
0.1µF
2.2µF
REFL
ENC+
ENC–
PAR/SER CS SCK SDI SDO
218210 F01
0.1µF
Figure 1. Functional Block Diagram
218210f
18
LTC2182/LTC2181/LTC2180
APPLICATIONS INFORMATION
CONVERTER OPERATION
The LTC2182/LTC2181/LTC2180 are low power, twochannel, 16-bit, 65Msps/40Msps/25Msps A/D converters that are powered by a single 1.8V supply. The analog
inputs should be driven differentially. The encode input
can be driven differentially, or single ended for lower
power consumption. The digital outputs can be CMOS,
double data rate CMOS (to halve the number of output
lines), or double data rate LVDS (to reduce digital noise
in the system.) Many additional features can be chosen
by programming the mode control registers through a
serial SPI port.
The two channels are simultaneously sampled by a shared
encode circuit (Figure 2).
Single-Ended Input
For applications less sensitive to harmonic distortion, the
AIN+ input can be driven single-ended with a 1VP-P signal
centered around VCM. The AIN– input should be connected
to VCM and the VCM bypass capacitor should be increased
to 2.2µF. With a single-ended input the harmonic distortion
and INL will degrade, but the noise and DNL will remain
unchanged.
INPUT DRIVE CIRCUITS
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM1 or
VCM2 output pins, which are nominally VDD/2. For the 2V
input range, the inputs should swing from VCM – 0.5V
to VCM + 0.5V. There should be 180° phase difference
between the inputs.
LTC2182
VDD
AIN+
RON
15Ω
10Ω
CPARASITIC
1.8pF
VDD
AIN–
CSAMPLE
5pF
RON
15Ω
10Ω
CSAMPLE
5pF
CPARASITIC
1.8pF
Input filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
also limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with VCM, setting the A/D input at its optimal
DC level. At higher input frequencies a transmission line
balun transformer (Figure 4 to Figure 6) has better balance,
resulting in lower A/D distortion.
VDD
50Ω
VCM
0.1µF
1.2V
0.1µF
ANALOG
INPUT
10k
ENC+
T1
1:1
25Ω
25Ω
AIN+
LTC2182
0.1µF
12pF
ENC–
25Ω
10k
1.2V
218210 F02
Figure 2. Equivalent Input Circuit. Only One of the Two
Analog Channels Is Shown
25Ω
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
AIN–
218210 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
218210f
19
LTC2182/LTC2181/LTC2180
APPLICATIONS INFORMATION
Amplifier Circuits
Reference
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is ACcoupled to the A/D so the amplifier’s output common mode
voltage can be optimally set to minimize distortion.
The LTC2182/LTC2181/LTC2180 has an internal 1.25V
voltage reference. For a 2V input range using the internal
reference, connect SENSE to VDD. For a 1V input range
using the internal reference, connect SENSE to ground.
For a 2V input range with an external reference, apply a
1.25V reference voltage to SENSE (Figure 9).
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figure 4
to Figure 6) should convert the signal to differential before
driving the A/D.
50Ω
VCM
0.1µF
0.1µF
ANALOG
INPUT
12Ω
T2
T1
25Ω
AIN+
LTC2182
0.1µF
8.2pF
0.1µF
25Ω
12Ω
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE.
The VREF, REFH and REFL pins should be bypassed as
shown in Figure 8. A low inductance 2.2µF interdigitated
capacitor is recommended for the bypass between REFH
and REFL. This type of capacitor is available at a low cost
from multiple suppliers.
AIN–
50Ω
218210 F04
0.1µF
Figure 4. Recommended Front-End Circuit for Input
Frequencies from 5MHz to 150MHz
50Ω
ANALOG
INPUT
25Ω
4.7nH
Figure 6. Recommended Front-End Circuit for Input
Frequencies Above 250MHz
LTC2182
0.1µF
25Ω
AIN–
218210 F06
VCM
1.8pF
0.1µF
LTC2182
0.1µF
25Ω
25Ω
AIN+
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
VCM
AIN+
T2
T1
T1
0.1µF
0.1µF
0.1µF
4.7nH
ANALOG
INPUT
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
VCM
0.1µF
AIN–
HIGH SPEED
DIFFERENTIAL
0.1µF
AMPLIFIER
200Ω
200Ω
25Ω
218210 F05
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 5. Recommended Front-End Circuit for Input
Frequencies from 150MHz to 250MHz
ANALOG
INPUT
+
+
–
–
0.1µF
AIN+
12pF
0.1µF
25Ω
LTC2182
AIN–
12pF
218210 F07
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
218210f
20
LTC2182/LTC2181/LTC2180
APPLICATIONS INFORMATION
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
LTC2182
VREF
1.25V
5Ω
2.2µF
1.25V BANDGAP
REFERENCE
0.625V
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • VSENSE FOR
0.625V < VSENSE < 1.300V
RANGE
DETECT
AND
CONTROL
SENSE
BUFFER
INTERNAL ADC
HIGH REFERENCE
C2
0.1µF
–
+
REFH
+
–
REFL
–
+
REFH
+
–
REFL
0.8x
DIFF AMP
C1
C3
0.1µF
Figure 8c. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8a
INTERNAL ADC
LOW REFERENCE
C1: 2.2µF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
OR EQUIVALENT
218210 F08a
Figure 8d. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8b
VREF
Figure 8a. Reference Circuit
2.2µF
Alternatively C1 can be replaced by a standard 2.2µF
capacitor between REFH and REFL (see Figure 8b). The
capacitors should be as close to the pins as possible (not
on the back side of the circuit board).
Figure 8c and Figure 8d show the recommended circuit
board layout for the REFH/REFL bypass capacitors. Note
that in Figure 8c, every pin of the interdigitated capacitor
(C1) is connected since the pins are not internally connected
in some vendors’ capacitors. In Figure 8d the REFH and
REFH
C3
0.1µF
REFL
C1
2.2µF
C2
0.1µF
LTC2182
REFH
REFL
CAPACITORS ARE 0402 PACKAGE SIZE
218210 F08b
Figure 8b. Alternative REFH/REFL Bypass Circuit
1.25V
EXTERNAL
REFERENCE
LTC2182
SENSE
1µF
218210 F09
Figure 9. Using an External 1.25V Reference
Encode Inputs
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals – do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figure 12 and
Figure 13). The encode inputs are internally biased to 1.2V
through 10kΩ equivalent resistance. The encode inputs
can be taken above VDD (up to 3.6V), and the common
mode range is from 1.1V to 1.6V. In the differential encode
218210f
21
LTC2182/LTC2181/LTC2180
APPLICATIONS INFORMATION
LTC2182
mode, ENC– should stay at least 200mV above ground to
avoid falsely triggering the single ended encode mode.
For good jitter performance ENC+ and ENC– should have
fast rise and fall times.
VDD
DIFFERENTIAL
COMPARATOR
VDD
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC– is connected
to ground and ENC+ is driven with a square wave encode
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC+ threshold
is 0.9V. For good jitter performance ENC+ should have fast
rise and fall times.
15k
ENC+
ENC–
30k
218210 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
If the encode signal is turned off or drops below approximately 500kHz, the A/D enters nap mode.
LTC2182
Clock Duty Cycle Stabilizer
ENC+
1.8V TO 3.3V
0V
ENC–
30k
CMOS LOGIC
BUFFER
218210 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
0.1µF
ENC+
T1
0.1µF
50Ω
LTC2182
100Ω
50Ω
0.1µF
ENC–
218210 F12
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
0.1µF
PECL OR
LVDS
CLOCK
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle. The
duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
ENC+
LTC2182
0.1µF
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency, the duty cycle stabilizer circuit
requires one hundred clock cycles to lock onto the input
clock. The duty cycle stabilizer is enabled by mode control
register A2 (serial programming mode), or by CS (parallel
programming mode).
ENC–
218210 F13
Figure 13. PECL or LVDS Encode Drive
The LTC2182/LTC2181/LTC2180 can operate in three digital
output modes: full rate CMOS, double data rate CMOS (to
halve the number of output lines), or double data rate LVDS
(to reduce digital noise in the system.) The output mode
is set by mode control register A3 (serial programming
mode), or by SCK (parallel programming mode). Note that
double data rate CMOS cannot be selected in the parallel
programming mode.
218210f
22
LTC2182/LTC2181/LTC2180
APPLICATIONS INFORMATION
Full Rate CMOS Mode
In full rate CMOS mode the data outputs (D1_0 to D1_15
and D2_0 to D2_15), overflow (OF2, OF1), and the data
output clocks (CLKOUT+, CLKOUT–) have CMOS output
levels. The outputs are powered by OVDD and OGND which
are isolated from the A/D core power and ground. OVDD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double Data Rate CMOS Mode
In Double Data Rate CMOS mode, two data bits are multiplexed and output on each data pin. This reduces the number of digital lines by seventeen, simplifying board routing
and reducing the number of input pins needed to receive
the data. The data outputs (D1_0_1, D1_2_3, D1_4_5,
D1_6_7, D1_8_9, D1_10_11, D1_12_13, D1_14_15,
D2_0_1, D2_2_3, D2_4_5, D2_6_7, D2_8_9, D2_10_11,
D2_12_13, D2_14_15), overflow (OF2_1), and the data
output clocks (CLKOUT+, CLKOUT–) have CMOS output
levels. The outputs are powered by OVDD and OGND which
are isolated from the A/D core power and ground. OVDD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs. Note that the overflow for both ADC
channels is multiplexed onto the OF2_1 pin.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double Data Rate LVDS Mode
In double data rate LVDS mode, two data bits are multiplexed and output on each differential output pair. There
are eight LVDS output pairs per ADC channel (D1_0_1+/
D1_0_1– through D1_14_15+/D1_14_15– and D2_0_1+/
D2_0_1– through D2_14_15+/D2_14_15–) for the digital
output data. Overflow (OF2_1+/OF2_1–) and the data
output clock (CLKOUT+/CLKOUT–) each have an LVDS
output pair. Note that the overflow for both ADC channels
is multiplexed onto the OF2_1+/OF2_1– output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground. In LVDS
mode, OVDD must be 1.8V.
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
Overflow Bit
The overflow output bit outputs a logic high when the
analog input is either over-ranged or under-ranged. The
overflow bit has the same pipeline latency as the data bits.
In Full-Rate CMOS mode each ADC channel has its own
overflow pin (OF1 for channel 1, OF2 for channel 2). In
DDR CMOS or DDR LVDS mode the overflow for both ADC
channels is multiplexed onto the OF2_1 output.
218210f
23
LTC2182/LTC2181/LTC2180
APPLICATIONS INFORMATION
Phase Shifting the Output Clock
DATA FORMAT
In Full Rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In Double Data Rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
set-up and hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially programming mode control register A4.
The LTC2182/LTC2181/LTC2180 can also phase shift the
CLKOUT+/CLKOUT– signals by serially programming mode
control register A2. The output clock can be shifted by 0°,
45°, 90°, or 135°. To use the phase shifting feature the
clock duty cycle stabilizer must be turned on. Another
control register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase shift. The combination of these two features enables phase shifts of 45° up
to 315° (Figure 14).
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D15-D0
(OFFSET BINARY)
D15-D0
(2’s COMPLEMENT)
>1.000000V
1
1111 1111 1111 1111
0111 1111 1111 1111
+0.999970V
0
1111 1111 1111 1111
0111 1111 1111 1111
+0.999939V
0
1111 1111 1111 1110
0111 1111 1111 1110
+0.000030V
0
1000 0000 0000 0001
0000 0000 0000 0001
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