LTC2192
LTC2191/LTC2190
16-Bit, 65Msps/40Msps/
25Msps Low Power
Dual ADCs
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
2-Channel Simultaneous Sampling ADC
Serial LVDS Outputs: 1, 2 or 4 Bits per Channel
77dB SNR
90dB SFDR
Low Power: 198mW/146mW/104mW Total
99mW/73mW/52mW per Channel
Single 1.8V Supply
Selectable Input Ranges: 1VP-P to 2VP-P
550MHz Full-Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
52-Pin (7mm × 8mm) QFN Package
APPLICATIONS
Communications
Cellular Base Stations
n Software-Defined Radios
n Portable Medical Imaging
n Multi-Channel Data Acquisition
n Nondestructive Testing
n
n
The LTC®2192/LTC2191/LTC2190 are 2-channel, simultaneous sampling 16-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 77dB SNR and 90dB
spurious free dynamic range (SFDR). Ultralow jitter of
0.07psRMS allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.3LSBRMS.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs one bit, two bits or
four bits at a time. The LVDS drivers have optional internal
termination and adjustable output levels to ensure clean
signal integrity.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An internal clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
2-Tone FFT, fIN = 70MHz and 69MHz
VDD
CH1
ANALOG
INPUT
S/H
CH2
ANALOG
INPUT
S/H
ENCODE
INPUT
1.8V
16-BIT
ADC CORE
16-BIT
ADC CORE
DATA
SERIALIZER
PLL
GND
–10
OVDD
OGND
219210 TA01a
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
–20
–30
SERIALIZED
LVDS
OUTPUTS
AMPLITUDE (dBFS)
1.8V
0
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
20
10
FREQUENCY (MHz)
30
219210 G07
219210f
1
LTC2192
LTC2191/LTC2190
OUT1B–
OUT1B+
OUT1A–
OUT1A+
GND
SDO
GND
VREF
GND
TOP VIEW
SENSE
Supply Voltages
VDD, OVDD................................................. –0.3V to 2V
Analog Input Voltage
AIN+, AIN–, PAR/SER, SENSE
(Note 3).....................................–0.3V to (VDD + 0.2V)
Digital Input Voltage
ENC+, ENC–, CS, SDI, SCK (Note 4)....... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage................. –0.3V to (OVDD + 0.3V)
Operating Temperature Range
LTC2192C, LTC2191C, LTC2190C............. 0°C to 70°C
LTC2192I, LTC2191I, LTC2190I............. –40°C to 85°C
Storage Temperature Range.................... –65°C to 150°C
PIN CONFIGURATION
VDD
(Notes 1, 2)
VDD
ABSOLUTE MAXIMUM RATINGS
52 51 50 49 48 47 46 45 44 43 42 41
VCM1 1
40 OUT1C+
GND 2
39 OUT1C–
AIN1+ 3
38 OUT1D+
AIN1– 4
37 OUT1D–
GND 5
36 DCO+
REFH 6
35 DCO–
REFL 7
34 OVDD
53
GND
REFH 8
33 OGND
REFL 9
32 FR+
PAR/SER 10
31 FR–
AIN2+ 11
30 OUT2A+
AIN2– 12
29 OUT2A–
GND 13
28 OUT2B+
VCM2 14
27 OUT2B–
OUT2C+
OUT2C–
OUT2D+
OUT2D–
GND
SDI
SCK
CS
ENC–
ENC+
VDD
VDD
15 16 17 18 19 20 21 22 23 24 25 26
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
TJMAX = 150°C, θJA = 29°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2192CUKG#PBF
LTC2192CUKG#TRPBF
LTC2192UKG
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2192IUKG#PBF
LTC2192IUKG#TRPBF
LTC2192UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
LTC2191CUKG#PBF
LTC2191CUKG#TRPBF
LTC2191UKG
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2191IUKG#PBF
LTC2191IUKG#TRPBF
LTC2191UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
LTC2190CUKG#PBF
LTC2190CUKG#TRPBF
LTC2190UKG
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2190IUKG#PBF
LTC2190IUKG#TRPBF
LTC2190UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
219210f
2
LTC2192
LTC2191/LTC2190
CONVERTER
CHARACTERISTICS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
MIN
l
16
LTC2192
TYP
MAX
MIN
LTC2191
TYP
MAX
16
MIN
LTC2190
TYP
MAX
UNITS
16
Bits
Integral Linearity Error
Differential Analog Input
(Note 6)
l
–6
±2
6
–6
±2
6
–6
±2
6
LSB
Differential Linearity Error
Differential Analog Input
l
–0.9
±0.5
0.9
–0.9
±0.5
0.9
–0.9
±0.5
0.9
LSB
Offset Error
(Note 7)
l
–7
±1.5
7
–7
±1.5
7
–7
±1.5
7
mV
Gain Error
Internal Reference
External Reference
l
–1.7
±1.5
–0.4
0.9
–1.7
±1.5
–0.4
0.9
–1.7
±1.5
–0.4
0.9
%FS
%FS
Offset Drift
±10
±10
±10
µV/°C
±30
±10
±30
±10
±30
±10
ppm/°C
ppm/°C
Gain Matching
±0.3
±0.3
±0.3
%FS
Offset Matching
±1.5
±1.5
±1.5
mV
Transition Noise
3.3
3.3
3.2
LSBRMS
Full-Scale Drift
Internal Reference
External Reference
ANALOG
INPUT l denotes the specifications which apply over the full operating temperature range, otherwise
The
specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (AIN+ – AIN–)
1.7V < VDD < 1.9V
l
MIN
TYP
MAX
VIN(CM)
Analog Input Common Mode (AIN+ + AIN–)/2
Differential Analog Input (Note 8)
l
0.7
VCM
1.25
VSENSE
External Voltage Reference Applied to SENSE
External Reference Mode
l
0.625
1.250
1.300
IINCM
Analog Input Common Mode Current
Per Pin, 65Msps
Per Pin, 40Msps
Per Pin, 25Msps
IIN1
Analog Input Leakage Current (No Encode)
0 < AIN+, AIN– < VDD
l
–1
1
µA
1 to 2
UNITS
VP-P
104
64
40
V
V
µA
µA
µA
IIN2
PAR/SER Input Leakage Current
0 < PAR/SER < VDD
l
–3
3
µA
IIN3
SENSE Input Leakage Current
0.625V < SENSE < 1.3V
l
–6
6
µA
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Jitter
CMRR
Analog Input Common Mode Rejection Ratio
BW–3B
Full-Power Bandwidth
0
ns
Single-Ended Encode
Differential Encode
0.07
0.09
psRMS
psRMS
80
dB
Figure 6 Test Circuit
550
MHz
219210f
3
LTC2192
LTC2191/LTC2190
DYNAMIC
ACCURACY l denotes the specifications which apply over the full operating temperature range,
The
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
30MHz Input
70MHz Input
140MHz Input
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd Harmonic
30MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
3rd Harmonic
30MHz Input
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
30MHz Input
70MHz Input
140MHz Input
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
5MHz Input
30MHz Input
70MHz Input
140MHz Input
Crosstalk
10MHz Input
MIN
l
75.3
l
83
l
84
l
89
l
74.8
LTC2192
TYP
MAX
77
76.9
76.8
76.3
90
90
89
84
90
90
89
84
95
95
95
95
76.8
76.7
76.4
76.3
MIN
75.2
LTC2191
TYP
MAX
76.9
76.8
76.7
76.2
90
90
89
84
83
84
95
95
95
95
89
74.8
–110
75.6
83
90
90
89
84
84
MIN
89
76.7
76.6
76.3
75.2
75
–110
LTC2190
TYP
MAX
UNITS
77.1
77
76.9
76.4
dBFS
dBFS
dBFS
dBFS
90
90
89
84
dBFS
dBFS
dBFS
dBFS
90
90
89
84
dBFS
dBFS
dBFS
dBFS
95
95
95
95
dBFS
dBFS
dBFS
dBFS
76.9
76.8
76.5
76.4
dBFS
dBFS
dBFS
dBFS
–110
dBc
INTERNAL
REFERENCE CHARACTERISTICS l denotes the specifications which apply over the full
The
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
VCM Output Voltage
IOUT = 0
MIN
TYP
MAX
0.5 • VDD – 25mV
0.5 • VDD
0.5 • VDD + 25mV
VCM Output Temperature Drift
UNITS
±25
VCM Output Resistance
–600µA < IOUT < 1mA
VREF Output Voltage
IOUT = 0
ppm/°C
4
1.225
Ω
1.250
VREF Output Temperature Drift
1.275
V
±25
VREF Output Resistance
–400µA < IOUT < 1mA
VREF Line Regulation
1.7V < VDD < 1.9V
V
ppm/°C
7
Ω
0.6
mV/V
DIGITAL
INPUTS AND OUTPUTS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ENCODE INPUTS (ENC+, ENC–)
Differential Encode Mode (ENC– Not Tied to GND)
VID
Differential Input Voltage
(Note 8)
l
0.2
VICM
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
l
1.1
l
0.2
V
1.2
1.6
V
V
VIN
Input Voltage Range
ENC+, ENC– to GND (Note 8)
RIN
Input Resistance
See Figure 10
10
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
3.6
V
219210f
4
LTC2192
LTC2191/LTC2190
DIGITAL
INPUTS AND OUTPUTS l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Single-Ended Encode Mode (ENC– Tied to GND)
VIH
High Level Input Voltage
VDD =1.8V
l
VIL
Low Level Input Voltage
VDD =1.8V
l
1.2
V
VIN
Input Voltage Range
ENC+ to GND
l
RIN
Input Resistance
See Figure 11
30
kΩ
CIN
Input Capacitance
(Note 8)
3.5
pF
0
0.6
V
3.6
V
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
VIH
High Level Input Voltage
VDD =1.8V
l
VIL
Low Level Input Voltage
VDD =1.8V
l
IIN
Input Current
VIN = 0V to 3.6V
l
CIN
Input Capacitance
(Note 8)
1.3
V
–10
0.6
V
10
µA
3
pF
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
ROL
Logic Low Output Resistance to GND
VDD =1.8V, SDO = 0V
IOH
Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT
Output Capacitance
(Note 8)
200
l
Ω
–10
10
µA
3
pF
DIGITAL DATA OUTPUTS
VOD
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
247
125
350
175
454
250
mV
mV
VOS
Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l
l
1.125
1.125
1.250
1.250
1.375
1.375
RTERM
On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100
V
V
Ω
POWER
REQUIREMENTS l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 9)
VDD
Analog Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
OVDD
Output Supply Voltage
(Note 10)
l
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
IVDD
Analog Supply Current
Sine Wave Input
l
99
109
72
80
49
56
mA
IOVDD
Digital Supply Current
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
4-Lane Mode, 1.75mA Mode
4-Lane Mode, 3.5mA Mode
l
l
l
l
10.2
17.6
13.6
24.7
21.1
39.6
17
30
25
47
9.2
16.6
12.8
23.9
20.3
38.8
16
29
25
47
8.7
16.1
12.3
23.4
19.9
38.4
16
29
25
47
mA
mA
mA
mA
mA
mA
l
l
l
l
198
211
203
223
217
250
227
251
242
281
146
159
152
172
166
199
173
197
189
229
104
118
111
131
124
158
130
153
146
186
mW
mW
mW
mW
mW
mW
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
4-Lane Mode, 1.75mA Mode
4-Lane Mode, 3.5mA Mode
MIN
LTC2190
TYP MAX
CONDITIONS
Power Dissipation
MIN
LTC2191
TYP MAX
PARAMETER
PDISS
MIN
LTC2192
TYP MAX
SYMBOL
UNITS
PSLEEP
Sleep Mode Power
1
1
1
mW
PNAP
Nap Mode Power
50
50
50
mW
PDIFFCLK
Power Increase with Diffential Encode Mode Enabled
(No Increase for Sleep Mode)
20
20
20
mW
219210f
5
LTC2192
LTC2191/LTC2190
TIMING
CHARACTERISTICS l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
fS
Sampling Frequency
(Notes 10, 11)
tENCL
MIN
l
5
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2
tENCH
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2
tAP
Sample-and-Hold
Acquistion Delay Time
SYMBOL
PARAMETER
CONDITIONS
LTC2192
TYP MAX
MIN
65
5
7.69
7.69
100
100
11.88
2
7.69
7.69
100
100
11.88
2
LTC2191
TYP MAX
MIN
40
5
12.5
12.5
100
100
19
2
12.5
12.5
100
100
19
2
LTC2190
TYP MAX
UNITS
25
MHz
20
20
100
100
ns
ns
20
20
100
100
ns
ns
0
0
0
MIN
TYP
MAX
ns
UNITS
Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND On Each Output)
tSER
Serial Data Bit Period
4-Lane Output Mode
2-Lane Output Mode
1-Lane Output Mode
1/(4 • fS)
1/(8 • fS)
1/(16 • fS)
tFRAME
FR to DCO Delay
(Note 8)
l
tDATA
Data to DCO Delay
(Note 8)
l
0.35 • tSER
tPD
Propagation Delay
(Note 8)
l
0.7n + 2 • tSER
tr
Output Rise Time
Data, DCO, FR, 20% to 80%
0.17
ns
tf
Output Fall Time
Data, DCO, FR, 20% to 80%
0.17
ns
DCO Cycle-Cycle Jitter
tSER = 1ns
0.35 • tSER
Pipeline Latency
0.5 • tSER
Sec
0.65 • tSER
Sec
0.5 • tSER
0.65 • tSER
Sec
1.1n + 2 • tSER
1.5n + 2 • tSER
Sec
60
psP-P
7
Cycles
SPI Port Timing (Note 8)
tSCK
SCK Period
tS
Write Mode
Readback Mode,
CSDO = 20pF, RPULLUP = 2k
l
l
40
250
ns
ns
CS-to-SCK Setup Time
l
5
ns
tH
SCK-to-CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
ns
tDO
SCK Falling to SDO
Valid
Readback Mode,
CSDO = 20pF, RPULLUP = 2k
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above VDD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 65MHz (LTC2192), 40MHz
(LTC2191), or 25MHz (LTC2190), 2-lane output mode, differential
ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive,
unless otherwise noted.
125
ns
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = OVDD=1.8V, fSAMPLE = 65MHz (LTC2192),
40MHz (LTC2191), or 25MHz (LTC2190), 2-lane output mode,
ENC+ = single‑ended 1.8V square wave, ENC– = 0V, input range = 2VP-P
with differential drive, unless otherwise noted. The supply current and
power dissipation specifications are totals for the entire IC, not per
channel.
Note 10: Recommended operating conditions.
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
data rate is 1000Mbps, so tSER must be greater than or equal to 1ns.
219210f
6
LTC2192
LTC2191/LTC2190
TIMING DIAGRAMS
4-Lane Output Mode
tAP
ANALOG
INPUT
N
N+1
tENCL
tENCH
ENC–
ENC+
tDATA
DCO–
tSER
DCO+
FR–
OUT#A–
OUT#A+
OUT#B–
OUT#B+
OUT#C–
OUT#C+
OUT#D–
OUT#D+
tSER
tFRAME
FR+
tPD
tSER
D15
D13
D11
D9
D15
D13
D11
D9
D15
D14
D12
D10
D8
D14
D12
D10
D8
D14
D7
D5
D3
D1
D7
D5
D3
D1
D7
D6
D4
D2
D0
D6
D4
D2
D0
D6
SAMPLE N–7
SAMPLE N–6
SAMPLE N–5
219210 TD01
2-Lane Output Mode
tAP
ANALOG
INPUT
N+1
N
tENCL
tENCH
ENC–
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
tSER
tPD
OUT#A–
OUT#A+
tDATA
tSER
D7
D5
D3
D1
D15
D13
D11
D9
D7
D5
D3
D1
D15
D13
D11
D6
D4
D2
D0
D14
D12
D10
D8
D6
D4
D2
D0
D14
D12
D10
OUT#B–
OUT#B+
SAMPLE N–7
SAMPLE N–6
OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED
SAMPLE N–5
219210 TD02
219210f
7
LTC2192
LTC2191/LTC2190
TIMING DIAGRAMS
1-Lane Output Mode
tAP
ANALOG
INPUT
N+1
N
tENCH
ENC–
tENCL
ENC+
tSER
DCO–
DCO+
tFRAME
FR–
FR+
tSER
tPD
OUT#A–
OUT#A+
tDATA
D3
D2
D1
tSER
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
219210 TD03
SAMPLE N–7
SAMPLE N–6
SAMPLE N–5
OUT#B+, OUT#B–, OUT#C+, OUT#C–, OUT#D+, OUT#D– ARE DISABLED
SPI Port Timing (Readback Mode)
tDS
tS
tDH
tSCK
tH
CS
SCK
tDO
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
XX
D7
HIGH IMPEDANCE
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
XX
D1
D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
SDO
R/W
HIGH IMPEDANCE
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
219210 TD04
219210f
8
LTC2192
LTC2191/LTC2190
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2192: Integral
Nonlinearity (INL)
LTC2192: Differential
Nonlinearity (DNL)
4.0
3.0
0
0.8
–10
–20
0.6
1.0
0
–1.0
–2.0
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
2.0
INL ERROR (LSB)
1.0
0.2
0
–0.2
–0.4
–0.8
–4.0
–1.0
0
16384
32768
49152
OUTPUT CODE
65536
0
16384
32768
49152
OUTPUT CODE
–60
–70
–80
65536
–110
–120
LTC2192: 64k Point FFT,
fIN = 30MHz, –1dBFS, 65Msps
0
–10
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–60
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–100
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
20
10
FREQUENCY (MHz)
30
0
20
10
FREQUENCY (MHz)
219210 G04
LTC2192: 64k Point 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
65Msps
LTC2192: SNR vs Input Frequency,
–1dBFS, 65Msps, 2V Range
78
–20
77
8000
6000
5000
4000
–80
3000
–90
–100
2000
–110
–120
SNR (dBFS)
–70
20
10
FREQUENCY (MHz)
30
219210 G07
0
32831
75
74
DIFFERENTIAL
ENCODE
73
72
71
1000
0
SINGLE-ENDED
ENCODE
76
7000
–60
30
LTC2192: Shorted Input Histogram
9000
–50
20
10
FREQUENCY (MHz)
219210 G06
10000
–40
0
219210 G05
0
COUNT
AMPLITUDE (dBFS)
30
–10
–30
30
LTC2192: 64k Point FFT,
fIN = 140MHz, –1dBFS, 65Msps
–10
–50
20
10
FREQUENCY (MHz)
219210 G03
LTC2192: 64k Point FFT,
fIN = 70MHz, –1dBFS, 65Msps
–40
0
219210 G02
219210 G01
AMPLITUDE (dBFS)
–40
–50
–90
–100
–0.6
–3.0
LTC2192: 64k Point FFT,
fIN = 5MHz, –1dBFS, 65Msps
32837
32843
32849
OUTPUT CODE
32855
219210 G08
70
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
219210 G09
219210f
9
LTC2192
LTC2191/LTC2190
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2192: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 65Msps,
1V Range
100
95
95
90
3RD
85
80
2ND
75
70
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
120
85
2ND
80
75
100
90
70
60
50
40
30
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
300
219210 G11
219210 G10
LTC2192: SNR vs SENSE,
fIN = 5MHz, –1dBFS
45
110
78
4 LANE, 3.5mA
77
35
80
76
SNR (dBFS)
90
IOVDD (mA)
IVDD (mA)
100
2 LANE, 3.5mA
25
4 LANE, 1.75mA
1 LANE, 3.5mA
15
70
10
50
20
30
40
SAMPLE RATE (Msps)
5
60
0
75
74
73
72
2 LANE, 1.75mA
1 LANE, 1.75mA
0
0
219210 G12
LTC2192: IOVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave on
Each Input
LTC2192: IVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave on
Each Channel
60
dBc
80
70
300
dBFS
110
3RD
90
65
LTC2192: SFDR vs Input Level,
fIN = 70MHz, 65Msps, 2V Range
130
SFDR (dBc AND dBFS)
100
2ND AND 3RD HARMONIC (dBFS)
2ND AND 3RD HARMONIC (dBFS)
LTC2192: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 65Msps,
2V Range
71
70
20
40
60
SAMPLE RATE (Msps)
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
1.2
1.3
219210 G15
219210 G13
219210 G14
LTC2191: Integral
Nonlinearity (INL)
LTC2191: Differential
Nonlinearity (DNL)
4.0
1.0
0
3.0
0.8
–10
0
–1.0
–2.0
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
1.0
0.2
0
–0.2
–0.4
–0.8
0
16384
32768
49152
OUTPUT CODE
65536
219210 G16
–1.0
–40
–50
–60
–70
–80
–90
–100
–0.6
–3.0
–4.0
–20
0.6
2.0
INL ERROR (LSB)
LTC2191: 64k Point FFT,
fIN = 5MHz, –1dBFS, 40Msps
0
16384
32768
49152
OUTPUT CODE
65536
219210 G17
–110
–120
0
5
10
15
FREQUENCY (MHz)
20
219210 G18
219210f
10
LTC2192
LTC2191/LTC2190
TYPICAL PERFORMANCE CHARACTERISTICS
0
LTC2191: 64k Point FFT,
fIN = 70MHz, –1dBFS, 40Msps
–10
–20
–20
–20
–30
–30
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–10
–40
–50
–60
–70
–80
–50
–60
–70
–80
–90
–100
–90
–100
–110
–120
–110
–120
–110
–120
0
5
10
15
FREQUENCY (MHz)
20
0
5
10
15
FREQUENCY (MHz)
LTC2191: 64k Point 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
40Msps
0
10000
–10
9000
–20
–60
–70
–80
78
76
6000
5000
4000
0
32823
20
32829
32835 32841
OUTPUT CODE
95
95
2ND AND 3RD HARMONIC (dBFS)
100
80
2ND
75
70
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
219210 G25
50
100
150
200
250
INPUT FREQUENCY (MHz)
120
dBFS
110
3RD
85
2ND
80
75
100
90
80
dBc
70
60
50
40
70
65
LTC2191: SFDR vs Input Level,
fIN = 70MHz, 40Msps, 2V Range
130
90
300
219210 G24
LTC2191: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 40Msps,
1V Range
100
3RD
0
219210 G23
LTC2191: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 40Msps,
2V Range
85
73
70
32847
219210 G22
90
DIFFERENTIAL
ENCODE
74
71
SFDR (dBc AND dBFS)
10
15
FREQUENCY (MHz)
75
72
1000
5
SINGLE-ENDED
ENCODE
77
2000
0
20
LTC2191: SNR vs Input Frequency,
–1dBFS, 40Msps, 2V Range
3000
–90
–100
10
15
FREQUENCY (MHz)
LTC2191: Shorted Input Histogram
SNR (dBFS)
COUNT
AMPLITUDE (dBFS)
–50
5
219210 G21
7000
–40
0
219210 G20
8000
–30
–110
–120
20
LTC2191: 64k Point FFT,
fIN = 140MHz, –1dBFS, 40Msps
–40
–90
–100
219210 G19
2ND AND 3RD HARMONIC (dBFS)
0
–10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
LTC2191: 64k Point FFT,
fIN = 30MHz, –1dBFS, 40Msps
30
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
300
219210 G26
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
219210 G27
219210f
11
LTC2192
LTC2191/LTC2190
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2191: IOVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave on
Each Input
LTC2191: IVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave Input
on Each Channel
LTC2191: SNR vs SENSE,
fIN = 5MHz, –1dBFS
45
80
78
4 LANE, 3.5mA
75
77
35
76
65
25
2 LANE, 3.5mA
4 LANE, 1.75mA
60
1 LANE, 3.5mA
15
1 LANE, 1.75mA
0
10
20
30
SAMPLE RATE (Msps)
5
40
0
73
20
30
10
SAMPLE RATE (Msps)
70
40
1.0
0
3.0
0.8
–10
0.2
0
–0.2
–0.4
–3.0
–0.8
16384
32768
49152
OUTPUT CODE
–1.0
65536
0
16384
32768
49152
OUTPUT CODE
219210 G31
–40
–50
–60
–70
–80
65536
–110
–120
LTC2190: 64k Point FFT,
fIN = 70MHz, –1dBFS, 25Msps
0
–10
–20
–20
–20
–30
–30
–30
–70
–80
AMPLITUDE (dBFS)
0
–10
AMPLITUDE (dBFS)
0
–60
–40
–50
–60
–70
–80
–50
–70
–80
–90
–100
–110
–120
–110
–120
–110
–120
10
219210 G34
0
5
FREQUENCY (MHz)
10
219210 G35
LTC2190: 64k Point FFT,
fIN = 140MHz, –1dBFS, 25Msps
–60
–90
–100
5
FREQUENCY (MHz)
10
–40
–90
–100
0
5
FREQUENCY (MHz)
219210 G33
–10
–50
0
219210 G32
LTC2190: 64k Point FFT,
fIN = 30MHz, –1dBFS, 25Msps
–40
1.3
–90
–100
–0.6
0
1.2
–30
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
–2.0
–4.0
0.9
1
1.1
SENSE PIN (V)
–20
0.6
2.0
–1.0
0.8
LTC2190: 64k Point FFT,
fIN = 5MHz, –1dBFS, 25Msps
4.0
0
0.7
219210 G30
LTC2190: Differential
Nonlinearity (DNL)
1.0
0.6
219210 G29
LTC2190: Integral
Nonlinearity (INL)
INL ERROR (LSB)
74
71
219210 G28
AMPLITUDE (dBFS)
75
72
2 LANE, 1.75mA
55
50
SNR (dBFS)
IOVDD (mA)
IVDD (mA)
70
0
5
FREQUENCY (MHz)
10
219210 G36
219210f
12
LTC2192
LTC2191/LTC2190
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2190: 64k Point, 2-Tone FFT,
fIN = 69MHz, 70MHz, –7dBFS,
25Msps
0
10000
–10
9000
–20
77
–60
–70
–80
6000
SNR (dBFS)
–50
5000
4000
3000
–90
–100
0
32836
10
32842
32848
32854
OUTPUT CODE
95
2ND
75
70
65
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
120
110
3RD
85
2ND
80
75
0
50
100
150
200
250
INPUT FREQUENCY (MHz)
LTC2190: IOVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave on Each
Input
78
77
35
SNR (dBFS)
76
2 LANE, 3.5mA
4 LANE, 1.75mA
1 LANE, 3.5mA
20
219210 G43
15
0
5
15
20
10
SAMPLE RATE (Msps)
75
74
73
72
2 LANE, 1.75mA
71
1 LANE, 1.75mA
25
0
LTC2190: SNR vs SENSE,
fIN = 5MHz, –1dBFS
40
I0VDD (mA)
IVDD (mA)
50
15
20
10
SAMPLE RATE (Msps)
50
219210 G42
4 LANE, 3.5mA
5
60
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
300
45
0
dBc
70
219210 G41
55
35
90
80
30
219210 G40
40
dBFS
100
40
70
LTC2190: IVDD vs Sample Rate,
5MHz, –1dBFS Sine Wave Input on
Each Channel
300
130
90
65
300
45
100
150
200
250
INPUT FREQUENCY (MHz)
LTC2190: SFDR vs Input Level,
fIN = 70MHz, 25Msps, 2V Range
SFDR (dBc AND dBFS)
95
2ND AND 3RD HARMONIC (dBFS)
2ND AND 3RD HARMONIC (dBFS)
100
80
50
219210 G39
LTC2190: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 25Msps,
1V Range
100
3RD
0
219210 G38
LTC2190: 2nd, 3rd Harmonic vs
Input Frequency, –1dBFS, 25Msps,
2V Range
85
DIFFERENTIAL
ENCODE
73
70
32860
219210 G37
90
74
71
1000
5
FREQUENCY (MHz)
75
72
2000
0
SINGLE-ENDED
ENCODE
76
7000
–40
COUNT
AMPLITUDE (dBFS)
78
8000
–30
–110
–120
LTC2190: SNR vs Input Frequency,
–1dBFS, 25Msps, 2V Range
LTC2190: Shorted Input Histogram
25
70
0.6
0.7
0.8
0.9
1
1.1
SENSE PIN (V)
1.2
1.3
219210 G45
219210 G44
219210f
13
LTC2192
LTC2191/LTC2190
PIN FUNCTIONS
VCM1 (Pin 1): Common Mode Bias Output, Nominally Equal
to VDD/2. VCM1 should be used to bias the common mode
of the analog inputs of channel 1. Bypass to ground with
a 0.1µF ceramic capacitor.
GND (Pins 2, 5, 13, 22, 45, 47, 49, Exposed Pad Pin 53):
ADC Power Ground. The exposed pad must be soldered
to the PCB ground.
AIN1+ (Pin 3): Channel 1 Positive Differential Analog
Input.
AIN1– (Pin 4): Channel 1 Negative Differential Analog
Input.
REFH (Pins 6, 8): ADC High Reference. See the Reference
section in the Applications Information for recommended
bypassing circuits for REFH and REFL.
REFL (Pins 7, 9): ADC Low Reference. See the Reference
section in the Applications Information for recommended
bypassing circuits for REFH and REFL.
PAR/SER (Pin 10): Programming Mode Selection Pin.
Connect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the VDD of the part and not be driven
by a logic signal.
AIN2+ (Pin 11): Channel 2 Positive Differential Analog
Input.
AIN2– (Pin 12): Channel 2 Negative Differential Analog
Input.
VCM2 (Pin 14): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM2 should be used to bias the common
mode of the analog inputs of channel 2. Bypass to ground
with a 0.1µF ceramic capacitor.
VDD (Pins 15, 16, 51, 52): Analog Power Supply, 1.7V
to 1.9V. Bypass to ground with 0.1µF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
ENC+ (Pin 17): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the falling edge. Tie to GND for single-ended
encode mode.
CS (Pin 19): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = VDD), CS along with SCK selects 1-,
2- or 4-lane output mode (see Table 3). CS can be driven
with 1.8V to 3.3V logic.
SCK (Pin 20): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK along with CS
selects 1-, 2- or 4-lane output mode (see Table 3). SCK
can be driven with 1.8V to 3.3V logic.
SDI (Pin 21): In Serial Programming Mode, (PAR/SER =
0V), SDI is the Serial Interface Data Input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In the parallel programming pode (PAR/SER
= VDD), SDI can be used to power down the part. SDI can
be driven with 1.8V to 3.3V logic.
OGND (Pin 33): Output Driver Ground. This pin must be
shorted to the ground plane by a very low inductance path.
Use multiple vias close to the pin.
OVDD (Pin 34): Output Driver Supply. Bypass to ground
with a 0.1µF ceramic capacitor.
SDO (Pin 46): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO
is an open-drain NMOS output that requires an external
2k pull-up resistor to 1.8V to 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In the
parallel programming mode (PAR/SER = VDD), SDO selects
3.5mA or 1.75mA LVDS output currents. When used as an
input, SDO can be driven with 1.8V to 3.3V logic through
a 1k series resistor.
219210f
14
LTC2192
LTC2191/LTC2190
PIN FUNCTIONS
VREF (Pin 48): Reference Voltage Output. Bypass to ground
with a 2.2µF ceramic capacitor. The reference output is
nominally 1.25V.
SENSE (Pin 50): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
LVDS Outputs
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
OUT2D–/OUT2D+, OUT2C–/OUT2C+, OUT2B–/OUT2B+,
OUT2A–/OUT2A+ (Pins 23/24, 25/26, 27/28, 29/30): Serial
Data Outputs for Channel 2. In 1-lane output mode only
OUT2A–/OUT2A+ are used. In 2-Lane output mode only
OUT2A–/OUT2A+ and OUT2B–/OUT2B+ are used.
FR–/FR+ (Pins 31/32): Frame Start Outputs.
DCO–/DCO+ (Pins 35/36): Data Clock Outputs.
OUT1D–/OUT1D+, OUT1C–/OUT1C+, OUT1B–/OUT1B+,
OUT1A–/OUT1A+ (Pins 37/38, 39/40, 41/42, 43/44): Serial
Data Outputs for Channel 1. In 1-lane output mode only
OUT1A–/OUT1A+ are used. In 2-lane output mode only
OUT1A–/OUT1A+ and OUT1B–/OUT1B+ are used.
219210f
15
LTC2192
LTC2191/LTC2190
FUNCTIONAL BLOCK DIAGRAM
1.8V
ENC+
ENC–
1.8V
VDD
CH1
ANALOG
INPUT
OVDD
PLL
16-BIT
ADC CORE
S/H
DATA
SERIALIZER
CH2
ANALOG
INPUT
16-BIT
ADC CORE
S/H
OUT1A
OUT1B
OUT1C
OUT1D
OUT2A
OUT2B
OUT2C
OUT2D
DATA CLOCK OUT
FRAME
OGND
VREF
2.2µF
1.25V
REFERENCE
RANGE
SELECT
REF BUF
REFH
REFL
SENSE
VDD/2
DIFF REF
AMP
MODE
CONTROL
REGISTERS
219210 F01
REFH
2.2µF
0.1µF
REFL
VCM1
VCM2
0.1µF
0.1µF
PAR/SER CS SCK SDI SDO
0.1µF
Figure 1. Functional Block Diagram
219210f
16
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
CONVERTER OPERATION
Single-Ended Input
The LTC2192/LTC2191/LTC2190 are low power, 2-channel,
16-bit, 65/40/25Msps A/D converters that are powered
by a single 1.8V supply. The analog inputs should be
driven differentially. The encode input can be driven differentially or single ended for lower power consumption.
To minimize the number of data lines the digital outputs
are serial LVDS. Each channel outputs one bit at a time
(1-lane mode), two bits at a time (2-lane mode) or four
bits at a time (4‑lane mode). Many additional features can
be chosen by programming the mode control registers
through a serial SPI port.
For applications less sensitive to harmonic distortion, the
AIN+ input can be driven singled ended with a 1VP-P signal
centered around VCM. The AIN– input should be connected
to VCM and the VCM bypass capacitor should be increased
to 2.2µF. With a singled-ended input the harmonic distortion
and INL will degrade, but the noise and DNL will remain
unchanged.
ANALOG INPUT
The analog inputs are differential CMOS sample-andhold circuits (Figure 2). The inputs should be driven
differentially around a common mode voltage set by the
VCM1 or VCM2 output pins, which are nominally VDD/2.
For the 2V input range, the inputs should swing from
VCM – 0.5V to VCM + 0.5V. There should be 180° phase
difference between the inputs.
The two channels are simultaneously sampled by a shared
encode circuit (Figure 2).
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
also limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
LTC2192
VDD
AIN+
RON
15Ω
10Ω
CPARASITIC
1.8pF
VDD
AIN–
CSAMPLE
5pF
RON
15Ω
10Ω
CSAMPLE
5pF
CPARASITIC
1.8pF
VDD
1.2V
10k
ENC+
ENC–
10k
1.2V
219210 F02
Figure 2. Equivalent Input Circuit. Only One of Two Analog Channels Is Shown
219210f
17
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
50Ω
50Ω
VCM
0.1µF
0.1µF
0.1µF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
0.1µF
AIN+
ANALOG
INPUT
LTC2192
0.1µF
AIN+
T2
T1
25Ω
1.8pF
0.1µF
AIN–
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
25Ω
AIN–
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
219210 F03
50Ω
ANALOG
INPUT
12Ω
T1
T2
25Ω
50Ω
VCM
VCM
0.1µF
0.1µF
AIN+
LTC2192
0.1µF
219210 F05
Figure 5. Recommended Front-End Circuit for Input Frequencies
from 150MHz to 250MHz
0.1µF
0.1µF
LTC2192
0.1µF
25Ω
12pF
25Ω
VCM
ANALOG
INPUT
4.7nH
T1
AIN+
LTC2192
0.1µF
25Ω
8.2pF
0.1µF
25Ω
12Ω
0.1µF
25Ω
AIN–
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
tap is biased with VCM, setting the A/D input at its optimal
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is AC
coupled to the A/D so the amplifier’s output common mode
voltage can be optimally set to minimize distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single ended, then a transformer circuit (Figures 4
to 6) should convert the signal to differential before driving the A/D.
AIN–
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
219210 F04
Figure 4. Recommended Front-End Circuit for Input Frequencies
from 5MHz to 150MHz
4.7nH
219210 F06
Figure 6. Recommended Front-End Circuit for Input Frequencies
Above 250MHz
VCM
HIGH SPEED
DIFFERENTIAL
0.1µF
AMPLIFIER
ANALOG
INPUT
200Ω
200Ω
25Ω
+
–
0.1µF
AIN+
12pF
0.1µF
25Ω
LTC2192
AIN–
12pF
219210 F07
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
219210f
18
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
Reference
The LTC2192/LTC2191/LTC2190 have an internal 1.25V
voltage reference. For a 2V input range using the internal
reference, connect SENSE to VDD. For a 1V input range
using the internal reference, connect SENSE to ground.
For a 2V input range with an external reference, apply a
1.25V reference voltage to SENSE (Figure 9).
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • VSENSE.
The VREF, REFH and REFL pins should be bypassed as
shown in Figure 8. A low inductance 2.2µF interdigitated
capacitor is recommended for the bypass between REFH
and REFL. This type of capacitor is available at a low cost
from multiple suppliers.
Alternatively, C1 can be replaced by a standard 2.2µF
capacitor between REFH and REFL. The capacitors should
be as close to the pins as possible (not on the back side
of the circuit board).
Figure 8c and 8d show the recommended circuit board
layout for the REFH/REFL bypass capacitors. Note that in
Figure 8c, every pin of the interdigitated capacitor (C1)
is connected since the pins are not internally connected
in some vendors’ capacitors. In Figure 8d the REFH and
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
REFH
C3
0.1µF
LTC2192
REFL
C1
2.2µF
REFH
C2
0.1µF
REFL
CAPACITORS ARE 0402 PACKAGE SIZE
219210 F08b
Figure 8b. Alternative REFH/REFL Bypass Circuit
LTC2192
VREF
1.25V
5Ω
2.2µF
1.25V BANDGAP
REFERENCE
0.625V
TIE TO VDD FOR 2V RANGE;
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • VSENSE FOR
0.625V < VSENSE < 1.300V
219210 F08c
Figure 8c. Recommended Layout for the REFH/REFL Bypass
Circuit in Figure 8a
RANGE
DETECT
AND
CONTROL
SENSE
BUFFER
INTERNAL ADC
HIGH REFERENCE
C2
0.1µF
+
REFH
–
REFL
–
+
REFH
+
–
REFL
–
+
C1
C3
0.1µF
C1: 2.2µF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
OR EQUIVALENT
219210 F08d
Figure 8d. Recommended Layout for the REFH/REFL Bypass
Circuit in Figure 8b
0.8x
DIFF AMP
VREF
INTERNAL ADC
LOW REFERENCE
Figure 8a. Reference Circuit
2.2µF
219210 F08a
1.25V
EXTERNAL
REFERENCE
LTC2192
SENSE
1µF
219210 F09
Figure 9. Using an External 1.25V Reference
219210f
19
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken above
VDD (up to 3.6V), and the common mode range is from 1.1V
to 1.6V. In the differential encode mode, ENC– should stay
at least 200mV above ground to avoid falsely triggering the
single-ended encode mode. For good jitter performance
ENC+ should have fast rise and fall times.
The single-ended encode mode should be used with
CMOS encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave
LTC2192
VDD
encode input. ENC+ can be taken above VDD (up to 3.6V)
so 1.8V to 3.3V CMOS logic levels can be used. The ENC+
threshold is 0.9V. For good jitter performance ENC+ should
have fast rise and fall times. If the encode signal is turned
off or drops below approximately 500kHz, the A/D enters
nap mode.
0.1µF
ENC+
T1
50Ω
100Ω
0.1µF
50Ω
ENC–
0.1µF
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
219210 F12
Figure 12. Sinusoidal Encode Drive
0.1µF
PECL OR
LVDS
CLOCK
ENC+
LTC2192
0.1µF
ENC–
DIFFERENTIAL
COMPARATOR
VDD
LTC2192
219210 F13
Figure 13. PECL or LVDS Encode Drive
15k
ENC+
Clock PLL and Duty Cycle Stabilizer
ENC–
30k
219210 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
LTC2192
1.8V TO 3.3V
0V
ENC+
ENC–
30k
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25µs to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
CMOS LOGIC
BUFFER
219210 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
20
219210f
LTC2192
LTC2191/LTC2190
APPLICATIONS INFORMATION
DIGITAL OUTPUTS
Optional LVDS Driver Internal Termination
The digital outputs of the LTC2192/LTC2191/LTC2190 are
serialized LVDS signals. Each channel outputs one bit at
a time (1-lane mode), two bits at a time (2-lane mode) or
four bits at a time (4-lane mode). Please refer to the Timing Diagrams for details. In 4-lane mode the clock duty
cycle stabilizer must be enabled.
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When
the internal termination is enabled, the output driver
current is doubled to maintain the same output voltage
swing. Internal termination can only be selected in serial
programming mode.
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins.
The maximum serial data rate for the data outputs is 1Gbps,
so the maximum sample rate of the ADC will depend on
the serialization mode as well as the speed grade of the
ADC (See Table 1). The minimum sample rate for all serialization modes is 5Msps.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
Table 1. Maximum Sampling Frequency for All Serialization
Modes. Note That These Limits are for the LTC2192. The
Sampling Frequency for the Slower Speed Grades Cannot
Exceed 40MHz (LTC2191) or 25MHz (LTC2190)
MAXIMUM
SAMPLING
SERIALIZATION FREQUENCY,
DCO
FR
SERIAL
MODE
fS (MHz)
FREQUENCY FREQUENCY DATA RATE
4-Lane
65
2 • fS
fS
4 • fS
2-Lane
65
4 • fS
fS
8 • fS
1-Lane
62.5
8 • fS
fS
16 • fS
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by control register A2 in the
serial programming mode. Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
In the parallel programming mode the SDO pin can select
either 3.5mA or 1.75mA.
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
Table 2. Output Codes vs Input Voltage
AIN+-AIN–
(2V RANGE)
D15-D0
(OFFSET BINARY)
D15-D0
(2’ s COMPLEMENT)
>1.000000V
+0.999970V
+0.999939V
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1110
0111 1111 1111 1111
0111 1111 1111 1111
0111 1111 1111 1110
+0.000030V
+0.000000V
–0.000030V
–0.000061V
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
–0.999939V
–1.000000V
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