LTC2230/LTC2231
10-Bit,170Msps/
135Msps ADCs
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FEATURES
DESCRIPTIO
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The LTC®2230 and LTC2231 are 170Msps/135Msps, sampling 10-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2230/
LTC2231 are perfect for demanding communications
applications with AC performance that includes 61dB SNR
and 75dB spurious free dynamic range for signals
up to 200MHz. Ultralow jitter of 0.15psRMS allows
undersampling of IF frequencies with excellent noise
performance.
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■
■
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Sample Rate: 170Msps/135 Msps
61dB SNR up to 140MHz Input
75dB SFDR up to 200MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 890mW/660mW
LVDS, CMOS, or Demultiplexed CMOS Outputs
Selectable Input Ranges: ±0.5V or ±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
185Msps: LTC2220-1 (12-Bit)
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
64-Pin 9mm x 9mm QFN Package
DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.12LSBRMS.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data rate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
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APPLICATIO S
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Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
The ENC+ and ENC – inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
3.3V
VDD
REFH
REFL
SFDR vs Input Frequency
90
0.5V
TO 3.6V
FLEXIBLE
REFERENCE
85
4th OR HIGHER
80
OVDD
ANALOG
INPUT
INPUT
S/H
–
10-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
D9
•
•
•
D0
OUTPUT
DRIVERS
75
CMOS
OR
LVDS
SFDR (dBFS)
+
70
2nd OR 3rd
65
60
55
OGND
50
45
CLOCK/DUTY
CYCLE
CONTROL
40
0
100
300
500
200
400
INPUT FREQUENCY (MHz)
600
22301 TA01
ENCODE INPUT
2230 TA01b
22301fb
1
LTC2230/LTC2231
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PACKAGE/ORDER I FOR ATIO
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ABSOLUTE
AXI U RATI GS
OVDD = VDD (Notes 1, 2)
TOP VIEW
64 GND
63 VDD
62 VDD
61 GND
60 VCM
59 SENSE
58 MODE
57 LVDS
56 OF +/OFA
55 OF –/DA9
54 D9+/DA8
53 D9–/DA7
52 D8+/DA6
51 D8–/DA5
50 OGND
49 OVDD
Supply Voltage (VDD) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ............... –0.3V to (OVDD + 0.3V)
Power Dissipation ............................................ 1500mW
Operating Temperature Range
LTC2230C, LTC2231C ............................. 0°C to 70°C
LTC2230I, LTC2231I ...........................–40°C to 85°C
Storage Temperature Range ..................–65°C to 150°C
AIN+ 1
AIN+ 2
AIN– 3
AIN– 4
REFHA 5
REFHA 6
REFLB 7
REFLB 8
REFHB 9
REFHB 10
REFLA 11
REFLA 12
VDD 13
VDD 14
VDD 15
GND 16
48 D7+/DA4
47 D7–/DA3
46 D6+/DA2
45 D6–/DA1
44 D5+/DA0
43 D5–/DNC
42 OVDD
41 OGND
40 D4+/DNC
39 D4–/CLOCKOUTA
38 D3+/CLOCKOUTB
37 D3–/OFB
36 CLOCKOUT +/DB9
35 CLOCKOUT –/DB8
34 OVDD
33 OGND
ENC + 17
ENC – 18
SHDN 19
OE 20
DNC 21
DNC 22
DNC/DB1 23
DNC/DB1 24
OGND 25
OVDD 26
D0–/DB2 27
+
D0 /DB3 28
D1–/DB4 29
D1+/DB5 30
D2–/DB6 31
D2+/DB7 32
65
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
UP PART MARKING*
ORDER PART NUMBER
LTC2230CUP
LTC2230IUP
LTC2231CUP
LTC2231IUP
LTC2230UP
LTC2230UP
LTC2231UP
LTC2231UP
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The temperature grade is identified by a label on the shipping container.
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CO VERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
LTC2230
TYP
MAX
MIN
±0.2
1
–0.8
±0.1
0.6
–0.6
LTC2231
TYP
MAX
UNITS
±0.2
0.8
LSB
±0.1
0.6
LSB
●
10
Differential Analog Input (Note 5)
●
–1
Differential Linearity Error
Differential Analog Input
●
–0.6
Integral Linearity Error
Single-Ended Analog Input (Note 5)
±0.5
±0.5
LSB
Differential Linearity Error
Single-Ended Analog Input
±0.1
±0.1
LSB
Offset Error
(Note 6)
●
–35
±3
35
–35
±3
35
mV
Gain Error
External Reference
●
–2.5
±0.5
2.5
–2.5
±0.5
2.5
%FS
Resolution (No Missing Codes)
Integral Linearity Error
10
Bits
±10
±10
μV/C
Full-Scale Drift
Internal Reference
External Reference
±30
±15
±30
±15
ppm/C
ppm/C
Transition Noise
SENSE = 1V
0.12
0.12
LSBRMS
Offset Drift
22301fb
2
LTC2230/LTC2231
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A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (AIN+ – AIN–)
3.1V < VDD < 3.5V (Note 7)
●
VIN, CM
Analog Input Common Mode (AIN+
Differential Input (Note 7)
Single Ended Input (Note 7)
●
●
1
0.5
IIN
Analog Input Leakage Current
0 < AIN+, AIN– < VDD
●
–1
ISENSE
SENSE Input Leakage
0V < SENSE < 1V
●
–1
IMODE
MODE Pin Pull-Down Current to GND
10
μA
ILVDS
LVDS Pin Pull-Down Current to GND
10
μA
tAP
Sample and Hold Acquisition Delay Time
0
ns
tJITTER
Sample and Hold Acquisition Delay Time Jitter
0.15
CMRR
Analog Input Common Mode Rejection Ratio
80
dB
775
MHz
+ AIN–)/2
Full Power Bandwidth
MIN
TYP
MAX
UNITS
±0.5 to ±1
Figure 8 Test Circuit
1.6
1.6
V
1.9
2.1
V
V
1
μA
μA
1
psRMS
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DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio (Note 10)
5MHz Input (1V Range)
5MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic (Note 11)
Spurious Free Dynamic Range
4th Harmonic or Higher (Note 11)
Signal-to-Noise
Plus Distortion Ratio (Note 12)
Intermodulation Distortion
MIN
59.5
61.2
●
60.4
59.5
61.1
60.4
LTC2231
TYP
MAX
UNITS
59.5
61.2
dB
dB
59.5
61.1
dB
dB
59.4
61.0
dB
dB
250MHz Input (1V Range)
250MHz Input (2V Range)
59.0
60.6
59.0
60.6
dB
dB
80
78
80
78
dB
dB
80
78
dB
dB
5MHz Input (1V Range)
5MHz Input (2V Range)
●
64
80
78
68
140MHz Input (1V Range)
140MHz Input (2V Range)
78
78
78
78
dB
db
250MHz Input (1V Range)
250MHz Input (2V Range)
75
74
78
78
dB
dB
5MHz Input (1V Range)
5MHz Input (2V Range)
86
86
86
86
dB
dB
86
86
dB
dB
●
73
86
86
74
140MHz Input (1V Range)
140MHz Input (2V Range)
86
86
86
86
dB
dB
250MHz Input (1V Range)
250MHz Input (2V Range)
85
85
85
85
dB
dB
59.5
61.2
59.5
61.2
dB
dB
59.5
61.1
dB
dB
81
dBc
5MHz Input (1V Range)
5MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
IMD
MAX
59.4
61.0
70MHz Input (1V Range)
70MHz Input (2V Range)
S/(N+D)
LTC2230
TYP
140MHz Input (1V Range)
140MHz Input (2V Range)
70MHz Input (1V Range)
70MHz Input (2V Range)
SFDR
MIN
fIN1 = 138MHz,
fIN2 = 140MHz
●
59.5
59.5
61.1
81
60
22301fb
3
LTC2230/LTC2231
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I TER AL REFERE CE CHARACTERISTICS
(Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
VCM Output Voltage
IOUT = 0
1.570
1.600
1.630
±25
VCM Output Tempco
UNITS
V
ppm/°C
VCM Line Regulation
3.1V < VDD < 3.5V
3
mV/V
VCM Output Resistance
–1mA < IOUT < 1mA
4
Ω
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2.5
V
V
ENCODE INPUTS (ENC +, ENC –)
VID
Differential Input Voltage
VICM
Common Mode Input Voltage
RIN
Input Resistance
CIN
Input Capacitance
●
Internally Set
Externally Set (Note 7)
●
0.2
1.1
(Note 7)
V
1.6
1.6
6
kΩ
3
pF
LOGIC INPUTS (OE, SHDN)
VIH
High Level Input Voltage
VDD = 3.3V
●
VIL
Low Level Input Voltage
VDD = 3.3V
●
IIN
Input Current
VIN = 0V to VDD
●
CIN
Input Capacitance
(Note 7)
2
V
–10
0.8
V
10
μA
3
pF
LOGIC OUTPUTS (CMOS MODE)
OVDD = 3.3V
COZ
Hi-Z Output Capacitance
OE = High (Note 7)
3
pF
ISOURCE
Output Source Current
VOUT = 0V
50
mA
ISINK
Output Sink Current
VOUT = 3.3V
50
mA
VOH
High Level Output Voltage
IO = –10μA
IO = –200μA
●
IO = 10μA
IO = 1.6mA
●
VOL
Low Level Output Voltage
3.1
3.295
3.29
0.005
0.09
V
V
0.4
V
V
OVDD = 2.5V
VOH
High Level Output Voltage
IO = –200μA
2.49
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
VOH
High Level Output Voltage
IO = –200μA
1.79
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
OVDD = 1.8V
LOGIC OUTPUTS (LVDS MODE)
VOD
Differential Output Voltage
100Ω Differential Load
●
247
350
454
VOS
Output Common Mode Voltage
100Ω Differential Load
●
1.125
1.250
1.375
mV
V
22301fb
4
LTC2230/LTC2231
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POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
MIN
LTC2230
TYP
MAX
PARAMETER
CONDITIONS
VDD
Analog Supply Voltage
(Note 8)
PSHDN
Shutdown Power
SHDN = H, OE = H, No CLK
2
2
mW
PNAP
Nap Mode Power
SHDN = H, OE = L, No CLK
35
35
mW
●
3.1
3.3
3.5
MIN
LTC2231
TYP
MAX
SYMBOL
3.1
3.3
UNITS
3.5
V
LVDS OUTPUT MODE
(Note 8)
●
OVDD
Output Supply Voltage
3
3.3
3.6
264
288
3
3.3
3.6
V
IVDD
Analog Supply Current
●
196
212
mA
IOVDD
Output Supply Current
●
53
68
53
68
mA
PDISS
Power Dissipation
●
1045
1175
822
924
mW
CMOS OUTPUT MODE
OVDD
Output Supply Voltage
IVDD
Analog Supply Current
PDISS
Power Dissipation
(Note 8)
●
0.5
●
3.3
3.6
264
288
0.5
890
3.3
3.6
V
196
212
mA
660
mW
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TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
fS
Sampling Frequency
(Note 8)
●
1
tL
ENC Low Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
●
2.8
2
tH
ENC High Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●
●
2.8
2
tAP
Sample-and-Hold Aperture Delay
tOE
Output Enable Delay
(Note 7)
●
LTC2230
TYP
MAX
MIN
LTC2231
TYP
MAX
UNITS
135
MHz
170
1
2.94
2.94
500
500
3.5
2
3.7
3.7
500
500
ns
ns
2.94
2.94
500
500
3.5
2
3.7
3.7
500
500
ns
ns
0
0
5
10
ns
5
10
ns
LVDS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
●
1.3
2.2
3.5
1.3
2.2
3.5
ns
tC
ENC to CLOCKOUT Delay
(Note 7)
●
1.3
2.2
3.5
1.3
2.2
3.5
ns
DATA to CLOCKOUT Skew
(tC - tD) (Note 7)
●
–0.6
0
0.6
–0.6
0
0.6
ns
Rise Time
0.5
0.5
ns
Fall Time
0.5
0.5
ns
5
5
Pipeline Latency
Cycles
CMOS OUTPUT MODE
tD
ENC to DATA Delay
(Note 7)
●
1.3
2.1
3.5
1.3
2.1
3.5
ns
tC
ENC to CLOCKOUT Delay
(Note 7)
●
1.3
2.1
3.5
1.3
2.1
3.5
ns
DATA to CLOCKOUT Skew
(tC - tD) (Note 7)
●
–0.6
0
0.6
–0.6
0
0.6
Pipeline Latency Full Rate CMOS
Demuxed Interleaved
Demuxed Simultaneous
ns
5
5
Cycles
5
5
Cycles
5 and 6
5 and 6
Cycles
22301fb
5
LTC2230/LTC2231
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they will
be clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 170MHz (LTC2230) or 135MHz (LTC2231),
LVDS outputs differential, ENC+/ENC– = 2VP-P sine wave, input range =
2VP-P with differential drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve. The
deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when the
output code flickers between 00 0000 0000 and 11 1111 1111 in 2’s
complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
Note 9: VDD = 3.3V, fSAMPLE = 170MHz (LTC2230) or 135MHz (LTC2231),
differential ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential
drive, output CLOAD = 5pF.
Note 10: SNR minimum and typical values are for LVDS mode. Typical values
for CMOS mode are typically 0.1dB lower.
Note 11: SFDR minimum values are for LVDS mode. Typical values are for
both LVDS and CMOS modes.
Note 12: SINAD minimum and typical values are for LVDS mode. Typical
values for CMOS mode are typically 0.1dB lower.
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC2230: Shorted Input Noise
Histogram
LTC2230: DNL, 2V Range
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0
– 0.2
100000
0
– 0.2
– 0.4
– 0.6
– 0.6
– 0.8
– 0.8
80000
60000
40000
20000
– 1.0
256
0
512
OUTPUT CODE
768
512
OUTPUT CODE
768
2230 G01
7
6
0
256
0
1024
131059
120000
0.2
– 0.4
– 1.0
140000
COUNT
ERROR (LSB)
ERROR (LSB)
LTC2230: INL, 2V Range
1024
513
514
515
CODE
2230 G02
LTC2230: SNR
vs Input Frequency, –1dB,
2V Range
2230 G23
LTC2230: SNR
vs Input Frequency, –1dB,
1V Range
63
63
62
62
61
61
LTC2230: SFDR (HD2 and HD3)
vs Input Frequency, –1dB,
2V Range
90
60
80
75
SFDR (dBFS)
SNR (dBFS)
SNR (dBFS)
85
60
59
59
58
58
57
57
70
65
60
55
50
45
0
100
300
400
500
200
INPUT FREQUENCY (MHz)
600
2230 G03
0
100
300
400
500
200
INPUT FREQUENCY (MHz)
600
2230 G04
40
0
100
300
500
200
400
INPUT FREQUENCY (MHz)
600
2230 G05
22301fb
6
LTC2230/LTC2231
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC2230: SFDR (HD4+) vs Input
Frequency, –1dB, 2V Range
90
85
85
80
80
80
75
75
75
70
65
60
SFDR (dBFS)
90
85
70
65
60
70
65
60
55
55
55
50
50
50
45
45
45
40
40
100
300
500
200
400
600
INPUT FREQUENCY (MHz)
2230 G06
85
SFDR AND SNR (dBFS)
SFDR
75
70
65
SNR
60
55
100
40
300
500
200
400
600
INPUT FREQUENCY (MHz)
2230 G07
LTC2230: SFDR and SNR
vs Sample Rate, 1V Range,
fIN = 30MHz, –1dB
90
80
0
90
290
85
280
SFDR
80
70
65
SNR
2V RANGE
250
1V RANGE
240
210
0 20 40 60 80 100 120 140 160 180 200
SAMPLE RATE (Msps)
2230 G10
0
20 40 60 80 100 120 140 160 180 200
SAMPLE RATE (Msps)
2230 G11
LTC2230: SFDR vs Input Level,
f IN = 70MHz, 2V Range
LTC2230: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
60
100
90
LVDS OUTPUTS, 0VDD = 3.3V
50
dBFS
SFDR (dBc AND dBFS)
80
40
IOVDD (mA)
260
220
50
0 20 40 60 80 100 120 140 160 180 200
SAMPLE RATE (Msps)
2230 G09
300
500
200
400
600
INPUT FREQUENCY (MHz)
2230 G08
230
55
50
100
270
75
60
0
LTC2230: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
IVDD (mA)
0
LTC2230: SFDR and SNR
vs Sample Rate, 2V Range,
fIN = 30MHz, –1dB
SFDR AND SNR (dBFS)
LTC2230: SFDR (HD4+) vs Input
Frequency, –1dB, 1V Range
90
SFDR (dBFS)
SFDR (dBFS)
LTC2230: SFDR (HD2 and HD3) vs
Input Frequency, –1dB, 1V Range
30
20
CMOS OUTPUTS, 0VDD = 1.8V
10
70
60
dBc
50
40
30
20
10
0
0
20 40 60 80 100 120 140 160 180 200
SAMPLE RATE (Msps)
2230 G12
0
–50
–40
–30
–10
–20
INPUT LEVEL (dBFS)
0
2230 G13
22301fb
7
LTC2230/LTC2231
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC2230: 8192 Point FFT,
f IN = 30MHz, –1dB, 1V Range
LTC2230: 8192 Point FFT,
f IN = 70MHz, –1dB, 2V Range
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
–50
–60
–70
–80
AMPLITUDE (dB)
0
–10
AMPLITUDE (dB)
AMPLITUDE (dB)
LTC2230: 8192 Point FFT,
f IN = 30MHz, –1dB, 2V Range
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
10
20
2230 G14
LTC2230: 8192 Point FFT,
f IN = 70MHz, –1dB, 1V Range
30 40 50 60
FREQUENCY (MHz)
70
80
–120
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
–70
–80
AMPLITUDE (dB)
0
–60
–50
–60
–70
–80
–90
–100
–110
–110
–110
–120
–120
70
80
10
20
2230 G17
LTC2230: 8192 Point FFT,
f IN = 250MHz, –1dB, 2V Range
30 40 50 60
FREQUENCY (MHz)
70
80
–120
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
–70
–80
AMPLITUDE (dB)
0
–60
–50
–60
–70
–80
–90
–100
–110
–110
–110
–120
–120
70
80
2230 G20
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
2230 G19
–80
–100
30 40 50 60
FREQUENCY (MHz)
70
–70
–100
20
30 40 50 60
FREQUENCY (MHz)
–60
–90
10
20
–50
–90
0
10
LTC2230: 8192 Point FFT,
f IN = 500MHz, –6dB, 1V Range
–10
–50
0
2230 G18
LTC2230: 8192 Point FFT,
f IN = 250MHz, –1dB, 1V Range
AMPLITUDE (dB)
AMPLITUDE (dB)
0
80
2230 G16
–80
–100
30 40 50 60
FREQUENCY (MHz)
70
–70
–100
20
30 40 50 60
FREQUENCY (MHz)
–60
–90
10
20
–50
–90
0
10
LTC2230: 8192 Point FFT,
f IN = 140MHz, –1dB, 1V Range
–10
–50
0
2230 G15
LTC2230: 8192 Point FFT,
f IN = 140MHz, –1dB, 2V Range
AMPLITUDE (dB)
AMPLITUDE (dB)
0
80
2230 G21
–120
0
10
20
30 40 50 60
FREQUENCY (MHz)
70
80
2230 G22
22301fb
8
LTC2230/LTC2231
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2231: Shorted Input Noise
Histogram
LTC2231: DNL, 2V Range
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0
– 0.2
100000
0
– 0.2
– 0.4
– 0.6
– 0.6
– 0.8
– 0.8
512
OUTPUT CODE
768
20000
512
OUTPUT CODE
768
513
1024
2231 G23
LTC2231: SFDR (HD2 and HD3) vs
Input Frequency, –1dB, 2V Range
90
64
85
63
63
62
62
61
60
59
58
58
57
57
56
56
55
0
100
500
200
300
400
INPUT FREQUENCY (MHz)
55
600
80
SFDR (dBFS)
SNR (dBFS)
65
64
59
75
70
65
60
55
0
100
500
200
300
400
INPUT FREQUENCY (MHz)
2231 G03
50
600
LTC2231: SFDR (HD4+) vs Input
Frequency, –1dB, 2V Range
85
85
80
80
80
75
75
75
SFDR (dBFS)
85
SFDR (dBFS)
90
70
65
65
60
60
55
55
55
100
200
300
400
500
INPUT FREQUENCY (MHz)
600
2231 G06
50
0
100
200
300
400
500
INPUT FREQUENCY (MHz)
600
70
60
0
200
300
400
500
INPUT FREQUENCY (MHz)
LTC2231: SFDR (HD4+) vs Input
Frequency, –1dB, 1V Range
90
50
100
2231 G05
90
65
0
2231 G04
LTC2231: SFDR (HD2 and HD3) vs
Input Frequency, –1dB, 1V Range
70
515
CODE
65
60
514
2231 G02
LTC2231: SNR vs Input
Frequency, –1dB, 1V Range
61
3
5
0
256
0
1024
LTC2231: SNR vs Input
Frequency, –1dB, 2V Range
SNR (dBFS)
60000
40000
2231 G01
SFDR (dBFS)
80000
– 1.0
256
0
131064
120000
0.2
– 0.4
– 1.0
140000
COUNT
ERROR (LSB)
ERROR (LSB)
LTC2231: INL, 2V Range
600
2231 G07
50
0
100
200
300
400
500
INPUT FREQUENCY (MHz)
600
2231 G08
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9
LTC2230/LTC2231
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2231: SFDR and SNR
vs Sample Rate, 2V Range,
fIN = 30MHz, –1dB
LTC2231: SFDR and SNR
vs Sample Rate, 1V Range,
fIN = 30MHz, –1dB
85
85
SFDR
220
SFDR
80
75
70
65
SNR
60
55
210
75
200
IVDD (mA)
SFDR AND SNR (dBFS)
80
SFDR AND SNR (dBFS)
LTC2231: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
70
65
SNR
60
160
50
0
20
40 60 80 100 120 140 160
SAMPLE RATE (Msps)
150
0
20
40 60 80 100 120 140 160
SAMPLE RATE (Msps)
2231 G09
0
20
40
60 80 100 120 140 160 180
SAMPLE RATE (Msps)
2231 G10
2231 G11
LTC2231: SFDR vs Input Level,
f IN = 70MHz, 2V Range
LTC2231: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
100
60
90
LVDS OUTPUTS, OVDD = 3.3V
50
dBFS
SFDR (dBc AND dBFS)
80
40
IOVDD (mA)
1V RANGE
180
170
55
50
2V RANGE
190
30
20
CMOS OUTPUTS, OVDD = 1.8V
10
70
60
dBc
50
40
30
20
10
0
0
20
40
60 80 100 120 140 160 180
SAMPLE RATE (Msps)
2231 G12
0
–50
–40
–30
–10
–20
INPUT LEVEL (dBFS)
0
2231 G13
22301fb
10
LTC2230/LTC2231
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2231: 8192 Point FFT,
f IN = 30MHz, –1dB, 1V Range
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
–50
–60
–70
–80
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
–120
0 5 10 15 20 25 30 35 40 45 50 55 60 65
0 5 10 15 20 25 30 35 40 45 50 55 60 65
0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2231 G14
2231 G15
LTC2231: 8192 Point FFT,
f IN = 140MHz, –1dB, 2V Range
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
–60
–70
–80
AMPLITUDE (dB)
0
–50
2231 G16
LTC2231: 8192 Point FFT,
f IN = 140MHz, –1dB, 1V Range
–10
AMPLITUDE (dB)
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
–120
0 5 10 15 20 25 30 35 40 45 50 55 60 65
0 5 10 15 20 25 30 35 40 45 50 55 60 65
0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2231 G17
LTC2231: 8192 Point FFT,
f IN = 250MHz, –1dB, 2V Range
2231 G18
LTC2231: 8192 Point FFT,
f IN = 250MHz, –1dB, 1V Range
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
AMPLITUDE (dB)
0
–10
–50
–60
–70
–80
2231 G19
LTC2231: 8192 Point FFT,
f IN = 500MHz, –6dB, 1V Range
AMPLITUDE (dB)
AMPLITUDE (dB)
AMPLITUDE (dB)
0
LTC2231: 8192 Point FFT,
f IN = 70MHz, –1dB, 1V Range
AMPLITUDE (dB)
LTC2231: 8192 Point FFT,
f IN = 70MHz, –1dB, 2V Range
–10
AMPLITUDE (dB)
AMPLITUDE (dB)
LTC2231: 8192 Point FFT,
f IN = 30MHz, –1dB, 2V Range
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–90
–100
–100
–100
–110
–110
–110
–120
–120
–120
0 5 10 15 20 25 30 35 40 45 50 55 60 65
0 5 10 15 20 25 30 35 40 45 50 55 60 65
0 5 10 15 20 25 30 35 40 45 50 55 60 65
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2231 G20
2231 G21
2231 G22
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11
LTC2230/LTC2231
U
U
U
PI FU CTIO S
(CMOS Mode)
AIN+ (Pins 1, 2): Positive Differential Analog Input.
AIN – (Pins 3, 4): Negative Differential Analog Input.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin
function.
DNC (Pins 21, 22, 40, 43): Do not connect these pins.
REFHA (Pins 5, 6): ADC High Reference. Bypass to
Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, 12
with a 2.2μF ceramic capacitor and to ground with 1μF
ceramic capacitor.
DB0 - DB9 (Pins 23, 24, 27, 28, 29, 30, 31, 32, 35, 36):
Digital Outputs, B bus. At high impedance in full rate
CMOS mode. DB9 is MSB.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,
6 with 0.1μF ceramic chip capacitor. Do not connect to
Pins 11, 12.
OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output
Drivers. Bypass to ground with 0.1μF ceramic chip
capacitor.
REFHB (Pins 9, 10): ADC High Reference. Bypass to
Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not
connect to Pins 5, 6.
OFB (Pin 37): Over/Under Flow Output for B bus. High
when an over or under flow has occurred. At high impedance in full rate CMOS mode.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6
with a 2.2μF ceramic capacitor and to ground with 1μF
ceramic capacitor.
CLKOUTB (Pin 38): Data Valid Output for B bus. In demux
mode with interleaved update, latch B bus data on the
falling edge of CLKOUTB. In demux mode with simultaneous update, latch B bus data on the rising edge of
CLKOUTB. This pin does not become high impedance in
full rate CMOS mode.
VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to
GND with 0.1μF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC+ (Pin 17): Encode Input. The input sample starts on
the positive edge.
ENC – (Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1μF
ceramic for single-ended ENCODE signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
CLKOUTA (Pin 39): Data Valid Output for A bus. Latch A
bus data on the falling edge of CLKOUTA.
DA0 - DA9 (Pins 44 to 48, 51 to 55): Digital Outputs, A bus.
DA9 is the MSB.
OFA (Pin 56): Over/Under Flow Output for A bus. High
when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting
LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux
CMOS mode with interleaved update. Connecting LVDS to
VDD selects LVDS mode.
22301fb
12
LTC2230/LTC2231
U
U
U
PI FU CTIO S
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3VDD selects offset
binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pin 60): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2μF ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
(LVDS Mode)
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, 6
with a 2.2μF ceramic capacitor and to ground with 1μF
ceramic capacitor.
VDD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to
GND with 0.1μF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC+ (Pin 17): Encode Input. The input sample starts on
the positive edge.
ENC– (Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1μF
ceramic for single-ended ENCODE signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
AIN+ (Pins 1, 2): Positive Differential Analog Input.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin
function.
AIN– (Pins 3, 4): Negative Differential Analog Input.
DNC (Pins 21, 22, 23, 24): Do not connect these pins.
REFHA (Pins 5, 6): ADC High Reference. Bypass to
Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, 12
with a 2.2μF ceramic capacitor and to ground with 1μF
ceramic capacitor.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,
6 with 0.1μF ceramic chip capacitor. Do not connect to
Pins 11, 12.
D0–/D0+ to D9–/D9+ (Pins 27 to 32, 37 to 40, 43 to 48, 51
to 54): LVDS Digital Outputs. All LVDS outputs require
differential 100Ω termination resistors at the LVDS receiver. D9 –/D9+ is the MBS.
REFHB (Pins 9, 10): ADC High Reference. Bypass to
Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not
connect to Pins 5, 6.
OVDD (Pins 26, 34, 42, 49): Positive Supply for the
Output Drivers. Bypass to ground with 0.1μF ceramic chip
capacitor.
22301fb
13
LTC2230/LTC2231
U
U
U
PI FU CTIO S
CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid
Output. Latch data on rising edge of CLKOUT–, falling edge
of CLKOUT+.
OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output.
High when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting
LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux
CMOS mode with interleaved update. Connecting LVDS to
VDD selects LVDS mode.
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and turns the clock duty cycle
stabilizer off. Connecting MODE to 1/3VDD selects offset
binary output format and turns the clock duty cycle stabi-
lizer on. Connecting MODE to 2/3VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2’s complement
output format and turns the clock duty cycle stabilizer off.
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pin 60): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2μF ceramic chip capacitor.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
22301fb
14
LTC2230/LTC2231
W
FUNCTIONAL BLOCK DIAGRA
U
U
AIN+
AIN–
VCM
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
1.6V
REFERENCE
2.2μF
SHIFT REGISTER
AND CORRECTION
RANGE
SELECT
REFH
SENSE
FIFTH PIPELINED
ADC STAGE
REFL
INTERNAL CLOCK SIGNALS
OVDD
REF
BUF
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DIFF
REF
AMP
REFLB REFHA
2.2μF
0.1μF
1μF
CONTROL
LOGIC
•
•
•
OUTPUT
DRIVERS
+ OF
–+
– D9
+
–+
–
D0
CLKOUT
22201 F01
REFLA REFHB
OGND
ENC+
ENC–
M0DE LVDS SHDN
OEL
0.1μF
1μF
Figure 1. Functional Block Diagram
22301fb
15
LTC2230/LTC2231
W
UW
TI I G DIAGRA S
LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
N+1
tL
ENC –
ENC +
tD
N–5
D0-D9, OF
N–4
N–3
N–2
N–1
tC
CLOCKOUT –
CLOCKOUT +
22201 TD01
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
N+1
tL
ENC –
ENC +
tD
N–5
DA0-DA9, OFA
N–4
N–3
N–2
N–1
tC
CLOCKOUTB
CLOCKOUTA
DB0-DB9, OFB
HIGH IMPEDANCE
22201 TD02
22301fb
16
LTC2230/LTC2231
W
UW
TI I G DIAGRA S
Demultiplexed CMOS Outputs with Interleaved Update
All Outputs Are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
N+1
tL
ENC –
ENC +
tD
N–5
DA0-DA9, OFA
N–3
N–1
tD
N–6
DB0-DB9, OFB
N–4
tC
N–2
tC
CLOCKOUTB
CLOCKOUTA
22201 TD03
Demultiplexed CMOS Outputs with Simultaneous Update
All Outputs Are Single-Ended and Have CMOS Levels
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
N+1
tL
ENC –
ENC +
tD
DA0-DA9, OFA
N–6
N–4
N–2
N–5
N–3
N–1
tD
DB0-DB9, OFB
tC
CLOCKOUTB
CLOCKOUTA
22201 TD04
22301fb
17
LTC2230/LTC2231
U
U
W
U
APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE
input tone to the RMS value of the largest 3rd order
intermodulation product.
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Spurious Free Dynamic Range (SFDR)
Signal-to-Noise Ratio
Input Bandwidth
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Aperture Delay Time
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
2
2
2
2
THD = 20Log (√(V2 + V3 + V4 + . . . Vn )/V1)
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
The time from when a rising ENC+ equals the ENC– voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
CONVERTER OPERATION
As shown in Figure 1, the LTC2230/LTC2231 is a CMOS
pipelined multistep converter. The converter has five
pipelined ADC stages; a sampled analog input will result in
a digitized value five cycles later (see the Timing Diagram
section). For optimal AC performance the analog inputs
should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with
slightly worse harmonic distortion. The encode input is
differential for improved common mode noise immunity.
The LTC2230/LTC2231 has two phases of operation,
determined by the state of the differential ENC+/ENC– input
pins. For brevity, the text will refer to ENC+ greater than
ENC– as ENC high and ENC+ less than ENC– as ENC low.
22301fb
18
LTC2230/LTC2231
U
W
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APPLICATIO S I FOR ATIO
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth
stage residue that is sent to the fifth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2230/
LTC2231 CMOS differential sample-and-hold. The analog
inputs are connected to the sampling capacitors (CSAMPLE)
through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all
other capacitance associated with each input.
During the sample phase when ENC is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to, and track the differential input voltage.
When ENC transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when ENC is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As ENC transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
LTC2230/LTC2231
VDD
AIN+
CSAMPLE
1.6pF
15Ω
CPARASITIC
1pF
VDD
AIN–
CSAMPLE
1.6pF
15Ω
CPARASITIC
1pF
VDD
1.6V
6k
ENC+
ENC–
6k
1.6V
22201 F02
Figure 2. Equivalent Input Circuit
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.6V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.6V. The VCM output pin (Pin
22301fb
19
LTC2230/LTC2231
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60) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2μF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2230/LTC2231 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and input
reactance can influence SFDR. At the falling edge of ENC,
the sample-and-hold circuit will connect the 1.6pF sampling capacitor to the input pin and start the sampling
period. The sampling period ends when ENC rises, holding
the sampled input on the sampling capacitor. Ideally the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2230/LTC2231 being driven by an
RF transformer with a center tapped secondary. The
secondary center tap is DC biased with VCM, setting the
ADC input signal at its optimum DC level. Terminating on
the transformer secondary is desirable, as this provides a
common mode path for charging glitches caused by the
sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source
impedance seen by the ADC does not exceed 100Ω for
each ADC input. A disadvantage of using a transformer is
the loss of low frequency response. Most small RF transformers have poor performance at frequencies below
1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input
frequencies.
Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
sample-and-hold charging glitches and limiting the
wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be
decreased to prevent excessive signal loss.
VCM
2.2μF
0.1μF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
AIN+
0.1μF
AIN+
LTC2230/
LTC2231
12pF
25Ω
AIN–
25Ω
AIN–
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22301 F03
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
VCM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
ANALOG
INPUT
+
2.2μF
+
25Ω
AIN+
3pF
AIN+
12pF
CM
–
–
LTC2230/
LTC2231
AIN–
25Ω
AIN–
AMPLIFIER = LTC6600-20, AD8138, ETC.
22301 F04
3pF
Figure 4. Differential Drive with an Amplifier
VCM
1k
0.1μF
ANALOG
INPUT
2.2μF
1k
25Ω
AIN+
AIN+
12pF
25Ω
LTC2230/
LTC2231
AIN–
AIN–
0.1μF
22301 F05
Figure 5. Single-Ended Drive
22301fb
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The AIN+ and AIN– inputs each have two pins to reduce
package inductance. The two AIN+ and the two AIN– pins
should be shorted together.
For input frequencies above 100MHz the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux
coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.6V. In
Figure 8 the series inductors are impedance matching
elements that maximize the ADC bandwidth.
VCM
2.2μF
0.1μF
ANALOG
INPUT
25Ω
12Ω
AIN+
0.1μF
AIN+
T1
0.1μF
LTC2230/
LTC2231
8pF
25Ω
12Ω
AIN–
AIN–
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22301 F06
Figure 6. Recommended Front End Circuit for Input
Frequencies Between 100MHz and 250MHz
VCM
2.2μF
0.1μF
AIN+
ANALOG
INPUT
25Ω
0.1μF
AIN+
LTC2230/
LTC2231
Reference Operation
Figure 9 shows the LTC2230/LTC2231 reference circuitry
consisting of a 1.6V bandgap reference, a difference
amplifier and switching and control circuit. The internal
voltage reference can be configured for two pin selectable
input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range;
typing the SENSE pin to VCM selects the 1V range.
The 1.6V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.6V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has four pins: two each of REFHA
and REFHB for the high reference and two each of REFLA
and REFLB for the low reference. The multiple output pins
are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9.
LTC2230/LTC2231
T1
0.1μF
AIN–
25Ω
1.6V
AIN–
VCM
4.7nH
0.1μF
T1
0.1μF
1V
AIN+
AIN+
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
1μF
2.2μF
25Ω
LTC2230/
LTC2231
4.7nH
SENSE
REFLB
0.1μF
REFHA
2.2μF
1μF
REFLA
AIN–
Figure 8. Recommended Front End Circuit
for Input Frequencies Above 500MHz
BUFFER
INTERNAL ADC
HIGH REFERENCE
DIFF AMP
AIN–
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
0.5V
RANGE
DETECT
AND
CONTROL
2pF
25Ω
1.6V BANDGAP
REFERENCE
22301 F07
Figure 7. Recommended Front End Circuit for Input
Frequencies Between 250MHz and 500MHz
0.1μF
4Ω
2.2μF
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
ANALOG
INPUT
VCM
22301 F08
0.1μF
REFHB
INTERNAL ADC
LOW REFERENCE
22301 F09
Figure 9. Equivalent Reference Circuit
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Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1μF ceramic capacitor.
1.6V
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at both
inputs as common mode noise. The encode inputs have a
common mode range of 1.1V to 2.5V. Each input may be
driven from ground to VDD for single-ended drive.
VCM
LTC2230/LTC2231
2.2μF
VDD
12k
0.8V
12k
SENSE
LTC2230/
LTC2231
TO INTERNAL
ADC CIRCUITS
1μF
VDD
6k
22301 F10
ENC+
Figure 10. 1.6V Range ADC
Input Range
0.1μF
1:4
CLOCK
INPUT
VDD
50Ω
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 1.7dB. See the Typical Performance Characteristics section.
1.6V BIAS
1.6V BIAS
6k
ENC–
22201 F11
Figure 11. Transformer Driven ENC+/ENC–
Driving the Encode Inputs
Maximum and Minimum Encode Rates
The noise performance of the LTC2230/LTC2231 can
depend on the encode signal quality as much as on the
analog input. The ENC+/ENC– inputs are intended to be
driven differentially, primarily for noise immunity from
common mode noise sources. Each input is biased through
a 6k resistor to a 1.6V bias. The bias resistors set the DC
operating point for transformer coupled drive circuits and
can set the logic threshold for single-ended drive circuits.
The maximum encode rate for the LTC2230/LTC2231 is
170Msps (LTC2230) and 135Msps (LTC2231). For the
ADC to operate properly, the encode signal should have a
50% (±5%) duty cycle. Each half cycle must have at least
2.8ns (LTC2230) or 3.5ns (LTC2231) for the ADC internal
circuitry to have enough settling time for proper operation.
Achieving a precise 50% duty cycle is easy with differential
sinusoidal drive using a transformer or using symmetric
differential logic such as PECL or LVDS.
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequencies) take the following into consideration:
1. Differential drive should be used.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the ENC+ pin to sample the analog
input. The falling edge of ENC+ is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 30% to 70% and the clock
duty cycle stabilizer will maintain a constant 50% internal
22301fb
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duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To use
the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2230/LTC2231 sample rate is
determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operating frequency for the LTC2230/LTC2231 is 1Msps.
ENC+
VTHRESHOLD = 1.6V
1.6V ENC–
LTC2230/
LTC2231
0.1μF
22301 F12a
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
3.3V
MC100LVELT22
3.3V
130Ω
Q0
130Ω
Digital Output Modes
The LTC2230/LTC2231 can operate in several digital output modes: LVDS, CMOS running at full speed, and CMOS
demultiplexed onto two buses, each of which runs at half
speed. In the demultiplexed CMOS modes the two buses
(referred to as bus A and bus B) can either be updated on
alternate clock cycles (interleaved mode) or simultaneously
(simultaneous mode). For details on the clock timing, refer
to the timing diagrams.
The LVDS pin selects which digital output mode the part
uses. This pin has a four-level logic input which should be
connected to GND, 1/3VDD, 2/3VDD or VDD. An external
resistor divider can be used to set the 1/3VDD or 2/3VDD
logic values. Table 2 shows the logic states for the
LVDS pin.
Table 2. LVDS Pin Function
LVDS
Digital Output Mode
GND
Full-Rate CMOS
1/3VDD
Demultiplexed CMOS, Simultaneous Update
2/3VDD
Demultiplexed CMOS, Interleaved Update
VDD
LVDS
ENC+
D0
Digital Output Buffers (CMOS Modes)
ENC–
Q0
83Ω
LTC2230/
LTC2231
83Ω
22301 F12b
Figure 12b. ENC Drive Using a CMOS to PECL Translator
Figure 13a shows an equivalent circuit for a single output
buffer in the CMOS output mode. Each buffer is powered
by OVDD and OGND, isolated from the ADC power and
ground. The additional N-channel transistor in the output
driver allows operation down to low voltages. The internal
resistor in series with the output makes the output appear
DIGITAL OUTPUTS
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
LTC2230/LTC2231
(2V Range)
OF
D9 – D0
(Offset Binary)
D9 – D0
(2’s Complement)
>+1.000000V
+0.998047V
+0.996094V
1
0
0
11 1111 1111
11 1111 1111
11 1111 1110
01 1111 1111
01 1111 1111
01 1111 1110
+0.001953V
0.000000V
–0.001953V
–0.003906V
0
0
0
0
10 0000 0001
10 0000 0000
01 1111 1111
01 1111 1110
00 0000 0001
00 0000 0000
11 1111 1111
11 1111 1110
–0.998047V
–1.000000V
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