LTC2250CUH#TRPBF

LTC2251/LTC2250 10-Bit, 125/105Msps Low Noise 3V ADCs U FEATURES DESCRIPTIO ■ The LTC®2251/LTC2250 are 10-bit 125Msps/105Msps, low noise 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2251/ LTC2250 are perfect for demanding imaging and communications applications with AC performance that includes 61.6dB SNR and 85dB SFDR for signals at the Nyquist frequency. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Sample Rate: 125Msps/105Msps Single 3V Supply (2.85V to 3.4V) Low Power: 395mW/320mW 61.6dB SNR 85dB SFDR No Missing Codes Flexible Input: 1VP-P to 2VP-P Range 640MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family: 125Msps: LTC2251 (10-Bit), LTC2253 (12-Bit) 105Msps: LTC2250 (10-Bit), LTC2252 (12-Bit) 80Msps: LTC2239 (10-Bit), LTC2229 (12-Bit) 65Msps: LTC2238 (10-Bit), LTC2228 (12-Bit) 40Msps: LTC2237 (10-Bit), LTC2227 (12-Bit) 25Msps: LTC2236 (10-Bit), LTC2226 (12-Bit) 32-Pin (5mm × 5mm) QFN Package U APPLICATIO S ■ ■ ■ ■ ■ DC specs include ±0.1LSB INL (typ), ±0.05LSB DNL (typ) and ±0.6LSB INL, ±0.6LSB DNL over temperature. The transition noise is a low 0.08LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.3V logic. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Wireless and Wired Broadband Communication Imaging Systems Ultrasound Spectral Analysis Portable Instrumentation U TYPICAL APPLICATIO LTC2251: SNR vs Input Frequency, –1dB, 2V Range, 125Msps REFL 65 FLEXIBLE REFERENCE + ANALOG INPUT INPUT S/H – 64 10-BIT PIPELINED ADC CORE CORRECTION LOGIC OUTPUT DRIVERS OVDD 63 D9 • • • D0 62 OGND SNR (dBFS) REFH 61 60 59 58 57 CLOCK/DUTY CYCLE CONTROL 56 55 0 22510 TA01 50 100 150 200 250 300 350 22510 G09 INPUT FREQUENCY (MHz) CLK 22510fa 1 LTC2251/LTC2250 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO OVDD = VDD (Notes 1, 2) ORDER PART NUMBER D7 D8 D9 OF MODE SENSE VCM TOP VIEW VDD Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2251C, LTC2250C ............................. 0°C to 70°C LTC2251I, LTC2250I ...........................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C LTC2251CUH LTC2251IUH LTC2250CUH LTC2250IUH 32 31 30 29 28 27 26 25 AIN+ 1 24 D6 AIN– 2 23 D5 REFH 3 22 D4 REFH 4 21 OVDD 33 REFL 5 20 OGND REFL 6 19 D3 VDD 7 18 D2 GND 8 17 D1 QFN PART* MARKING D0 NC NC NC NC OE CLK SHDN 9 10 11 12 13 14 15 16 2251 2250 UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 33) IS GND MUST BE SOLDERED TO PCB Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. U CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS Resolution (No Missing Codes) MIN ● 10 LTC2251 TYP MAX MIN LTC2250 TYP MAX 10 UNITS Bits Integral Linearity Error Differential Analog Input (Note 5) ● –0.6 ±0.1 0.6 –0.6 ±0.1 0.6 LSB Differential Linearity Error Differential Analog Input ● –0.6 ±0.05 0.6 –0.6 ±0.05 0.6 LSB Offset Error (Note 6) ● –12 ±2 12 –12 ±2 12 mV Gain Error External Reference ● –2.5 ±0.5 2.5 –2.5 ±0.5 2.5 %FS Offset Drift ±10 ±10 µV/°C Full-Scale Drift Internal Reference External Reference ±30 ±5 ±30 ±5 ppm/°C ppm/°C Transition Noise SENSE = 1V 0.08 0.08 LSBRMS 22510fa 2 LTC2251/LTC2250 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ –AIN–) 2.85V < VDD < 3.4V (Note 7) ● VIN,CM Analog Input Common Mode Differential Input (Note 7) ● 1 1.9 V IIN Analog Input Leakage Current 0V < AIN+, AIN– < VDD ● –1 1 µA ISENSE SENSE Input Leakage 0V < SENSE < 1V ● –3 3 µA IMODE MODE Pin Leakage ● –3 3 µA tAP Sample-and-Hold Acquisition Delay Time tJITTER Sample-and-Hold Acquisition Delay Time Jitter CMRR MIN MAX UNITS ±0.5V to ±1V 1.5 V 0 0.2 Analog Input Common Mode Rejection Ratio Full Power Bandwidth TYP Figure 8 Test Circuit ns psRMS 80 dB 640 MHz W U DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input 61.6 61.6 dB 30MHz Input 61.6 61.6 dB ● 60 140MHz Input SFDR SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 30MHz Input 70MHz Input IMD Signal-to-Noise Plus Distortion Ratio Intermodulation Distortion 60 69 UNITS 61.5 dB 61.4 61.4 dB 85 85 dB 85 ● 82 69 85 dB 83 dB 140MHz Input 77 77 dB 5MHz Input 85 85 dB 30MHz Input 85 85 dB 70MHz Input ● 75 140MHz Input S/(N+D) 61.5 MIN LTC2250 TYP MAX PARAMETER 70MHz Input MIN LTC2251 TYP MAX SYMBOL 5MHz Input 30MHz Input 70MHz Input 85 85 dB 85 75 85 dB 61.5 61.6 dB 61.5 ● 60 61.4 60 61.6 dB 61.5 dB 140MHz Input 61.2 61.3 dB fIN1 = 28.2MHz, fIN2 = 26.8MHz 80 80 dB 22510fa 3 LTC2251/LTC2250 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V ±25 VCM Output Tempco ppm/°C VCM Line Regulation 2.85V < VDD < 3.4V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS (CLK, OE, SHDN) VIH High Level Input Voltage VDD = 3V ● VIL Low Level Input Voltage VDD = 3V ● IIN Input Current VIN = 0V to VDD ● CIN Input Capacitance (Note 7) 3 pF COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF ISOURCE Output Source Current VOUT = 0V 50 mA ISINK Output Sink Current VOUT = 3V 50 mA VOH High Level Output Voltage IO = –10µA IO = –200µA ● IO = 10µA IO = 1.6mA ● 2 V –10 0.8 V 10 µA LOGIC OUTPUTS OVDD = 3V VOL Low Level Output Voltage 2.7 2.995 2.99 0.005 0.09 V V 0.4 V V OVDD = 2.5V VOH High Level Output Voltage IO = –200µA 2.49 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V OVDD = 1.8V VOH High Level Output Voltage IO = –200µA 1.79 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V 22510fa 4 LTC2251/LTC2250 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) MIN LTC2251 TYP MAX MIN LTC2250 TYP MAX SYMBOL PARAMETER CONDITIONS UNITS VDD Analog Supply Voltage (Note 9) ● 2.85 3 3.4 2.85 3 3.4 V OVDD Output Supply Voltage (Note 9) ● 0.5 3 3.6 0.5 3 3.6 V IVDD Supply Current ● 132 156 107 126 mA PDISS Power Dissipation ● 395 468 320 378 mW PSHDN Shutdown Power SHDN = H, OE = H, No CLK 2 2 mW PNAP Nap Mode Power SHDN = H, OE = L, No CLK 15 15 mW WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN LTC2251 TYP MAX MIN LTC2250 TYP MAX UNITS 105 MHz SYMBOL PARAMETER CONDITIONS fs Sampling Frequency (Note 9) ● 1 tL CLK Low Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 3.8 3 tH CLK High Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 3.8 3 tAP Sample-and-Hold Aperture Delay tD CLK to DATA Delay CL = 5pF (Note 7) ● 2.7 5.4 2.7 5.4 ns Data Access Time After OE↓ CL = 5pF (Note 7) ● 4.3 10 4.3 10 ns BUS Relinquish Time (Note 7) ● 3.3 8.5 3.3 8.5 125 1 4 4 500 500 4.5 3 4.76 4.76 500 500 ns ns 4 4 500 500 4.5 3 4.76 4.76 500 500 ns ns 0 Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 125MHz (LTC2251) or 105MHz (LTC2250), input range = 2VP-P with differential drive, clock duty cycle stabilizer on, unless otherwise noted. 1.4 5 0 1.4 5 ns ns Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 and 11 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 125MHz (LTC2251) or 105MHz (LTC2250), input range = 1VP-P with differential drive. Note 9: Recommended operating conditions. 22510fa 5 LTC2251/LTC2250 U W TYPICAL PERFOR A CE CHARACTERISTICS 1.0 1.0 0 0.8 0.8 –10 0.6 0.6 –20 0.4 0.4 0 –0.2 –0.4 0.2 0 –0.2 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 256 512 CODE 768 –40 –50 –60 –70 –80 –90 –100 –110 0 1024 256 22510 G01 512 CODE 768 –120 1024 0 –10 –20 –20 –20 –30 –30 –30 –60 –70 –80 AMPLITUDE (dB) 0 –10 AMPLITUDE (dB) 0 –50 –40 –50 –60 –70 –80 –70 –80 –90 –100 –100 –110 –110 –110 –120 –120 50 60 –120 0 10 22510 G04 LTC2251: 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range, 125Msps 20 30 40 FREQUENCY (MHz) 60 50 0 70000 10 20 30 40 FREQUENCY (MHz) 50 60 22510 G06 LTC2251: SNR vs Input Frequency, –1dB, 2V Range, 125Msps 65 65528 64 60000 –20 –30 63 50000 COUNT –50 –60 –70 62 SNR (dBFS) –40 40000 30000 –80 61 60 59 58 20000 –90 57 –100 10000 –110 –120 0 22510 G05 LTC2251: Grounded Input Histogram, 125Msps –10 22510 G03 –60 –100 20 30 40 FREQUENCY (MHz) 60 50 –50 –90 10 20 30 40 FREQUENCY (MHz) –40 –90 0 10 LTC2251: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 125Msps –10 –40 0 22510 G02 LTC2251: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 125Msps LTC2251: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 125Msps AMPLITUDE (dB) –30 AMPLITUDE (dB) 0.2 0 AMPLITUDE (dB) LTC2251: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 125Msps LTC2251: Typical DNL, 2V Range, 125Msps DNL ERROR (LSB) INL ERROR (LSB) LTC2251: Typical INL, 2V Range, 125Msps 0 10 20 30 40 FREQUENCY (MHz) 50 60 22510 G07 0 56 0 0 510 511 CODE 55 512 22510 G08 0 50 100 150 200 250 300 350 22510 G09 INPUT FREQUENCY (MHz) 22510fa 6 LTC2251/LTC2250 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2251: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2251: SFDR vs Input Frequency, –1dB, 2V Range, 125Msps 90 95 80 70 SFDR 85 80 75 dBFS 80 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) 90 70 SNR 60 60 50 40 dBc 30 20 70 10 50 65 0 100 150 200 250 300 350 INPUT FREQUENCY (MHz) 55210 G10 50 20 0 –50 40 60 80 100 120 140 160 SAMPLE RATE (Msps) 22510 G11 –40 –30 –10 –20 INPUT LEVEL (dBFS) 0 22510 G12 LTC2251: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB LTC2251: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps 145 100 140 dBFS 90 135 80 70 130 dBc 60 IVDD (mA) SFDR (dBc AND dBFS) 50 40 125 110 105 10 100 95 –40 –20 –10 –30 INPUT LEVEL (dBFS) 0 0 61.8 7 61.6 6 61.4 5 61.2 4 3 1 60.4 0 120 140 22510 G14 60.8 60.6 80 100 60 SAMPLE RATE (Msps) 120 61.0 2 40 60 80 100 40 SAMPLE RATE (Msps) LTC2251: SNR vs SENSE, fIN = 5MHz, –1dB 8 20 20 22510 G13 LTC2251: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 0 1V RANGE 115 20 0 –50 2V RANGE 120 30 SNR (dBFS) 0 IOVDD (mA) SFDR (dBFS) LTC2251: SNR vs Input Level, fIN = 70MHz, 2V Range, 125Msps 140 22510 G15 60.2 0.4 0.5 0.6 0.7 0.8 0.9 SENSE PIN (V) 1 1.1 22510 G31 22510fa 7 LTC2251/LTC2250 U W TYPICAL PERFOR A CE CHARACTERISTICS 1.0 1.0 0 0.8 0.8 –10 0.6 0.6 –20 0.4 0.4 0 –0.2 –0.4 0.2 0 –0.2 –0.4 –40 –50 –60 –70 –80 –90 –0.6 –0.8 –0.8 –1.0 –1.0 0 256 512 CODE 768 –100 –110 0 1024 256 22510 G16 LTC2250: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 105Msps 512 CODE 768 –120 1024 0 0 0 –10 –10 –20 –20 –20 –30 –30 –30 –60 –70 –80 –40 AMPLITUDE (dB) –50 –50 –60 –70 –80 –60 –70 –80 –90 –100 –100 –100 –110 –110 –110 10 20 30 40 FREQUENCY (MHz) –120 50 0 10 22510 G19 LTC2250: 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range, 105Msps 50 –120 0 70000 10 20 30 40 FREQUENCY (MHz) 50 22510 G21 LTC2250: SNR vs Input Frequency, –1dB, 2V Range, 105Msps 65 65528 64 60000 –20 0 22510 G20 LTC2250: Grounded Input Histogram, 105Msps –10 63 –30 50000 COUNT –50 –60 –70 –80 62 SNR (dBFS) –40 40000 30000 61 60 59 58 20000 –90 57 –100 10000 –110 –120 20 30 40 FREQUENCY (MHz) 50 22510 G18 –50 –90 0 20 30 40 FREQUENCY (MHz) –40 –90 –120 10 LTC2250: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 105Msps –10 –40 0 22510 G17 LTC2250: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 105Msps AMPLITUDE (dB) AMPLITUDE (dB) –30 AMPLITUDE (dB) 0.2 –0.6 AMPLITUDE (dB) LTC2250: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 105Msps LTC2250: Typical DNL, 2V Range, 105Msps DNL ERROR (LSB) INL ERROR (LSB) LTC2250: Typical INL, 2V Range, 105Msps 0 10 20 30 40 FREQUENCY (MHz) 50 22510 G22 0 56 0 0 510 511 CODE 55 512 22510 G23 0 50 100 150 200 250 300 350 22510 G24 INPUT FREQUENCY (MHz) 22510fa 8 LTC2251/LTC2250 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2250: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2250: SFDR vs Input Frequency, –1dB, 2V Range, 105Msps 95 90 80 70 SFDR 85 80 75 dBFS 80 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) 90 70 SNR 60 60 50 40 dBc 30 20 70 10 65 50 100 150 200 250 300 350 INPUT FREQUENCY (MHz) 55210 G25 0 20 40 60 80 100 SAMPLE RATE (Msps) 100 0 –50 140 –40 –30 –10 –20 INPUT LEVEL (dBFS) 22510 G26 0 22510 G27 120 dBFS 90 115 80 110 70 120 LTC2250: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB LTC2250: SFDR vs Input Level, fIN = 70MHz, 2V Range, 105Msps 105 dBc IVDD (mA) 60 50 40 2V RANGE 100 1V RANGE 95 90 30 20 85 10 80 0 –50 75 –40 –20 –10 –30 INPUT LEVEL (dBFS) 0 0 20 22510 G28 40 60 80 SAMPLE RATE (Msps) 100 120 22510 G29 LTC2250: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V LTC2250: SNR vs SENSE, fIN = 5MHz, –1dB 7 61.8 6 61.6 61.4 5 SNR (dBFS) 50 SFDR (dBc AND dBFS) 0 IOVDD (mA) SFDR (dBFS) LTC2250: SNR vs Input Level, fIN = 70MHz, 2V Range, 105Msps 4 3 2 61.2 61.0 60.8 60.6 1 60.4 0 0 20 80 60 100 40 SAMPLE RATE (Msps) 120 60.2 0.4 0.5 0.6 0.7 0.8 0.9 SENSE PIN (V) 1 1.1 22510 G32 22510 G30 22510fa 9 LTC2251/LTC2250 U U U PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. NC (Pins 12, 13, 14, 15): Do Not Connect These Pins. AIN- (Pin 2): Negative Differential Analog Input. D0-D9 (Pins 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D9 is the MSB. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pin 8): ADC Power Ground. CLK (Pin 9): Clock Input. The input sample starts on the positive edge. SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 11): Output Enable Pin. Refer to SHDN pin function. OGND (Pin 20): Output Driver Ground. OVDD (Pin 21): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OVDD can be set from 0.5V to 3.6V. OF (Pin 28): Over/Under Flow Output. High when an over or under flow has occurred. MODE (Pin 29): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 30): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 31): 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad) (Pin 33): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground. 22510fa 10 LTC2251/LTC2250 W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE SIXTH PIPELINED ADC STAGE 1.5V REFERENCE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D9 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 0.1µF 22510 F01 REFL OGND CLK MODE SHDN OE 2.2µF 1µF 1µF Figure 1. Functional Block Diagram WU W TI I G DIAGRA tAP ANALOG INPUT N+4 N+2 N N+3 tH N+5 N+1 tL CLK tD D0-D9, OF N–5 N–4 N–3 N–2 N–1 N 22510 TD01 22510fa 11 LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Input Bandwidth Total Harmonic Distortion Aperture Delay Time Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: The time from when CLK reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. 2 2 2 2 THD = 20Log (√(V2 + V3 + V4 + . . . Vn )/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) CONVERTER OPERATION As shown in Figure 1, the LTC2251/LTC2250 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2251/LTC2250 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and 22510fa 12 LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.5V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin (Pin 31) may be used to provide the common mode bias level. SAMPLE/HOLD OPERATION AND INPUT DRIVE LTC2251/LTC2250 VDD Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2251/ LTC2250 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input CSAMPLE 3.5pF 15Ω AIN+ CPARASITIC 1pF VDD AIN– CSAMPLE 3.5pF 15Ω CPARASITIC 1pF VDD CLK 22510 F02 Figure 2. Equivalent Input Circuit 22510fa 13 LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2251/LTC2250 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sample-and-hold circuit will connect the 3.5pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the VCM 2.2µF 0.1µF ANALOG INPUT Figure 3 shows the LTC2251/LTC2250 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low AIN+ 25Ω 0.1µF 25Ω LTC2251/ LTC2250 12pF 25Ω AIN– T1 = MA/COM ETC1-1T 25Ω RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 22510 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits T1 1:1 VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT + AIN+ LTC2251/ LTC2250 + CM – 2.2µF 12pF – 25Ω AIN– 22510 F04 Figure 4. Differential Drive with an Amplifier VCM 1k 0.1µF ANALOG INPUT 1k 2.2µF 25Ω AIN+ LTC2251/ LTC2250 12pF 25Ω AIN– 0.1µF 22510 F05 Figure 5. Single-Ended Drive 22510fa 14 LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth. The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. Reference Operation VCM Figure 9 shows the LTC2251/LTC2250 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. 2.2µF 0.1µF 25Ω 2.2µF 12Ω ANALOG INPUT 25Ω 25Ω 12Ω AIN– 22510 F08 LTC2251/LTC2250 AIN– 1.5V VCM 4Ω 1.5V BANDGAP REFERENCE 2.2µF 1V 22510 F06 TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V VCM SENSE 1µF 2.2µF 0.5V RANGE DETECT AND CONTROL Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz REFH BUFFER INTERNAL ADC HIGH REFERENCE AIN+ ANALOG INPUT 25Ω LTC2251/ LTC2250 0.1µF 2.2µF 0.1µF T1 0.1µF 8.2nH LTC2251/ LTC2250 T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 0.1µF LTC2251/ LTC2250 T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE 8pF 25Ω 0.1µF Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz AIN+ 0.1µF T1 0.1µF AIN+ T1 0.1µF VCM 0.1µF 8.2nH ANALOG INPUT 25Ω 1µF AIN– T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE DIFF AMP REFL 22510 F07 INTERNAL ADC LOW REFERENCE 22510 F09 Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz Figure 9. Equivalent Reference Circuit 22510fa 15 LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source. Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of FERRITE BEAD 0.1µF 1k 0.1µF SINUSOIDAL CLOCK INPUT LTC2251/ LTC2250 CLK 50Ω 1.5V CLEAN SUPPLY 4.7µF 1k NC7SVU04 VCM 22510 F11 2.2µF 12k 0.75V 12k SENSE LTC2251/ LTC2250 Figure 11. Sinusoidal Single-Ended CLK Drive CLEAN SUPPLY 1µF 4.7µF 22510 F10 FERRITE BEAD Figure 10. 1.5V Range ADC 0.1µF Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 0.9dB. CLK 100Ω LTC2251/ LTC2250 22510 F12 IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter Driving the Clock Input The CLK input can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low-jitter squaring circuit before the CLK pin (see Figure 11). The noise performance of the LTC2251/LTC2250 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. ETC1-1T CLK 5pF-30pF LTC2251/ LTC2250 DIFFERENTIAL CLOCK INPUT 22510 F13 0.1µF FERRITE BEAD VCM Figure 13. LVDS or PECL CLK Drive Using a Transformer 22510fa 16 LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact. The transformer shown in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10Ω to 20Ω ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2251/LTC2250 is 125Msps (LTC2251) and 105Msps (LTC2250). The lower limit of the LTC2251/LTC2250 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2251/LTC2250 is 1Msps. Clock Duty Cycle Stabilizer An optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. Using the clock duty cycle stabilizer is recommended for most applications. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (±5%) duty cycle. DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) OF D9 – D0 (Offset Binary) D9 – D0 (2’s Complement) >+1.000000V +0.998047V +0.996094V 1 0 0 11 1111 1111 11 1111 1111 11 1111 1110 01 1111 1111 01 1111 1111 01 1111 1110 +0.001953V 0.000000V –0.001953V –0.003906V 0 0 0 0 10 0000 0001 10 0000 0000 01 1111 1111 01 1111 1110 00 0000 0001 00 0000 0000 11 1111 1111 11 1111 1110 –0.998047V –1.000000V