LTC2253IUH#PBF

LTC2253/LTC2252 12-Bit, 125/105Msps Low Power 3V ADCs U FEATURES DESCRIPTIO ■ The LTC®2253/LTC2252 are 12-bit 125Msps/105Msps, low power 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2253/ LTC2252 are perfect for demanding imaging and communications applications with AC performance that includes 70.1dB SNR and 85dB SFDR for signals at the Nyquist frequency. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Sample Rate: 125Msps/105Msps Single 3V Supply (2.85V to 3.4V) Low Power: 395mW/320mW 70.2dB SNR 88dB SFDR No Missing Codes Flexible Input: 1VP-P to 2VP-P Range 640MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit) 105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit) 80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit) 65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit) 40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit) 25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit) 10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit) 32-Pin (5mm × 5mm) QFN Package DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.32LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.3V logic. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U APPLICATIO S ■ ■ ■ ■ Wireless and Wired Broadband Communication Imaging Systems Ultrasound Spectral Analysis Portable Instrumentation U ■ TYPICAL APPLICATIO REFH REFL LTC2253: SNR vs Input Frequency, –1dB, 2V Range, 125Msps 73 FLEXIBLE REFERENCE 72 OVDD ANALOG INPUT INPUT S/H – 12-BIT PIPELINED ADC CORE CORRECTION LOGIC D11 • • • D0 OUTPUT DRIVERS OGND CLOCK/DUTY CYCLE CONTROL SNR (dBFS) 71 + 70 69 68 67 66 65 0 22532 TA01 50 100 150 200 250 300 350 22532 G09 INPUT FREQUENCY (MHz) CLK 22532fa 1 LTC2253/LTC2252 U W U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER D9 D10 SENSE VCM TOP VIEW VDD Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2253C, LTC2252C ............................. 0°C to 70°C LTC2253I, LTC2252I ...........................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C D11 W OVDD = VDD (Notes 1, 2) OF W W AXI U RATI GS MODE U ABSOLUTE 32 31 30 29 28 27 26 25 AIN+ 1 24 D8 AIN– 2 23 D7 REFH 3 22 D6 REFH 4 21 OVDD 33 REFL 5 LTC2253CUH LTC2253IUH LTC2252CUH LTC2252IUH 20 OGND REFL 6 19 D5 VDD 7 18 D4 GND 8 17 D3 QFN PART* MARKING D2 D1 D0 NC NC OE CLK SHDN 9 10 11 12 13 14 15 16 2253 2252 UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 33) IS GND MUST BE SOLDERED TO PCB Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. U CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS Resolution (No Missing Codes) MIN ● 12 LTC2253 TYP MAX MIN LTC2252 TYP MAX 12 UNITS Bits Integral Linearity Error Differential Analog Input (Note 5) ● –1.5 ±0.3 1.5 –1.5 ±0.3 1.5 LSB Differential Linearity Error Differential Analog Input ● –0.7 ±0.15 0.7 –0.7 ±0.15 0.7 LSB Offset Error (Note 6) ● –12 ±2 12 –12 ±2 12 mV Gain Error External Reference ● –2.5 ±0.5 2.5 –2.5 ±0.5 2.5 %FS Offset Drift ±10 ±10 µV/°C Full-Scale Drift Internal Reference External Reference ±30 ±5 ±30 ±5 ppm/°C ppm/°C Transition Noise SENSE = 1V 0.32 0.32 LSBRMS 22532fa 2 LTC2253/LTC2252 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS +– –) MIN TYP MAX UNITS ±0.5V to ±1V VIN Analog Input Range (AIN 2.85V < VDD < 3.4V (Note 7) ● VIN,CM Analog Input Common Mode Differential Input (Note 7) ● 1 IIN Analog Input Leakage Current 0V < AIN+, AIN– < VDD ● ISENSE SENSE Input Leakage 0V < SENSE < 1V IMODE MODE Pin Leakage tAP Sample-and-Hold Acquisition Delay Time tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2 psRMS CMRR Analog Input Common Mode Rejection Ratio 80 dB 640 MHz AIN Full Power Bandwidth 1.5 V 1.9 V –1 1 µA ● –3 3 µA ● –3 3 µA 0 Figure 8 Test Circuit ns W U DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input MIN dB 69.6 69.8 dB 5MHz Input 88 88 dB 30MHz Input 85 88 dB 84 dB 68 ● 72 IMD 82 68.5 71 78 79 dB 5MHz Input 90 90 dB 30MHz Input 90 90 dB ● 77 5MHz Input 30MHz Input 70MHz Input Intermodulation Distortion 70 140MHz Input 140MHz Input Signal-to-Noise Plus Distortion Ratio dB dB 70MHz Input S/(N+D) UNITS 70.2 70MHz Input Spurious Free Dynamic Range 4th Harmonic or Higher 70.2 70.1 ● 140MHz Input SFDR LTC2252 TYP MAX 70.1 70MHz Input SFDR MIN 70.2 30MHz Input Spurious Free Dynamic Range 2nd or 3rd Harmonic LTC2253 TYP MAX 90 90 dB 90 78 90 dB 69.8 70.1 dB 69.7 ● 67 69.6 67.5 70.1 dB 70 dB 140MHz Input 68.5 68.7 dB fIN1 = 28.2MHz, fIN2 = 26.8MHz 85 85 dB 22532fa 3 LTC2253/LTC2252 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V ±25 VCM Output Tempco ppm/°C VCM Line Regulation 2.85V < VDD < 3.4V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS (CLK, OE, SHDN) VIH High Level Input Voltage VDD = 3V ● VIL Low Level Input Voltage VDD = 3V ● IIN Input Current VIN = 0V to VDD ● CIN Input Capacitance (Note 7) 3 pF COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF ISOURCE Output Source Current VOUT = 0V 50 mA ISINK Output Sink Current VOUT = 3V 50 mA VOH High Level Output Voltage IO = –10µA IO = –200µA ● IO = 10µA IO = 1.6mA ● 2 V –10 0.8 V 10 µA LOGIC OUTPUTS OVDD = 3V VOL Low Level Output Voltage 2.7 2.995 2.99 0.005 0.09 V V 0.4 V V OVDD = 2.5V VOH High Level Output Voltage IO = –200µA 2.49 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V OVDD = 1.8V VOH High Level Output Voltage IO = –200µA 1.79 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V 22532fa 4 LTC2253/LTC2252 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) MIN LTC2253 TYP MAX MIN LTC2252 TYP MAX SYMBOL PARAMETER CONDITIONS UNITS VDD Analog Supply Voltage (Note 9) ● 2.85 3 3.4 2.85 3 3.4 V OVDD Output Supply Voltage (Note 9) ● 0.5 3 3.6 0.5 3 3.6 V IVDD Supply Current ● 132 156 107 126 mA PDISS Power Dissipation ● 395 468 320 378 mW PSHDN Shutdown Power SHDN = H, OE = H, No CLK 2 2 mW PNAP Nap Mode Power SHDN = H, OE = L, No CLK 15 15 mW WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN LTC2253 TYP MAX MIN LTC2252 TYP MAX UNITS 105 MHz 500 500 ns ns 500 500 ns ns SYMBOL PARAMETER CONDITIONS fs Sampling Frequency (Note 9) ● 1 125 1 tL CLK Low Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 3.8 3 4 4 500 500 4.5 3 4.76 4.76 tH CLK High Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 3.8 3 4 4 500 500 4.5 3 4.76 4.76 tAP Sample-and-Hold Aperture Delay tD CLK to DATA Delay CL = 5pF (Note 7) ● Data Access Time After OE↓ CL = 5pF (Note 7) BUS Relinquish Time (Note 7) 0 Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 125MHz (LTC2253) or 105MHz (LTC2252), input range = 2VP-P with differential drive, clock duty cycle stabilizer on, unless otherwise noted. 1.4 0 2.7 5.4 ● 4.3 ● 3.3 5 1.4 ns 2.7 5.4 ns 10 4.3 10 ns 8.5 3.3 8.5 ns 5 Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 125MHz (LTC2253) or 105MHz (LTC2252), input range = 1VP-P with differential drive. Note 9: Recommend operating conditions. 22532fa 5 LTC2253/LTC2252 U W TYPICAL PERFOR A CE CHARACTERISTICS 1.0 1.0 0 0.8 0.8 –10 0.6 0.6 0.4 0.4 0 –0.2 –0.4 –30 0.2 0 –0.2 –0.4 –40 –50 –60 –70 –80 –90 –0.6 –0.8 –0.8 –1.0 –1.0 0 1024 2048 CODE 3072 4096 –100 –110 0 1024 22532 G01 2048 CODE 3072 –120 4096 0 –10 –20 –20 –20 –30 –30 –30 –60 –70 –80 AMPLITUDE (dB) 0 –10 AMPLITUDE (dB) 0 –50 –40 –50 –60 –70 –80 –70 –80 –90 –100 –100 –110 –110 –110 –120 –120 50 60 0 10 22532 G04 LTC2253: 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range, 125Msps 20 30 40 FREQUENCY (MHz) 60 50 –30 –60 –70 40000 30000 20000 –90 0 10 20 30 40 FREQUENCY (MHz) 50 60 22532 G07 0 70 69 68 67 10000 –110 60 22532 G06 71 –80 –100 50 72 SNR (dBFS) COUNT –50 20 30 40 FREQUENCY (MHz) 73 50000 –40 10 LTC2253: SNR vs Input Frequency, –1dB, 2V Range, 125Msps 58717 60000 –20 0 22532 G05 70000 –10 –120 –120 LTC2253: Grounded Input Histogram, 125Msps 0 22532 G03 –60 –100 20 30 40 FREQUENCY (MHz) 60 50 –50 –90 10 20 30 40 FREQUENCY (MHz) –40 –90 0 10 LTC2253: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 125Msps –10 –40 0 22532 G02 LTC2253: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 125Msps LTC2253: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 125Msps AMPLITUDE (dB) –20 AMPLITUDE (dB) 0.2 –0.6 AMPLITUDE (dB) LTC2253: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 125Msps LTC2253: Typical DNL, 2V Range, 125Msps DNL ERROR (LSB) INL ERROR (LSB) LTC2253: Typical INL, 2V Range, 125Msps 4249 2562 0 2044 2045 2046 CODE 2047 66 0 2048 22532 G08 65 0 50 100 150 200 250 300 350 22532 G09 INPUT FREQUENCY (MHz) 22532fa 6 LTC2253/LTC2252 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2253: SFDR vs Input Frequency, –1dB, 2V Range, 125Msps LTC2253: SNR vs Input Level, fIN = 70MHz, 2V Range, 125Msps LTC2253: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 95 90 80 SFDR 70 80 75 80 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) 85 SNR 70 60 dBFS 60 50 dBc 40 30 20 70 10 65 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 20 40 60 80 100 120 140 160 SAMPLE RATE (Msps) 22532 G10 0 –60 LTC2253: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps –20 –40 –30 INPUT LEVEL (dBFS) –10 0 22532 G13 LTC2253: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 145 110 100 140 dBFS 90 135 80 130 70 IVDD (mA) dBc 60 50 40 2V RANGE 125 1V RANGE 120 115 110 30 20 105 10 100 0 –60 95 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 0 20 60 80 100 40 SAMPLE RATE (Msps) LTC2253: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 72 7 71 6 70 5 69 4 3 68 67 2 66 1 65 20 60 80 100 40 SAMPLE RATE (Msps) 120 140 LTC2253: SNR vs SENSE, fIN = 5MHz, –1dB 8 0 120 22532 G15 22532 G14 0 –50 22532 G11 SNR (dBFS) 50 SFDR (dBc AND dBFS) 0 IOVDD (mA) SFDR (dBFS) 90 140 22532 G16 64 0.4 0.5 0.6 0.7 0.8 0.9 SENSE PIN (V) 1.0 1.1 22532 G32 22532fa 7 LTC2253/LTC2252 U W TYPICAL PERFOR A CE CHARACTERISTICS 1.0 1.0 0 0.8 0.8 –10 0.6 0.6 –20 0.4 0.4 0 –0.2 –0.4 0.2 0 –0.2 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 1024 2048 CODE 3072 –30 AMPLITUDE (dB) 0.2 0 –50 –60 –70 –80 –90 –110 1024 22532 G17 2048 CODE 3072 –120 4096 0 –10 –20 –20 –20 –30 –30 –30 –60 –70 –80 AMPLITUDE (dB) 0 –10 AMPLITUDE (dB) 0 –50 –40 –50 –60 –70 –80 –60 –70 –80 –90 –100 –100 –100 –110 –110 –110 –120 –120 30 40 20 FREQUENCY (MHz) 50 0 10 22532 G20 30 40 20 FREQUENCY (MHz) –120 50 30 40 20 FREQUENCY (MHz) 50 22532 G22 73 56911 72 50000 71 –30 COUNT –50 –60 –70 SNR (dBFS) 40000 –40 30000 20000 –80 70 69 68 67 –90 10000 –100 –110 –120 10 LTC2252: SNR vs Input Frequency, –1dB, 2V Range, 105Msps 60000 –10 –20 0 22532 G21 LTC2252: Grounded Input Histogram, 105Msps 0 50 22532 G19 –50 –90 10 30 40 20 FREQUENCY (MHz) –40 –90 0 10 LTC2252: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 105Msps –10 –40 0 22532 G18 LTC2252: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 105Msps LTC2252: 8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range, 105Msps AMPLITUDE (dB) –40 –100 0 4096 LTC2252: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 105Msps AMPLITUDE (dB) LTC2252: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 105Msps LTC2252: Typical DNL, 2V Range, 105Msps DNL ERROR (LSB) INL ERROR (LSB) LTC2252: Typical INL, 2V Range, 105Msps 0 0 10 30 40 20 FREQUENCY (MHz) 50 22532 G23 66 0 2044 6704 1913 2045 2046 CODE 2047 0 2048 22532 G24 65 0 50 100 150 200 250 300 350 22532 G25 INPUT FREQUENCY (MHz) 22532fa 8 LTC2253/LTC2252 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2252: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2252: SFDR vs Input Frequency, –1dB, 2V Range, 105Msps 95 LTC2252: SNR vs Input Level, fIN = 70MHz, 2V Range, 105Msps 80 90 SFDR 70 80 75 80 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) 85 SNR 70 60 dBFS 60 50 dBc 40 30 20 70 10 50 65 100 150 200 250 300 INPUT FREQUENCY (MHz) 0 350 20 40 60 80 100 SAMPLE RATE (Msps) 120 0 –60 140 –20 –40 –30 INPUT LEVEL (dBFS) –50 LTC2252: SFDR vs Input Level, fIN = 70MHz, 2V Range, 105Msps –10 0 22532 G28 22532 G27 22532 G26 LTC2252: IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 110 120 100 115 dBFS 90 110 80 105 70 IVDD (mA) dBc 60 50 40 2V RANGE 100 95 1V RANGE 90 30 85 20 80 10 0 –60 75 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 0 20 80 40 60 SAMPLE RATE (Msps) 22532 G29 100 120 22532 G30 LTC2252: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V LTC2252: SNR vs SENSE, fIN = 5MHz, –1dB 7 72 6 71 70 5 SNR (dBFS) 50 SFDR (dBc AND dBFS) 0 IOVDD (mA) SFDR (dBFS) 90 4 3 69 68 67 2 66 1 65 0 0 20 80 120 60 100 40 22532 G31 SAMPLE RATE (Msps) 64 0.4 0.5 0.6 0.7 0.8 0.9 SENSE PIN (V) 1.0 1.1 22532 G33 22532fa 9 LTC2253/LTC2252 U U U PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. NC (Pins 12, 13): Do Not Connect These Pins. AIN- (Pin 2): Negative Differential Analog Input. D0 – D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D11 is the MSB. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pin 8): ADC Power Ground. CLK (Pin 9): Clock Input. The input sample starts on the positive edge. SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 11): Output Enable Pin. Refer to SHDN pin function. OGND (Pin 20): Output Driver Ground. OVDD (Pin 21): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. OVDD can be set to 0.5V to 3.6V. OF (Pin 28): Over/Under Flow Output. High when an over or under flow has occurred. MODE (Pin 29): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 30): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 31): 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad) (Pin 33): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground. 22532fa 10 LTC2253/LTC2252 W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE SIXTH PIPELINED ADC STAGE 1.5V REFERENCE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D11 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 0.1µF 22532 F01 REFL OGND M0DE CLK SHDN OE 2.2µF 1µF 1µF Figure 1. Functional Block Diagram WU W TI I G DIAGRA Timing Diagram tAP ANALOG INPUT N+4 N+2 N N+3 tH N+5 N+1 tL CLK tD D0-D11, OF N–5 N–4 N–3 N–2 N–1 N 22532 TD01 22532fa 11 LTC2253/LTC2252 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Input Bandwidth Total Harmonic Distortion Aperture Delay Time Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: The time from when CLK reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. 2 2 2 2 THD = 20Log (√(V2 + V3 + V4 + . . . Vn )/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) CONVERTER OPERATION As shown in Figure 1, the LTC2253/LTC2252 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2253/LTC2252 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and 22532fa 12 LTC2253/LTC2252 U W U U APPLICATIO S I FOR ATIO the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.5V or VCM. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin (Pin 31) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer LTC2253/LTC2252 VDD Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2253/ LTC2252 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input CSAMPLE 3.5pF 15Ω AIN+ CPARASITIC 1pF VDD AIN– CSAMPLE 3.5pF 15Ω CPARASITIC 1pF VDD CLK 22532 F02 Figure 2. Equivalent Input Circuit 22532fa 13 LTC2253/LTC2252 U W U U APPLICATIO S I FOR ATIO to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. Input Drive Impedance Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. As with all high performance, high speed ADCs, the dynamic performance of the LTC2253/LTC2252 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of CLK, the sample-and-hold circuit will connect the 3.5pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the VCM 2.2µF 0.1µF ANALOG INPUT Figure 3 shows the LTC2253/LTC2252 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low AIN+ 25Ω 25Ω 0.1µF LTC2253/ LTC2252 12pF 25Ω AIN– T1 = MA/COM ETC1-1T 25Ω RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 22532 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits T1 1:1 VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT + AIN+ + CM – 2.2µF LTC2253/ LTC2252 12pF – 25Ω AIN– 22532 F04 Figure 4. Differential Drive with an Amplifier VCM 1k 0.1µF ANALOG INPUT 1k 2.2µF 25Ω AIN+ LTC2253/ LTC2252 12pF 25Ω AIN– 0.1µF 22532 F05 Figure 5. Single-Ended Drive 22532fa 14 LTC2253/LTC2252 U W U U APPLICATIO S I FOR ATIO sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth. The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. Reference Operation VCM Figure 9 shows the LTC2253/LTC2252 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. VCM 0.1µF 12Ω 25Ω 0.1µF 25Ω 25Ω LTC2253/ LTC2252 VCM 4Ω 1.5V BANDGAP REFERENCE 2.2µF 1V 0.5V 22532 F06 TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V VCM AIN+ 0.1µF RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE 1µF REFH 2.2µF 25Ω 22532 F08 LTC2253/LTC2252 AIN– Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz ANALOG INPUT 8.2nH – 12Ω 0.1µF LTC2253/ LTC2252 AIN T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE 1.5V T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 0.1µF T1 0.1µF 8pF 25Ω AIN+ AIN+ 0.1µF T1 8.2nH ANALOG INPUT Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz 2.2µF ANALOG INPUT 2.2µF 0.1µF LTC2253/ LTC2252 2.2µF 0.1µF DIFF AMP T1 0.1µF 1µF 25Ω T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE REFL AIN– 22532 F07 INTERNAL ADC LOW REFERENCE 22532 F09 Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz Figure 9. Equivalent Reference Circuit 22532fa 15 LTC2253/LTC2252 U W U U APPLICATIO S I FOR ATIO The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source. Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of CLEAN SUPPLY 4.7µF FERRITE BEAD 0.1µF 1k 0.1µF SINUSOIDAL CLOCK INPUT NC7SVU04 1k 50Ω 1.5V LTC2253/ LTC2252 CLK VCM 22532 F11 2.2µF 12k 0.75V 12k SENSE LTC2253/ LTC2252 Figure 11. Sinusoidal Single-Ended CLK Drive 1µF CLEAN SUPPLY 4.7µF 22532 F10 FERRITE BEAD Figure 10. 1.5V Range ADC Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 4.2dB. 0.1µF CLK 100Ω LTC2253/ LTC2252 22532 F12 IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter Driving the Clock Input The CLK input can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low jitter squaring circuit before the CLK pin (Figure 11). The noise performance of the LTC2253/LTC2252 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. ETC1-1T CLK 5pF-30pF LTC2253/ LTC2252 DIFFERENTIAL CLOCK INPUT 22532 F13 0.1µF FERRITE BEAD VCM Figure 13. LVDS or PECL CLK Drive Using a Transformer 22532fa 16 LTC2253/LTC2252 U W U U APPLICATIO S I FOR ATIO a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact. The transformer in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10Ω to 20Ω ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2253/LTC2252 is 125Msps (LTC2253) and 105Msps (LTC2252). The lower limit of the LTC2253/LTC2252 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2253/LTC2252 is 1Msps. Clock Duty Cycle Stabilizer An optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. Using the clock duty cycle stabilizer is recommended for most applications. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (±5%) duty cycle. DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits and the overflow bit. Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) OF D11 – D0 (Offset Binary) D11 – D0 (2’s Complement) >+1.000000V +0.999512V +0.999024V 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 0111 1111 1111 0111 1111 1110 +0.000488V 0.000000V –0.000488V –0.000976V 0 0 0 0 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 –0.999512V –1.000000V