LTC2313HTS8-12#TRMPBF

LTC2313-12 12-Bit, 2.5Msps Serial Sampling ADC in TSOT DESCRIPTION FEATURES 2.5Msps Throughput Rate nn No Cycle Latency nn Guaranteed 12-Bit No Missing Codes nn Single 3V or 5V Supply nn Low Noise: 73dB SNR nn Low Power: 14mW at 2.5Msps and 3V Supply nn Low Drift (20ppm/°C Maximum) 2.048V or 4.096V Internal Reference nn Sleep Mode with < 1µA Typical Supply Current nn Nap Mode with Quick Wake-Up < 1 Conversion nn Separate 1.8V to 5V Digital I/O Supply nn High Speed SPI-Compatible Serial I/O nn Guaranteed Operation from –40°C to 125°C nn 8-Lead TSOT-23 Package nn APPLICATIONS Communication Systems High Speed Data Acquisition nn Handheld Terminal Interface nn Medical Imaging nn Uninterrupted Power Supplies nn Battery Operated Systems nn Automotive nn nn The LTC®2313-12 is a 12-bit, 2.5Msps, serial sampling A/D converter that draws only 5mA from a single 3V or 5V supply. The LTC2313-12 contains an integrated low drift reference and reference buffer providing a low cost, high performance (20ppm/°C maximum) and space saving solution. The LTC2313-12 achieves outstanding AC performance of 72.6dB SINAD and –84dB THD while sampling at 2.5Msps. The extremely high sample rate-topower ratio makes the LTC2313-12 ideal for compact, low power, high speed systems. The supply current decreases at lower sampling rates as the device automatically enters nap mode after conversions. The LTC2313-12 has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3V and 5V logic. The fast 2.5Msps throughput with no cycle latency makes the LTC2313-12 ideally suited for a wide variety of high speed applications. Complete 14-/12-Bit Pin-Compatible SAR ADC Family 500ksps 2.5Msps 4.5Msps 5Msps 14-Bit LTC2312-14 LTC2313-14 LTC2314-14 12-Bit LTC2312-12 LTC2313-12 LTC2315-12 Power 3V/5V 9mW/15mW 14mW/25mW 18mW/31mW 19mW/32mW L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 5V Supply, Internal Reference, 2.5Msps, 12-Bit Sampling ADC 2.2µF 0 LTC2313-12 VDD CONV –40 2.2µF REF GND ANALOG INPUT 0V TO 4.096V AIN VDD = 5V SNR = 73dBFS SINAD = 72.6dBFS THD = –84dB SFDR = 87dB –20 SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS SCK SDO OVDD 2.2µF DIGITAL OUTPUT SUPPLY 1.8V TO 5V AMPLITUDE (dBFS) 5V 16k Point FFT, fS = 2.5Msps, fIN = 497kHz –60 –80 –100 –120 –140 231312 TA01a –160 0 250 500 750 INPUT FREQUENCY (kHz) 1000 231312 TA01b 231312fb For more information www.linear.com/LTC2313-12 1 LTC2313-12 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) Supply Voltage (VDD, OVDD)........................................6V Reference (REF) and Analog Input (AIN) Voltage (Note 3).......................................(–0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 3).... (–0.3V) to (OVDD + 0.3V) Digital Output Voltage.............. (–0.3V) to (OVDD + 0.3V) Power Dissipation................................................100mW Operating Temperature Range LTC2313C................................................. 0°C to 70°C LTC2313I..............................................–40°C to 85°C LTC2313H........................................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature Range (Soldering, 10 sec)......... 300°C TOP VIEW VDD REF GND AIN 1 2 3 4 8 7 6 5 CONV SCK SDO OVDD TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 195°C/W ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2313CTS8-12#TRMPBF LTC2313CTS8-12#TRPBF LTFZJ 8-Lead Plastic TSOT-23 0°C to 70°C LTC2313ITS8-12#TRMPBF LTC2313ITS8-12#TRPBF LTFZJ 8-Lead Plastic TSOT-23 LTC2313HTS8-12#TRMPBF LTC2313HTS8-12#TRPBF LTFZJ 8-Lead Plastic TSOT-23 TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2 –40˚C to 85˚C –40˚C to 125˚C 231312fb For more information www.linear.com/LTC2313-12 LTC2313-12 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VAIN Absolute Input Range VIN Input Voltage Range IIN Analog Input DC Leakage Current CIN Analog Input Capacitance CONDITIONS (Note 11) MIN TYP MAX UNITS l –0.05 VDD + 0.05 V l 0 VREF V l –1 1 µA Sample Mode Hold Mode 13 3 pF pF CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS Resolution No Missing Codes MIN l 12 l 12 TYP MAX UNITS Bits Bits Transition Noise (Note 6) 0.33 LSBRMS INL Integral Linearity Error VDD = 5V (Note 5) VDD = 3V (Note 5) l l –1.25 –1.5 ±0.3 ±0.4 1.25 1.5 LSB LSB DNL Differential Linearity Error VDD = 5V VDD = 3V l l –0.99 –0.99 ±0.2 ±0.25 0.99 0.99 LSB LSB Offset Error VDD = 5V VDD = 3V l l –3.5 –5 ±0.2 ±0.5 3.5 5 LSB LSB Full-Scale Error VDD = 5V VDD = 3V l l –7 –10 ±1 ±1.5 7 10 LSB LSB Total Unadjusted Error VDD = 5V VDD = 3V l l –8 –11 ±1.5 ±2 8 11 LSB LSB DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP SINAD Signal-to-(Noise + Distortion) Ratio fIN = 497kHz, VDD = 5V fIN = 497kHz, VDD = 3V SNR Signal-to-Noise Ratio THD l l 70 67.5 72.6 70.3 dB dB fIN = 497kHz, VDD = 5V fIN = 497kHz, VDD = 3V l l 70.5 68 73 70.6 dB dB Total Harmonic Distortion First 5 Harmonics fIN = 497kHz, VDD = 5V fIN = 497kHz, VDD = 3V l l SFDR Spurious Free Dynamic Range fIN = 497kHz, VDD = 5V fIN = 497kHz, VDD = 3V l l IMD Intermodulation Distortion 2nd Order Terms 3rd Order Terms fIN1 = 255kHz, fIN2 = 285kHz, AIN1, AIN2 = –7dBFS Full Power Bandwidth At 3dB At 0.1dB –3dB Input Linear Bandwidth SINAD ≥ 68dB –84 –84 78 77 MAX –76 –76 UNITS dB dB 87 87 dB dB –80.4 –91.8 dBc dBc 130 20 MHz MHz 5 MHz tAP Aperture Delay 1 ns tJITTER Aperture Jitter 10 psRMS 231312fb For more information www.linear.com/LTC2313-12 3 LTC2313-12 REFERENCE INPUT/OUTPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VREF CONDITIONS VREF Output Voltage 2.7V ≤ VDD ≤ 3.6V 4.75 ≤ VDD ≤ 5.25V VREF Temperature Coefficient l l MIN TYP MAX UNITS 2.040 4.080 2.048 4.096 2.056 4.112 V V 7 20 l ppm/°C VREF Output Resistance Normal Operation, ILOAD = 0mA to 5mA Overdrive Condition (VREFIN ≥ VREFOUT + 50mV) 1 52 Ω kΩ VREF Line Regulation 2.7V ≤ VDD ≤ 3.6V 4.75 ≤ VDD ≤ 5.25V 0.4 0.2 mV/V mV/V 4.15 V VREF 2.048V/ 4.096V Supply Threshold VREF 2.048V/ 4.096V Supply Threshold Hysteresis VREF Input Voltage Range (External Reference Input) 150 2.7V ≤ VDD ≤ 3.6V 4.75 ≤ VDD ≤ 5.25V l l VREF + 50mV VREF + 50mV mV V V VDD 4.3 DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage l VIL Low Level Input Voltage l IIN Digital Input Current l –10 OVDD–0.2 CIN Digital Input Capacitance High Level Output Voltage IO = –500µA (Source) l MAX UNITS 0.8 • OVDD VIN = 0V to OVDD VOH TYP V 0.2 • OVDD V 10 μA 5 VOL Low Level Output Voltage IO = 500µA (Sink) l IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD, CONV = High l COZ Hi-Z Output Capacitance CONV = High ISOURCE Output Source Current ISINK Output Sink Current pF V –10 0.2 V 10 µA 4 pF VOUT = 0V, OVDD = 1.8V –20 mA VOUT = OVDD = 1.8V 20 mA POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VDD Supply Voltage 3V Operational Range 5V Operational Range CONDITIONS MIN TYP MAX UNITS l l 2.7 4.75 3 5 3.6 5.25 V V l 1.71 OVDD Digital Output Supply Voltage ITOTAL = IVDD + IOVDD Supply Current, Static Mode Operational Mode Nap Mode Sleep Mode CONV = 0V, SCK = 0V l l PD Power Dissipation, Static Mode Operational Mode Nap Mode Sleep Mode CONV = 0V, SCK = 0V l l 4 l l 5.25 V 3.4 5 2 0.2 4.4 6 mA mA mA µA 17 25 10 1 22 30 5 25 mW mW mW µW 231312fb For more information www.linear.com/LTC2313-12 LTC2313-12 ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS fSAMPLE(MAX) Maximum Sampling Frequency fSCK Shift Clock Frequency tSCK Shift Clock Period MIN TYP MAX UNITS (Notes 7, 8) l 2.5 MHz (Notes 7, 8) l 90 MHz l tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV 11.1 ns 400 l ns tCONV Conversion Time l 247 ns tACQ Acquisition Time l 153 ns t1 Minimum CONV Pulse Width (Note 7) Valid for Nap and Sleep Mode Only l 10 ns t2 SCK↑ Setup Time After CONV↓ (Note 7) l 10 t3 SDO Enable Time After CONV↓ (Notes 7, 8) l 10 ns t4 SDO Data Valid Access Time after SCK↓ (Notes 7, 8, 9) l 9.1 ns ns t5 SCK Low Time l 4 ns t6 SCK High Time l 4 ns t7 SDO Data Valid Hold Time After SCK↓ (Notes 7, 8, 9) l 1 ns t8 SDO into Hi-Z State Time After CONV↑ (Notes 7, 8, 10) l 3 t9 CONV↑ Quiet Time After 12th SCK↓ (Note 7) l 15 tWAKE_NAP Power-Up Time from Nap Mode See Nap Mode Section 50 ns tWAKE_SLEEP Power-Up Time from Sleep Mode See Sleep Mode Section 1.1 ms Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to ground. Note 3. When these pin voltages are taken below ground or above VDD (AIN, REF) or OVDD (SCK, CONV, SDO) they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above VDD or OVDD without latch-up. Note 4. VDD = 5V, OVDD = 2.5V, fSMPL = 2.5MHz, fSCK = 90MHz, AIN = –1dBFS and internal reference unless otherwise noted. Note 5. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 10 ns ns Note 6. Typical RMS noise at code transitions. Note 7. Parameter tested and guaranteed at OVDD = 2.5V. All input signals are specified with tr = tf = 1ns (10% to 90% of OVDD) and timed from a voltage level of OVDD/2. Note 8. All timing specifications given are with a 10pF capacitance load. Load capacitances greater than this will require a digital buffer. Note 9. The time required for the output to cross the VOH or VOL voltage. Note 10. Guaranteed by design, not subject to test. Note 11. Recommended operating conditions. 231312fb For more information www.linear.com/LTC2313-12 5 LTC2313-12 TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. 0.75 0.75 0.50 0.50 0.25 0.25 0.0 –0.25 –0.75 –0.75 16k Point FFT, fS = 2.5Msps fIN = 497kHz –60 –80 –100 –120 250 500 750 INPUT FREQUENCY (kHz) VDD = 5V 71 VDD = 3V 70 231312 G04 THD 73 SNR, SINAD (dBFS) –85 74 2ND –90 3RD –95 SNR SINAD 0 250 500 750 1000 INPUT FREQUENCY (kHz) 1250 231312 G07 THD –85 2ND –90 3RD –95 –100 0 250 500 750 1000 INPUT FREQUENCY (kHz) –105 1250 231312 G05 VDD = 5V VDD = 3V 69 –55 –35 –15 –75 SNR 72 SNR SINAD 5 25 45 65 85 105 125 TEMPERATURE (°C) 231312 G08 0 250 500 750 1000 INPUT FREQUENCY (kHz) 1250 231312 G06 SNR, SINAD vs Temperature, fIN = 497kHz 70 –100 231312 G03 RIN/CIN = 50Ω/47pF fS = 2.5Msps –80 VDD = 5V SNR SINAD 71 2049 –75 72 68 1000 2048 THD, Harmonics vs Input Frequency (100kHz to 1.2MHz) THD, Harmonics vs Temperature, fIN = 497kHz VDD = 3V –80 THD, HARMONICS (dB) 0 2047 2046 CODE 69 RIN/CIN = 50Ω/47pF fS = 2.5Msps –80 VDD = 3V THD, HARMONICS (dB) 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 231312 G02 SINAD –75 6 0 73 THD, Harmonics vs Input Frequency (100kHz to 1.2MHz) –105 4000 74 –140 –160 8000 THD, HARMONICS (dB) –40 σ = 0.33 12000 SNR, SINAD vs Input Frequency (100kHz to 1.2MHz) VDD = 5V SNR = 73dBFS SINAD = 72.6dBFS THD = –84dB SFDR = 87dB –20 AMPLITUDE (dBFS) –1.00 SNR, SINAD (dBFS) 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 231312 G01 DC Histogram Near Mid-Scale (Code 2048) –0.25 –0.50 0 16000 0.00 –0.50 –1.00 Differential Nonlinearity vs Output Code COUNTS 1.00 DNL (LSB) INL (LSB) 1.00 Integral Nonlinearity vs Output Code TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 2.5Msps, THD –85 2ND –90 3RD –95 –100 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 231312 G09 231312fb For more information www.linear.com/LTC2313-12 LTC2313-12 TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. THD, Harmonics vs Temperature, fIN = 497kHz SNR, SINAD vs Reference Voltage fIN = 497kHz 400 SNR THD 2ND –90 –95 –100 3RD 72 SINAD VDD = 3.6V 71 –105 –110 –55 –35 –15 70 5 25 45 65 85 105 125 TEMPERATURE (°C) 231312 G10 SINAD VDD = 5V SNR Full-Scale Error vs Temperature 2 OPERATION NOT ALLOWED 2.5 3 3.5 4 REFERENCE VOLTAGE (V) VDD = 3.6V OPERATION NOT ALLOWED 250 200 100 4.5 2 231312 G11 Offset Error vs Temperature 2.5 3 3.5 4 REFERENCE VOLTAGE (V) 4.5 231312 G12 Supply Current vs Temperature 5.50 3 5.25 1 0 –1 –2 0.5 SUPPLY CURRENT (mA) OFFSET ERROR (LSB) 2 0 –0.5 VDD = 5V 5.00 4.75 VDD = 3V 4.50 4.25 –3 –4 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 231312 G13 –1 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 231312 G14 Shutdown Current vs Temperature 1 IVDD + IOVDD 0.5 0.25 VDD = 3V 4 ITOT IVDD 3 2 1 VDD = 5V 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 231312 G15 VDD = 5V OVDD = 2.5V 5 0.75 4.00 –55 –35 –15 Supply Current vs Sample Rate 6 SUPPLY CURRENT (mA) SHUTDOWN CURRENT (µA) FULL-SCALE ERROR (LSB) 300 150 1 4 VDD = 5V 350 73 –85 Reference Current vs Reference Voltage REFERENCE CURRENT (µA) –80 THD, HARMONICS (dB) 74 VDD = 5V SNR, SINAD (dBFS) –75 TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 2.5Msps, IOVDD 5 25 45 65 85 105 125 TEMPERATURE (°C) 231312 G16 0 0 500 1000 1500 2000 SAMPLE RATE (kHz) 2500 231312 G17 231312fb For more information www.linear.com/LTC2313-12 7 LTC2313-12 TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. 5.75 Supply Current (IVDD) vs Supply Voltage (VDD) 2.5 OUTPUT SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 5.50 5.25 5.00 4.75 OPERATION NOT ALLOWED 4.50 4.25 4.00 3.75 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 SUPPLY VOLTAGE (V) 231312 G18 TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 2.5Msps, Output Supply Current (IOVDD) vs Output Supply Voltage (OVDD) 2.0 1.5 1.0 0.5 0 1.7 2.3 2.9 3.5 4.1 4.7 OUTPUT SUPPLY VOLTAGE (V) 5.3 231312 G19 PIN FUNCTIONS VDD (Pin 1): Power Supply. The ranges of VDD are 2.7V to 3.6V and 4.75V to 5.25V. Bypass VDD to GND with a 2.2µF ceramic chip capacitor. REF (Pin 2): Reference Input/Output. The REF pin voltage defines the input span of the ADC, 0V to VREF. By default, REF is an output pin and produces a reference voltage VREF of either 2.048V or 4.096V depending on VDD (see Table 2). Bypass to GND with a 2.2µF, low ESR, high quality ceramic chip capacitor. The REF pin may be overdriven with a voltage at least 50mV higher than the internal reference voltage output. GND (Pin 3): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 4): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VREF. OVDD (Pin 5): I/O Interface Digital Power. The OVDD range is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V or 5V). Bypass to GND with a 2.2µF ceramic chip capacitor. 8 SDO (Pin 6): Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with the MSB first through the LSB last. The data stream consists of 12 bits of conversion data followed by trailing zeros. There is no cycle latency. Logic levels are determined by OVDD. SCK (Pin 7): Serial Data Clock Input. The SCK serial clock synchronizes the serial data transfer. SDO data transitions on the falling edge of SCK. Logic levels are determined by OVDD. CONV (Pin 8): Convert Input. This active high signal starts a conversion on the rising edge. The conversion is timed via an internal oscillator. The device automatically powers down following the conversion process. The SDO pin is in high impedance when CONV is a logic high. Bringing CONV low enables the SDO pin and outputs the MSB. Subsequent bits of the conversion data are read out serially on the falling edge of SCK. A logic low on CONV also places the sample-and-hold into sample mode. Logic levels are determined by OVDD. 231312fb For more information www.linear.com/LTC2313-12 LTC2313-12 BLOCK DIAGRAM 2.2µF 2.2µF ANALOG SUPPLY 3V OR 5V I/O INTERFACE SUPPLY RANGE 1.8V TO 5V 1 5 VDD OVDD 2.5V LDO ANALOG INPUT RANGE 0V TO VREF AIN + 4 12-BIT SAR ADC S/H – THREE-STATE SERIAL OUTPUT PORT SDO 6 REF SCK 2 2.2µF GND 3 2×/4× 7 TIMING LOGIC 1.024V BANDGAP CONV 8 TS8 PACKAGE 231312 BD ALL CAPACITORS UNLESS NOTED ARE HIGH QUALITY, CERAMIC CHIP TYPE TIMING DIAGRAMS t3 CONV SDO CONV OVDD/2 Hi-Z MSB VOH VOL Figure 1. SDO Enabled After CONV↓ t8 OVDD/2 Hi-Z SDO Figure 2. SDO Into Hi-Z After CONV↑ 231312 TD01 SCK SDO t7 231312 TD02 SCK OVDD/2 VOH VOL SDO Figure 3. SDO Data Valid Hold After SCK↓ t4 OVDD/2 VOH VOL Figure 4. SDO Data Valid Access After SCK↓ 231312 TD03 231312 TD04 231312fb For more information www.linear.com/LTC2313-12 9 LTC2313-12 APPLICATIONS INFORMATION Overview Serial Data Output (SDO) The LTC2313-12 is a low noise, high speed, 12-bit successive approximation register (SAR) ADC. The LTC2313-12 operates from a single 3V or 5V supply and provides a low drift (20ppm/°C maximum), internal reference and reference buffer. The internal reference buffer is automatically configured with a 2.048V span in low supply range (2.7V to 3.6V) and with a 4.096V span in the high supply range (4.75V to 5.25V). The LTC2313-12 samples up to a 2.5Msps rate and supports a 90MHz serial data read clock. The LTC2313-12 achieves excellent dynamic performance (72.6dB SINAD, –84dB THD) while dissipating only 25mW from a 5V supply at the 2.5Msps conversion rate. The LTC2313-12 outputs the conversion data with no cycle latency onto the SDO pin. The SDO pin output logic levels are supplied by the dedicated OVDD supply pin which has a wide supply range (1.71V to 5.25V) allowing the LTC2313-12 to communicate with 1.8V, 2.5V, 3V or 5V systems. The LTC2313-12 automatically switches to nap mode following the conversion process to save power. The device also provides a sleep power-down mode through serial interface control to reduce power dissipation during long inactive periods. The SDO output is always forced into the high impedance state while CONV is high. The falling edge of CONV enables SDO and also places the sample and hold into sample mode. The A/D conversion result is shifted out on the SDO pin as a serial data stream with the MSB first. The MSB is output on SDO on the falling edge of CONV. Delay t3 is the data valid access time for the MSB. The following 11 bits of conversion data are shifted out on SDO on the falling edge of SCK. Delay t4 is the data valid access time for output data shifted out on the falling edge of SCK. There is no data latency. Subsequent falling SCK edges applied after the LSB is output will output zeros indefinitely on the SDO pin. Serial Interface The LTC2313-12 communicates with microcontrollers, DSPs and other external circuitry via a 3-wire interface. A rising CONV edge starts the conversion process which is timed via an internal oscillator. Following the conversion process the device automatically switches to nap mode to save power as shown in Figure 7. This feature saves considerable power for the LTC2313-12 operating at lower sampling rates. As shown in Figures 5 and 6, it is recommended to hold SCK static low or high during tCONV. A falling CONV edge enables SDO and outputs the MSB. Subsequent SCK falling edges clock out the remaining data as shown in Figures 5 and 6. CONV must be held high for the minimum conversion time, tCONV(MIN).Data is serially output MSB first through LSB last, followed by trailing zeros if further SCK falling edges are applied. 10 The output swing on the SDO pin is controlled by the OVDD pin voltage and supports a wide operating range from 1.71V to 5.25V independent of the VDD pin voltage. Power Considerations The LTC2313-12 provides two sets of power supply pins: the analog power supply (VDD) and the digital input/output interface power supply (OVDD). The flexible OVDD supply allows the LTC2313-12 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. Entering Nap/Sleep Mode Pulsing CONV two times and holding SCK static places the LTC2313-12 into nap mode. Pulsing CONV four times and holding SCK static places the LTC2313-12 into sleep mode. In sleep mode, all bias circuitry is shut down, including the internal bandgap and reference buffer, and only leakage currents remain (0.2µA typical). Because the reference buffer is externally bypassed with a large capacitor (2.2µF), the LTC2313-12 requires a significant wait time (1.1ms) to recharge this capacitance before an accurate conversion can be made. In contrast, nap mode does not power down the internal bandgap or reference buffer allowing for a fast wake-up and accurate conversion within one conversion clock cycle. Supply current during nap mode is nominally 2mA. 231312fb For more information www.linear.com/LTC2313-12 LTC2313-12 APPLICATIONS INFORMATION t9 tACQ-MIN = 11.5 • tSCK + t2 + t9 CONV tCONV-MIN t2 tACQ t6 SCK 1 t8 t3 HI-Z STATE SDO 2 3 t5 B11 4 t4 B10 B9 10 11 12 t7 B8 B1 B0 0 (MSB) tTHROUGHPUT 231312 F05 Figure 5. LTC2313-12 Serial Interface Timing Diagram (SCK Low During tCONV) t9 tACQ-MIN = 11.5 • tSCK + t2 + t9 CONV tCONV-MIN t2 SCK 1 HI-Z STATE SDO 2 3 t5 t3 t8 tACQ t6 B11 4 t4 B10 B9 10 11 12 t7 B8 B1 B0 0 (MSB) tTHROUGHPUT 231312 F06 Figure 6. LTC2313-12 Serial Interface Timing Diagram (SCK High During tCONV) t9 t2 CONV CONVERT POWER-DOWN tCONV-MIN NAP MODE tACQ SCK t8 SDO HI-Z STATE tCONV > tCONV-MIN t3 B11 B10 (MSB) 231312 F07 Figure 7. LTC2313-12 Nap Mode Power-Down Following Conversion for tCONV > tCONV-MIN 231312fb For more information www.linear.com/LTC2313-12 11 LTC2313-12 APPLICATIONS INFORMATION Exiting Nap/Sleep Mode with high source impedance, a buffer amplifier should be used. The main requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. Settling time must be less than tACQ-MIN (153ns) for full performance at the maximum throughput rate. While choosing an input amplifier, also keep in mind the amount of noise and harmonic distortion the amplifier contributes. Waking up the LTC2313-12 from either nap or sleep mode, as shown in Figures 8 and 9, requires SCK to be pulsed one time. A conversion cycle (tACQ) may be started immediately following nap mode as shown in Figure 8. A period of time allowing the reference voltage to recover must follow waking up from sleep mode as shown in Figure 9. The wait period required before initiating a conversion for the recommended value of CREF of 2.2µF is 1.1ms. Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (12-bit resolution within the minimum acquisition time (tACQ-MIN) of 153ns. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 10 shows a recommended singleended buffered drive circuit using the LT1818 in unity gain + – LT1818 LTC2313-12 50Ω AIN 47pF GND 231312 F10 Figure 10. RC Input Filter ADC Reference A low noise, low temperature drift reference is critical to achieving the full data sheet performance of the ADC. The LTC2313-12 provides an excellent internal reference with a guaranteed 20ppm/°C maximum temperature coefficient. For added flexibility, an external reference may also be used. The high speed, low noise internal reference buffer is used only in the internal reference configuration. The reference For more information www.linear.com/LTC2313-12 231312fb 13 LTC2313-12 APPLICATIONS INFORMATION buffer must be overdriven in the external reference configuration with a voltage 50mV higher than the nominal reference output voltage in the internal configuration. Using the Internal Reference The internal bandgap and reference buffer are active by default when the LTC2313-12 is not in sleep mode. The reference voltage at the REF pin scales automatically with the supply voltage at the VDD pin. The scaling of the reference voltage with supply is shown in Table 2. Table 2. Reference Voltage vs Supply Range SUPPLY VOLTAGE (VDD) REF VOLTAGE (VREF) 2.7V < VDD < 3.6V 2.048V 4.75V < VDD < 5.25V 4.096V The reference voltage also determines the full-scale analog input range of the LTC2313-12. For example, a 2.048V reference voltage will accommodate an analog input range from 0V to 2.048V. An analog input voltage that goes below 0V will be coded as all zeros and an analog input voltage that exceeds 2.048V will be coded as all ones. It is recommended that the REF pin be bypassed to ground with a low ESR, 2.2µF ceramic chip capacitor for optimum performance. External Reference An external reference can be used with the LTC2313-12 if better performance is required or to accommodate a larger input voltage span. The only constraints are that the external reference voltage must be 50mV higher than the internal reference voltage (see Table 2) and must be less than or equal to the supply voltage (or 4.3V for the 5V supply range). For example, a 3.3V external reference may be used with a 3.3V VDD supply voltage to provide a 3.3V analog input voltage span (i.e. 3.3V > 2.048V + 50mV). Or alternatively, a 2.5V reference may be used with a 3V supply voltage to provide a 2.5V input voltage range (i.e. 2.5V > 2.048V + 50mV). The LTC6655-3.3, LTC6655-2.5, available from Linear Technology, may be suitable for many applications requiring a high performance external reference for either 3.3V or 2.5V input spans respectively. Transfer Function Figure 11 depicts the transfer function of the LTC2313-12. The code transitions occur midway between successive integer LSB values (i.e. 0.5LSB, 1.5LSB, 2.5LSB… FS0.5LSB). The output code is straight binary with 1LSB = VREF/4096. DC Performance The noise of an ADC can be evaluated in two ways: signalto-noise ratio (SNR) in the frequency domain and histogram in the time domain. The LTC2313-12 excels in both. The noise in the time domain histogram is the transition noise associated with a 12-bit resolution ADC which can be measured with a fixed DC signal applied to the input of the ADC. The resulting output codes are collected over a large number of conversions. The shape of the distribution of codes will give an indication of the magnitude of the transition noise. In Figure 12, the distribution of output codes is shown for a DC input that has been digitized 16000 111...111 σ = 0.33 111...110 COUNTS OUTPUT CODE 12000 8000 4000 000...001 0 000...000 0 1LSB INPUT VOLTAGE (V) FS – 1LSB Figure 11. LTC2313-12 Transfer Function 14 2046 2047 2048 CODE 231312 F11 2049 231312 F12 Figure 12. Histogram for 16384 Conversions 231312fb For more information www.linear.com/LTC2313-12 LTC2313-12 APPLICATIONS INFORMATION 16,384 times. The distribution is Gaussian and the RMS code transition noise is 0.33LSB. This corresponds to a noise level of 73dB relative to a full scale voltage of 4.096V. At the maximum sampling rate of 2.5MHz, the LTC231312 maintains an ENOB above 11.7 bits up to an input frequency of 1MHz. (Figure 14) Dynamic Performance Signal-to-Noise Ratio (SNR) The LTC2313-12 has excellent high speed sampling capability. Fast Fourier Transform (FFT) techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the applied fundamental. The LTC2313-12 provides guaranteed tested limits for both AC distortion and noise measurements. The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 13 shows that the LTC2313-12 achieves a typical SNR of 73dB at a 2.5MHz sampling rate with a 497kHz input frequency. Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling frequency. Figure 14 shows the LTC2313-12 maintains a SINAD above 72dB up to an input frequency of 1MHz. Effective Number of Bits (ENOB) The effective number of bits (ENOB) is a measurement of the resolution of an ADC and is directly related to SINAD by the equation where ENOB is the effective number of bits of resolution and SINAD is expressed in dB: Total Harmonic Distortion (THD) Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: THD=20log V22 + V32 + V42 + VN2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. THD versus Input Frequency is shown in the Typical Performance Characteristics section. The LTC2313-12 has excellent distortion performance up to the Nyquist frequency. ENOB = (SINAD – 1.76)/6.02 0 –20 SINAD (dBFS) –60 73 –80 –100 –120 72 11.67 71 11.50 –140 –160 11.83 VDD = 5V ENOB AMPLITUDE (dBFS) –40 12.00 74 VDD = 5V SNR = 73dBFS SINAD = 72.6dBFS THD = –84dB SFDR = 87dB VDD = 3V 0 250 500 750 INPUT FREQUENCY (kHz) 1000 70 0 500 750 INPUT FREQUENCY (kHz) 231312 F13 Figure 13. 16k Point FFT of the LTC2313-12 at fIN = 497kHz 250 11.34 1000 231312 F14 Figure 14. LTC2313-12 ENOB/SINAD vs fIN For more information www.linear.com/LTC2313-12 231312fb 15 LTC2313-12 APPLICATIONS INFORMATION Intermodulation Distortion (IMD) Full-Power and –3dB Input Linear Bandwidth If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. The full-power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies m • fa ± n • fb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa ± fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: IMD(fa ± fb) = 20 • log[VA (fa ± fb)/VA (fa)] The LTC2313-12 has excellent IMD, as shown in Figure 15. 0 fb fa –20 MAGNITUDE (dB) –40 –60 f –f –80 b a 2fa – fb –100 VDD = 5V fs = 2.5Msps fa = 255.421kHz fb = 285.421kHz IMD2 (fb – fa) = –80.4dBc IMD3 (2fb – fa) = –91.8dBc 2fb – fa fa + fb –120 –140 –160 0 250 500 750 1000 INPUT FREQUENCY (kHz) 1250 231312 F15 Figure 15. LTC2313-12 IMD Plot Spurious Free Dynamic Range (SFDR) The spurious free dynamic range is the largest spectral component excluding DC and the input signal. This value is expressed in decibels relative to the RMS value of a full-scale input signal. 16 The –3dB linear bandwidth is the input frequency at which the SINAD has dropped to 68dB (11 effective bits). The LTC2313-12 has been designed to optimize the input bandwidth, allowing the ADC to under-sample input signals with frequencies above the converter’s Nyquist frequency. The noise floor stays very low at high frequencies and SINAD becomes dominated by distortion at frequencies beyond Nyquist. Recommended Layout To obtain the best performance from the LTC2313-12 a printed circuit board is required. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Figures 16 through 20 are an example of a recommended PCB layout. A single solid ground plane is used. Bypass capacitors to the supplies are placed as close as possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low noise operation of the ADC. The analog input traces are screened by ground. For more details and information refer to DC1563, the evaluation kit for the LTC2313-12. Bypassing Considerations High quality ceramic bypass capacitors should be used at the VDD, OVDD and REF pins. For optimum performance, a 2.2µF ceramic chip capacitor should be used for the VDD and OVDD pins. The recommended bypassing for the REF pin is also a low ESR, 2.2µF ceramic chip capacitor. The traces connecting the pins and the bypass capacitors must be kept as short as possible and should be made as wide as possible avoiding the use of vias. All analog circuitry grounds should be terminated at the LTC2313-12. The ground return from the LTC2313-12 to the power supply should be low impedance for noise free operation. Digital circuitry grounds must be connected to the digital supply common. 231312fb For more information www.linear.com/LTC2313-12 LTC2313-12 APPLICATIONS INFORMATION In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feed-through from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a “Wait” state during conversion or by using three-state buffers to isolate the ADC data bus. Figure 16. Top Silkscreen Figure 17. Layer 1 Top Layer Figure 18. Layer 2 GND Plane 231312fb For more information www.linear.com/LTC2313-12 17 LTC2313-12 APPLICATIONS INFORMATION Figure 19. Layer 3 PWR Plane Figure 20. Layer 4 Bottom Layer 18 231312fb For more information www.linear.com/LTC2313-12 LTC2313-12 APPLICATIONS INFORMATION REF U5 LT1790ACS6-2.048 9V TO 10V 4 VI GND GND 1 2 JP1 HD1X3-100 J4 AIN 0V TO 4.096V C6 4.7µF R14 0k VO AC R9 1k C8 10µF VCCIO C9 4.7µF C10 OPT C11 OPT C12 4.7µF DC COUPLING 1 2 3 C18 OPT C7 OPT VDD VCM 6 + R15 49.9Ω C17 1µF 3 2 1 U1 * 4 C19 47pF NP0 JP2 VCM 1.024V 1 2 5 VDD REF OVDD AIN CSL SCK GND 3 SDO 231312 F21 8 CSL* 7 SCK SDO 6 R16 33Ω 2.048V HD1X3-100 R18 1k *CSL = CONV Figure 21. Partial 1563 Demo Board Schematic 231312fb For more information www.linear.com/LTC2313-12 19 LTC2313-12 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 0.40 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 – 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) 1.95 BSC TS8 TSOT-23 0710 REV A NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 20 231312fb For more information www.linear.com/LTC2313-12 LTC2313-12 REVISION HISTORY REV DATE DESCRIPTION A 11/13 Added pin-compatible family table B 01/15 PAGE NUMBER 1 Reordered/renumbered notes 3, 5 Updated Timing Diagrams (Figures 8 and 9) 12 231312fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. For more www.linear.com/LTC2313-12 21 LTC2313-12 TYPICAL APPLICATION Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Re-Timing Flip-Flop VCC 0.1µF 50Ω 1k NC7SVU04P5X MASTER CLOCK VCC 1k PRE D > Q CONV CLR NL17SZ74 CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) SDO ENABLE CONV SCK LTC2313-12 NC7SVUO4P5X SDO 33Ω 231312 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2315-12 12-Bit, 5Msps Serial ADC 3V/5V, 19mW/32mW, 20ppm/°C Max Internal Reference, Single-Ended Input, 8-Lead TSOT-23 Package LTC2312-12 12-Bit, 500ksps Serial ADC 3V/5V, 19mW/15mW, 20ppm/°C Max Internal Reference, Single-Ended Input, 8-Lead TSOT-23 Package LTC1403/LTC1403-1 12-Bit, 2.8Msps Serial ADC 3V, 14mW, Unipolar/Bipolar Inputs, MSOP Package LTC1407/LTC1407-1 12-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, Unipolar/Bipolar Inputs, 14mW, MSOP Package LTC2355/LTC2356 12-/14-Bit, 3.5Msps Serial ADC 3.3V Supply, Differential Inputs, 18mW, MSOP Package LTC2365/LTC2366 12-Bit, 1Msps/3Msps Serial Sampling ADC 3.3V Supply, Single-Ended, 8mW, TSOT-23 Package LT6200/LT6201 Single/Dual Operational Amplifiers 165MHz, 0.95nV/√Hz LT6230/LT6231 Single/Dual Operational Amplifiers 215MHz, 3.5mA/Amplifier, 1.1nV/√Hz LT6236/LT6237 Single/Dual Operational Amplifier with Low Wideband Noise 215MHz, 3.5mA/Amplifier, 1.1nV/√Hz LT1818/LT1819 Single/Dual Operational Amplifiers 400MHz, 9mA/Amplifier, 6nV/√Hz LTC6655-2.5/LTC6655-3.3 Precision Low Drift Low Noise Buffered Reference 2.5V/3.3V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package LT1461-3/LT1461-3.3V Precision Series Voltage Family 0.05% Initial Accuracy, 3ppm Drift ADCs Amplifiers References 22 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2313-12 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2313-12 231312fb LT 0115 REV B • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 2013