LTC2320-14
Octal, 14-Bit + Sign,
1.5Msps/Ch Simultaneous
Sampling ADC
DESCRIPTION
FEATURES
1.5Msps/Ch Throughput Rate
nn Eight Simultaneously Sampling Channels
nn Guaranteed 14-Bit, No Missing Codes
nn 8V
P-P Differential Inputs with Wide Input
Common Mode Range
nn 81dB SNR (Typ) at f = 500kHz
IN
nn –90dB THD (Typ) at f = 500kHz
IN
nn Guaranteed Operation to 125°C
nn Single 3.3V or 5V Supply
nn Low Drift (20ppm/°C Max) 2.048V or 4.096V
Internal Reference
nn 1.8V to 2.5V I/O Voltages
nn CMOS or LVDS SPI-Compatible Serial I/O
nn Power Dissipation 20mW/Ch (Typ)
nn Small 52-Lead (7mm × 8mm) QFN Package
The LTC®2320-14 is a low noise, high speed octal 14‑bit
+ sign successive approximation register (SAR) ADC with
differential inputs and wide input common mode range.
Operating from a single 3.3V or 5V supply, the LTC232014 has an 8VP-P differential input range, making it ideal
for applications which require a wide dynamic range with
high common mode rejection. The LTC2320-14 achieves
±1LSB INL typical, no missing codes at 14 bits and 81dB
SNR.
nn
The LTC2320-14 has an onboard low drift (20ppm/°C
max) 2.048V or 4.096V temperature-compensated
reference. The LTC2320-14 also has a high speed SPIcompatible serial interface that supports CMOS or LVDS.
The fast 1.5Msps per channel throughput with no latency
makes the LTC2320-14 ideally suited for a wide variety
of high speed applications. The LTC2320-14 dissipates
only 20mW per channel and offers nap and sleep modes
to reduce the power consumption to 26μW for further
power savings during inactive periods.
APPLICATIONS
High Speed Data Acquisition Systems
Communications
nn Optical Networking
nn Multiphase Motor Control
nn
nn
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
10µF
1µF
1.8V TO 2.5V
3.3V OR 5V
IN+, IN –
VDD
ARBITRARY
0V
VDD
0V
VDD
DIFFERENTIAL
VDD
AIN2+
S/H
AIN2–
AIN3+
S/H
AIN3–
AIN4+
S/H
AIN4–
0V
BIPOLAR
AIN1+
S/H
AIN1–
UNIPOLAR
0V
AIN5+
S/H
AIN5–
AIN6+
S/H
AIN6–
AIN7+
S/H
AIN7–
AIN8+
S/H
AIN8–
REF
EIGHT SIMULTANEOUS
SAMPLING CHANNELS
VDD
GND
GND
MUX
14-BIT
+ SIGN
SAR ADC
CMOS/LVDS
SDR/DDR
REFBUFEN
MUX
14-BIT
+ SIGN
SAR ADC
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
SDO8
CLKOUT
SCK
LTC2320-14
MUX
14-BIT
+ SIGN
SAR ADC
CNV
MUX
32k Point FFT fSMPL = 1.5Msps,
fIN = 500kHz
OVDD
SAMPLE
CLOCK
10µF
–60
–80
–100
–140
232014 TA01a
10µF
IN
SNR = 81.1dB
THD = –90.2dB
–20 SINAD = 80.8dB
SFDR = 94.7dB
–40
–120
14-BIT
+ SIGN
SAR ADC
REFOUT1 REFOUT2 REFOUT3 REFOUT4
1µF
SMPL
0
AMPLITUDE (dBFS)
TRUE DIFFERENTIAL INPUTS
NO CONFIGURATION REQUIRED
10µF
10µF
0
0.1
0.2 0.3 0.4 0.5
FREQUENCY (MHz)
0.6
0.7
232014 TA01b
232014fa
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1
LTC2320-14
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
SCK/SCK+
DNC/SCK–
VDD
REFOUT4
GND
AIN8–
AIN8+
GND
AIN7–
AIN7+
VDD
TOP VIEW
52 51 50 49 48 47 46 45 44 43 42 41
AIN6– 1
40 SDO8/SDOD–
AIN6+ 2
39 SDO7/SDOD+
GND 3
38 GND
AIN5– 4
37 OVDD
AIN5+ 5
36 SDO6/SDOC–
REFOUT3 6
35 SDO5/SDOC+
GND 7
34 CLKOUTEN/CLKOUT –
53
GND
REF 8
33 CLKOUT/CLKOUT+
32 GND
REFOUT2 9
AIN4– 10
31 OVDD
AIN4+ 11
30 SDO4/SDOB–
GND 12
29 SDO3/SDOB+
AIN3– 13
28 SDO2/SDOA–
AIN3+ 14
27 SDO1/SDOA+
GND
CMOS/LVDS
CNV
SDR/DDR
VDD
REFOUT1
AIN1+
GND
AIN1–
AIN2+
VDD
15 16 17 18 19 20 21 22 23 24 25 26
AIN2–
Supply Voltage (VDD)...................................................6V
Supply Voltage (OVDD).................................................3V
Analog Input Voltage
AIN+, AIN – (Note 3).................... –0.3V to (VDD + 0.3V)
REFOUT1,2,3,4........................ .–0.3V to (VDD + 0.3V)
CNV........................................ –0.3V to (OVDD + 0.3V)
Digital Input Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Operating Temperature Range
LTC2320C................................................. 0°C to 70°C
LTC2320I..............................................–40°C to 85°C
LTC2320H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
REFBUFEN
(Notes 1, 2)
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
TJMAX = 150°C, θJA = 31°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
http://www.linear.com/product/LTC2320-14#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2320CUKG-14#PBF
LTC2320CUKG-14#TRPBF
LTC2320UKG-14
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2320IUKG-14#PBF
LTC2320IUKG-14#TRPBF
LTC2320UKG-14
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
LTC2320HUKG-14#PBF
LTC2320HUKG-14#TRPBF
LTC2320UKG-14
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
232014fa
For more information www.linear.com/LTC2320-14
LTC2320-14
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
Absolute Input Range (AIN+ to AIN–)
Absolute Input Range (AIN+ to AIN–)
VIN+ – VIN–
Input Differential Voltage Range
VCM
Common Mode Input Range
VIN = VIN+ – VIN–
VCM = (VIN+ – VIN–)/2
IIN
Analog Input DC Leakage Current
+
VIN
VIN–
MIN
MAX
UNITS
0
VDD
V
0
VDD
V
l
–REFOUT1,2,3,4
REFOUT1,2,3,4
V
l
0
VDD
V
l
–1
1
μA
(Note 5)
l
(Note 5)
l
CIN
Analog Input Capacitance
CMRR
Input Common Mode Rejection Ratio
VIHCNV
CNV High Level Input Voltage
l
VILCNV
CNV Low Level Input Voltage
l
IINCNV
CNV Input Current
l
TYP
fIN = 500kHz
10
pF
102
dB
1.5
V
–10
0.5
V
10
μA
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER
CONDITIONS
MIN
Resolution
l
14
No Missing Codes
l
14
Transition Noise
INL
Integral Linearity Error
DNL
Differential Linearity Error
BZE
Bipolar Zero-Scale Error
MAX
(Note 6)
UNITS
Bits
Bits
0.8
LSBRMS
l
–3
±1
3
LSB
l
–0.99
±0.4
0.99
LSB
(Note 7)
l
–3
0
3
LSB
Bipolar Full-Scale Error
VREFOUT1,2,3,4 = 4.096V (REFBUFEN Grounded) (Note 7)
l
–8
Bipolar Full-Scale Error Drift
VREFOUT1,2,3,4 = 4.096V (REFBUFEN Grounded)
Bipolar Zero-Scale Error Drift
FSE
TYP
0.005
0
15
LSB/°C
8
LSB
ppm/°C
232014fa
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3
LTC2320-14
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS (Notes 4, 8).
SYMBOL PARAMETER
SINAD
CONDITIONS
MIN
Signal-to-(Noise + Distortion) Ratio fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference
l
75.5
fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference
SNR
Signal-to-Noise Ratio
fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference
THD
Total Harmonic Distortion
fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference
SFDR
Spurious Free Dynamic Range
fIN = 500kHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference
l
76.5
fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference
TYP
MAX
UNITS
80
dB
84
dB
81
dB
82.5
fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference
l
dB
–90
l
77
fIN = 500kHz, VREFOUT1,2,3,4 = 5V, External Reference
–77
dB
–91
dB
93
dB
93
dB
–3dB Input Bandwidth
55
MHz
Aperture Delay
500
ps
Aperture Delay Matching
500
ps
Aperture Jitter
Transient Response
Full-Scale Step
1
psRMS
3
ns
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
VREFOUT1,2,3,4
Internal Reference Output Voltage
4.75V < VDD < 5.25V
3.13V < VDD < 3.47V
l
l
VREF Temperature Coefficient
(Note 14)
l
MIN
TYP
MAX
UNITS
4.078
2.034
4.096
2.048
4.115
2.064
V
V
3
20
REFOUT1,2,3,4 Output Impedance
IREFOUT1,2,3,4
4
ppm/°C
0.25
Ω
VREFOUT1,2,3,4 Line Regulation
4.75V < VDD < 5.25V
0.3
mV/V
External Reference Current
REFBUFEN = 0V
REFOUT1,2,3,4 = 4.096V
REFOUT1,2,3,4 = 2.048V
(Notes 9, 10)
385
204
μA
μA
232014fa
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LTC2320-14
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER
CONDITIONS
CMOS Digital Inputs and Outputs
MIN
TYP
MAX
UNITS
CMOS/LVDS = GND
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Digital Input Current
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –500μA
l
VOL
Low Level Output Voltage
IO = 500μA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
ISOURCE
Output Source Current
VOUT = 0V
l
–10
mA
ISINK
Output Sink Current
VOUT = OVDD
l
10
mA
l
0.8 • OVDD
V
l
VIN = 0V to OVDD
l
–10
V
10
μA
5
l
LVDS Digital Inputs and Outputs
0.2 • OVDD
pF
OVDD – 0.2
V
–10
0.2
V
10
μA
CMOS/LVDS = OVDD
VID
LVDS Differential Input Voltage
100Ω Differential Termination
OVDD = 2.5V
l
240
600
mV
VIS
LVDS Common Mode Input Voltage
100Ω Differential Termination
OVDD = 2.5V
l
1
1.45
V
VOD
LVDS Differential Output Voltage
100Ω Differential Termination
OVDD = 2.5V
l
220
350
600
mV
VOS
LVDS Common Mode Output Voltage
100Ω Differential Termination
OVDD = 2.5V
l
0.85
1.2
1.4
V
VOD_LP
Low Power LVDS Differential Output Voltage
100Ω Differential Termination
OVDD = 2.5V
l
100
200
350
mV
VOS_LP
Low Power LVDS Common Mode Output Voltage
100Ω Differential Termination
OVDD = 2.5V
l
0.85
1.2
1.4
V
232014fa
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5
LTC2320-14
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
VDD
Supply Voltage
5V Operation
3.3V Operation
l
l
IVDD
Supply Current
1.5Msps Sample Rate (IN+ = IN– = 0V)
l
CMOS I/O Mode
MIN
TYP
4.75
3.13
31
MAX
UNITS
5.25
3.47
V
V
38
mA
CMOS/LVDS = GND
OVDD
Supply Voltage
2.63
V
IOVDD
Supply Current
1.5Msps Sample Rate (CL = 5pF)
l
1.71
4.4
7.0
mA
INAP
Nap Mode Current
Conversion Done (IVDD)
l
5.3
6.2
mA
l
ISLEEP
Sleep Mode Current
Sleep Mode (IVDD + IOVDD)
l
20
110
µA
PD_3.3V
Power Dissipation
VDD = 3.3V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
l
l
l
102
18
20
130
20.6
355
mW
mW
µW
PD_5V
Power Dissipation
VDD = 5V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
l
l
l
162
27
30
208
31.2
525
mW
mW
µW
LVDS I/O Mode
CMOS/LVDS = OVDD, OVDD = 2.5V
OVDD
Supply Voltage
IOVDD
Supply Current
1.5Msps Sample Rate (CL = 5pF, RL = 100Ω)
l
2.37
26
INAP
Nap Mode Current
Conversion Done (IVDD)
l
ISLEEP
Sleep Mode Current
Sleep Mode (IVDD + IOVDD)
l
PD_3.3V
Power Dissipation
VDD = 3.3V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
PD_5V
Power Dissipation
VDD = 5V, 1.5Msps Sample Rate
Nap Mode
Sleep Mode
l
2.63
V
34
mA
5.3
6.2
mA
20
110
µA
l
l
l
151
52
80
195
58
355
mW
mW
µW
l
l
l
214
60
30
280
68.5
525
mW
mW
µW
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
fSMPL
Maximum Sampling Frequency
CONDITIONS
MIN
TYP
tCYC
Time Between Conversions
tCONV
Conversion Time
l
tCNVH
CNV High Time
l
tACQUISITION
Sampling Aperture
(Note 11) tACQUISITION = tCYC – tCONV
215
ns
tWAKE
REFOUT1,2,3,4 Wake-Up Time
CREFOUT1,2,3,4 = 10µF
50
ms
l
(Note 11) tCYC = tCNVH + tCONV + tREADOUT
l
0.667
MAX
UNITS
1.5
Msps
1000
450
30
µs
ns
ns
CMOS I/O Mode, SDR CMOS/LVDS = GND, SDR/ DDR = GND
tSCK
SCK Period
tSCKH
tSCKL
tHSDO_SDR
SDO Data Remains Valid Delay from CLKOUT↓
tDSCKCLKOUT
SCK to CLKOUT Delay
6
(Note 13)
l
9.1
ns
SCK High Time
l
4.1
ns
SCK Low Time
l
4.1
ns
CL = 5pF (Note 12)
l
0
1.5
ns
(Note 12)
l
2
4.5
ns
232014fa
For more information www.linear.com/LTC2320-14
LTC2320-14
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tDCNVSDOZ
Bus Relinquish Time After CNV↑
(Note 11)
l
3
ns
tDCNVSDOV
SDO Valid Delay from CNV↓
(Note 11)
l
3
ns
tDSCKHCNVH
SCK Delay Time to CNV↑
(Note 11)
l
0
ns
CMOS I/O Mode, DDR CMOS/LVDS = GND, SDR/ DDR = OVDD
tSCK
SCK Period
l
18.2
ns
tSCKH
SCK High Time
l
8.2
ns
tSCKL
SCK Low Time
l
8.2
ns
tHSDO_DDR
SDO Data Remains Valid Delay from CLKOUT↓
CL = 5pF (Note 12)
l
0
1.5
ns
tDSCKCLKOUT
SCK to CLKOUT Delay
(Note 12)
l
2
4.5
ns
tDCNVSDOZ
Bus Relinquish Time After CNV↑
(Note 11)
l
3
ns
tDCNVSDOV
SDO Valid Delay from CNV↓
(Note 11)
l
tDSCKHCNVH
SCK Delay Time to CNV↑
(Note 11)
l
0
ns
3
ns
LVDS I/O Mode, SDR CMOS/LVDS = OVDD, SDR/DDR = GND
tSCK
SCK Period
l
3.3
ns
tSCKH
SCK High Time
l
1.5
ns
tSCKL
SCK Low Time
l
1.5
ns
tHSDO_SDR
SDO Data Remains Valid Delay from CLKOUT↓
CL = 5pF (Note 12)
l
0
1.5
ns
tDSCKCLKOUT
SCK to CLKOUT Delay
(Note 12)
l
2
4
ns
tDSCKHCNVH
SCK Delay Time to CNV↑
(Note 11)
l
0
ns
LVDS I/O Mode, DDR CMOS/LVDS = OVDD, SDR/DDR = OVDD = 2.5V
tSCK
SCK Period
l
6.6
ns
tSCKH
SCK High Time
l
3
ns
tSCKL
SCK Low Time
l
3
ns
tHSDO_DDR
SDO Data Remains Valid Delay from CLKOUT↓
l
0
1.5
ns
tDSCKCLKOUT
SCK to CLKOUT Delay
l
2
4
ns
tDSCKHCNVH
SCK Delay Time to CNV↑
l
0
CL = 5pF
(Note 11)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground, or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle input
currents up to 100mA below ground, or above VDD or OVDD, without latch-up.
Note 4: VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 = 4.096V, fSMPL = 1.5MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 000 0000 0000 0000 and 111
1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS
ns
untrimmed deviation from ideal first and last code transitions and includes
the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±4.096V input
with REF = 4.096V.
Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer
must be turned off by setting REFBUFEN = 0V.
Note 10: fSMPL = 1.5MHz, IREFOUT1,2,3,4 varies proportionally with sample rate.
Note 11: Guaranteed by design, not subject to test.
Note 12: Parameter tested and guaranteed at OVDD = 1.71V and OVDD = 2.5V.
Note 13: tSCK of 9.1ns allows a shift clock frequency up to 105MHz for
rising edge capture.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: CNV is driven from a low jitter digital source, typically at OVDD
logic levels.
232014fa
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7
LTC2320-14
ADC TIMING CHARACTERISTICS
0.8 • OVDD
tWIDTH
0.2 • OVDD
tDELAY
tDELAY
0.8 • OVDD
0.8 • OVDD
0.2 • OVDD
0.2 • OVDD
50%
50%
232014 F01
Figure 1. Voltage Levels for Timing Specifications
8
232014fa
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LTC2320-14
TYPICAL
PERFORMANCE CHARACTERISTICS A = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4
T
= 4.096V, fSMPL = 1.5Msps, unless otherwise noted.
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
Histogram
DC HISTOGRAM
30
1.0
2.0
0.5
0
–0.5
NUMBER OF PARTS
DNL ERROR (LSB)
INL ERROR (LSB)
24
0.5
1.0
0
–0.5
–1.0
–8192
0
8192
OUTPUT CODE
–1.0
–16384
16384
–8192
0
8192
OUTPUT CODE
–80
–100
–120
0.1
0.2 0.3 0.4 0.5
FREQUENCY (MHz)
0.6
0.7
–80
–84
81.6
81.4
SNR
81.2
81.0
SINAD
80.8
80.6
80.4
80.0
0
0.1
0.2
0.3 0.4 0.5 0.6
FREQUENCY (MHz)
HD3
–112
–116
–120
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3
INPUT COMMON MODE (V)
232014 G07
0.7
–88
2
3
THD
–92
–96
–100
HD3
–104
HD2
–108
–112
–120
0.8
0
0.1
0.2
0.3 0.4 0.5 0.6
FREQUENCY (MHz)
83
f = 500kHz
82 IN
81
80
79
78
77
76
75
74
73
72
71
70
69
0.5 1 1.5 2
0.7
0.8
232014 G06
0
SNR
32k Point FFT, IMD, fSMPL = 1.5Msps,
+ = 490kHz, A – = 510kHz
AININ
ININ
THD = 86dB
VCM = 20kHz, 4VP-P
–20
SINAD
AMPLITUDE (dBFS)
–108
1
–116
SNR, SINAD vs Reference Voltage,
fIN = 500kHz
SNR, SINAD LEVEL (dBFS)
THD, HARMONICS LEVEL (dBFS)
–104
HD2
0
CODE
232014 G05
fIN = 500kHz
–96
–100
–1
THD, Harmonics vs Input
81.8
THD, Harmonics vs Input Common
Mode
THD
–2
Frequency
(1kHz to 750kHz)
(1kHz
to 750kHz)
80.2
0
–3
232014 G03
82.0
232014 G04
–92
9
0
16384
THD, HARMONICS LEVEL (dBFS)
–60
–88
12
SNR, SINAD vs Input Frequency
(1kHz to 750kHz)
IN
SNR, SINAD LEVEL (dBFS)
AMPLITUDE (dBFS)
32k Point FFT, fSMPL = 1.5Msps,
fIN = 500kHz SMPL
SNR = 81.1dB
THD = –90.2dB
–20 SINAD = 80.8dB
SFDR = 94.7dB
–40
–84
15
232014 G02
232014 G01
–80
18
3
–2.0
–16384
–140
21
6
–1.5
0
σ = 0.72
27
1.5
–40
–60
–80
–100
–120
2.5 3 3.5
VREF(V)
4
4.5
5
232014 G08
–140
0
0.1
0.2 0.3 0.4 0.5
FREQUENCY (MHz)
0.6
0.7
232014 G09
232014fa
For more information www.linear.com/LTC2320-14
9
LTC2320-14
TYPICAL
PERFORMANCE CHARACTERISTICS A = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4
T
= 4.096V, fSMPL = 1.5Msps, unless otherwise noted.
CMRR vs Input Frequency
120
16384
–90
VCM = 4VP-P
–91
115
12288
–92
105
100
OUTPUT CODE (LSB)
–93
CROSSTALK (dB)
110
CMRR (dB)
Step Response
(Large Signal Settling)
Crosstalk vs Input Frequency
–94
–95
–96
–97
8192
4.096V RANGE
4096
0
–98
95
IN+ = 1.5MHz SQUARE WAVE
IN– = 0V
–99
0
500
1000
FREQUENCY (kHz)
1500
–100
0
232014 G10
200 300 400 500
FREQUENCY (kHz)
600
Step Response
232014 G12
External Reference Supply
Current vs Sample Frequency
REF Output vs Temperature
400
125
1.0
REFBUFEN = 0V
350 (EXT REF BUF
SUPPLY CURRENT (uA)
75
50
25
0
–25
–50
4.096V RANGE
–75
IN+ = 1.5MHz
SQUARE WAVE
–100
300
250
200
0.5
OVERDRIVING REF BUF)
VREFOUT1,2,3,4 = 4.096V
150
100
VREFOUT1,2,3,4 = 2.048V
50
IN– = 0V
0
–125
–20 –10 0 10 20 30 40 50 60 70 80 90
SETTLING TIME (ns)
0
0.3
0.6
0.9
1.2
SAMPLE FREQUENCY (Msps)
1.5
–0.5
–1
5 25 45 65 85 105 125
TEMPERATURE (°C)
232014 G16
10
–1.0
VDD = 5V
–1.5
–2.0
–3.0
–55 –35 –15
1.5
5 25 45 65 85 105 125
TEMPERATURE (°C)
232014 G15
33
8
31
7
29
VDD = 5V
27
25
VDD = 3.3V
23
26
24
22
CMOS(1.8V, 8 LANES)
20
3
18
2
0
232014 G17
CMOS (2.5V, 8 LANES)
4
19
1.5
30
LVDS (4 LANES) 28
5
1
0.3
0.6
0.9
1.2
SAMPLE FREQUENCY (Msps)
32
FULL SCALE SINUSOIDAL INPUT
6
21
0
OVDD Current vs SCK Frequency,
CLOAD
LOAD = 10pF
LOW POWER LVDS (4 LANES)
16
OVDD CURRENT LVDS (mA)
SUPPLY CURRENT (mA)
1
0
–0.5
–2.5
Supply Current
vs Sample Frequency
Offset Error
Error vs
vs Temperature
Temperature
Offset
0.5
VDD = 3.3V
0
232014 G14
232014 G13
–1.5
–55 –35 –15
REF OUTPUT ERROR (mV)
100
LSB
–4096
–20 –10 0 10 20 30 40 50 60 70 80 90
SETTLING TIME (ns)
700
232014 G11
(Fine Settling)
DEVIATION FROM FINAL VALUE (LSB)
100
OVDD CURRENT CMOS (mA)
90
14
0
50
100
150
200
250
SCK FREQUENCY (MHz)
12
300
232014 G18
232014fa
For more information www.linear.com/LTC2320-14
LTC2320-14
PIN FUNCTIONS
Pins that are the same for all digital I/O modes.
AIN6+, AIN6– (Pins 2, 1): Analog Differential Input Pins.
Full-scale range (AIN6+ – AIN6–) is ±REFOUT3 voltage.
These pins can be driven from VDD to GND.
GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49): Ground.
These pins and exposed pad (Pin 53) must be tied directly
to a solid ground plane.
AIN5+, AIN5– (Pins 5, 4): Analog Differential Input Pins.
Full-scale range (AIN5+ – AIN5–) is ±REFOUT3 voltage.
These pins can be driven from VDD to GND.
REFOUT3 (Pin 6): Reference Buffer 3 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by grounding the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
REF (Pin 8): Common 4.096V reference output. Decouple
to GND with a 1μF low ESR ceramic capacitor. May be
overdriven with a single external reference to establish a
common reference for ADC cores 1 through 4.
REFOUT2 (Pin 9): Reference Buffer 2 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by grounding the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
AIN4+, AIN4– (Pins 11, 10): Analog Differential Input Pins.
Full-scale range (AIN4+ – AIN4–) is ±REFOUT2 voltage.
These pins can be driven from VDD to GND.
AIN3+, AIN3– (Pins 14, 13): Analog Differential Input Pins.
Full-scale range (AIN3+ – AIN3–) is ±REFOUT2 voltage.
These pins can be driven from VDD to GND.
VDD (Pins 15, 21, 44, 52): Power Supply. Bypass VDD to
GND with a 10µF ceramic capacitor and a 0.1µF ceramic
capacitor close to the part. The VDD pins should be shorted
together and driven from the same supply.
AIN2+, AIN2– (Pins 17, 16): Analog Differential Input Pins.
Full-scale range (AIN2+ – AIN2–) is ±REFOUT1 voltage.
These pins can be driven from VDD to GND.
AIN1+, AIN1– (Pins 20, 19): Analog Differential Input Pins.
Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage.
These pins can be driven from VDD to GND.
REFOUT1 (Pin 22): Reference Buffer 1 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by grounding the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
SDR/DDR (Pin 23): Double Data Rate Input. Controls the
frequency of SCK and CLKOUT. Tie to GND for the falling
edge of SCK to shift each serial data output (Single Data
Rate, SDR). Tie to OVDD to shift serial data output on each
edge of SCK (Double Data Rate, DDR). CLKOUT will be a
delayed version of SCK for both pin states.
CNV (Pin 24): Convert Input. This pin, when high, defines
the acquisition phase. When this pin is driven low, the
conversion phase is initiated and output data is clocked
out. This input must be driven at OVDD levels with a low
jitter pulse. This pin is unaffected by the CMOS/LVDS pin.
CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin
to enable CMOS mode, tie to OVDD to enable LVDS mode.
Float this pin to enable low power LVDS mode.
OVDD (Pins 31, 37): I/O Interface Digital Power. The range
of OVDD is 1.71V to 2.63V. This supply is nominally set
to the same supply as the host interface (CMOS: 1.8V or
2.5V, LVDS: 2.5V). Bypass OVDD to GND (Pins 32 and 38)
with 0.1µF capacitors.
232014fa
For more information www.linear.com/LTC2320-14
11
LTC2320-14
PIN FUNCTIONS
REFBUFEN (Pin 43): Reference Buffer Output Enable. Tie
to VDD when using the internal reference. Tie to ground
to disable the internal REFOUT1–4 buffers for use with
external voltage references. This pin has a 500k internal
pull-up to VDD.
REFOUT4 (Pin 45): Reference Buffer 4 Output. An
onboard buffer nominally outputs 4.096V to this pin. This
pin is referred to GND and should be decoupled closely to
the pin with a 10µF (X5R, 0805 size) ceramic capacitor.
The internal buffer driving this pin may be disabled by
grounding the REFBUFEN pin. If the buffer is disabled,
an external reference may drive this pin in the range of
1.25V to 5V.
AIN8+, AIN8– (Pins 48, 47): Analog Differential Input Pins.
Full-scale range (AIN8+ – AIN8–) is ±REFOUT4 voltage.
These pins can be driven from VDD to GND.
AIN7+, AIN7– (Pins 51, 50): Analog Differential Input Pins.
Full-scale range (AIN7+ – AIN7–) is ±REFOUT4 voltage.
These pins can be driven from VDD to GND.
Exposed Pad (Pin 53): Ground. Solder this pad to ground.
SDO3 (Pin 29): CMOS Serial Data Output for ADC Channel
3. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from AIN3 on SDO3 in SDR mode, 16 SCK
edges in DDR mode. Supplying more clocks will yield data
from subsequent channels (CH4, CH5, CH6, CH7, CH8,
CH1, CH2).
SDO4 (Pin 30): CMOS Serial Data Output for ADC Channel
4. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from AIN4 on SDO4 in SDR mode, 16 SCK
edges in DDR mode. Supplying more clocks will yield data
from subsequent channels (CH5, CH6, CH7, CH8, CH1,
CH2, CH3).
CLKOUT (Pin 33): Serial Data Clock Output. CLKOUT provides a skew-matched clock to latch the SDO output at the
receiver (FPGA). The logic level is determined by OVDD.
This pin echoes the input at SCK with a small delay.
CMOS DATA OUTPUT OPTION (CMOS/LVDS = LOW)
CLKOUTEN (Pin 34): CLKOUT can be disabled by tying
Pin 34 to OVDD for a small power savings. If CLKOUT is
used, ground this pin.
SDO1 (Pin 27): CMOS Serial Data Output for ADC Channel
1. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from AIN1 on SDO1 in SDR mode, 16 SCK
edges in DDR mode. Supplying more clocks will yield data
from subsequent channels (CH2, CH3, CH4, CH5, CH6,
CH7, CH8).
SDO5 (Pin 35): CMOS Serial Data Output for ADC Channel
5. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from AIN5 on SDO5 in SDR mode, 16 SCK
edges in DDR mode. Supplying more clocks will yield data
from subsequent channels (CH6, CH7, CH8, CH1, CH2,
CH3, CH4).
SDO2 (Pin 28): CMOS Serial Data Output for ADC Channel
2. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from AIN2 on SDO2 in SDR mode, 16 SCK
edges in DDR mode. Supplying more clocks will yield data
from subsequent channels (CH3, CH4, CH5, CH6, CH7,
CH8, CH1).
SDO6 (Pin 36): CMOS Serial Data Output for ADC Channel
6. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from AIN6 on SDO6 in SDR mode, 16 SCK
edges in DDR mode. Supplying more clocks will yield data
from subsequent channels (CH7, CH8, CH1, CH2, CH3,
CH4, CH5).
12
232014fa
For more information www.linear.com/LTC2320-14
LTC2320-14
PIN FUNCTIONS
SDO7 (Pin 39): CMOS Serial Data Output for ADC Channel
7. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from AIN7 on SDO7 in SDR mode, 16 SCK
edges in DDR mode. Supplying more clocks will yield data
from subsequent channels (CH8, CH1, CH2, CH3, CH4,
CH5, CH6).
SDO8 (Pin 40): CMOS Serial Data Output for ADC Channel
8. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 14-bit conversion
data to be read from AIN8 on SDO8 in SDR mode, 16 SCK
edges in DDR mode. Supplying more clocks will yield data
from subsequent channels (CH1, CH2, CH3, CH4, CH5,
CH6, CH7).
SCK (Pin 41): Serial Data Clock Input. The falling edge
of this clock shifts the conversion result MSB first onto
the SDO pins in SDR mode (DDR = LOW). In DDR mode
(SDR/DDR = HIGH) each edge of this clock shifts the
conversion result MSB first onto the SDO pins. The logic
level is determined by OVDD.
DNC (Pin 42): In CMOS mode do not connect this pin.
LVDS DATA OUTPUT OPTION (CMOS/LVDS = HIGH OR
FLOAT)
SDOA+, SDOA– (Pins 27, 28): LVDS Serial Data Output
for ADC Channels 1 and 2. The conversion result is
shifted CH1 MSB first on each falling edge of SCK in SDR
mode and each SCK edge in DDR mode. 32 SCK edges
are required for 14-bit conversion data to be read from
AIN1 and AIN2 on SDOA in SDR mode, 16 SCK edges in
DDR mode. Supplying more clocks will yield data from
subsequent channels (CH3, CH4, CH5, CH6, CH7, CH8).
Terminate with a 100Ω resistor at the receiver (FPGA).
SDOB+, SDOB– (Pins 29, 30): LVDS Serial Data Output
for ADC Channels 3 and 4. The conversion result is
shifted CH3 MSB first on each falling edge of SCK in SDR
mode and each SCK edge in DDR mode. 32 SCK edges
are required for 14-bit conversion data to be read from
AIN3 and AIN4 on SDOB in SDR mode, 16 SCK edges in
DDR mode. Supplying more clocks will yield data from
subsequent channels (CH5, CH6, CH7, CH8, CH1, CH2).
Terminate with a 100Ω resistor at the receiver (FPGA).
CLKOUT+, CLKOUT– (Pins 33, 34): Serial Data Clock
Output. CLKOUT provides a skew-matched clock to latch
the SDO output at the receiver. These pins echo the input
at SCK with a small delay. These pins must be differentially terminated by an external 100Ω resistor at the
receiver (FPGA).
SDOC+, SDOC– (Pins 35, 36): LVDS Serial Data Output
for ADC channels 5 and 6. The conversion result is
shifted CH5 MSB first on each falling edge of SCK in SDR
mode and each SCK edge in DDR mode. 32 SCK edges
are required for 14-bit conversion data to be read from
AIN5 and AIN6 on SDOA in SDR mode, 16 SCK edges in
DDR mode. Supplying more clocks will yield data from
subsequent channels (CH7, CH8, CH1, CH2, CH3, CH4).
Terminate with a 100Ω resistor at the receiver (FPGA).
SDOD+, SDOD– (Pins 39, 40): LVDS Serial Data Output
for ADC Channels 7 and 8. The conversion result is
shifted CH7 MSB first on each falling edge of SCK in SDR
mode and each SCK edge in DDR mode. 32 SCK edges
are required for 14-bit conversion data to be read from
AIN7 and AIN8 on SDOA in SDR mode, 16 SCK edges in
DDR mode. Supplying more clocks will yield data from
subsequent channels (CH1, CH2, CH3, CH4, CH5, CH6).
Terminate with a 100Ω resistor at the receiver (FPGA).
SCK+, SCK– (Pins 41, 42): Serial Data Clock Input. The
falling edge of this clock shifts the conversion result MSB
first onto the SDO pins in SDR mode (SDR/DDR = LOW).
In DDR mode (SDR/DDR = HIGH) each edge of this clock
shifts the conversion result MSB first onto the SDO pins.
These pins must be differentially terminated by an external
100Ω resistor at the receiver (ADC).
232014fa
For more information www.linear.com/LTC2320-14
13
LTC2320-14
FUNCTIONAL BLOCK DIAGRAM
CMOS IO Mode
VDD
(15, 21, 44, 52)
24 CNV
20
19
17
16
AIN1+
AIN1–
AIN2+
AIN2–
+
S/H
–
14-BIT+ SIGN
SAR ADC
MUX
+
S/H
–
REF
+
14
13
11
10
AIN3
AIN3–
AIN4+
AIN4–
42
5
4
2
1
SCK
DNC
AIN5+
AIN5–
AIN6+
AIN6–
51
50
48
47
AIN7
AIN7–
AIN8+
AIN8–
REF
SDO2
SDO3
SDO4
REFOUT2
OUTPUT
CLOCK DRIVER
CLKOUT
CLKOUTEN
27
28
22
29
30
9
33
34
SDR/DDR 23
+
S/H
–
14-BIT+ SIGN
SAR ADC
MUX
+
S/H
–
250μA
×1.7
×3.4
SDO6
SDO6
REFOUT3
14-BIT+ SIGN
SAR ADC
MUX
+
S/H
–
CMOS
I/O
×1
+
S/H
–
REF
8
CMOS
I/O
×1
CMOS
RECEIVERS
REF
+
SDO1
REFOUT1
14-BIT+ SIGN
SAR ADC
MUX
+
S/H
–
CMOS
I/O
×1
+
S/H
–
REF
41
GND
(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)
CMOS
I/O
×1
1.2V INT REF
SDO7
SDO8
REFOUT4
35
36
6
39
40
45
OVDD (31, 37)
REFBUFEN 43
CMOS/LVDS 25
232014 BDa
14
232014fa
For more information www.linear.com/LTC2320-14
LTC2320-14
FUNCTIONAL BLOCK DIAGRAM
LVDS IO Mode
VDD
(15, 21, 44, 52)
24 CNV
20
19
17
16
AIN1+
AIN1–
AIN2+
AIN2–
+
S/H
–
14-BIT+ SIGN
SAR ADC
MUX
+
S/H
–
REF
14
13
11
10
AIN3+
AIN3–
AIN4+
AIN4–
42
5
4
2
1
SCK+
SCK–
LVDS
RECEIVERS
AIN5+
+
S/H
–
AIN5–
AIN6+
AIN6–
50
48
47
AIN7+
AIN7–
AIN8+
AIN8–
REF
SDOA–
SDOB+
SDOB–
REFOUT2
×1
CLKOUT+
CLKOUT–
27
28
22
29
30
9
33
34
SDR/DDR 23
14-BIT+ SIGN
SAR ADC
MUX
+
S/H
–
250μA
×1.7
×3.4
SDOC+
SDOC–
REFOUT3
14-BIT+ SIGN
SAR ADC
MUX
+
S/H
–
LVDS
I/O
×1
+
S/H
–
REF
8
LVDS
I/O
OUTPUT
CLOCK DRIVER
REF
51
SDOA+
REFOUT1
14-BIT+ SIGN
SAR ADC
MUX
+
S/H
–
LVDS
I/O
×1
+
S/H
–
REF
41
GND
(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)
LVDS
I/O
×1
1.2V INT REF
SDOD+
SDOD–
REFOUT4
35
36
6
39
40
45
OVDD (31, 37)
REFBUFEN 43
CMOS/LVDS 25
232014 BDb
232014fa
For more information www.linear.com/LTC2320-14
15
LTC2320-14
TIMING DIAGRAM
SDR Mode, CMOS (Reading 1 Channel per SDO)
SAMPLE N
CNV
SAMPLE N+1
CONVERT
ACQUIRE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
CLKOUT
SDO1
Hi-Z
Hi-Z
Hi-Z
DONT CARE
D14
D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
D14
CHANNEL 1
CONVERSION N
SDO8
Hi-Z
DONT CARE
D14
D13 D12 D11 D10 D9
D8
D7
D6
Hi-Z
CHANNEL 2
CONVERSION N
D5
D4
D3
D2
D1
D0
0
D14
CHANNEL 8
CONVERSION N
Hi-Z
CHANNEL 1
CONVERSION N
232014 TD01
DDR Mode, CMOS (Reading 1 Channel per SDO)
SAMPLE N
CNV
SAMPLE N+1
CONVERT
ACQUIRE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
CLKOUT
SDO1
Hi-Z
Hi-Z
Hi-Z
DONT CARE
D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CHANNEL 1
CONVERSION N
SDO8
Hi-Z
DONT CARE
D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D14
Hi-Z
CHANNEL 2
CONVERSION N
D4
D3
CHANNEL 8
CONVERSION N
D2
D1
D0
D14
Hi-Z
CHANNEL 1
CONVERSION N
232014 TD02
16
232014fa
For more information www.linear.com/LTC2320-14
LTC2320-14
TIMING DIAGRAM
SDR Mode, LVDS (Reading 2 Channels per SDO Pair)
SAMPLE N
CNV
SAMPLE N+1
CONVERT
ACQUIRE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
17
18
19
20
21
22
23
24
25
D14 D13 D12 D11 D10 D9
D8
D7
D6
26
27
28
29
30
31 32
SCK
CLKOUT
SDOA
DONT CARE
D14
CHANNEL 1
CONVERSION N
SDOD
DONT CARE
D14
D13 D12 D11 D10 D9
D8
D7
D6
D5
D5
D4
D3 D2
D1 D0
0
D14
CHANNEL 2
CONVERSION N
D4
D3
D2
D1
D0
0
D14 D13 D12 D11 D10 D9
D8
CHANNEL 7
CONVERSION N
D7
D6
D5
CHANNEL 3
CONVERSION N
D4
D3 D2
D1 D0
0
D14
CHANNEL 8
CONVERSION N
CHANNEL 1
CONVERSION N
232014 TD03
DDR Mode, LVDS (Reading 2 Channels per SDO Pair)
SAMPLE N
CNV
SAMPLE N+1
ACQUIRE
CONVERT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
17
18
19
20
21
22 23
24
25
D7
D6
26
27
28
29
30
31 32
SCK
CLKOUT
SDOA
DONT CARE
D14 D13 D12 D11 D10 D9
D8
CHANNEL 1
CONVERSION N
SDOD
DONT CARE
D14
D13 D12 D11 D10 D9
D8
D7
D6
D5
D5
D4
D3 D2
D1 D0
0
D14
CHANNEL 2
CONVERSION N
D4
D3
D2
D1
D0
0
D14 D13 D12 D11 D10 D9
CHANNEL 7
CONVERSION N
D8
D7
D6
D5
CHANNEL 8
CONVERSION N
CHANNEL 3
CONVERSION N
D4
D3 D2
D1 D0
0
D14
CHANNEL 1
CONVERSION N
232014 TD04
232014fa
For more information www.linear.com/LTC2320-14
17
LTC2320-14
APPLICATIONS INFORMATION
The LTC2320-14 is a low noise, high speed 14-bit successive approximation register (SAR) ADC with differential
inputs and a wide input common mode range. Operating
from a single 3.3V or 5V supply, the LTC2320-14 has a
4VP-P or 8VP-P differential input range, making it ideal for
applications which require a wide dynamic range. The
LTC2320-14 achieves ±1LSB INL typical, no missing
codes at 14 bits and 81dB SNR.
The LTC2320-14 has an onboard reference buffer and
low drift (20ppm/°C max) 4.096V temperature-compensated reference. The LTC2320-14 also has a high speed
SPI-compatible serial interface that supports CMOS or
LVDS. The fast 1.5Msps per channel throughput with no
latency makes the LTC2320-14 ideally suited for a wide
variety of high speed applications. The LTC2320-14 dissipates only 20mW per channel. Nap and sleep modes
are also provided to reduce the power consumption
of the LTC2320-14 during inactive periods for further
power savings.
inputs, the transfer function spans 215 codes. When
driven by pseudo differential inputs, the transfer function spans 214 codes.
Table 1: Code Ranges for the Analog Input Operational Modes
MODE
Span (VIN+ – VIN–) Min Code
Fully Differential
–REFOUT to
+REFOUT
110 0000 0000 001 1111 1111
0000
1111
Pseudo-Differential 0 to REFOUT
Unipolar
000 0000 0000 011 1111 1111
0000
1111
011 1111 1111 1111
011 1111 1111 1110
000 0000 0000 0001
000 0000 0000 0000
111 1111 1111 1111
100 0000 0000 0001
100 0000 0000 0000
CONVERTER OPERATION
–REFOUT/2
The LTC2320-14 operates in two phases. During the
acquisition phase, the sample capacitor is connected to
the analog input pins AIN+ and AIN – to sample the differential analog input voltage, as shown in Figure 3. A falling
edge on the CNV pin initiates a conversion. During the
conversion phase, the 14-bit CDAC is sequenced through
a successive approximation algorithm effectively comparing the sampled input with binary-weighted fractions
of the reference voltage (e.g., VREFOUT/2, VREFOUT/4 …
VREFOUT/32768) using a differential comparator. At the
end of conversion, a CDAC output approximates the sampled analog input. The ADC control logic then prepares
the 14-bit digital output code for serial transfer.
Max Code
100 0000 0000 011 1111 1111
0000
1111
Pseudo-Differential –REFOUT/2 to
Bipolar
+REFOUT/2
OUTPUT CODE (TWO’S COMPLEMENT)
OVERVIEW
1LSB = 2 • REFOUT
32768
–1 0 1
LSB
LSB
INPUT VOLTAGE (V)
REFOUT/2
–1LSB
232014 F02
Figure 2. LTC2320-14 Transfer Function
Analog Input
TRANSFER FUNCTION
The differential inputs of the LTC2320-14 provide great
flexibility to convert a wide variety of analog signals with
no configuration required. The LTC2320-14 digitizes the
difference voltage between the AIN+ and AIN – pins while
supporting a wide common mode input range. The analog
input signals can have an arbitrary relationship to each
other, provided that they remain between VDD and GND.
The LTC2320-14 can also digitize more limited classes
of analog input signals such as pseudo-differential unipolar/bipolar and fully differential with no configuration
required.
The LTC2320-14 digitizes the full-scale voltage of 2 •
REFOUT into 215 levels, resulting in a 15-bit resolution
size of 250µV with REFBUF = 4.096V. The ideal transfer function is shown in Figure 2. The output data is in
2’s complement format. When driven by fully differential
The analog inputs of the LTC2320-14 can be modeled
by the equivalent circuit shown in Figure 3. The back-toback diodes at the inputs form clamps that provide ESD
protection. In the acquisition phase, 10pF (CIN) from
the sampling capacitor in series with approximately
18
232014fa
For more information www.linear.com/LTC2320-14
LTC2320-14
APPLICATIONS INFORMATION
wide common mode input range relaxes the accuracy
requirements of any signal conditioning circuits prior
to the analog inputs.
VDD
RON
15Ω
AIN+
CIN
10pF
Pseudo-Differential Bipolar Input Range
BIAS
VOLTAGE
VDD
RON
15Ω
AIN–
CIN
10pF
232014 F03
Figure 3. The Equivalent Circuit for the Differential
Analog Input of the LTC2320-14
15Ω (RON) from the on-resistance of the sampling
switch is connected to the input. Any unwanted signal
that is common to both inputs will be reduced by the
common mode rejection of the ADC sampler. The inputs
of the ADC core draw a small current spike while charging the CIN capacitors during acquisition.
The pseudo-differential bipolar configuration represents
driving one of the analog inputs at a fixed voltage, typically VREF /2, and applying a signal to the other AIN pin. In
this case the analog input swings symmetrically around
the fixed input yielding bipolar two’s complement output
codes with an ADC span of half of full-scale. This configuration is illustrated in Figure 4, and the corresponding
transfer function in Figure 5. The fixed analog input pin
need not be set at VREF /2, but at some point within the
VDD rails allowing the alternate input to swing symmetrically around this voltage. If the input signal (AIN+ – AIN –)
swings beyond ±REFOUT1,2,3,4/2, valid codes will be
generated by the ADC and must be clamped by the user,
if necessary.
Pseudo-Differential Unipolar Input Range
Single-Ended Signals
Single-ended signals can be directly digitized by the
LTC2320-14. These signals should be sensed pseudodifferentially for improved common mode rejection. By
connecting the reference signal (e.g., ground sense) of
the main analog signal to the other AIN pin, any noise or
disturbance common to the two signals will be rejected
by the high CMRR of the ADC. The LTC2320-14 flexibility handles both pseudo-differential unipolar and
bipolar signals, with no configuration required. The
VREF
LT1819
+
–
0V
The pseudo-differential unipolar configuration represents
driving one of the analog inputs at ground and applying a
signal to the other AIN pin. In this case, the analog input
swings between ground and VREF yielding unipolar two’s
complement output codes with an ADC span of half of fullscale. This configuration is illustrated in Figure 6, and the
corresponding transfer function in Figure 7. If the input
signal (AIN+ – AIN –) swings negative, valid codes will be
generated by the ADC and must be clamped by the user,
if necessary.
VREF
0V
LTC2320-14
25Ω
AIN1+
REFOUT1
VREF
REF
220pF
10k
VREF /2
10k
1µF
+
–
VREF /2
25Ω
AIN1–
SDO1
CLKOUT
SCK
ONLY CHANNEL 1 SHOWN FOR CLARITY
10µF
1µF
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
232014 F04
Figure 4. Pseudo-Differential Bipolar Application Circuit
232014fa
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19
LTC2320-14
APPLICATIONS INFORMATION
ADC CODE
(2’s COMPLEMENT)
16383
8191
–VREF
–VREF /2
0
VREF /2
AIN
(AIN+ – AIN–)
VREF
DOTTED REGIONS AVAILABLE
–8192
232014 F05
–16384
Figure 5. Pseudo-Differential Bipolar Transfer Function
VREF
0V
LT1818
VREF
+
–
0V
LTC2320-14
25Ω
AIN1+
REF
220pF
25Ω
REFOUT1
AIN1–
SDO1
CLKOUT
SCK
10µF
1µF
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
232014 F06
Figure 6. Pseudo-Differential Unipolar Application Circuit
ADC CODE
(2’s COMPLEMENT)
16383
8191
–VREF
–VREF /2
–8192
–16384
0
VREF /2
VREF
AIN
(AIN+ – AIN–)
DOTTED REGIONS AVAILABLE
232014 F07
Figure 7. Pseudo-Differential Unipolar Transfer Function
20
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LTC2320-14
APPLICATIONS INFORMATION
Single-Ended-to-Differential Conversion
While single-ended signals can be directly digitized as
previously discussed, single-ended to differential conversion circuits may also be used when higher dynamic range
is desired. By producing a differential signal at the inputs
of the LTC2320-14, the signal swing presented to the ADC
is maximized, thus increasing the achievable SNR.
±REFOUT1,2,3,4. The common mode input voltage can
span the entire supply range up to VDD, limited by the
input signal swing. The fully-differential configuration is
illustrated in Figure 10, with the corresponding transfer
function illustrated in Figure 11.
INPUT DRIVE CIRCUITS
The LT®1819 high speed dual operational amplifier is
recommended for performing single-ended-to-differential conversions, as shown in Figure 8. In this case, the
first amplifier is configured as a unity-gain buffer and the
single-ended input signal directly drives the high impedance input of this amplifier.
A low impedance source can directly drive the high impedance inputs of the LTC2320-14 without gain error. A high
impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is
important even for DC inputs, because the ADC inputs
draw a current spike during acquisition.
Fully-Differential Inputs
For best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2320-14. The amplifier
provides low output impedance to minimize gain error
and allows for fast settling of the analog signal during
the acquisition phase. It also provides isolation between
the signal source and the ADC inputs, which draw a small
current spike during acquisition.
To achieve the best distortion performance of the
LTC2320‑14, we recommend driving a fully-differential
signal through LT1819 amplifiers configured as two unitygain buffers, as shown in Figure 9. This circuit achieves
the full data sheet THD specification of –90dB at input
frequencies up to 500kHz. A fully-differential input signal can span the maximum full-scale of the ADC, up to
VREF
0V
200Ω
VREF /2
VREF
LT1819
+
–
VREF
+
–
VREF
200Ω
0V
0V
VREF
0V
0V
LT1819
+
–
VREF
+
–
VREF
0V
0V
232014 F09
232014 F08
Figure 8. Single-Ended to Differential Driver
Figure 9. LT1819 Buffering a Fully-Differential Signal Source
232014fa
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21
LTC2320-14
APPLICATIONS INFORMATION
VREF
0V
LT1819
VREF
+
–
0V
LTC2320-14
25Ω
AIN1+
REFOUT1
REF
220pF
VREF
0V
VREF
+
–
0V
25Ω
AIN1–
SDO1
CLKOUT
SCK
ONLY CHANNEL 1 SHOWN FOR CLARITY
10µF
1µF
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
232014 F10
Figure 10. Fully-Differential Application Circuit
ADC CODE
(2’s COMPLEMENT)
16383
8192
–VREF
–VREF /2
0
VREF /2
VREF
AIN
(AINn + – AINn –)
–8192
–16384
232014 F11
Figure 11. Fully-Differential Transfer Function
22
232014fa
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LTC2320-14
APPLICATIONS INFORMATION
Input Filtering
ADC REFERENCE
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC
noise and distortion. Noisy input signals should be filtered
prior to the buffer amplifier input with a low bandwidth
filter to minimize noise. The simple 1-pole RC lowpass filter shown in Figure 12 is sufficient for many applications.
Internal Reference
The sampling switch on-resistance (RON) and the sample
capacitor (CIN) form a second lowpass filter that limits
the input bandwidth to the ADC core to 110MHz. A buffer
amplifier with a low noise density must be selected to
minimize the degradation of the SNR over this bandwidth.
High quality capacitors and resistors should be used in
the RC filters since these components can add distortion. NPO and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
SINGLE-ENDED
INPUT SIGNAL
The LTC2320-14 has an on-chip, low noise, low
drift (20ppm/°C max), temperature compensated bandgap reference. It is internally buffered and is available
at REF (Pin 8). The reference buffer gains the internal
reference voltage to 4.096V for supply voltages VDD = 5V
and to 2.048V for VDD = 3.3V. The REF pin also drives
the four internal reference buffers with a current limited
output (250μA) so it may be easily overdriven with an
external reference in the range of 1.25V to 5V. Bypass
REF to GND with a 1μF (X5R, 0805 size) ceramic capacitor
to compensate the reference buffer and minimize noise.
The 1μF capacitor should be as close as possible to the
LTC2320-14 package to minimize wiring inductance. The
voltage on the REF pin must be externally buffered if used
for external circuitry.
IN+
50Ω
IN–
3.3nF
BW = 1MHz
LTC2320
SINGLE-ENDED
TO DIFFERENTIAL
DRIVER
232014 F12
Figure 12. Input Signal Chain
Table 2. Reference Configurations and Ranges
REFERENCE CONFIGURATION
VDD
Internal Reference with Internal Buffers
Common External Reference with Internal Buffer (REF Pin
Externally Overdriven)
External Reference with REF Buffers Disabled
REFBUFEN
REF PIN
REFOUT1,2,3,4
PIN
DIFFERENTIAL INPUT
RANGE PIN
5V
5V
4.096V
4.096V
±4.096V
3.3V
3.3V
2.048V
2.048V
±2.048V
5V
5V
1.25V to 5V
1.25V to 3.3V
±1.25V to ±5V
3.3V
3.3V
1.25V to 5V
1.25V to 3.3V
±1.25V to ±3.3V
5V
0V
4.096V
1.25V to 5V
±1.25V to ±5V
3.3V
0V
2.048V
1.25V to 3.3V
±1.25V to ±3.3V
232014fa
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23
LTC2320-14
APPLICATIONS INFORMATION
External Reference
The internal REFOUT1,2,3,4 buffers can also be overdriven from 1.25V to 5V with an external reference at
REFOUT1,2,3,4 as shown in Figure 13 (c). To do so,
REFBUFEN must be grounded to disable the REF buffers.
A 55k internal resistance loads the REFOUT1,2,3,4 pins
when the REF buffers are disabled. To maximize the input
signal swing and corresponding SNR, the LTC6655-5 is
VDD
3.3V TO 5V
REF
LTC2320-14
LTC6655-4.096
REFBUFEN
VIN
SHDN
REF
VOUT_F
VOUT_S
10µF
REFOUT1
10µF
REFOUT2
10µF
LTC2320-14
10µF
0.1µF
REFOUT1
10µF
VDD
+5V
5V TO
13.2V
REFBUFEN
1µF
recommended when overdriving REFOUT. The LTC6655-5
offers the same small size, accuracy, drift and extended
temperature range as the LTC6655-4.096. By using a 5V
reference, a higher SNR can be achieved. We recommend
bypassing the LTC6655-5 with a 10μF ceramic capacitor
(X5R, 0805 size) close to each of the REFOUT1,2,3,4 pins.
If the REF pin voltage is used as a REFOUT reference when
REFBUFEN is connected to GND, it should be buffered
externally.
REFOUT2
10µF
REFOUT3
REFOUT3
10µF
REFOUT4
10µF
GND
10µF
232014 F13a
REFOUT4
GND
232014 F13b
(13a) LTC2320-14 Internal Reference Circuit
(13b) LTC2320-14 with a Shared External Reference Circuit
+5V
VDD
REFBUFEN
REF
1µF
5V TO 13.2V
LTC6655-4.096
VIN
VOUT_F
SHDN VOUT_S
REFOUT1
10µF
0.1µF
5V TO 13.2V
LTC2320-14
LTC6655-2.048
VIN
VOUT_F
SHDN VOUT_S
REFOUT2
10µF
0.1µF
5V TO 13.2V
LTC6655-2.5
VIN
VOUT_F
SHDN VOUT_S
REFOUT3
10µF
0.1µF
5V TO 13.2V
LTC6655-3
VIN
VOUT_F
SHDN VOUT_S
REFOUT4
10µF
0.1µF
GND
232014 F13c
(13c) LTC2320-14 with Different External Reference Voltages
Figure 13. Reference Connections
24
232014fa
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LTC2320-14
APPLICATIONS INFORMATION
Internal Reference Buffer Transient Response
DYNAMIC PERFORMANCE
The REFOUT1,2,3,4 pins of the LTC2320-14 draw charge
(QCONV) from the external bypass capacitors during each
conversion cycle. If the internal reference buffer is overdriven, the external reference must provide all of this charge
with a DC current equivalent to IREF = QCONV/tCYC.
Thus, the DC current draw of IREFOUT1,2,3,4 depends
on the sampling rate and output code. In applications
where a burst of samples is taken after idling for long
periods, as shown in Figure 14 , IREFBUF quickly goes from
approximately ~75µA to a maximum of 500µA for REFOUT
= 5V at 1.5Msps. This step in DC current draw triggers a
transient response in the external reference that must be
considered since any deviation in the voltage at REFOUT
will affect the accuracy of the output code. If an external
reference is used to overdrive REFOUT1,2,3,4, the fast
settling LTC6655 reference is recommended.
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2320-14 provides
guaranteed tested limits for both AC distortion and noise
measurements.
CNV
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is bandlimited
to frequencies from above DC and below half the sampling
frequency. Figure 16 shows that the LTC2320-14 achieves
a typical SINAD of 80dB at a 1.5MHz sampling rate with
a 500kHz input.
Signal-to-Noise Ratio (SNR)
IDLE
PERIOD
232014 F14
Figure 14. CNV Waveform Showing Burst Sampling
16384
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 16 shows
that the LTC2320-14 achieves a typical SNR of 81dB at a
1.5MHz sampling rate with a 500kHz input.
SMPL
0
8192
4.096V RANGE
4096
0
IN+ = 1.5MHz SQUARE WAVE
IN– = 0V
–4096
–20 –10 0 10 20 30 40 50 60 70 80 90
SETTLING TIME (ns)
232014 F15
AMPLITUDE (dBFS)
OUTPUT CODE (LSB)
12288
IN
SNR = 81.1dB
THD = –90.2dB
–20 SINAD = 80.8dB
SFDR = 94.7dB
–40
–60
–80
–100
–120
–140
Figure 15. Transient Response of the LTC2320-14
0
0.1
0.2 0.3 0.4 0.5
FREQUENCY (MHz)
0.6
0.7
232014 F16
Figure 16. 32k Point FFT of the LTC2320-14
232014fa
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25
LTC2320-14
APPLICATIONS INFORMATION
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the
RMS sum of all harmonics of the input signal to the
fundamental itself. The out-of-band harmonics alias into
the frequency band between DC and half the sampling
frequency (fSMPL /2). THD is expressed as:
THD = 20 log
V2 2 + V3 2 + V 4 2 + …+ VN
2
TIMING AND CONTROL
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2320-14 requires two power supplies: the 3.3V
to 5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2320-14 to communicate with any digital
logic operating between 1.8V and 2.5V. When using LVDS
I/O, the OVDD supply must be set to 2.5V.
Power Supply Sequencing
The LTC2320-14 does not have any specific power supply sequencing requirements. Care should be taken to
adhere to the maximum voltage relationships described in
the Absolute Maximum Ratings section. The LTC2320‑14
has a power-on-reset (POR) circuit that will reset the
LTC2320-14 at initial power-up or whenever the power
33
SUPPLY CURRENT (mA)
31
29
VDD = 5V
27
VDD = 3.3V
23
21
0
0.3
0.6
0.9
1.2
SAMPLE FREQUENCY (Msps)
1.5
232014 F17
Figure 17. Power Supply Current of the LTC2320-14
Versus Sampling Rate
26
CNV Timing
The LTC2320-14 sampling and conversion is controlled
by CNV. A rising edge on CNV will start sampling and the
falling edge starts the conversion and readout process.
The conversion process is timed by the SCK input clock.
For optimum performance, CNV should be driven by a
clean low jitter signal. The Typical Application at the back
of the data sheet illustrates a recommended implementation to reduce the relatively large jitter from an FPGA
CNV pulse source. Note the low jitter input clock times
the falling edge of the CNV signal. The rising edge jitter
of CNV is much less critical to performance. The typical
pulse width of the CNV signal is 30ns with < 1.5ns rise
and fall times at a 1.5Msps conversion rate.
SCK Serial Data Clock Input
In SDR mode (SDR/DDR Pin 23 = GND), the falling edge
of this clock shifts the conversion result MSB first onto
the SDO pins. A 100MHz external clock must be applied at
the SCK pin to achieve 1.5Msps throughput using all eight
SDO outputs. In DDR mode (SDR/DDR Pin 23 = OVDD),
each input edge of SCK shifts the conversion result MSB
first onto the SDO pins. A 50MHz external clock must be
applied at the SCK pin to achieve 1.5Msps throughput
using all eight SDO1 through SDO8 outputs.
CLKOUT Serial Data Clock Output
25
19
supply voltage drops below 2V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 10ms after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
The CLKOUT output provides a skew-matched clock to
latch the SDO output at the receiver. The timing skew
of the CLKOUT and SDO outputs are matched. For high
throughput applications, using CLKOUT instead of SCK to
capture the SDO output eases timing requirements at the
receiver. For low throughput speed applications, CLKOUT
can be disabled by tying Pin 34 to OVDD.
232014fa
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LTC2320-14
APPLICATIONS INFORMATION
Nap/Sleep Modes
Nap mode is a method to save power without sacrificing
power-up delays for subsequent conversions. Sleep mode
has substantial power savings, but a power-up delay is
incurred to allow the reference and power systems to
become valid. To enter nap mode on the LTC2320-14,
the SCK signal must be held high or low and a series
of two CNV pulses must be applied. This is the case for
both CMOS and LVDS modes. The second rising edge of
CNV initiates the nap state. The nap state will persist until
either a single rising edge of SCK is applied, or further
CNV pulses are applied. The SCK rising edge will put the
LTC2320-14 back into the operational (full-power) state.
When in nap mode, two additional pulses will put the
LTC2320-14 in sleep mode. When configured for CMOS
I/O operation, a single rising edge of SCK can return the
LTC2320-14 into operational mode. A 10ms delay is necessary after exiting sleep mode to allow the reference buffer to recharge the external filter capacitor. In LVDS mode,
exit sleep mode by supplying a fifth CNV pulse. The fifth
pulse will return the LTC2320-14 to operational mode,
and further SCK pulses will keep the part from re-entering
nap and sleep modes. The fifth SCK pulse also works in
CMOS mode as a method to exit sleep. In the absence of
SCK pulses, repetitive CNV pulses will cycle the LTC232014 between operational, nap and sleep modes indefinitely.
Refer to the timing diagrams in Figure 18, Figure 19, Figure 20
and Figure 21 for more detailed timing information about
sleep and nap modes.
DIGITAL INTERFACE
The LTC2320-14 features a serial digital interface that
is simple and straightforward to use. The flexible OVDD
supply allows the LTC2320-14 to communicate with any
digital logic operating between 1.8V and 2.5V. In addition to a standard CMOS SPI interface, the LTC2320-14
provides an optional LVDS SPI interface to support low
noise digital design. The CMOS /LVDS pin is used to select
the digital interface mode. The SCK input clock shifts the
conversion result MSB first on the SDO pins. CLKOUT
provides a skew-matched clock to latch the SDO output
at the receiver. The timing skew of the CLKOUT and SDO
outputs are matched. For high throughput applications,
using CLKOUT instead of SCK to capture the SDO output
eases timing requirements at the receiver. In CMOS mode,
use the SDO1 – SDO8, and CLKOUT pins as outputs. Use
the SCK pin as an input. In LVDS mode, use the SDOA+/
SDOA– through SDOD+/SDOD– and CLKOUT+/CLKOUT–
pins as differential outputs. Each LVDS lane yields two
channels worth of data: SDOA yields CH1 and CH2 data,
SDOB yields CH3 and CH4 data, SDOC yields CH5 and
CH6 data and SDOD yields CH7 and CH8 data. These pins
must be differentially terminated by an external 100Ω
resistor at the receiver (FPGA). The SCK+/SCK– pins are
differential inputs and must be terminated differentially by
an external 100Ω resistor at the receiver(ADC).
SDR/DDR Modes
The LTC2320-14 has an SDR (single data rate) and DDR
(double data rate) mode for reading conversion data from
the SDO pins. In both modes, CLKOUT is a delayed version of SCK. In SDR mode, each negative edge of SCK
shifts the conversion data out the SDO pins. In DDR
mode, each edge of the SCK input shifts the conversion
data out. In DDR mode, the required SCK frequency is half
of what is required in SDR mode. Tie SDR/DDR to ground
to configure for SDR mode and to OVDD for DDR mode.
The CLKOUT signal is a delayed version of the SCK input
and is phase aligned with the SDO data. In SDR mode, the
SDO transitions on the falling edge of CLKOUT as illustrated in Figure 21. We recommend using the rising edge
of CLKOUT to latch the SDO data into the FPGA register
in SDR mode. In DDR mode, The SDO transitions on each
input edge of SCK. We recommend using the CLKOUT rising and falling edges to latch the SDO data into the FPGA
registers in DDR mode. Since CLKOUT and SDO data is
phase aligned, the SDO signals will need to be digitally
delayed in the FPGA to provide adequate setup and hold
timing margins in DDR mode.
232014fa
For more information www.linear.com/LTC2320-14
27
LTC2320-14
APPLICATIONS INFORMATION
CNV
1
2
FULL POWER MODE
NAP MODE
SCK
HOLD STATIC HIGH OR LOW
WAKE ON 1ST SCK EDGE
SDO1 – 8
Z
Z
232014 F18
Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK
REFOUT1 – 4
REFOUT
RECOVERY
4.096V
4.096V
tWAKE
CNV
1
2
3
4
NAP MODE
SCK
SLEEP MODE
FULL POWER MODE
HOLD STATIC HIGH OR LOW
WAKE ON 1ST SCK EDGE
SDO1 – 8
Z
Z
Z
Z
232014 F19
Figure 19. CMOS Mode SLEEP and WAKE Using SCK
REFOUT1 – 4
REFOUT
RECOVERY
4.096V
4.096V
tWAKE
CNV
1
2
3
4
NAP MODE
SCK
SDO1 – 8
WAKE ON 5TH
CNV EDGE
5
SLEEP MODE
FULL POWER MODE
HOLD STATIC HIGH OR LOW
Z
Z
Z
Z
Z
232014 F20
Figure 20. LVDS and CMOS Mode SLEEP and WAKE Using CNV
28
232014fa
For more information www.linear.com/LTC2320-14
LTC2320-14
APPLICATIONS INFORMATION
SDR MODE TIMING
DDR MODE TIMING
tCYC
tCNVH
tCYC
tCONV
tREADOUT
tCNVH
tDSCKCNVH
CNV
1
2
3
tREADOUT
tDSCKCNVH
CNV
tSCKH
tSCK
SCK
tCONV
tSCKH
tSCK
14
15
SCK
16
1
2
3
CLKOUT
1
2
3
14
15
CLKOUT
16
1
tDSCKCLKOUT
SDO
HI-Z
D15
D14
D13
15
D2
D1
D0
D15
2
3
14
tDSCKCLKOUT
tDCNVSDOZ
tHSDO
tDCNVSDOV
14
16
tSCKL
tSCKL
tDCNVSDOV
HI-Z
SDO
HI-Z
D14
D13
D2
16
tDCNVSDOZ
tHSDO
D15
15
D1
D0
D15
HI-Z
232014 F21
Figure 21. LTC2320-14 Timing Diagram
232014fa
For more information www.linear.com/LTC2320-14
29
LTC2320-14
APPLICATIONS INFORMATION
Multiple Data Lanes
The LTC2320-14 has up to eight SDO data lanes in CMOS
mode and four SDO lanes in LVDS mode. In CMOS mode,
the number of possible data lanes range from eight
(SDO1 – SDO8), four (SDO1, SDO3, SDO5 and SDO7), two
(SDO1 and SDO5) and one (SDO1). Generally, the more
data lanes used, the lower the required SCK frequency.
When using less than eight lanes in CMOS mode, there is a
limit on the maximum possible conversion frequency (see
Table 3). Each SDO pin will hold the MSB of the conversion
data. In DDR mode you can use a SCK frequency half of
SDR mode. See Table 3 for examples of various possibilities and the resulting SCK frequency required.
Multiple Data Lanes
The LTC2320-14 has up to eight serial data output data
lanes in CMOS mode and four serial data output lane pairs
in LVDS mode. The data on each lane consists of 14-bit
conversion results presented MSB first.
CMOS
In CMOS mode, the number of possible data lanes range
from eight (SDO1 – SDO8), four (SDO1, SDO3, SDO5 and
SDO7), two (SDO1 and SDO5) and one (SDO1). As suggested in the CMOS Timing Diagrams, each SDO lane outputs the conversion results for all analog input channels in
LTC2320-14
2.5V
2.5V
CMOS/LVDS
Applications that cannot accommodate the full eight lanes
of serial data may employ fewer lanes without reconfiguring the LTC2320-14. For example, capturing the first two
conversion results (32 SCK cycles total in SDR mode and
32 SCK edges in DDR mode) from SDO1, SDO3, SDO5, and
SDO7 provides data for analog input channels 1 and 2, 3
and 4, 5 and 6, and 7 and 8, respectively, using four output
lanes. Similarly, capturing the first four conversion results
(64 SCK cycles total in SDR mode and 64 SCK edges in
DDR mode) from SDO1 and SDO5 provides data for analog input channels 1 to 4 and 5 to 8, respectively, using
two output lanes. If only one lane can be accommodated,
capturing the first eight conversion results (128 SCK cycles
total in SDR mode and 128 SCK edges in DDR mode)
from SDO1 provides data for all analog input channels.
Generally, the more data lanes used, the lower the required
SCK frequency. When using less than eight lanes in CMOS
mode, there is a limit on the maximum possible conversion
FPGA OR DSP
OVDD
SCK+
SCK–
a sequential circular manner. For example, the first conversion result on SDO1 corresponds to analog input channel 1,
followed by the conversion results for channels 2 through
8. The data output on SDO1 then wraps back to channel
1 and this pattern repeats indefinitely. Other SDO lanes
follow a similar circular pattern except the first conversion
result presented on each lane corresponds to its associated
analog input channel.
LTC2320-14
+
–
100Ω
SCK+
SCK–
SDOD+
SDOD–
100Ω
+
–
SDOC+
SDOC–
100Ω
+
–
CLKOUT+
CLKOUT –
100Ω
+
–
SDOB+
SDOB–
100Ω
+
–
SDOB+
SDOB–
SDOA+
SDOA–
100Ω
+
–
SDOA+
SDOA–
CNV
FPGA OR DSP
+
–
100Ω
SDOD+
SDOD–
SDOC+
SDOC–
2.5V
CMOS/LVDS
RETIMING
FLIP-FLOP
CLKOUT+
CLKOUT –
CNV
232014 F22
Figure 22. LTC2320-14 Using the LVDS Interface
30
2.5V
OVDD
100Ω
+
–
100Ω
+
–
RETIMING
FLIP-FLOP
232014 F23
Figure 23. LTC2320-14 Using the LVDS Interface with One Lane
232014fa
For more information www.linear.com/LTC2320-14
LTC2320-14
APPLICATIONS INFORMATION
frequency. See Table 3 for examples of various possibilities
and the resulting SCK frequency required.
and 128 SCK edges in DDR mode) from SDOA provides
data for all analog input channels. Generally, the more
data lanes used, the lower the required SCK frequency.
When using less than four lanes in LVDS mode, there is
a limit on the maximum possible conversion frequency.
See Table 3 for examples of various possibilities and the
resulting SCK frequency required.
LVDS
In LVDS mode, the number of possible data lane pairs
range from four (SDOA – SDOD), two (SDOA and SDOC)
and one (SDOA). As suggested in the LVDS Timing
Diagrams, each SDO lane pair outputs the conversion
results for all analog input channels in a sequential circular manner. For example, the first conversion result on
SDOA corresponds to analog input channel pair 1 and 2,
followed by the conversion results for channels 3 through
8. The data output on SDOA then wraps back to channel
1 and this pattern repeats indefinitely. Other SDO lanes
follow a similar circular pattern except the first conversion
result presented on each lane corresponds to its associated analog input channel pairs (SDOA: analog inputs 1
and 2, SDOB: analog inputs 3 and 4, SDOC: analog inputs
5 and 6 and SDOD: analog inputs 7 and 8).
BOARD LAYOUT
To obtain the best performance from the LTC2320-14,
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals adjacent to analog signals or underneath
the ADC.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common
returns for these bypass capacitors are essential to the
low noise operation of the ADC. A single solid ground
plane is recommended for this purpose. When possible,
screen the analog input traces using ground.
Applications that cannot accommodate the full four lanes
of serial data may employ fewer lanes without reconfiguring the LTC2320-14. For example, capturing the first four
conversion results (64 SCK cycles total in SDR mode
and 64 SCK edges in DDR mode) from SDOA and SDOC
provides data for analog input channels 1 through 4, and
5 through 8, respectively, using two output lanes. If only
one lane can be accommodated, capturing the first eight
conversion results (128 SCK cycles total in SDR mode
Recommended Layout
For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer
to DC2395A, the evaluation kit for the LTC2320-14.
Table 3. Conversion Frequency for Various I/O Modes
I/O MODE
CMOS
CMOS/
LVDS PIN
GND
(CMOS)
SDR/
DDR PIN
GND (SDR)
OVDD (DDR)
OVDD (DDR)
SDO1 – 8
LANES
SDO1 – SDO8
SDO1 – SDO8
SDO1, SDO3,
SDO5, SDO7
SDO1
SDOA – D
LANES
SCK FREQ
(MHz)
100
50
CLKOUT FREQ
(MHz)
100
50
SCK
CYCLES
16
8
50
50
16
100
200
100
150
300
100
200
100
150
300
128
32
16
32
128
GND (SDR)
GND (SDR)
SDOA – SDOD
OVDD (DDR)
SDOA – SDOD
OVDD
LVDS
(LVDS)
SDOA, SDOC
OVDD (DDR)
GND (SDR)
SDOA
Notes: Conversion Period (SDR) = tCNV_MIN + tCONV_MAX + (128/(Lanes • fSCK))
Conversion Period (DDR) = tCNV_MIN + tCONV_MAX + (64/(Lanes • fSCK))
Conversion Frequency = 1/Conversion Period
SCK Cycles (SDR) = 128/Lanes
SCK Cycles (DDR) = 64/Lanes
OVDD
1.8V to 2.5V
2.5V
CONVERSION
FREQUENCY
(Msps/CH)
1.5
1.5
1.25
0.5
1.5
1.5
1.4
1.0
232014fa
For more information www.linear.com/LTC2320-14
31
LTC2320-14
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2320-14#packaging for the most recent package drawings.
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
Package
(Reference LTCUKG
DWG
# 05-08-1729 Rev Ø)
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
7.50 ±0.05
6.10 ±0.05
5.50 REF
(2 SIDES)
0.70 ±0.05
6.45 ±0.05
6.50 REF 7.10 ±0.05 8.50 ±0.05
(2 SIDES)
5.41 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
0.00 – 0.05
5.50 REF
(2 SIDES)
51
52
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
8.00 ±0.10
(2 SIDES)
6.50 REF
(2 SIDES)
6.45 ±0.10
5.41 ±0.10
R = 0.10
TYP
TOP VIEW
0.200 REF
0.00 – 0.05
0.75 ±0.05
(UKG52) QFN REV Ø 0306
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
SIDE VIEW
32
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
For more information www.linear.com/LTC2320-14
232014fa
LTC2320-14
REVISION HISTORY
REV
DATE
DESCRIPTION
A
01/18
Corrected no latency operation.
PAGE NUMBER
18, 25
232014fa
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
For more
information
www.linear.com/LTC2320-14
subject to change without notice. No license
is granted
by implication
or otherwise under any patent or patent rights of Analog Devices.
33
LTC2320-14
TYPICAL APPLICATION
Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop
VCC
0.1µF
50Ω
1k
NC7SVUO4P5X
MASTER_CLOCK
VCC
1k
D
PRE
NC7SV74K8X Q
CLR
CONV
CONV ENABLE
CNV
LTC2320-14
SCK
CLKOUT
GND
CMOS/LVDS
GND
SDR/DDR
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
SDO1 – 8
10Ω
10Ω
NC7SVU04P5X (× 9)
232014 TA02
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34
232014fa
LT 0118 REV A • PRINTED IN USA
For more information www.linear.com/LTC2320-14
www.linear.com/LTC2320-14
ANALOG DEVICES, INC. 2018