LTC2364-16
16-Bit, 250ksps, PseudoDifferential Unipolar SAR
ADC with 94.7dB SNR
FEATURES
DESCRIPTION
250ksps Throughput Rate
±0.75LSB INL (Max)
n Guaranteed 16-Bit No Missing Codes
n Low Power: 3.4mW at 250ksps, 3.4µW at 250sps
n 94.7dB SNR (Typ) at f = 2kHz
IN
n –120dB THD (Typ) at f = 2kHz
IN
n Guaranteed Operation to 125°C
n 2.5V Supply
n Pseudo-Differential Unipolar Input Range: 0V to V
REF
n V
Input
Range
from
2.5V
to
5.1V
REF
n No Pipeline Delay, No Cycle Latency
n 1.8V to 5V I/O Voltages
n SPI-Compatible Serial I/O with Daisy-Chain Mode
n Internal Conversion Clock
n 16-Lead MSOP and 4mm × 3mm DFN Packages
The LTC®2364-16 is a low noise, low power, high speed
16-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2364-16 has a 0V
to VREF pseudo-differential unipolar input range with VREF
ranging from 2.5V to 5.1V. The LTC2364-16 consumes
only 3.4mW and achieves ±0.75LSB INL maximum, no
missing codes at 16 bits with 94.7dB SNR.
n
n
The LTC2364-16 has a high speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisy-chain mode. The fast 250ksps
throughput with no cycle latency makes the LTC2364-16
ideally suited for a wide variety of high speed applications.
An internal oscillator sets the conversion time, easing external timing considerations. The LTC2364-16 automatically
powers down between conversions, leading to reduced
power dissipation that scales with the sampling rate.
APPLICATIONS
n
n
n
n
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 7705765.
Medical Imaging
High Speed Data Acquisition
Portable or Compact Instrumentation
Industrial Process Control
Low Power Battery-Operated Instrumentation
ATE
TYPICAL APPLICATION
32k Point FFT fS = 250ksps, fIN = 2kHz
2.5V
0
1.8V TO 5V
SNR = 94.7dB
THD = –121dB
SINAD = 94.7dB
SFDR = 125dB
–20
VREF
0V
+
LT®6202
–
VDD
10Ω
0.1µF
OVDD
IN+
LTC2364-16
10nF
IN–
REF
2.5V TO 5.1V
GND
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
236416 TA01a
47µF
(X5R, 0805 SIZE)
–40
SAMPLE CLOCK
AMPLITUDE (dBFS)
10µF
–60
–80
–100
–120
–140
–160
–180
0
25
50
75
FREQUENCY (kHz)
100
125
236416 TA01b
236416fa
1
LTC2364-16
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VDD)................................................2.8V
Supply Voltage (OVDD).................................................6V
Reference Input (REF)..................................................6V
Analog Input Voltage (Note 3)
IN+, IN–..........................(GND – 0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Power Dissipation............................................... 500mW
Operating Temperature Range
LTC2364C................................................. 0°C to 70°C
LTC2364I..............................................–40°C to 85°C
LTC2364H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
CHAIN
1
VDD
2
GND
3
+
4
IN–
5
GND
6
REF
7
REF
8
IN
16 GND
15 OVDD
17
GND
TOP VIEW
CHAIN
VDD
GND
IN+
IN–
GND
REF
REF
14 SDO
13 SCK
12 RDL/SDI
11 BUSY
10 GND
9 CNV
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
GND
CNV
MS PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 110°C/W
DE PACKAGE
16-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2364CMS-16#PBF
LTC2364CMS-16#TRPBF
236416
16-Lead Plastic MSOP
0°C to 70°C
LTC2364IMS-16#PBF
LTC2364IMS-16#TRPBF
236416
16-Lead Plastic MSOP
–40°C to 85°C
LTC2364HMS-16#PBF
LTC2364HMS-16#TRPBF 236416
16-Lead Plastic MSOP
–40°C to 125°C
LTC2364CDE-16#PBF
LTC2364CDE-16#TRPBF
23646
16-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2364IDE-16#PBF
LTC2364IDE-16#TRPBF
23646
16-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
236416fa
2
LTC2364-16
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN+
Absolute Input Range (IN+)
MIN
TYP
MAX
UNITS
(Note 5)
l
–0.1
VIN –
Absolute Input Range (IN–)
(Note 5)
l
VIN+ – VIN–
Input Differential Voltage Range
VIN = VIN+ – VIN–
l
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
Sample Mode
Hold Mode
45
5
pF
pF
CMRR
Input Common Mode Rejection Ratio
fIN = 125kHz
80
dB
VREF + 0.1
V
–0.1
0.1
V
0
VREF
V
±1
µA
l
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
UNITS
Resolution
l
16
Bits
No Missing Codes
l
16
Bits
l
–0.75
±0.1
0.75
LSB
l
–0.5
±0.1
0.5
LSB
l
–4
0
4
Transition Noise
INL
Integral Linearity Error
DNL
Differential Linearity Error
ZSE
Zero-Scale Error
0.5
(Note 6)
(Note 7)
Zero-Scale Error Drift
FSE
TYP
Full-Scale Error
LSBRMS
4
(Note 7)
l
–20
Full-Scale Error Drift
±2
LSB
mLSB/°C
20
±0.1
LSB
ppm/°C
DYNAMIC
ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
SINAD
Signal-to-(Noise + Distortion) Ratio
fIN = 2kHz, VREF = 5V
l
91.9
94.7
dB
fIN = 2kHz, VREF = 5V, (H-Grade)
l
91.7
94.7
dB
SNR
Signal-to-Noise Ratio
fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 2.5V
l
l
92.5
87.7
94.7
90.7
dB
dB
fIN = 2kHz, VREF = 5V, (H-Grade)
fIN = 2kHz, VREF = 2.5V, (H-Grade)
l
l
92.2
87.3
94.7
90.7
dB
dB
THD
Total Harmonic Distortion
fIN = 2kHz, VREF = 5V
fIN = 2kHz, VREF = 2.5V
l
l
SFDR
Spurious Free Dynamic Range
fIN = 2kHz, VREF = 5V
l
–120
–120
–102
–102
UNITS
dB
dB
122
dB
–3dB Input Bandwidth
34
MHz
Aperture Delay
500
ps
4
ps
3.46
µs
Aperture Jitter
Transient Response
Full-Scale Step
103
MAX
236416fa
3
LTC2364-16
REFERENCE
INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VREF
Reference Voltage
(Note 5)
l
MIN
IREF
Reference Input Current
(Note 9)
l
TYP
2.5
0.12
MAX
UNITS
5.1
V
0.2
mA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –500µA
l
VOL
Low Level Output Voltage
IO = 500µA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = OVDD
10
mA
VIN = 0V to OVDD
0.8 • OVDD
V
–10
l
0.2 • OVDD
V
10
µA
5
pF
OVDD – 0.2
V
0.2
–10
V
10
µA
POWER
REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VDD
Supply Voltage
OVDD
Supply Voltage
IVDD
IOVDD
IPD
IPD
Supply Current
Supply Current
Power Down Mode
Power Down Mode
250ksps Sample Rate
250ksps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V)
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V, H-Grade)
PD
Power Dissipation
Power Down Mode
Power Down Mode
250ksps Sample Rate
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V)
Conversion Done (IVDD + IOVDD + IREF, VREF > 2V, H-Grade)
MIN
TYP
MAX
UNITS
l
2.375
2.5
2.625
V
l
1.71
l
l
l
1.36
0.1
0.9
0.9
3.4
2.25
2.25
5.25
V
1.7
90
140
mA
mA
µA
µA
4.25
225
315
mW
µW
µW
ADC
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
fSMPL
Maximum Sampling Frequency
l
tCONV
Conversion Time
l
1.9
tACQ
Acquisition Time
l
3.460
tHOLD
Maximum Time Between Acquisitions
l
tCYC
Time Between Conversions
l
4
µs
tCNVH
CNV High Time
l
20
ns
tBUSYLH
CNV↑ to BUSY Delay
CL = 20pF
l
tCNVL
Minimum Low Time for CNV
(Note 11)
l
20
ns
SCK Quiet Time from CNV↑
(Note 10)
l
20
ns
tQUIET
CONDITIONS
tACQ = tCYC – tHOLD (Note 10)
MIN
TYP
MAX
UNITS
250
ksps
3
µs
540
ns
µs
13
ns
236416fa
4
LTC2364-16
ADC
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
tSCK
SCK Period
(Notes 11, 12)
tSCKH
tSCKL
tSSDISCK
SDI Setup Time From SCK↑
tHSDISCK
MIN
TYP
MAX
UNITS
l
10
ns
SCK High Time
l
4
ns
SCK Low Time
l
4
ns
(Note 11)
l
4
ns
SDI Hold Time From SCK↑
(Note 11)
l
1
ns
13.5
tSCKCH
SCK Period in Chain Mode
tSCKCH = tSSDISCK + tDSDO (Note 11)
l
tDSDO
SDO Data Valid Delay from SCK↑
CL = 20pF (Note 11)
l
tHSDO
SDO Data Remains Valid Delay from SCK↑
CL = 20pF (Note 10)
l
tDSDOBUSYL
SDO Data Valid Delay from BUSY↓
CL = 20pF (Note 10)
l
5
ns
tEN
Bus Enable Time After RDL↓
(Note 11)
l
16
ns
tDIS
Bus Relinquish Time After RDL↑
(Note 11)
l
13
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 250kHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
ns
9.5
1
ns
ns
Note 7: Zero-scale error is the offset voltage measured from 0.5LSB
when the output code flickers between 0000 0000 0000 0000 and
0000 0000 0000 0001. Full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale 5V input with a
5V reference voltage.
Note 9: fSMPL = 250kHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
tWIDTH
0.2*OVDD
tDELAY
tDELAY
0.8*OVDD
0.8*OVDD
0.2*OVDD
0.2*OVDD
50%
50%
236416 F01
Figure 1. Voltage Levels for Timing Specifications
236416fa
5
LTC2364-16
TYPICAL PERFORMANCE CHARACTERISTICS
fSMPL = 250ksps, unless otherwise noted.
Differential Nonlinearity
vs Output Code
DC Histogram
0.5
100000
0.8
0.4
90000
0.6
0.3
80000
0.4
0.2
70000
0.1
60000
0.2
0.0
–0.2
–0.4
COUNTS
1.0
DNL ERROR (LSB)
INL ERROR (LSB)
Integral Nonlinearity
vs Output Code
0.0
–0.1
40000
30000
–0.6
–0.3
20000
–0.8
–0.4
10000
–1.0
–0.5
0
16384
32768
49152
OUTPUT CODE
65536
0
16384
32768
49152
OUTPUT CODE
–120
–140
90
85
80
75
–160
–180
HARMONICS, THD (dBFS)
–100
0
25
50
75
FREQUENCY (kHz)
100
70
32680
125
–80
–90
THD
–100
2ND
–110
3RD
–120
–130
–140
–150
0
25
50
75
FREQUENCY (kHz)
100
236416 G04
96.0
32679
–70
SNR
SINAD
–80
32678
CODE
–60
95
–60
32677
THD, Harmonics
vs Input Frequency
100
SNR, SINAD (dBFS)
–40
32676
236416 G03
SNR, SINAD vs Input Frequency
SNR = 94.7dB
THD = –121dB
SINAD = 94.7dB
SFDR = 125dB
–20
0
65536
236416 G02
32k Point FFT fS = 250ksps,
fIN = 2kHz
0
σ = 0.5
50000
–0.2
236416 G01
AMPLITUDE (dBFS)
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V,
–160
125
0
25
75
50
FREQUENCY (kHz)
100
236416 G05
SNR, SINAD vs Input level,
fIN = 2kHz
125
236416 G06
SNR, SINAD vs Reference
Voltage, fIN = 2kHz
–100
95
THD, Harmonics vs Reference
Voltage, fIN = 2kHz
95.0
SNR, SINAD (dBFS)
SNR, SINAD (dBFS)
94
SNR
SINAD
94.5
94.0
SNR
HARMONICS, THD (dBFS)
–105
95.5
SINAD
93
92
91
93.5
–110
–115
THD
–120
2ND
–125
–130
3RD
–135
–140
–145
93.0
–40
–30
–20
–10
INPUT LEVEL (dB)
0
236416 G07
90
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
5
236416 G08
–150
2.5
3
4
4.5
3.5
REFERENCE VOLTAGE (V)
5
236416 G09
236416fa
6
LTC2364-16
TYPICAL PERFORMANCE CHARACTERISTICS
fSMPL = 250ksps, unless otherwise noted.
SNR, SINAD vs Temperature,
fIN = 2kHz
THD, Harmonics vs Temperature,
fIN = 2kHz
96.0
94.5
94.0
93.5
–115
THD
–120
2ND
INL/DNL ERROR (LSB)
HARMONICS, THD (dBFS)
SNR, SINAD (dBFS)
SNR
SINAD
–125
–130
3RD
–135
5 25 45 65 85 105 125
TEMPERATURE (°C)
–145
–55 –35 –15
MAX INL
MAX DNL
0
–0.5
Full-Scale Error vs Temperature
236416 G12
Supply Current vs Temperature
Offset Error vs Temperature
1.4
8
3
1.2
OFFSET ERROR (LSB)
6
2
0
–2
–4
–6
POWER SUPPLY CURRENT (mA)
4
4
2
1
0
–1
–2
–3
–8
–10
–55 –35 –15
–4
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
1.0
0.8
0.6
0.4
0.2
IREF
IOVDD
5 25 45 65 85 105 125
TEMPERATURE (°C)
236416 G15
236416 G14
Shutdown Current vs Temperature
Reference Current
vs Reference Voltage
CMRR vs Input Frequency
100
IVDD + IOVDD + IREF
0.20
30
REFERENCE CURRENT (mA)
95
35
CMRR (dB)
90
25
20
15
85
80
10
75
5
0
–55 –35 –15
IVDD
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
236416 G13
40
5 25 45 65 85 105 125
TEMPERATURE (°C)
236416 G11
10
45
MIN DNL
MIN INL
–1.0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
236416 G10
FULL-SCALE ERROR (LSB)
0.5
–140
93.0
–55 –35 –15
POWER-DOWN CURRENT (µA)
INL/DNL vs Temperature
1.0
–110
95.5
95.0
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V,
5 25 45 65 85 105 125
TEMPERATURE (°C)
236416 G16
70
0
25
50
75
FREQUENCY (kHz)
100
125
236416 G17
0.15
0.10
0.05
0
2.5
3
4.5
4
3.5
REFERENCE VOLTAGE (V)
5
236416 G18
236416fa
7
LTC2364-16
PIN FUNCTIONS
CHAIN (Pin 1): Chain Mode Selector Pin. When low, the
LTC2364-16 operates in normal mode and the RDL/SDI
input pin functions to enable or disable SDO. When high,
the LTC2364-16 operates in chain mode and the RDL/SDI
pin functions as SDI, the daisy-chain serial data input.
Logic levels are determined by OVDD.
VDD (Pin 2): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDD to GND with a 10µF ceramic
capacitor.
GND (Pins 3, 6, 10 and 16): Ground.
IN+ (Pin 4): Analog Input. IN+ operates differential with
respect to IN– with an IN+-IN– range of 0V to VREF.
IN– (Pin 5): Analog Ground Sense. IN– has an input range
of ±100mV with respect to GND and must be tied to the
ground plane or a remote ground sense.
REF (Pins 7, 8): Reference Inputs. The range of REF is 2.5V
to 5.1V. This pin is referred to the GND pin and should be
decoupled closely to the pin with a 47µF ceramic capacitor
(X5R, 0805 size).
CNV (Pin 9): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by OVDD.
BUSY (Pin 11): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OVDD.
RDL/SDI (Pin 12): When CHAIN is low, the part is in normal mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy chain is input. Logic levels are
determined by OVDD.
SCK (Pin 13): Serial Data Clock Input. When SDO is enabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by OVDD.
SDO (Pin 14): Serial Data Output. The conversion result
or daisy-chain data is output on this pin on each rising
edge of SCK MSB first. The output data is in straight binary
format. Logic levels are determined by OVDD.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1µF capacitor.
GND (Exposed Pad Pin 17, DFN Package Only): Ground.
Exposed pad must be soldered directly to the ground plane.
236416fa
8
LTC2364-16
FUNCTIONAL BLOCK DIAGRAM
VDD = 2.5V
REF = 5V
IN+
+
16-BIT SAMPLING ADC
IN–
–
OVDD = 1.8V to 5V
SPI
PORT
CHAIN
SDO
RDL/SDI
SCK
CNV
CONTROL LOGIC
BUSY
GND
236416 BD
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0
CNV
CONVERT
BUSY
HOLD
POWER-DOWN
ACQUIRE
SCK
D15 D14 D13
SDO
D2 D1 D0
236416 TD01
236416fa
9
LTC2364-16
APPLICATIONS INFORMATION
OVERVIEW
Fast 250ksps throughput with no cycle latency makes
the LTC2364-16 ideally suited for a wide variety of high
speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The
LTC2364-16 dissipates only 3.4mW at 250ksps, while an
auto power-down feature is provided to further reduce
power dissipation during inactive periods.
CONVERTER OPERATION
The LTC2364-16 operates in two phases. During the acquisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and IN– pins to
sample the pseudo-differential analog input voltage. A rising edge on the CNV pin initiates a conversion. During the
conversion phase, the 16-bit CDAC is sequenced through a
successive approximation algorithm, effectively comparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g. VREF/2, VREF/4 … VREF/65536) using
the differential comparator. At the end of conversion, the
CDAC output approximates the sampled analog input. The
ADC control logic then prepares the 16-bit digital output
code for serial transfer.
TRANSFER FUNCTION
The LTC2364-16 digitizes the full-scale voltage of REF
into 216 levels, resulting in an LSB size of 76µV with
REF = 5V. The ideal transfer function is shown in Figure 2.
The output data is in straight binary format.
1LSB = FS/65536
111...110
111...101
OUTPUT CODE
The LTC2364-16 is a low noise, low power, high speed
16-bit successive approximation register (SAR) ADC.
Operating from a single 2.5V supply, the LTC2364-16
supports a 0V to VREF pseudo-differential unipolar input
range with VREF ranging from 2.5V to 5.1V, making it ideal
for high performance applications which require a wide
dynamic range. The LTC2364-16 achieves ±0.75LSB INL
max, no missing codes at 16 bits and 94.7dB SNR.
111...111
111...100
000...011
UNIPOLAR
ZERO
000...010
000...001
000...000
0V
1
LSB
FS – 1LSB
INPUT VOLTAGE (V)
236416 F02
Figure 2. LTC2364-16 Transfer Function
ANALOG INPUT
The analog inputs of the LTC2364-16 are pseudo-differential in order to reduce any unwanted signal that is common
to both inputs. The analog inputs can be modeled by the
equivalent circuit shown in Figure 3. The diodes at the input
provide ESD protection. In the acquisition phase, each
input sees approximately 45pF (CIN) from the sampling
CDAC in series with 40Ω (RON) from the on-resistance
of the sampling switch. The IN+ input draws a current
spike while charging the CIN capacitor during acquisition.
During conversion, the analog inputs draw only a small
leakage current.
REF
RON
40Ω
IN+
REF
IN–
RON
40Ω
CIN
45pF
CIN
45pF
BIAS
VOLTAGE
236416 F03
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2364-16
236416fa
10
LTC2364-16
APPLICATIONS INFORMATION
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high impedance input of the LTC2364-16 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC input
draws a current spike when entering acquisition.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Pseudo-Differential Unipolar Inputs
For best performance, a buffer amplifier should be used
to drive the analog input of the LTC2364-16. The amplifier provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the current spike the ADC input draws.
For most applications, we recommend the low power
LT6202 ADC driver to drive the LTC2364-16. With a low
noise density of 1.9nV/√Hz and a low supply current of
3mA, the LT6202 is flexible and may be configured to
convert signals of various amplitudes to the 0V to 5V input
range of the LTC2364-16.
Input Filtering
To achieve the full distortion performance of the
LTC2364‑16, a low distortion single-ended signal source
driven through the LT6202 configured as a unity-gain
buffer as shown in Figure 4 can be used to get the full
data sheet THD specification of –120dB.
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimize noise. The simple 1-pole RC lowpass filter (LPF1)
shown in Figure 4 is sufficient for many applications.
LPF1
VREF
0V
50Ω
66nF
BW = 48kHz
LPF2
+
LT6202
–
10Ω
IN+
10nF
LTC2364-16
IN–
BW = 1.6MHz
236416 F04
Figure 4. Input Signal Chain
Another filter network consisting of LPF2 should be used
between the buffer and ADC input to both minimize the
noise contribution of the buffer and to help minimize disturbances reflected into the buffer from sampling transients.
Long RC time constants at the analog inputs will slow
down the settling of the analog inputs. Therefore, LPF2
requires a wider bandwidth than LPF1. A buffer amplifier
with a low noise density must be selected to minimize
degradation of the SNR.
The LT6202 can also be used to buffer and convert large
true bipolar signals which swing below ground to the 0V
to 5V input range of the LTC2364-16. Figure 5a shows the
LT6202 being used to convert a ±10V true bipolar signal
for use by the LTC2364-16. In this case, the LT6202 is
configured as an inverting amplifier stage, which acts to
attenuate and level shift the input signal to the 0V to 5V input
range of the LTC2364-16. In the inverting configuration, the
single-ended input signal source no longer directly drives
a high impedance input. The input impedance is instead
set by resistor RIN. RIN must be chosen carefully based on
the source impedance of the signal source. Higher values
of RIN tend to degrade both the noise and distortion of
the LT6202 and LTC2364-16 as a system. Table 1 shows
the resulting SNR and THD for several values of RIN, R1,
R2, R3 and R4 in this configuration. Figure 5b shows the
resulting FFT when using the LT6202 as shown in Figure 5a.
236416fa
11
LTC2364-16
APPLICATIONS INFORMATION
VCM = VREF/2
200pF
R2
499Ω
R4
402Ω
ADC REFERENCE
3
R3
2k
10µF
+
LT6202
RIN
2k
10V
0V
–10V
4
–
5V
1
0V
R1
499Ω
200pF
236416 F05a
Figure 5a. LT6202 Converting a ±10V Bipolar Signal
to a 0V to 5V Input Signal
0
SNR = 94.6dB
THD = –99.2dB
SINAD = 92.2dB
SFDR = 99.9dB
AMPLITUDE (dBFS)
–20
–40
–60
The REF pin of the LTC2364-16 draws charge (QCONV) from
the 47µF bypass capacitor during each conversion cycle.
The reference replenishes this charge with a DC current,
IREF = QCONV/tCYC. The DC current draw of the REF pin,
IREF, depends on the sampling rate and output code. If
the LTC2364-16 is used to continuously sample a signal
at a constant rate, the LTC6655-5 will keep the deviation
of the reference voltage over the entire code span to less
than 0.5LSBs.
–80
–100
–120
–140
–160
0
25
50
75
FREQUENCY (kHz)
100
The LTC2364-16 requires an external reference to define
its input range. A low noise, low temperature drift reference is critical to achieving the full data sheet performance
of the ADC. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power and high
accuracy, the LTC6655-5 is particularly well suited for
use with the LTC2364-16. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications. The LTC6655-5
is fully specified over the H-grade temperature range and
complements the extended temperature operation of the
LTC2364-16 up to 125°C. We recommend bypassing the
LTC6655-5 with a 47µF ceramic capacitor (X5R, 0805
size) close to the REF pin.
125
236416 F05b
Figure 5b. 32k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 5a
Table 1. SNR, THD vs RIN for ±10V Input Signal
RIN
(Ω)
R1
(Ω)
R2
(Ω)
R3
(Ω)
R4
(Ω)
SNR
(dB)
THD
(dB)
2k
499
499
2k
402
94.6
–99.2
10k
2.49k
2.49k
10k
2k
94.4
–93.8
100k
24.9k
24.9k
100k
20k
92.4
–93.7
When idling, the REF pin on the LTC2364-16 draws only
a small leakage current (< 1µA). In applications where a
burst of samples is taken after idling for long periods as
shown in Figure 6, IREF quickly goes from approximately
0µA to a maximum of 0.2mA at 250ksps. This step in DC
current draw triggers a transient response in the reference
that must be considered since any deviation in the reference output voltage will affect the accuracy of the output
CNV
236416 F06
IDLE
PERIOD
IDLE
PERIOD
Figure 6. CNV Waveform Showing Burst Sampling
236416fa
12
LTC2364-16
APPLICATIONS INFORMATION
In applications where power management is critical and
the external reference may be powered down, it is recommended that REF is kept greater than 2V in order to
guarantee a maximum shutdown current of 140µA. In such
applications, a Schottky diode can be placed between REF
and VDD, as shown in Figure 7.
REF
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 8 shows
that the LTC2364-16 achieves a typical SNR of 94.7dB at
a 250kHz sampling rate with a 2kHz input.
0
SNR = 94.7dB
THD = –121dB
SINAD = 94.7dB
SFDR = 125dB
–20
–40
AMPLITUDE (dBFS)
code. In applications where the transient response of the
reference is important, the fast settling LTC6655-5 reference is also recommended.
VDD
–60
–80
–100
–120
–140
–160
LTC2364-16
–180
0
236416 F07
Figure 7. A Schottky Diode Between REF and VDD Maintains
REF > 2V for Applications Where the Reference May Be
Powered Down
DYNAMIC PERFORMANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2364-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Signal-to-Noise and Distortion Ratio (SINAD)
25
50
75
FREQUENCY (kHz)
100
125
236416 F08
Figure 8. 32k Point FFT with fIN = 2kHz of the LTC2364-16
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD= 20log
V22 + V32 + V42 +…+ VN2
V1
where V1 is the RMS amplitude of the fundamental fre
quency and V2 through VN are the amplitudes of the second
through Nth harmonics.
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 8 shows that the LTC2364-16 achieves
a typical SINAD of 94.7dB at a 250kHz sampling rate with
a 2kHz input.
The LTC2364-16 provides two power supply pins: the
2.5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2364-16 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Signal-to-Noise Ratio (SNR)
Power Supply Sequencing
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
The LTC2364-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
POWER CONSIDERATIONS
236416fa
13
LTC2364-16
APPLICATIONS INFORMATION
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2364‑16
has a power-on-reset (POR) circuit that will reset the
LTC2364-16 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 20µs after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
new conversion is initiated on the rising edge of CNV.
During power down, data from the last conversion can
be clocked out. To minimize power dissipation during
power down, disable SDO and turn off SCK. The auto
power-down feature will reduce the power dissipation of
the LTC2364-16 as the sampling frequency is reduced.
Since power is consumed only during a conversion, the
LTC2364-16 remains powered down for a larger fraction of
the conversion cycle (tCYC) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 9.
TIMING AND CONTROL
The LTC2364-16 conversion is controlled by CNV. A rising edge on CNV will start a conversion and power up
the LTC2364-16. Once a conversion has been initiated,
it cannot be restarted until the conversion is complete.
For optimum performance, CNV should be driven by a
clean low jitter signal. Converter status is indicated by the
BUSY output which remains high while the conversion is
in progress. To ensure that no errors occur in the digitized
results, any additional transitions on CNV should occur
within 40ns from the start of the conversion or after the
conversion has been completed. Once the conversion has
completed, the LTC2364-16 powers down and begins
acquiring the input signal.
Acquisition
A proprietary sampling architecture allows the LTC2364-16
to begin acquiring the input signal for the next conversion 527ns after the start of the current conversion. This
extends the acquisition time to 3.460µs, easing settling
requirements and allowing the use of extremely low power
ADC drivers. (Refer to the Timing Diagram.)
Internal Conversion Clock
The LTC2364-16 has an internal clock that is trimmed
to achieve a maximum conversion time of 3µs.
Auto Power-Down
The LTC2364-16 automatically powers down after a
conversion has been completed and powers up once a
14
POWER SUPPLY CURRENT (mA)
CNV Timing
1.6
1.4
1.2
1.0
IVDD
0.8
0.6
0.4
0.2
0
IOVDD
1
50
100
150
200
SAMPLING RATE (kHz)
IREF
250
236416 F09
Figure 9. Power Supply Current of the LTC2364-16 Versus
Sampling Rate
DIGITAL INTERFACE
The LTC2364-16 has a serial digital interface. The flexible
OVDD supply allows the LTC2364-16 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
20MHz, a 250ksps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D15 remains valid till the first rising edge of SCK.
The serial interface on the LTC2364-16 is simple and
straightforward to use. The following sections describe the
operation of the LTC2364-16. Several modes are provided
236416fa
LTC2364-16
TIMING DIAGRAMS
depending on whether a single or multiple ADCs share the
SPI bus or are daisy chained.
Figure 10 shows a single LTC2364-16 operated in normal mode with CHAIN and RDL/SDI tied to ground. With
RDL/SDI grounded, SDO is enabled and the MSB(D15) of
the new conversion data is available at the falling edge of
BUSY. This is the simplest way to operate the LTC2364-16.
Normal Mode, Single Device
When CHAIN = 0, the LTC2364-16 operates in normal
mode. In normal mode, RDL/SDI enables or disables the
serial data output pin SDO. If RDL/SDI is high, SDO is in
high impedance. If RDL/SDI is low, SDO is driven.
CONVERT
DIGITAL HOST
CNV
CHAIN
LTC2364-16
RDL/SDI
BUSY
IRQ
SDO
DATA IN
SCK
CLK
POWER-DOWN
ACQUIRE
CONVERT
POWER-DOWN
CONVERT
ACQUIRE
CHAIN = 0
RDL/SDI = 0
tCYC
tCNVH
tCNVL
CNV
tHOLD
tACQ
tACQ = tCYC – tHOLD
tCONV
BUSY
tSCK
tBUSYLH
tSCKH
1
SCK
2
3
tHSDO
tDSDOBUSYL
SDO
tQUIET
14
15
16
tSCKL
tDSDO
D15
D14
D13
D1
D0
236416 F10
Figure 10. Using a Single LTC2364-16 in Normal Mode
236416fa
15
LTC2364-16
TIMING DIAGRAMS
Normal Mode, Multiple Devices
be used to allow only one LTC2364-16 to drive SDO at a
time in order to avoid bus conflicts. As shown in Figure 11,
the RDL/SDI inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDI is brought low, the MSB of the selected
device is output onto SDO.
Figure 11 shows multiple LTC2364-16 devices operating
in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.
By sharing CNV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
Since SDO is shared, the RDL/SDI input of each ADC must
RDLB
RDLA
CONVERT
CNV
CHAIN
LTC2364-16
B
CNV
CHAIN
BUSY
LTC2364-16
SDO
A
IRQ
DIGITAL HOST
SDO
RDL/SDI
RDL/SDI
SCK
SCK
DATA IN
CLK
POWER-DOWN
CONVERT
POWER-DOWN
ACQUIRE
CONVERT
ACQUIRE
CHAIN = 0
tCNVL
CNV
tHOLD
BUSY
tCONV
tBUSYLH
RDL/SDIA
RDL/SDIB
tSCK
SCK
1
2
tSCKH
3
14
15
16
tHSDO
SDO
Hi-Z
D15A
D14A
D13A
17
18
19
30
31
32
tSCKL
tDSDO
tEN
tQUIET
tDIS
D1A
D0A
Hi-Z
D15B
D14B
D13B
D1B
D0B
Hi-Z
236416 F11
Figure 11. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO
236416fa
16
LTC2364-16
TIMING DIAGRAMS
Chain Mode, Multiple Devices
number of converters. Figure 12 shows an example with
two daisy-chained devices. The MSB of converter A will
appear at SDO of converter B after 16 SCK cycles. The
MSB of converter A is clocked in at the SDI/RDL pin of
converter B on the rising edge of the first SCK.
When CHAIN = OVDD, the LTC2364-16 operates in
chain mode. In chain mode, SDO is always enabled and
RDL/SDI serves as the serial data input pin (SDI) where
daisy-chain data output from another ADC can be input.
This is useful for applications where hardware constraints
may limit the number of lines needed to interface to a large
CONVERT
OVDD
OVDD
CNV
CHAIN
RDL/SDI
A
CNV
CHAIN
LTC2364-16
DIGITAL HOST
LTC2364-16
RDL/SDI
SDO
IRQ
BUSY
B
DATA IN
SDO
SCK
SCK
CLK
POWER-DOWN
ACQUIRE
CONVERT
POWER-DOWN
ACQUIRE
CONVERT
CHAIN = OVDD
RDL/SDIA = 0
tCYC
tCNVL
CNV
tHOLD
BUSY
tCONV
tBUSYLH
tSCKCH
SCK
1
2
3
14
15
tSSDISCK
16
17
18
30
31
32
tSCKL
tHSDO
tHSDISCK
SDOA = RDL/SDIB
tQUIET
tSCKH
tDSDO
D15A
D14A
D13A
D1A
D0A
D15B
D14B
D13B
D1B
D0B
tDSDOBUSYL
SDOB
D15A
D14A
D1A
D0A
236416 F12
Figure 12. Chain Mode Timing Diagram
236416fa
17
LTC2364-16
BOARD LAYOUT
To obtain the best performance from the LTC2364-16
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals alongside analog signals or underneath
the ADC.
Recommended Layout
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1813A, the
evaluation kit for the LTC2364-16.
Partial Top Silkscreen
236416fa
18
LTC2364-16
BOARD LAYOUT
Partial Layer 1 Component Side
Partial Layer 2 Ground Plane
236416fa
19
LTC2364-16
BOARD LAYOUT
Partial Layer 3 PWR Plane
Partial Layer 4 Bottom Layer
236416fa
20
J8
AIN –
E7
EXT
VREF/2
R14
0Ω
R39
0Ω
JP5
HD1X3-100
EXT_CM
AIN+
J4
COUPLING
AC
DC
C46
1µF
3
2
1
C8
1µF
+2.5V
R15
OPT
HD1X3-100
JP2
CM
C18
OPT
C17
10µF
JP1
HD1X3-100
C47
OPT C48
10µF
6.3V
4
2
5
4
+3.3V
C2
0.1µF
R3
CLK
33Ω
TO CPLD
R41
OPT
R40
OPT
R9
OPT
C49
OPT
C63
10µF
6.3V
2
C44
1µF
V+
4
C59
1µF
–IN1
OUT1 1
C57
0.1µF
V–
C43
0.1µF
C55
1µF
3 +IN1
V–
C61
10µF
6.3V
C42
15pF
R32
0Ω
V+
U15
5 LT6202CS5
V+
U2
R6 3 U8
3
NC7SZ04P5X NC7SVU04P5X
1k
5
+3.3V
C1
0.1µF
COUPLING
AC
DC
1
R5
49.9Ω
1206
2
R2
1k
+3.3V
2
J1
CLKIN
1
3
C5
0.1µF
2
C60
0.1µF
C58
OPT
R35
OPT
R45
ØΩ
R32
10Ω
R31
OPT
C11
0.1µF
9V TO 10V
+2.5V
C9
10µF
6.3V
+3.3V
C10
0.1µF
C6
10µF
6.3V
C7
0.1µF
R46
ØΩ
C20
47µF
6.3V
0805
3
2
1
JP6
FS
C56
0.1µF
3
SDO
1
3
5
7
9
11
13
9V TO
10V
J3
DC590
2
4
6
8
10
12
14
R17 R13
2k
1k
4
VSS
U7
C14
0.1µF 8 24LC025-I/ST
VCC
SCL
SCK
SDA
WP
CNV
ARRAY
A2
EEPROM
A1
A0
3
6
5
7
3
2
1
R10
4.99k
R11
4.99k
CLKOUT
C16 1
0.1µF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
3
5
2 CNVST_33
FROM CPLD
U4
NC7SVU04P5X
+3.3V
C4
0.1µF
R12
4.99k
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
236416 BL
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
J2
CON-EDGE 40-100
R4
7 33Ω 4
8
+3.3V
C3
0.1µF
R8
33Ω
DC590 DETECT
TO CPLD
5
PR\
Q
CLR\
Q\
2
D
VCC
1
CP
GND
+3.3V
C13
0.8VREF
0.1µF
VREF
6
4
U3
NL17SZ74
+3.3V
HD1X3-100
U6
OPT NC7SZ66P5X 5
C39
CNV
VCC
0.01µF R16
9
2 B
A 1
0Ω 4
NPO
CNV
13 SCK
IN+
SCK
OE 4
C65
14 SDO
SDO
OPT
R19
LTC2364-16
GND
11 BUSY
BUSY
0805 NPO
0Ω
3
IN–
12 RD
RDL/SDI
C40 5
R58
OPT
ØΩ
R7
+3.3V
NPO
R38
1k
OPT
U9
C15
NC7SZ04P5X
5
0.1µF
2
4
1
2
3
4
U20
LTC6655AHMS8-5
8
SHDN
GND
7
VIN
OUT_F
6
GND OUT_S
5
GND
GND
GND
GND
GND
GND
3
6
10
16
1
–
+
3
VDD 2
15
OV
DD
REF 7
8
REF
R1
33Ω
LTC2364-16
BOARD LAYOUT
Partial Schematic of Demoboard
236416fa
21
LTC2364-16
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
4.039 ± 0.102
(.159 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
16151413121110 9
0.254
(.010)
3.20 – 3.45
(.126 – .136)
DETAIL “A”
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
0° – 6° TYP
0.280 ± 0.076
(.011 ± .003)
REF
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
NOTE:
PLANE
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.17 – 0.27
(.007 – .011)
TYP
1234567 8
0.86
(.034)
REF
0.1016 ± 0.0508
(.004 ± .002)
0.50
(.0197)
BSC
MSOP (MS16) 1107 REV Ø
DE Package
16-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1732 Rev Ø)
R = 0.05
TYP
9
4.00 ±0.10
(2 SIDES)
R = 0.115
TYP
0.40 ±0.10
16
0.70 ±0.05
3.60 ±0.05
2.20 ±0.05
3.30 ±0.05
1.70 ±0.05
PACKAGE
OUTLINE
PIN 1
TOP MARK
(SEE NOTE 6)
3.30 ±0.10
3.00 ±0.10
(2 SIDES)
1.70 ±0.10
(DE16) DFN 0806 REV Ø
8
0.25 ±0.05
0.45 BSC
0.200 REF
1
0.23 ±0.05
0.45 BSC
0.75 ±0.05
3.15 REF
3.15 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
236416fa
22
LTC2364-16
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
08/12
Corrected resolution from 18-bit to 16-bit in Description section
1
236416fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2364-16
TYPICAL APPLICATION
LT6202 Converting a ±10V Bipolar Signal to a 0V to 5V Input Signal Into the LTC2364-16
LTC6655-5
VIN
VOUT_F
VOUT_S
8V
5V
200pF
R2
3k
10µF
47µF
5
V+
R4
402Ω
3
R3
2k
LT6202
+
1
4
–
2.5V
5V
0V 10Ω
IN+
10nF
V–
REF
VDD
LTC2364-16
IN–
2
10V
0V
–10V
RIN
2k
R1
499Ω
236416 TA02
–3V
220pF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
ADCs
LTC2379-18/LTC2378-18 18-Bit, 1.6Msps/1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range,
LTC2377-18/LTC2376-18 Power ADC
DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16
Packages
LTC2380-16/LTC2378-16 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, Low
2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC,
LTC2377-16/LTC2376-16 Power ADC
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16
Packages
LTC2383-16/LTC238216-Bit, 1Msps/500ksps/250ksps Serial, Low
2.5V Supply, Differential Input, 92dB SNR, ±2.5V Input Range, Pin16/LTC2381-16
Power ADC
Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2393-16/LTC239216-Bit, 1Msps/500ksps/250ksps Parallel/Serial ADC
5V Supply, Differential Input, 94dB SNR, ±4.096V Input Range, Pin16/LTC2391-16
Compatible Family in 7mm × 7mm LQFP-48 and QFN-48 Packages
LTC1864/LTC1864L
16-Bit, 250ksps/150ksps 1-Channel µPower ADC
5V/3V Supply, 1-Channel, 4.3mW/1.5mW, MSOP-8 Package
LTC1865/LTC1865L
16-Bit, 250ksps/150ksps 2-Channel µPower ADC
5V/3V Supply, 2-Channel, 4.3mW/1.3mW, MSOP-10 Package
DACS
LTC2757
18-Bit, Single Parallel IOUT SoftSpan™ DAC
±1LSB INL/DNL, Software-Selectable Ranges, 7mm × 7mm
LQFP-48 Package
LTC2641
16-Bit/14-Bit/12-Bit Single Serial VOUT DACs
±1LSB INL/DNL, MSOP-8, 3mm × 3mm DFN, SO-8 Packages,
0V to 5V Output
SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)
LTC2630
12-Bit/10-Bit/8-Bit Single VOUT DACs
References
LTC6655
Precision Low Drift Low Noise Buffered Reference
5V/2.5V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6652
Precision Low Drift Low Noise Buffered Reference
5V/2.5V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
Amplifiers
LT6202/LT6203
Single/Dual 100MHz Rail-to-Rail Input/Output Noise
1.9nV√Hz, 3mA Maximum, 100MHz Gain Bandwidth
Low Power Amplifiers
LT6200/LT6200-5/
165MHz/800MHz/1.6GHz Op Amp with
Low Noise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dB at
LT6200-10
Unity Gain/AV = 5/AV = 10
1MHz, TSOT23-6, SO-8 Packages
236416fa
24 Linear Technology Corporation
LT 0812 Rev A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2012
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