LTC2365/LTC2366
1Msps/3Msps, 12-Bit Serial
Sampling ADCs in TSOT
Features
Description
12-Bit Resolution
n 1Msps/3Msps Sampling Rates
n Low Noise: 73dB SNR
n Low Power Dissipation: 6mW
n Single Supply 2.35V to 3.6V Operation
n No Data Latency
n Sleep Mode with 0.1µA Typical Supply Current
n Dedicated External Reference (TSOT23-8)
n 1V to 3.6V Digital Output Supply (TSOT23-8)
n SPI/MICROWIRE Compatible Serial I/O
n Guaranteed Operation from –40°C to 125°C
n 6- and 8-Lead TSOT-23 Packages
The LTC®2365/LTC2366 are 1Msps/3Msps, 12-bit,
sampling A/D converters that draw only 2mA and 2.6mA,
respectively, from a single 3V supply. These high performance devices include a high dynamic range sample-andhold and a high speed serial interface. The full-scale input
is 0V to VDD or VREF . Outstanding AC performance includes
72dB SINAD and –80dB THD at sample rates of 3Msps.
The serial interface provides flexible power management
and allows maximum power efficiency at low throughput
rates. These devices are available in tiny 6- and 8-lead
TSOT-23 packages.
n
Applications
n
n
n
n
n
n
n
Communication Systems
Data Acquisition Systems
Handheld Terminal Interface
Medical Imaging
Uninterrupted Power Supplies
Battery-Operated Systems
Automotive
The serial interface, tiny TSOT-23 package and extremely
high sample rate-to-power ratio make the LTC2365/
LTC2366 ideal for compact, low power, high speed systems.
The high impedance single-ended analog input and the
ability to operate with reduced spans (down to 1.4V full
scale) allow direct connection to sensors and transducers
in many applications, eliminating the need for gain stages.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
Typical Application
12-Bit TSOT23-6/-8 ADC Family
DATA OUTPUT RATE
3Msps
1Msps
500ksps
250ksps
100ksps
Part Number
LTC2366
LTC2365
LTC2362
LTC2361
LTC2360
1MHz Sine Wave 8192 FFT Plot
0
VDD = 3V
fSMPL = 3Msps
–20 f = 994kHz
IN
SINAD = 72dB
–40 THD = –80.3dB
Single 3V Supply, 3Msps, 12-Bit Sampling ADC
LTC2366
ANALOG INPUT
0V TO 3V
VDD
CS
VREF
SDO
GND
SCK
AIN
OVDD
23656 TA01
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
4.7µF
DIGITAL OUTPUT SUPPLY
1V TO VDD
MAGNITUE (dB)
3V
10µF
–60
–80
–100
–120
–140
0
250
750 1000 1250
500
INPUT FREQUENCY (kHz)
1500
23656 TA01b
23656fb
For more information www.linear.com/LTC2365
1
LTC2365/LTC2366
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (VDD)................................................4.0V
Supply Voltage (OVDD).................Min (VDD + 0.3V, 4.0V)
VREF and Analog Input Voltage
(Note 3)......................................... –0.3V to (VDD + 0.3V)
Digital Input Voltage..................... –0.3V to (VDD + 0.3V)
Digital Output Voltage................... –0.3V to (VDD + 0.3V)
Power Dissipation................................................100mW
Operating Temperature Range
LTC2365C/LTC2366C............................... 0°C to 70°C
LTC2365I/LTC2366I..............................–40°C to 85°C
LTC2365H/LTC2366H (Note 13)......... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
Pin Configuration
TOP VIEW
VDD 1
VREF 2
GND 3
AIN 4
TOP VIEW
8 CS
7 SCK
6 SDO
5 OVDD
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 250°C/W
VDD 1
6 CS
GND 2
5 SDO
AIN 3
4 SCK
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 250°C/W
Order Information
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2366CTS8#TRMPBF
LTC2366CTS8#TRPBF
LTCYZ
8-lead Plastic TSOT-23
0°C to 70°C
LTC2366ITS8#TRMPBF
LTC2366ITS8#TRPBF
LTCYZ
8-lead Plastic TSOT-23
–40°C to 85°C
LTC2366HTS8#TRMPBF
LTC2366HTS8#TRPBF
LTCYZ
8-lead Plastic TSOT-23
–40°C to 125°C
LTC2366CS6#TRMPBF
LTC2366CS6#TRPBF
LTCXK
6-lead Plastic TSOT-23
0°C to 70°C
LTC2366IS6#TRMPBF
LTC2366IS6#TRPBF
LTCXK
6-lead Plastic TSOT-23
–40°C to 85°C
LTC2366HS6#TRMPBF
LTC2366HS6#TRPBF
LTCXK
6-lead Plastic TSOT-23
–40°C to 125°C
LTC2365CTS8#TRMPBF
LTC2365CTS8#TRPBF
LTDCB
8-lead Plastic TSOT-23
0°C to 70°C
LTC2365ITS8#TRMPBF
LTC2365ITS8#TRPBF
LTDCB
8-lead Plastic TSOT-23
–40°C to 85°C
LTC2365HTS8#TRMPBF
LTC2365HTS8#TRPBF
LTDCB
8-lead Plastic TSOT-23
–40°C to 125°C
LTC2365CS6#TRMPBF
LTC2365CS6#TRPBF
LTDCC
6-lead Plastic TSOT-23
0°C to 70°C
LTC2365IS6#TRMPBF
LTC2365IS6#TRPBF
LTDCC
6-lead Plastic TSOT-23
–40°C to 85°C
LTC2365HS6#TRMPBF
LTC2365HS6#TRPBF
LTDCC
6-lead Plastic TSOT-23
–40°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
23656fb
For more information www.linear.com/LTC2365
LTC2365/LTC2366
Converter
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LTC2365
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
l
TYP
LTC2366
MAX
12
MIN
TYP
MAX
UNITS
12
Bits
±0.25
±1
±0.25
±1
LSB
±0.25
±1
±0.25
±1
LSB
Integral Linearity Error
(Note 5, 6)
l
Differential Linearity Error
(Note 6)
l
Transition Noise
(Note 7)
Offset Error
(Note 6)
l
2
±3.5
2
±3.5
LSB
Gain Error
(Note 6)
l
1
±2
1
±2
LSB
Total Unadjusted Error
S6 Package (Note 6)
TS8 Package (Note 6)
l
l
2
3
±3.5
±4.5
2
3
±3.5
±4.5
LSB
LSB
0.34
0.34
LSBRMS
Analog
Inputs The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Analog Input Voltage
S6 Package
TS8 Package
l
l
IIN
Analog Input Leakage Current
CS = High
l
CIN
Analog Input Capacitance
Between Conversions
During Conversions
VREF
Reference Input Voltage
TS8 Package
l
IREF
Reference Input Leakage Current
TS8 Package
l
CREF
Reference Input Capacitance
TS8 Package
tAP
Sample-and-Hold Aperture Delay Time
tJITTER
Sample-and-Hold Aperture Delay Time Jitter
TYP
MAX
–0.05
–0.05
UNITS
VDD + 0.05
VREF + 0.05
V
V
±1
µA
20
4
pF
pF
1.4
VDD + 0.05
V
±1
µA
4
pF
1
ns
0.3
ns
Dynamic
Accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 4)
LTC2365
SYMBOL
PARAMETER
CONDITIONS
SINAD
Signal-to-(Noise + Distortion) Ratio fIN = 1MHz
SNR
Signal-to-Noise Ratio
THD
SFDR
IMD
MIN
LTC2366
TYP MAX MIN
TYP MAX UNITS
l
68
72
68
71
dB
fIN = 1MHz
l
70
73
69
72
dB
Total Harmonic Distortion
fIN = 1MHz
l
Spurious Free Dynamic Range
fIN = 1MHz
87
Intermodulation Distortion
fIN1 = 0.97MHz, fIN2 = 1MHz for LTC2366
fIN1 = 97kHz, fIN2 = 100kHz for LTC2365
–76
Full-Power Bandwidth
At 3dB
At 0.1dB
30
5
50
8
MHz
MHz
Full-Linear Bandwidth
SINAD ≥ 68dB
2
2.5
MHz
–86
–72
–80
–72
dB
82
–71.5
dB
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3
LTC2365/LTC2366
Digital
Inputs and Digital Outputs
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VIH
High Level Input Voltage
2.7V < VDD ≤ 3.6V
2.35V ≤ VDD ≤ 2.7V
l
l
VIL
Low Level Input Voltage
2.7V < VDD ≤ 3.6V
2.35V ≤ VDD ≤ 2.7V
l
l
0.8
0.7
V
V
IIH
High Level Input Current
VIN = VDD
l
2.5
µA
IIL
Low Level Input Current
VIN = 0V
l
–2.5
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VDD = 2.35V to 3.6V, ISOURCE = 200µA
l
VOL
Low Level Output Voltage
VDD = 2.35V to 3.6V, ISINK = 200µA
l
0.2
V
IOZ
Hi-Z Output Leakage
CS = VDD
l
±3
µA
COZ
Hi-Z Output Capacitance
CS = VDD
4
pF
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
2
1.7
UNITS
V
V
2
pF
VDD – 0.2
V
Power
Requirement
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VDD
OVDD
IDD
Supply Current, Static Mode
Operational Mode, LTC2366
Operational Mode, LTC2365
Sleep Mode
Sleep Mode
CS = 0V, SCK = 0V or VDD
fSMPL = 3Msps
fSMPL = 1Msps
–40°C to 85°C
85°C to 125°C
l
l
l
l
Power Dissipation, Static Mode
Operational Mode, LTC2366
Operational Mode, LTC2365
Sleep Mode
Sleep Mode
CS = 0V, SCK = 0V or VDD
fSMPL = 3Msps
fSMPL = 1Msps
–40°C to 85°C
85°C to 125°C
l
l
l
l
PD
4
CONDITIONS
MIN
TYP
Supply Voltage
l
2.35
3.0
Digital Output Supply Voltage
l
1
1
2.6
2
0.1
7.8
6
0.3
MAX
UNITS
3.6
V
3.6
V
4
3.5
2
5
mA
mA
mA
µA
µA
3.6
14.4
12.6
7.2
18
mW
mW
mW
µW
µW
23656fb
For more information www.linear.com/LTC2365
LTC2365/LTC2366
Timing Characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
MIN
LTC2365
TYP MAX
PARAMETER
CONDITIONS
fSMPL(MAX)
Maximum Sampling Frequency
(Notes 8, 9)
l
1
fSCK
Shift Clock Frequency
(Notes 8, 9, 10)
l
0.5
tSCK
Shift Clock Period
l
62.5
tTHROUGHPUT
Minimum Throughput Time, tACQ + tCONV
l
tACQ
Acquisition Time
l
181.5
56
ns
tCONV
Conversion Time
l
818.5
277
ns
tQUIET
SDO Hi-Z State to CS↓
l
4
4
ns
t1
Minimum Positive or Negative CS Pulse Width (Notes 8)
l
4
t2
SCK↓ Setup Time After CS↓
(Notes 8)
l
6
t3
SDO Enabled Time After CS↓
(Notes 9, 11, 12)
l
t4
SDO Data Valid Access Time After SCK↓
(Notes 8, 9, 11)
l
t5
SCK LOW Time
t6
SCK HIGH Time
(Notes 8, 9)
MIN
LTC2366
TYP MAX UNITS
SYMBOL
3
16
0.5
48
2000
20.8
2000
ns
333
ns
1000
4
2000
6
ns
ns
4
4
ns
15
15
ns
l
40%
40%
tSCK
tSCK
l
40%
40%
SDO Data Valid Hold Time After SCK↓
l
5
5
t8
SDO into Hi-Z State Time After SCK↓
(Notes 9, 12)
l
5
t9
SDO into Hi-Z State Time After CS↑
(Notes 9, 12)
l
tPOWER-UP
Power-Up Time from Sleep Mode
See Sleep Mode section
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When this pin, AIN, is taken below GND or above VDD, it will be
clamped by internal diodes. These products can handle input currents
greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and
fSCK = fSCK(MAX) unless otherwise specified.
Note 5: Integral linearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
MHz
2000
(Notes 8, 9, 11)
t7
MHz
30
5
ns
14
ns
4.2
4.2
ns
1000
333
ns
Note 6: Linearity, offset and gain specifications apply for a single-ended
AIN input with respect to GND.
Note 7: Typical RMS noise at code transitions.
Note 8: Guaranteed by characterization. All input signals are specified with
tr = tf = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 9: All timing specifications given are with a 10pF capacitance load.
With a capacitance load greater than this value, a digital buffer or latch
must be used.
Note 10: Minimum fSCK at which specifications are guaranteed.
Note 11: The time required for the output to cross the VIH or VIL voltage.
Note 12: Guaranteed by design, not subject to test.
Note 13: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
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5
LTC2365/LTC2366
Typical Performance Characteristics
Integral Nonlinearity
vs Output Code
1.0
1.0
1.0
0.8
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0
–0.2
INL AND DNL (LSB)
0.6
0
–0.2
–0.6
–0.6
–0.8
–0.8
–0.8
–1.0
–1.0
3072
2048
OUTPUT CODE
4096
1024
0
3072
2048
OUTPUT CODE
73.1
SNR (dB)
6000
2047 2048
CODE
2049
72.8
72.9
VDD = 2.35V
72.2
461kHz Sine Wave 8192 FFT Plot
0
VDD = 3V
fSMPL = 1Msps
fIN = 1MHz
–79
VDD = 2.35V
VDD = 3.6V
–88
100
1000
INPUT FREQUENCY (kHz)
23656 G07
MAGNITUDE (dB)
THD (dB)
VDD = 3V
–87
23656 G06
THD vs Input Resistance
–78
–84
1000
INPUT FREQUENCY (kHz)
23656 G05
RIN = 10Ω
fSMPL = 1Msps
–85
72.0
100
1000
–83
6
72.6
INPUT FREQUENCY (kHz)
THD vs Input Frequency
–86
VDD = 3V
VDD = 2.35V
23656 G04
–82
VDD = 3.6V
73.0
VDD = 3V
72.5
100
2050
–80
–81
–82
–83
3.6
SINAD vs Input Frequency
VDD = 3.6V
72.7
2000
2046
3.0
3.3
2.7
SUPPLY VOLTAGE (V)
73.2
72.4
2045
2.4
23656 G03
SINAD (dB)
VDD = 3V
73.3
–81
–1.0
2.1
4096
SNR vs Input Frequency
8000
0
MIN INL
–0.4
73.5
4000
MAX DNL
23656 G02
Histogram for 16384 Conversions
10000
THD (dB)
–0.2
–0.6
1024
MIN DNL
0
–0.4
0
MAX INL
0.2
–0.4
23656 G01
COUNT
Integral and Differential
Nonlinearity vs Supply Voltage
VDD = 3V
0.8
DNL (LSB)
INL (LSB)
Differential Nonlinearity
vs Output Code
VDD = 3V
0.8
TA = 25°C, VDD = OVDD = VREF (LTC2365, Note 4)
VDD = 3V
fSMPL = 1Msps
–20 f = 461kHz
IN
SINAD = 72.8dB
–40 THD = –86.1dB
–60
–80
–100
–120
0
50
25
75
INPUT RESISTANCE (Ω)
100
23656 G08
–140
0
100
200
300
400
INPUT FREQUENCY (kHz)
500
23656 G09
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For more information www.linear.com/LTC2365
LTC2365/LTC2366
Typical Performance Characteristics
Integral Nonlinearity
vs Output Code
1.0
Differential Nonlinearity
vs Output Code
1.0
VDD = 3V
0.8
Integral and Differential
Nonlinearity vs Supply Voltage
1.0
VDD = 3V
0.8
0.8
0.6
0.4
0.4
0.4
0.2
0.2
0
–0.2
INL AND DNL (LSB)
0.6
DNL (LSB)
0.6
INL (LSB)
TA = 25°C, VDD = OVDD = VREF (LTC2366, Note 4)
0
–0.2
0
–0.4
–0.6
–0.6
–0.8
–0.8
–0.8
–1.0
–1.0
3072
2048
OUTPUT CODE
4096
1024
0
3072
2048
OUTPUT CODE
23656 G10
–0.4
MIN DNL
–1.0
2.1
4096
SNR vs Input Frequency
VDD = 3V
73.0
6000
72.8
SINAD vs Input Frequency
VDD = 3.6V
72.5
VDD = 2.35V
VDD = 3V
72.6
2046
2047 2048
CODE
2049
71.0
70.5
72.2
100
2050
THD vs Input Resistance
–64
VDD = 3V
VDD = 2.35V
1000 1500
INPUT FREQUENCY (kHz)
23656 G16
MAGNITUE (dB)
THD (dB)
THD (dB)
VDD = 3.6V
–84
–88
100
VDD = 3V
fSMPL = 3Msps
–20 f = 994kHz
IN
SINAD = 72dB
–40 THD = –80.3dB
–68
–78
–86
1MHz Sine Wave 8192 FFT Plot
0
VDD = 3V
fSMPL = 3Msps
fIN = 1.5MHz
–66
-76
–82
23656 G15
23656 G14
RIN = 10Ω
fSMPL = 3Msps
–80
1000 1500
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
THD vs Input Frequency
–74
70.0
100
1000 1500
23656 G13
–72
VDD = 3V
71.5
VDD = 2.35V
72.4
2045
SINAD (dB)
SNR (dB)
COUNT
72.0
2000
–70
–72
–60
–80
–74
–100
–76
–120
–78
3.6
73.0
VDD = 3.6V
8000
0
3.0
3.3
2.7
SUPPLY VOLTAGE (V)
23656 G12
73.2
4000
2.4
23656 G11
Histogram for 16384 Conversions
10000
MIN INL
–0.2
–0.6
1024
MAX DNL
0.2
–0.4
0
MAX INL
0
25
50
75
INPUT RESISTANCE (Ω)
100
23656 G17
–140
0
250
750 1000 1250
500
INPUT FREQUENCY (kHz)
1500
23656 G18
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For more information www.linear.com/LTC2365
7
LTC2365/LTC2366
Typical Performance Characteristics
Supply Current vs SCK Frequency
250
IDD (mA)
2.0
1.5
VDD = 3V
VDD = 2.35V
1.0
0.5
0
0
10
0.8
200
150
VDD = 3V
100
VDD = 3.6V
50
0
50
20
30
40
SCK FREQUENCY (MHz)
1.0
16 SCKS PER CONVERSION
NONLINEARITY ERROR (LSB)
REFERENCE CURRENT (µA)
VDD = 3.6V
VDD = 2.35V
5
0
MAGNITUDE (dB)
NONLINEARITY ERROR (LSB)
MAX DNL
MAX INL
MIN DNL
–0.4
–0.6
0.2
0
MAX INL
MIN DNL
–0.2
–0.4
MIN INL
–0.6
–1.0
0.6
1.2
2.4
3.0
1.8
REFERENCE VOLTAGE (V)
3.6
23656 G21
VDD = 3V
LTC2366
0.4
0
MAX DNL
0
0.6
–0.2
0.4
Input Power Bandwidth
2
LTC2366, VDD = 3.6V
0.2
0.6
23656 G20
Integral and Differential
Nonlinearity vs Reference
Voltage (TS8 Package)
0.8
LTC2365, VDD = 3.6V
–0.8
10 15 20 25 30 35 40 45 50
SCK FREQUENCY (MHz)
23656 G19
1.0
Integral and Differential
Nonlinearity vs Reference
Voltage (TS8 Package)
Reference Current vs SCK
Frequency (TS8 Package)
3.0
2.5
TA = 25°C, VDD = OVDD = VREF (LTC2365/LTC2366, Note 4)
MIN INL
–2
–4
LTC2365
–6
–8
–0.8
–1.0
0.6
1.2
2.4
3.0
1.8
REFERENCE VOLTAGE (V)
3.6
–10
1
10
INPUT FREQUENCY (MHz)
23656 G22
8
100
23656 G23
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LTC2365/LTC2366
Pin Functions
LTC2365/LTC2366 (S6 Package)
LTC2365/LTC2366 (TS8 Package)
VDD (Pin 1): Positive Supply. The VDD range is 2.35V to
3.6V. VDD also defines the input span of the ADC, 0V to
VDD. Bypass to GND and to a solid ground plane with a
10µF ceramic capacitor (or 10µF tantalum in parallel with
0.1µF ceramic).
VDD (Pin 1): Positive Supply. The VDD range is 2.35V to
3.6V. Bypass to GND and to a solid ground plane with a
10µF ceramic capacitor (or 10µF tantalum in parallel with
0.1µF ceramic).
GND (Pin 2): Ground. The GND pin must be tied directly
to a solid ground plane.
AIN (Pin 3): Analog Input. AIN is a single-ended input with
respect to GND with a range from 0V to VDD.
SCK (Pin 4): Shift Clock Input. The SCK serial clock advances the conversion process. SDO data transitions on
the falling edge of SCK.
SDO (Pin 5): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB first. The data stream consists of two
leading zeros followed by 12 bits of conversion data and
two trailing zeros.
CS (Pin 6): Chip Select Input. This active low signal starts
a conversion on the falling edge and frames the serial
data transfer.
VREF (Pin 2): Reference Input. VREF defines the input
span of the ADC, 0V to VREF and the VREF range is 1.4V
to VDD. Bypass to GND and to a solid ground plane with
a 4.7µF ceramic capacitor (or 4.7µF tantalum in parallel
with 0.1µF ceramic).
GND (Pin 3): Ground. The GND pin must be tied directly
to a solid ground plane.
AIN (Pin 4): Analog Input. AIN is a single-ended input with
respect to GND with a range from 0V to VREF.
OVDD (Pin 5): Output Driver Supply for SDO. The OVDD
range is 1V to VDD. Bypass to GND and to a solid ground
plane with a 4.7µF ceramic capacitor (or 4.7µF tantalum
in parallel with 0.1µF ceramic).
SDO (Pin 6): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB first. The data stream consists of two
leading zeros followed by 12 bits of conversion data and
two trailing zeros.
SCK (Pin 7): Shift Clock Input. The SCK serial clock advances the conversion process. SDO data transitions on
the falling edge of SCK.
CS (Pin 8): Chip Select Input. This active low signal starts
a conversion on the falling edge and frames the serial
data transfer.
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9
LTC2365/LTC2366
Block Diagram
10µF
4.7µF
+
AIN
4
+
ANALOG
INPUT RANGE
OV TO VREF
VDD
5
12-BIT ADC
THREESTATE
SERIAL
OUTPUT
PORT
+
S&H
OVDD
1
–
6
SDO
7
SCK
VREF
4.7µF
2
+
TIMING
LOGIC
GND
3
8
TS8 PACKAGE
CS
23656 BD
Timing Diagrams
t8
SCK
1.6V
Hi-Z
SDO
23656 TD01
Figure 1. SDO Into Hi-Z State After SCK Falling Edge
t7
SCK
SDO
1.6V
VIH
VIL
23656 TD02
Figure 2. SDO Data Valid Hold Time After SCK Falling Edge
t4
SCK
SDO
1.6V
VOH
VOL
23656 TD03
Figure 3. SDO Data Valid Access Time After SCK Falling Edge
10
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LTC2365/LTC2366
Applications Information
Dc Performance
Dynamic Performance
The noise of an ADC can be evaluated in two ways: signalto-noise ratio (SNR) in the frequency domain and histogram
in the time domain. The LTC2365/LTC2366 excel in both.
Figures 5 and 6 demonstrate that the LTC2365/LTC2366
have an SNR of over 72dB. The noise in the time domain
histogram is the transition noise associated with a 12-bit
resolution ADC which can be measured with a fixed DC signal
applied to the input of the ADC. The resulting output codes
are collected over a large number of conversions. The
shape of the distribution of codes will give an indication
of the magnitude of the transition noise. In Figure 4, the
distribution of output codes is shown for a DC input
that has been digitized 16384 times. The distribution is
Gaussian and the RMS code transition is about 0.34LSB.
This corresponds to a noise level of 72.7dB relative to a
full scale of 3V.
The LTC2365/LTC2366 have excellent high speed sampling
capability. Fast fourier transform (FFT) test techniques are
used to test the ADC’s frequency response, distortion and
noise at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental. Figures 5 and 6
show typical LTC2365 and LTC2366 FFT plots, respectively.
10000
MAGNITUDE (dB)
0
–60
–80
–100
–120
VDD = 3V
–140
8000
0
6000
100
200
300
400
INPUT FREQUENCY (kHz)
500
23656 F05
Figure 5. LTC2365 FFT Plot
4000
0
VDD = 3V
fSMPL = 3Msps
–20 f = 994kHz
IN
SINAD = 72dB
–40 THD = –80.3dB
2000
0
2045
2046
2047 2048
CODE
2049
2050
23656 F04
Figure 4. Histogram for 16384 Conversions
MAGNITUE (dB)
COUNT
VDD = 3V
fSMPL = 1Msps
–20 fIN = 461kHz
SINAD = 72.8dB
–40 THD = –86.1dB
–60
–80
–100
–120
–140
0
250
750 1000 1250
500
INPUT FREQUENCY (kHz)
1500
23656 F06
Figure 6. LTC2366 FFT Plot
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11
LTC2365/LTC2366
Applications Information
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 6 shows a typical FFT with a 3MHz sampling rate and a 1MHz input. The dynamic performance
is excellent for input frequencies up to and beyond the
Nyquist frequency of 1.5MHz.
Effective Number of Bits
The effective number of bits (ENOB) is a measurement
of the resolution of an ADC and is directly related to
SINAD by the equation:
ENOB = (SINAD – 1.76)/6.02
where ENOB is the effective number of bits of resolution and SINAD is expressed in dB. At the maximum
73.0
71.5
The total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
V22 + V32 + V42 + ...Vn2
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD versus Input Frequency is shown in Figure 8. The LTC2366 has excellent
distortion performance up to the Nyquist frequency and
beyond.
THD = 20log
11.83
–72
VDD = 3.6V
RIN = 10Ω
–74
–76
VDD = 2.35V
11.67
VDD = 3V
71.0
ENOB
SINAD (dB)
72.0
Total Harmonic Distortion
11.50
THD (dB)
72.5
sampling rate of 3MHz, the LTC2366 maintains ENOB
above 11 bits up to the Nyquist input frequency of 1.5MHz
(refer to Figure 7).
–78
–80
–82
VDD = 3.6V
–84
70.5
–86
70.0
100
11.34
1000 1500
INPUT FREQUENCY (kHz)
VDD = 2.35V
1000 1500
INPUT FREQUENCY (kHz)
23656 F07
Figure 7. LTC2366 ENOB and SINAD vs Input Frequency
12
–88
100
VDD = 3V
23656 F08
Figure 8. LTC2366 Distortion vs Input Frequency
23656fb
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LTC2365/LTC2366
Applications Information
Intermodulation Distortion
Peak Harmonic or Spurious Noise
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
The peak harmonic or spurious noise is the largest spectral
component excluding the input signal and DC. This value
is expressed in decibels relative to the RMS value of a
full-scale input signal.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa ± fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
The full-power bandwidth is that input frequency at which
the amplitude of reconstructed fundamental is reduced by
3dB for full-scale input signal.
IMD(fa ± f b) = 20log
Amplitude at (fa ± f b)
Amplitude at fa
The LTC2365/LTC2366 have good IMD as shown in
Figure 9a and Figure 9b, respectively.
Full-Power and Full-Linear Bandwidth
The full-linear bandwidth is the input frequency at which
the SINAD has dropped to 68dB (11 effective bits). The
LTC2365/LTC2366 have been designed to optimize input
bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise floor stays very low at high frequencies;
SINAD becomes dominated by distortion at frequencies
far beyond Nyquist.
0
VDD = 3V
= 1Msps
f
–20 fSMPL
b = 396kHz
fb = 424kHz
–40 IMD = –73.5dB
VDD = 3V
fSMPL = 3Msps
–20 f = 935kHz
a
fb = 1.045kHz
–40 IMD = –71.5dB
MAGNITUE (dB)
MAGNITUDE (dB)
0
–60
–80
–60
–80
–100
–100
–120
–120
–140
0
50 100 150 200 250 300 350 400 450 500
INPUT FREQUENCY (kHz)
–140
0
23656 F09a
Figure 9a. LTC2365 Intermodulation Distortion Plot
250
750 1000 1250
500
INPUT FREQUENCY (kHz)
1500
23656 F09b
Figure 9b. LTC2366 Intermodulation Distortion Plot
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13
LTC2365/LTC2366
Applications Information
OVERVIEW
gram, while Figures 11 and 12 detail the timing diagrams
of conversion cycles in 14 and 16 SCK cycles, respectively.
The LTC2365/LTC2366 use a successive approximation
algorithm and internal sample-and-hold circuit to convert
an analog signal to a 12-bit serial output. Both devices
operate from a single 2.35V to 3.6V supply. The LTC2366
samples at a rate of 3Msps with a 48MHz clock while the
LTC2365 samples at a rate of 1Msps with a 16MHz clock.
Data Transfer
A falling CS edge starts a conversion and frames the serial data transfer. SCK provides the conversion clock and
controls the data transfer during the conversion.
CS going LOW clocks out the first leading zero and subsequent SCK falling edges clock out the remaining data,
beginning with the second leading zero. (Therefore, the
first SCK falling edge captures the first leading zero and
clocks out the second leading zero). The timing diagram
in Figure 12 shows that the final bit in the data transfer is
valid on the 16th falling edge, since it is clocked out on
the previous 15th falling edge.
The LTC2365/LTC2366 contain a 12-bit, switched-capacitor
ADC, a sample-and-hold, and a serial interface (see Block
Diagram) and are available in tiny 6- and 8-lead TSOT-23
packages. The devices provide sleep mode control through
the serial interface to save power during inactive periods
(see the SLEEP MODE section).
The S6 package of the LTC2365/LTC2366 uses VDD as the
reference and has an analog input range of 0V to VDD. The
ADC samples the analog input with respect to GND and
outputs the result through the serial interface.
In applications with a slower SCK, it is possible to capture
data on each SCK rising edge. In such cases, the first
falling edge of SCK clocks out the second leading zero
and can be captured on the first rising edge. However,
the first leading zero clocked out when CS goes LOW is
missed, as shown in Figures 11 and 12. In Figure 12, the
15th falling edge of SCK clocks out the last bit and can
be captured on the 15th rising SCK edge.
The TS8 package provides two additional pins: a reference
input pin, VREF, and an output supply pin, OVDD. The ADC
can operate with reduced spans down to 1.4V and achieve
342µV resolution. OVDD controls the output swing of the
digital output pin, SDO, and allows the device to communicate with 1.8V, 2.5V or 3V digital systems.
If CS goes LOW while SCK is LOW, then CS clocks out the
first leading zero and can be captured on the SCK rising
edge. The next SCK falling edge clocks out the second
leading zero and can be captured on the following rising
edge, as shown in Figure 10.
SERIAL INTERFACE
The LTC2365/LTC2366 communicate with microcontrollers, DSPs and other external circuitry via a 3-wire
interface. Figure 10 shows the serial interface timing dia-
t1
CS
tCONV
t2
SCK
2
1
3
ZERO
5
t4
t3
SDO
t6
4
ZERO
B11
(MSB)
B10
B9
13
14
B1
15
16
t5
t7
B0
t8
ZERO
tQUIET
ZERO
13tSCK
Hi-Z STATE
tACQ
tTHROUGHPUT
23656 F10
Figure 10. LTC2365/LTC2366 Serial Interface Timing Diagram
14
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LTC2365/LTC2366
Applications Information
t1
CS
SCK
tACQ
tCONV
t2
1
2
3
t6
4
5
t4
t3
SDO
Z
ZERO
B11
B10
13
14
t5
t7
B9
B1
t9
tQUIET
B0
Hi-Z STATE
(MSB)
tTHROUGHPUT
23656 F11
Figure 11. LTC2365/LTC2366 Serial Interface Timing Diagram for 14 SCK Cycles
t1
CS
SCK
tACQ
tCONV
t2
1
2
3
t6
4
5
t4
t3
SDO
Z
ZERO
13
B11
B10
14
t7
B9
15
16
t5
B1
B0
t8 OR t9
tQUIET
ZERO
ZERO
(MSB)
Hi-Z STATE
tTHROUGHPUT
23656 F12
Figure 12. LTC2365/LTC2366 Serial Interface Timing Diagram for 16 SCK Cycles
Achieving 3Msps Sample Rate with LTC2366
Serial Data Output (SDO)
CS going LOW places the sample-and-hold into hold
mode and starts a conversion. The LTC2365/LTC2366
require at least 14 SCK cycles to finish the conversion.
The conversion terminates after the 13th falling SCK edge,
which clocks out B0. The 14th falling SCK edge places the
sample-and-hold back into sample mode.
The SDO output remains in the high impedance state while
CS is HIGH. The falling edge of CS starts the conversion
and enables SDO. The A/D conversion result is shifted out
on the SDO pin as a serial data stream with the MSB first.
The data stream consists of two leading zeros followed
by 12 bits of conversion data and two trailing zeros. The
SDO output returns to the high impedance state at the
16th falling edge of SCK or sooner by bringing CS HIGH
before the 16th falling edge of SCK.
Ignoring the last two trailing zeros, the user can bring CS
HIGH after the 14th falling SCK edge. The user can also
keep the last two trailing zeros by bringing CS HIGH right
after the 16th falling SCK. In both cases, a sample rate of
3Msps can be achieved by using a 48MHz SCK clock on
the LTC2366, where tTHROUGHPUT is 333ns.
The output swing on the SDO pin is controlled by the VDD
pin voltage in the S6 package and by the OVDD pin voltage
in the TS8 package.
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15
LTC2365/LTC2366
Applications Information
Sleep Mode
Entering Sleep Mode
The LTC2365/LTC2366 provide a sleep mode to conserve
power during inactive periods. Upon power-up, holding
CS HIGH initializes the ADC to sleep mode. In sleep mode,
all bias circuitry is shut down and only leakage currents
remain (0.1µA typ).
The ADC achieves the fastest sampling rate in operational
mode (full power-up). The device can also be put into sleep
mode for power savings during inactive periods. To force
the LTC2365/LTC2366 into sleep mode, the user can interrupt the conversion process by bringing CS HIGH between
the 2nd and 10th falling edges of SCK (see Figures 13 and
14). If CS is brought HIGH after the 10th falling edge and
before the 16th falling edge, the device remains powered
up, but the conversion is terminated and SDO returns to
the high impedance state.
CS
1
2
10
12
14
16
SCK
SDO
VALID DATA
23656 F13
Figure 13. LTC2365/LTC2366 Operational Mode
CS
1
2
10
12
14
16
SCK
Hi-Z STATE
SDO
23656 F14
Figure 14. LTC2365/LTC2366 Entering Sleep Mode
16
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LTC2365/LTC2366
Applications Information
Exiting Sleep Mode and Power-Up Time
POWER versus SAMPLING RATE
To exit sleep mode, pull CS LOW and perform a dummy
conversion. The LTC2365/LTC2366 device power up
completely after the 16th falling edge of SCK. After powering up, the ADC can continuously acquire an input signal
and perform conversions as described in the SERIAL
INTERFACE section (see Figure 15). The wake-up time is
333ns for the LTC2366 with a 48MHz SCK and 1µs for
the LTC2365 with a 16MHz SCK.
Figure 16 shows the power consumption of the LTC2365/
LTC2366 in operational mode. By taking the ADC into sleep
mode when not performing a conversion, the average
power consumption of the ADC decreases as the sampling
rate decreases. Figure 17 shows the power consumption
versus sampling rate with the device in sleep mode when
not performing a conversion.
The sample-and-hold is in hold mode while the device is
in sleep mode. The ADC returns to sample mode after the
1st falling edge of SCK during power-up (see Figure 15).
THE DEVICE BEGINS
TO POWER UP
THE DEVICE BEGINS
TO ACQUIRE INPUT
THE DEVICE IS FULLY
POWERED UP AND READY
TO PERFORM CONVERSION
tPOWER-UP
CS
1
2
10
12
14
16
1 2
10
12
14
16
SCK
SDO
INVALID DATA
VALID DATA
23656 F15
Figure 15. LTC2365/LTC2366 Exiting Sleep Mode
7.5
7.0
6.5
VDD = 3V
7 fSCK = 48MHz
6
6.0
POWER (mW)
POWER (mW)
8
VDD = 3V
fSCK = VARIABLE
16 SCKS PER CONVERSION
5.5
5.0
4.5
5
4
3
4.0
2
3.5
1
3.0
0
500
1000 1500 2000
SAMPLE RATE (ksps)
2500
3000
0
0
23656 F16
Figure 16. Power Consumption vs Sample Rate while
the Device Remains Powered Up Continuously
500
250
750
SAMPLE RATE (ksps)
1000
23656 F17
Figure 17. Power Consumption vs Sample Rate while the Device
Enters Sleep Mode when not Performing Conversions
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17
LTC2365/LTC2366
Applications Information
Single-ended Analog Input
LTC1566-1: Low Noise 2.3MHz Continuous Time Lowpass
Filter.
Driving the Analog Input
The analog input of the LTC2365/LTC2366 is easy to drive.
The input draws only one small current spike while charging
the sample-and-hold capacitor at the end of conversion.
During the conversion, the analog input draws only a small
leakage current. If the source impedance of the driving
circuit is low, then the input of the LTC2365/LT2366 can
be driven directly. As source impedance increases, so will
acquisition time. For minimum acquisition time with high
source impedance, a buffer amplifier should be used. The
main requirement is that the amplifier driving the analog
input must settle after the small current spike before the
next conversion starts (settling time must be less than
56ns for full throughput rate). While choosing an input
amplifier, also keep in mind the amount of noise and
harmonic distortion the amplifier contributes.
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by amplifier from charging the
sampling capacitor, choose an amplifier that has a low
output impedance (
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