LTC2430/LTC2431
20-Bit No Latency ∆ΣTM ADCs
with Differential Input and
Differential Reference
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FEATURES
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DESCRIPTIO
Low Supply Current (200µA in Conversion Mode
and 4µA in Autosleep Mode)
Differential Input and Differential Reference
with GND to VCC Common Mode Range
3ppm INL, No Missing Codes
10ppm Full-Scale Error and 1ppm Offset
0.56ppm Noise, 20.8 ENOBs
No Latency: Digital Filter Settles in a Single Cycle.
Each Conversion Is Accurate, Even After an
Input Step
Single Supply 2.7V to 5.5V Operation
Internal Oscillator—No External Components
Required
110dB Min, 50Hz/60Hz Notch Filter
Pin Compatible with 24-Bit LTC2410/LTC2411
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APPLICATIO S
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Direct Sensor Digitizer
Weight Scales
Direct Temperature Measurement
Gas Analyzers
Strain Gauge Transducers
Instrumentation
Data Acquisition
Industrial Process Control
DVMs and Meters
The LTC®2430/LTC2431 are 2.7V to 5.5V micropower
20-bit differential ∆Σ analog-to-digital converters with an
integrated oscillator, 3ppm INL and 0.56ppm RMS noise.
They use delta-sigma technology and provide single cycle
settling time for multiplexed applications. Through a
single pin, the LTC2430/LTC2431 can be configured for
better than 110dB differential mode rejection at 50Hz or
60Hz ±2%, or they can be driven by an external oscillator
for a user-defined rejection frequency. The internal oscillator requires no external frequency setting components.
The converters accept any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and
remote sensing measurement configurations. The fullscale differential input range is from – 0.5VREF to 0.5VREF.
The reference common mode voltage, VREFCM, and the
input common mode voltage, VINCM, may be independently set anywhere within GND to VCC. The DC common
mode input rejection is better than 120dB.
The LTC2430/LTC2431 communicate through a flexible
3-wire digital interface that is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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TYPICAL APPLICATIO S
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
(VOUT + 0.25V) TO 20V
4.7µF
6
1
5
4
LT1790
0.1µF
2
VCC
VCC
0.1µF
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
FO
LTC2431
REF +
SCK
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
IN +
SDO
IN –
CS
3-WIRE
SPI INTERFACE
TUE (ppm OF VREF)
VOUT
3V TO 5V
VCC = 5V
4 VREF = 5V
VINCM = VINCM = 2.5V
3 F = GND
O
2
25°C
85°C
1
0
–1
–45°C
–2
–3
–4
GND
24301 TA01
–5
–2.5 –2 –1.5 –1 – 0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
2.5
24301 G01
24301f
1
LTC2430/LTC2431
W W
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AXI U
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ABSOLUTE
RATI GS (Notes 1, 2)
Supply Voltage (VCC) to GND .......................– 0.3V to 7V
Analog Input Pins Voltage
to GND ......................................... – 0.3V to (VCC + 0.3V)
Reference Input Pins Voltage
to GND ......................................... – 0.3V to (VCC + 0.3V)
Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2430C/LTC2431C .............................. 0°C to 70°C
LTC2430I/LTC2431I ........................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW
GND
1
16 GND
VCC
2
15 GND
+
3
14 FO
REF –
4
13 SCK
IN +
5
12 SDO
IN –
6
11 CS
GND
7
10 GND
GND
8
9
REF
GND
GN PACKAGE
16-LEAD PLASTIC SSOP
LTC2430CGN
LTC2430IGN
GN PART MARKING
2430
2430I
ORDER PART NUMBER
LTC2431CMS
LTC2431IMS
TOP VIEW
VCC
REF +
REF –
IN +
IN –
1
2
3
4
5
10
9
8
7
6
FO
SCK
SDO
CS
GND
MS PACKAGE
10-LEAD PLASTIC MSOP
MS PART MARKING
LTXD
LTXE
TJMAX = 125°C, θJA = 120°C/W
TJMAX = 125°C, θJA = 110°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
Resolution (No Missing Codes)
Integral Nonlinearity
Offset Error
Offset Error Drift
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Total Unadjusted Error
Output Noise
CONDITIONS
0.1V ≤ VREF ≤ VCC, – 0.5 • VREF ≤ VIN ≤ 0.5 • VREF (Note 5)
4.5V ≤ VCC ≤ 5.5V, REF + = 2.5V, REF– = GND, VINCM = 1.25V (Note 6)
5V ≤ VCC ≤ 5.5V, REF + = 5V, REF – = GND, VINCM = 2.5V (Note 6)
REF + = 2.5V, REF – = GND, VINCM = 1.25V (Note 6)
2.5V ≤ REF + ≤ VCC, REF – = GND,
GND ≤ IN + = IN – ≤ VCC (Note 14)
2.5V ≤ REF + ≤ VCC, REF – = GND,
GND ≤ IN + = IN – ≤ VCC
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.75REF +, IN – = 0.25 • REF +
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.75REF +, IN – = 0.25 • REF +
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.25 • REF+, IN – = 0.75 • REF +
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.25 • REF+, IN – = 0.75 • REF +
4.5V ≤ VCC ≤ 5.5V, REF + = 2.5V, REF – = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF + = 5V, REF – = GND, VINCM = 2.5V
REF + = 2.5V, REF – = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF + = 5V, VREF – = GND,
GND ≤ IN – = IN + ≤ 5V, (Note 13)
●
●
●
MIN
20
TYP
2
3
10
5
MAX
20
20
50
●
10
nV/°C
20
0.1
●
10
UNITS
Bits
ppm of VREF
ppm of VREF
ppm of VREF
µV
ppm of VREF
ppm of VREF/°C
20
ppm of VREF
0.1
ppm of VREF/°C
3
6
15
2.8
ppm of VREF
ppm of VREF
ppm of VREF
µVRMS
24301f
2
LTC2430/LTC2431
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CO VERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ REF + ≤ V
MIN
TYP
●
110
120
Input Common Mode Rejection
60Hz ±2%
2.5V ≤ REF+ ≤ VCC, REF – = GND,
GND ≤ IN – = IN + ≤ 5V, (Notes 5, 7)
●
140
dB
Input Common Mode Rejection
50Hz ±2%
2.5V ≤ REF + ≤ VCC, REF – = GND,
GND ≤ IN – = IN + ≤ 5V, (Notes 5, 8)
●
140
dB
Input Normal Mode Rejection
60Hz ±2%
(Notes 5, 7)
●
110
140
dB
Input Normal Mode Rejection
50Hz ±2%
(Notes 5, 8)
●
110
140
dB
Reference Common Mode
Rejection DC
2.5V ≤ REF+ ≤ VCC, GND ≤ REF – ≤ 2.5V,
VREF = 2.5V, IN – = IN + = GND (Note 5)
●
130
140
dB
Power Supply Rejection, DC
REF + = 2.5V, REF – = GND, IN – = IN + = GND
110
dB
Power Supply Rejection, 60Hz ±2%
REF + = 2.5V, REF –
= GND, IN –
= IN + = GND, (Note 7)
120
dB
Power Supply Rejection, 50Hz ±2%
REF + = 2.5V, REF –
= GND, IN –
= IN + = GND, (Note 8)
120
dB
GND ≤
–
CC, REF = GND,
–
+
IN = IN ≤ 5V (Note 5)
MAX
UNITS
dB
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A ALOG I PUT A D REFERE CE
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN +
Absolute/Common Mode IN +
Voltage
●
GND – 0.3V
VCC + 0.3V
V
IN –
Absolute/Common Mode IN – Voltage
●
GND – 0.3V
VCC + 0.3V
V
VIN
Input Differential Voltage Range
(IN + – IN –)
●
– VREF/2
VREF/2
V
REF +
Absolute/Common Mode REF + Voltage
●
0.1
VCC
V
REF –
Absolute/Common Mode REF – Voltage
●
GND
VCC – 0.1V
V
VREF
Reference Differential Voltage Range
(REF + – REF –)
●
0.1
VCC
V
CS (IN +)
IN + Sampling Capacitance
CS
(IN –)
IN –
REF + Sampling Capacitance
CS (REF –)
REF – Sampling Capacitance
IDC_LEAK
IDC_LEAK (IN –)
IN +
MIN
DC Leakage Current
IN – DC Leakage Current
IDC_LEAK
(REF +)
REF + DC Leakage Current
IDC_LEAK
(REF –)
REF – DC Leakage Current
TYP
MAX
1.5
Sampling Capacitance
CS (REF +)
(IN +)
CONDITIONS
CS = VCC, IN + = GND
CS = VCC, IN – = VCC
CS = VCC, REF + = VCC
CS = VCC, REF – = GND
UNITS
pF
1.5
pF
1.5
pF
1.5
pF
●
–10
1
10
nA
●
–10
1
10
nA
●
–10
1
10
nA
●
–10
1
10
nA
24301f
3
LTC2430/LTC2431
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
CS, FO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
●
MIN
VIL
Low Level Input Voltage
CS, FO
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
●
VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
●
VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
●
IIN
Digital Input Current
CS, FO
0V ≤ VIN ≤ VCC
●
IIN
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9)
●
CIN
Digital Input Capacitance
CS, FO
CIN
Digital Input Capacitance
SCK
(Note 9)
VOH
High Level Output Voltage
SDO
IO = – 800µA
●
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
●
VOH
High Level Output Voltage
SCK
IO = – 800µA (Note 10)
●
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 10)
●
IOZ
Hi-Z Output Leakage
SDO
●
TYP
MAX
UNITS
2.5
2.0
V
V
0.8
0.6
V
V
2.5
2.0
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
10
pF
10
pF
VCC – 0.5V
V
0.4
V
VCC – 0.5V
V
–10
0.4
V
10
µA
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
Sleep Mode
CONDITIONS
MIN
●
CS = 0V (Note 12)
CS = VCC (Note 12)
CS = VCC, 2.7V ≤ VCC ≤ 3.3V
(Note 12)
●
●
TYP
2.7
200
4
2
MAX
UNITS
5.5
V
300
10
µA
µA
µA
24301f
4
LTC2430/LTC2431
WU
TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
fEOSC
External Oscillator Frequency Range
●
tHEO
External Oscillator High Period
●
tLEO
External Oscillator Low Period
●
0.25
tCONV
Conversion Time
FO = 0V
FO = VCC
External Oscillator (Note 11)
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
●
fESCK
External SCK Frequency Range
(Note 9)
●
tLESCK
External SCK Low Period
(Note 9)
●
250
ns
tHESCK
External SCK High Period
(Note 9)
●
250
ns
tDOUT_ISCK
Internal SCK 24-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
●
●
1.22
tDOUT_ESCK
External SCK 24-Bit Data Output Time (Note 9)
●
t1
CS ↓ to SDO Low Z
●
0
200
ns
t2
CS ↑ to SDO High Z
●
0
200
ns
t3
CS ↓ to SCK ↓
(Note 10)
●
0
200
ns
t4
CS ↓ to SCK ↑
(Note 9)
●
50
tKQMAX
SCK ↓ to SDO Valid
tKQMIN
SDO Hold After SCK ↓
t5
t6
●
●
●
MAX
UNITS
5
2000
kHz
0.25
200
µs
200
µs
130.86
133.53
136.20
157.03
160.23
163.44
20510/fEOSC (in kHz)
19.2
fEOSC/8
45
ms
ms
ms
kHz
kHz
55
%
2000
kHz
1.25
1.28
192/fEOSC (in kHz)
ms
ms
24/fESCK (in kHz)
ms
ns
220
●
(Note 5)
TYP
ns
●
15
ns
SCK Set-Up Before CS ↓
●
50
ns
SCK Hold After CS ↓
●
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF + – REF –, VREFCM = (REF + + REF –)/2;
VIN = IN + – IN –, VINCM = (IN + + IN –)/2.
Note 4: FO pin tied to GND or to VCC or to external conversion clock
source with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is calculated as the measured code minus the
expected value.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
50
ns
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
24301f
5
LTC2430/LTC2431
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
85°C
1
0
–1
–45°C
–2
VCC = 5V
4 VREF = 2.5V
VINCM = VINCM = 1.25V
3 F = GND
O
2
0
25°C
–1
85°C
–2
–3
–4
–4
2
–45°C
1
–3
–5
–2.5 –2 –1.5 –1 – 0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
VCC = 2.7V
15 VREF = 2.5V
VINCM = VINCM = 1.25V
10 FO = GND
INL (ppm OF VREF)
85°C
–2
VCC = 5V
–3 V
REF = 5V
–4 VINCM = VINCM = 2.5V
FO = GND
–5
–2.5 –2 –1.5 –1 – 0.5 0 0.5 1 1.5 2
INPUT VOLTAGE (V)
20
VCC = 5V
4 VREF = 2.5V
VINCM = VINCM = 1.25V
3 F = GND
O
2
85°C
1
VCC = 2.7V
15 VREF = 2.5V
VINCM = VINCM = 1.25V
10 FO = GND
0
–45°C
25°C
–1
–2
25
20
15
10
5
85°C
–20
–1.25 –1 –0.75–0.5 –0.25 0 0.25 0.5 0.75 1 1.25
INPUT VOLTAGE (V)
24301 G05
24301 G06
RMS Noise
vs Input Differential Voltage
20
18
16
14
12
10
10,000 CONSECUTIVE
READINGS
VCC = 2.7V
VREF = 2.5V
VIN = 0V
VINCM = 2.5V
FO = GND
TA = 25°C
1.0
GAUSSIAN
DISTRIBUTION
m = –1.07ppm
σ = 1.06ppm
0.9
8
6
4
2
2
–5
Noise Histogram (Output Rate =
7.5Hz, VCC = 2.7V, VREF = 2.5V)
GAUSSIAN
DISTRIBUTION
m = – 0.25ppm
σ = 0.550ppm
0
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
OUTPUT CODE (ppm OF VREF)
0
–15
–5
–1.25 –1 –0.75–0.5 –0.25 0 0.25 0.5 0.75 1 1.25
INPUT VOLTAGE (V)
2.5
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
30
25°C
–10
–4
Noise Histogram (Output Rate =
7.5Hz, VCC = 5V, VREF = 5V)
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = 2.5V
FO = GND
TA = 25°C
–45°C
5
–3
24301 G04
35
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
RMS NOISE (ppm OF VREF)
INL (ppm OF VREF)
25°C
0
40
24301 G03
INL (ppm OF VREF)
4
–1
–20
–1.25 –1 –0.75–0.5 –0.25 0 0.25 0.5 0.75 1 1.25
INPUT VOLTAGE (V)
5
–45°C
85°C
–5
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
5
1
0
24301 G02
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
2
25°C
5
–15
–5
–1.25 –1 –0.75–0.5 –0.25 0 0.25 0.5 0.75 1 1.25
INPUT VOLTAGE (V)
2.5
–45°C
–10
24301 G01
3
TUE (ppm OF VREF)
25°C
TUE (ppm OF VREF)
TUE (ppm OF VREF)
20
5
5
VCC = 5V
4 VREF = 5V
VINCM = VINCM = 2.5V
3 F = GND
O
2
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
2.5
24301 G07
0
0.8
0.7
VCC = 5V
VREF = 5V
VINCM = 2.5V
FO = GND
TA = 25°C
0.6
0.5
0.4
0.3
0.2
0.1
–4 –3 –2 –1 0 1 2 3 4
OUTPUT CODE (ppm OF VREF)
5
6
24301 G08
0
–2.5 –2 –1.5 –1 – 0.5 0 0.5 1 1.5 2
INPUT DIFFERENTIAL VOLTAGE (V)
2.5
24301 G10
24301f
6
LTC2430/LTC2431
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VCC = 5V
REF + = 5V
REF – = GND
VIN = 0V
VINCM = GND
FO = GND
TA = 25°C
3.0
2.8
3.2
3.0
2.8
2.6
–1
1
0
3
2
VINCM (V)
4
5
2.4
–50
6
2.4
–25
75
0
25
50
TEMPERATURE (°C)
1.0
0.8
0.8
0.6
0.4
0.2
0
–0.6
–0.8
–1.0
1
0
3
2
VREF (V)
4
–1
5
1
0
4
0.2
0
–0.8
–1.0
REF + = VCC
REF – = GND
VIN = 0V
VINCM = GND
FO = GND
TA = 25°C
2.7
3.1
3.5
–0.8
3
2
VINCM (V)
4
5
–1.0
–45 –30 –15
6
5.1
5.5
24301 G17
0 15 30 45 60
TEMPERATURE (°C)
75
90
24301 G16
Full-Scale Error vs Temperature
3
2
1
0
–1
VCC = 5V
REF – = GND
VIN = 0V
VINCM = GND
FO = GND
TA = 25°C
–2
–3
–5
4.7
VCC = 5V
VREF =5V
VIN = 0V
VINCM = GND
FO = GND
20
–4
3.9 4.3
VCC (V)
0
–0.6
FULL-SCALE ERROR (ppm OF VREF)
0.8
–0.6
0.2
Offset Error vs VREF
5
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
Offset Error vs VCC
5.5
5.1
0.4
24301 G15
1.0
0.4
4.7
0.6
–0.4
24301 G14
0.6
3.9 4.3
VCC (V)
–0.2
VCC = 5V
REF + = 5V
REF – = GND
VIN = 0V
FO = GND
TA = 25°C
–0.4
2.6
3.5
Offset Error vs Temperature
1.0
–0.2
2.8
3.1
24301 G13
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
RMS NOISE (µV)
3.0
2.7
100
Offset Error vs VINCM
VCC = 5V
REF – = GND
VIN = 0V
VINCM = GND
FO = GND
TA = 25°C
3.2
–0.4
2.8
24301 G12
RMS Noise vs VREF
3.4
REF + = 2.5V
REF – = GND
VIN = 0V
VINCM = GND
FO = GND
TA = 25°C
2.6
24301 G11
–0.2
3.0
2.6
2.4
2.4
RMS Noise vs VCC
3.4
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = GND
FO = GND
3.2
RMS NOISE (µV)
3.2
RMS NOISE (µV)
RMS Noise vs Temperature (TA)
3.4
RMS NOISE (µV)
RMS Noise vs VINCM
3.4
0
1
3
2
VREF (V)
4
5
24301 G18
+FS ERROR
10
0
VCC = 5V
VREF = 5V
FO = GND
VINCM = 2.5V
–FS ERROR
–10
–20
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
24301 G19
24301f
7
LTC2430/LTC2431
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Full-Scale Error vs VREF
PSRR vs Frequency at VCC
10
+FS ERROR
4
5
0
–5
–FS ERROR
–10
–15
3
+FS ERROR
2
VREF = 2.5V
REF – = GND
FO = GND
VINCM = 0.5VREF
TA = 25°C
1
0
–1
–2
–20
–40
0.5
1
1.5
2
2.5 3
VREF (V)
3.5
4
4.5
2.7
5
3.1
3.5
3.9 4.3
VCC (V)
5.1
4.7
24301 G22
PSRR vs Frequency at VCC
0
0
VCC = 4.1VDC
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
–20
–40
REJECTION (dB)
–60
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
–80
–60
Conversion Current vs Temperature
240
VCC = 4.1VDC ±0.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
VCC = 5.5V
230
CONVERSION CURRENT (µA)
PSRR vs Frequency at VCC
–40
–140
5.5
24301 G21
24301 G20
–20
–80
–120
–4
–5
0
–60
VCC = 4.1VDC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
–100
–FS ERROR
–3
–20
REJECTION (dB)
0
REJECTION (dB)
VCC = 5V
REF – = GND
FO = GND
VINCM = 0.5VREF
TA = 25°C
15
FULL-SCALE ERROR (ppm OF VREF)
FULL-SCALE ERROR (ppm OF VREF)
Full-Scale Error vs VCC
5
20
–80
220
VCC = 5V
210
200
190
FO = GND
CS = GND
SCK = NC
SDO = NC
–100
–100
–120
–120
170
–140
–140
15170
160
–45 –30 –15
180
VCC = 3V
VCC = 2.7V
1
10
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
1M
15220
15270
15320
FREQUENCY AT VCC (Hz)
24301 G23
SUPPLY CURRENT (µA)
800
700
600
500
90
24301 G25
6
5
VCC = 5V
VCC = 3V
400
75
Sleep Mode Current
vs Temperature
SLEEP MODE CURRENT (µA)
VREF = VCC
IN+ = GND
IN– = GND
SCK = NC
SDO = NC
SDI = GND
CS = GND
FO = EXT OSC
TA = 25°C
900
0 15 30 45 60
TEMPERATURE (°C)
24301 G24
Conversion Current
vs Output Data Rate
1000
15370
300
4
VCC = 5.5V
3
VCC = 5V
2
VCC = 3V
FO = GND
CS = VCC
SCK = NC
SDO = NC
1
200
VCC = 2.7V
100
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
24301 G26
0
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
24301 G27
24301f
8
LTC2430/LTC2431
U
U
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PI FU CTIO S
(LTC2430)
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground
pins internally connected for optimum ground current flow
and VCC decoupling. Connect each one of these pins to a
ground plane through a low impedance connection. All seven
pins must be connected to ground for proper operation.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with 0.1µF ceramic
capacitor as close to the part as possible.
REF + (Pin 3), REF – (Pin 4): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF +, is
maintained more positive than the reference negative
input, REF –, by at least 0.1V.
IN + (Pin 5), IN– (Pin 6): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and VCC + 0.3V. Within these limits the
converter bipolar input range (VIN = IN+ – IN–) extends
from – 0.5 • (VREF ) to 0.5 • (VREF ). Outside this input range
the converter produces unique overrange and underrange
output codes.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pullup is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
FO (Pin 14): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the FO pin is connected
to GND (FO = OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When FO
is driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency fEOSC/2560.
(LTC2431)
VCC (Pin 1): Positive Supply Voltage. Bypass to GND
(Pin␣ 6) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
from – 0.5 • (VREF ) to 0.5 • (VREF ). Outside this input
range, the converter produces unique overrange and
underrange output codes.
REF + (Pin 2), REF – (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF +, is
maintained more positive than the reference negative
input, REF –, by at least 0.1V.
GND (Pin 6): Ground. Connect this pin to a ground plane
through a low impedance connection.
IN + (Pin 4), IN– (Pin 5): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and VCC + 0.3V. Within these limits, the
converter bipolar input range (VIN = IN+ – IN–) extends
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
24301f
9
LTC2430/LTC2431
U
U
U
PI FU CTIO S
(LTC2431)
SDO (Pin 8): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = VCC), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as the digital input for the external serial
interface clock during the Data Output period. A weak
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode is
determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
FO (Pin 10): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the FO pin is connected
to GND (FO = OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When FO
is driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency fEOSC/2560.
W
FU CTIO AL BLOCK DIAGRA
U
U
INTERNAL
OSCILLATOR
VCC
GND
IN +
IN –
AUTOCALIBRATION
AND CONTROL
+
–∫
∫
FO
(INT/EXT)
∫
SDO
∑
SERIAL
INTERFACE
ADC
SCK
CS
REF +
REF –
DECIMATING FIR
DAC
2431 FD
Figure 1
TEST CIRCUITS
VCC
1.69k
SDO
SDO
1.69k
CLOAD = 20pF
2431 TA03
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
2431 TA04
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
24301f
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LTC2430/LTC2431
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APPLICATIO S I FOR ATIO
CONVERTER OPERATION
Converter Operation Cycle
The LTC2430/LTC2431 are low power, delta-sigma analogto-digital converters with an easy-to-use 3-wire serial interface (see Figure 1). Their operation is made up of three states.
The converters’ operating cycle begins with the conversion,
followed by the low power sleep state and ends with the data
output (see Figure 2). The 3-wire interface consists of serial
data output (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2430/LTC2431 perform a conversion.
Once the conversion is complete, the device enters the
sleep state. The part remains in the sleep state as long as
CS is HIGH. While in this sleep state, power consumption
is reduced by nearly two orders of magnitude. The conversion result is held indefinitely in a static shift register while
the converter is in the sleep state.
Once CS is pulled LOW, the device exits the low power mode
and enters the data output state. If CS is pulled HIGH before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still held
in the internal static shift register. If CS remains LOW after
the first rising edge of SCK, the device begins outputting
the conversion result. Taking CS high at this point will
terminate the data output state and start a new conversion.
There is no latency in the conversion result. The data output corresponds to the conversion just performed. This
result is shifted out on the serial data out pin (SDO) under
the control of the serial clock (SCK). Data is updated on the
Through timing control of the CS and SCK pins, the
LTC2430/LTC2431 offer several flexible modes of
operation (internal or external SCK and free-running
conversion modes). These various modes do not require
programming configuration registers; moreover, they do
not disturb the cyclic operation described above. These
modes of operation are described in detail in the Serial
Interface Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or
60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter
system clock. The LTC2430/LTC2431 incorporate a highly
accurate on-chip oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2430/
LTC2431 achieve a minimum of 110dB rejection at the line
frequency (50Hz or 60Hz ±2%).
Ease of Use
The LTC2430/LTC2431 data output has no latency, filter
settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog inputs is easy.
CONVERT
SLEEP
FALSE
falling edge of SCK allowing the user to reliably latch data
on the rising edge of SCK (see Figure 3). The data output
state is concluded once 24 bits are read out of the ADC or
when CS is brought HIGH. The device automatically initiates
a new conversion and the cycle repeats.
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
2431 F02
Figure 2. LTC2430/LTC2431 State Transition Diagram
The LTC2430/LTC2431 perform offset and full-scale calibrations in every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage change and temperature
drift.
24301f
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APPLICATIO S I FOR ATIO
Power-Up Sequence
The LTC2430/LTC2431 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 2V. This feature guarantees the
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the LTC2430 or LTC2431 creates an internal power-onreset (POR) signal with a duration of approximately 1ms.
The POR signal clears all internal registers. Following the
POR signal, the converter starts a normal conversion
cycle and follows the succession of states described
above. The first conversion result following POR is accurate within the specifications of the device if the power
supply voltage is restored within the operating range
(2.7V to 5.5V) before the end of the POR time interval.
Reference Voltage Range
The LTC2430/LTC2431 accept a differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF – pins covers the entire range
from GND to VCC. For correct converter operation, the
REF + pin must always be more positive than the REF – pin.
The LTC2430/LTC2431 can accept a differential reference
voltage from 0.1V to VCC. The converter (LTC2430 or
LTC2431) output noise is determined by the thermal noise
of the front-end circuits, and, as such, its value in microvolts is nearly constant with reference voltage. A decrease
in reference voltage will not significantly improve the
converter’s effective resolution. On the other hand, a reduced reference voltage will improve the converter’s overall INL performance. A reduced reference voltage will also
improve the converter performance when operated with
an external conversion clock (external FO signal) at substantially higher output data rates.
Input Voltage Range
The analog input is truly differential with an absolute/common mode range for the IN+ and IN– input pins extending
from GND – 0.3V to VCC + 0.3V. Outside these limits, the
ESD protection devices begin to turn on and the errors due
to input leakage current increase rapidly. Within these limits, the LTC2430 or LTC2431 converts the bipolar differential input signal, VIN = IN + – IN –, from – FS = – 0.5 • VREF
to +FS = 0.5 • VREF where VREF = REF+ – REF –. Outside this
range the converter indicates the overrange or the
underrange condition using distinct output codes.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the performance
of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between
these series resistors and the corresponding pins as low
as possible; therefore, the resistors should be located as
close as practical to the pins. In addition, series resistors
will introduce a temperature dependent offset error due to
the input leakage current. A 1nA input leakage current will
develop a 1ppm offset error on a 5k resistor if VREF = 5V.
This error has a very strong temperature dependency.
Output Data Format
The LTC2430/LTC2431 serial output data stream is 24 bits
long. The first 3 bits represent status information indicating the sign and conversion state. The next 21 bits are the
conversion result, MSB first. The third and fourth bits together are also used to indicate an underrange condition
(the differential input voltage is below – FS) or an overrange
condition (the differential input voltage is above + FS).
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is 0.01µF) may be
required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 21.6MΩ which will
generate a gain error of approximately 0.023ppm for each
ohm of source resistance driving IN+ or IN –. When FO =
HIGH (internal oscillator and 50Hz notch), the typical
differential input resistance is 26MΩ which will generate
a gain error of approximately 0.019ppm for each ohm of
source resistance driving IN+ or IN –. When FO is driven by
RSOURCE
VINCM + 0.5VIN
IN +
CPAR
≅ 20pF
CIN
LTC2430/
LTC2431
RSOURCE
VINCM – 0.5VIN
IN –
CPAR
≅ 20pF
CIN
2431 F12
Figure 12. An RC Network at IN + and IN –
50
VCC = 5V
VREF + = 5V
VREF – = GND
VIN + = 3.75V
CIN = 0.01µF
VIN – = 1.25V
FO = GND
TA = 25°C
CIN = 0.001µF
40
+FS ERROR (ppm)
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The CPAR capacitor
includes the LTC2430/LTC2431 pin capacitance (5pF typical) plus the capacitance of the test fixture used to obtain
the results shown in Figures 13 and 14. A careful implementation can bring the total input capacitance (CIN +
CPAR) closer to 5pF thus achieving better performance
than the one predicted by Figures 13 and 14. For simplicity, two distinct situations can be considered.
an external oscillator with a frequency fEOSC (external
conversion clock operation), the typical differential input
resistance is 3.3 • 1012/fEOSCΩ and each ohm of source
resistance driving IN+ or IN – will result in 0.15 • 10–6 •
fEOSCppm gain error. The effect of the source resistance on
the two input pins is additive with respect to this gain error.
30
20
CIN = 100pF
10
0
CIN = 0pF
–10
1
10
100
1k
RSOURCE (Ω)
10k
100k
2431 F13
Figure 13. +FS Error vs RSOURCE
10
at IN +
or IN – (Small CIN)
CIN = 0pF
0
–FS ERROR (ppm)
sampling charge transfers when integrated over a substantial time period (longer than 64 internal clock cycles).
CIN = 0.01µF
–10
CIN = 0.001µF
–20
VCC = 5V
VREF + = 5V
VREF – = GND
VIN + = 1.25V
VIN – = 3.75V
FO = GND
TA = 25°C
–30
–40
–50
1
10
CIN = 100pF
100
1k
RSOURCE (Ω)
10k
100k
2431 F14
Figure 14. –FS Error vs RSOURCE at IN + or IN – (Small CIN)
24301f
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APPLICATIO S I FOR ATIO
The typical +FS and –FS errors as a function of the sum of
the source resistance seen by IN+ and IN– for large values
of CIN are shown in Figure 15.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN+ and IN– and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modulation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, it is advisable to carefully match the source impedance seen by the IN+ and IN– pins. When FO = LOW
20
+FS ERROR (ppm)
15
VCC = 5V
VREF + = 5V
VREF – = GND
VIN + = 3.75V
VIN – = 1.25V
FO = GND
TA = 25°C
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
CIN = 1µF, 10µF
10
CIN = 0.1µF
5
CIN = 0.01µF
0
(internal oscillator and 60Hz notch), every 1Ω mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.023ppm. When FO = HIGH (internal oscillator and 50Hz
notch), every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a
differential mode input signal of 0.019ppm. When FO is
driven by an external oscillator with a frequency fEOSC,
every 1Ω mismatch in source impedance transforms a
full-scale common mode input signal into a differential
mode input signal of 0.15 • 10–6 • fEOSCppm. Figure 16
shows the typical offset error due to input common mode
voltage for various values of source resistance imbalance
between the IN+ and IN– pins when large CIN values are
used.
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 1%. Such
40
2431 F15a
or IN –
A
(Large CIN)
0
CIN = 0.01µF
–FS ERROR (ppm)
–5
CIN = 1µF, 10µF
CIN = 0.1µF
OFFSET ERROR (ppm)
Figure 15a. + FS Error vs RSOURCE
at IN +
20
B
C
D
E
0
F
–20
G
–10
–15
–20
VCC = 5V
VREF + = 5V
VREF – = GND
VIN + = 1.25V
VIN – = 3.75V
FO = GND
TA = 25°C
–40
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2431 F15b
Figure 15b. – FS Error vs RSOURCE at IN + or IN – (Large CIN)
VCC = 5V
VREF + = 5V
VREF – = GND
VIN+ = VIN– = VINCM
0
FO = GND
RSOURCEIN – = 500Ω
CIN = 10µF
TA = 25°C
0.5 1 1.5
A: ∆RIN = +1k
B: ∆RIN = +500Ω
C: ∆RIN = +200Ω
D: ∆RIN = 0Ω
2 2.5 3 3.5
VINCM (V)
4 4.5 5
E: ∆RIN = –200Ω
F: ∆RIN = –500Ω
G: ∆RIN = –1k
2431 F16
Figure 16. Offset Error vs Common Mode Voltage
(VINCM = VIN+ = VIN–) and Input Source Resistance Imbalance
(∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)
24301f
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Reference Current
In a similar fashion, the LTC2430 or LTC2431 samples the
differential reference pins REF+ and REF– transfering small
amount of charge to and from the external driving circuits
thus producing a dynamic reference current. This current
does not change the converter offset, but it may degrade
the gain and INL performance. The effect of this current
can be analyzed in the same two distinct situations.
For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01µF)
may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a
quasi constant reference differential impedance. When
FO = LOW (internal oscillator and 60Hz notch), the typical
differential reference resistance is 15.6MΩ which will
generate a gain error of approximately 0.032ppm for each
ohm of source resistance driving REF+ or REF–. When FO
= HIGH (internal oscillator and 50Hz notch), the typical
differential reference resistance is 18.7MΩ which will
generate a gain error of approximately 0.027ppm for each
ohm of source resistance driving REF+ or REF –. When FO
is driven by an external oscillator with a frequency fEOSC
In addition to this gain error, the converter INL performance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 60Hz notch), every
100Ω of source resistance driving REF+ or REF– translates
10
CREF = 0pF
0
+FS ERROR (ppm)
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.
(external conversion clock operation), the typical differential reference resistance is 2.4 • 1012/fEOSCΩ and each
ohm of source resistance drving REF+ or REF– will result
in 0.206 • 10–6 • fEOSCppm gain error. The effect of the
source resistance on the two reference pins is additive
with respect to this gain error. The typical FS errors for
various combinations of source resistance seen by the
REF+ and REF– pins and external capacitance CREF connected to these pins are shown in Figures 17 and 18.
Typical – FS errors are similar to + FS errors with opposite
polarity.
CREF = 0.01µF
–10
CREF = 0.001µF
–20
VCC = 5V CREF = 100pF
VREF + = 5V
VREF – = GND
VIN + = 3.75V
VIN – = 1.25V
FO = GND
TA = 25°C
–30
–40
–50
1
10
100
1k
RSOURCE (Ω)
10k
100k
2431 F17a
Figure 17a. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
50
VCC = 5V
VREF + = 5V
VREF – = GND
VIN + = 1.25V
C
= 0.01µF
VIN – = 3.75V REF
FO = GND
TA = 25°C CREF = 0.001µF
40
–FS ERROR (ppm)
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
30
20
CREF = 100pF
10
0
CREF = 0pF
–10
1
10
100
1k
RSOURCE (Ω)
10k
100k
2431 F17b
Figure 17b. – FS Error vs RSOURCE at REF+ or REF– (Small CIN)
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0
15
CREF = 0.01µF
12
9
–20
CREF = 1µF, 10µF
CREF = 0.1µF
–30
–40
–50
–60
VCC = 5V
VREF + = 5V
VREF – = GND
VIN + = 3.75V
VIN – = 1.25V
FO = GND
TA = 25°C
Figure 18a. +FS Error vs RSOURCE at REF+ or REF– (Large CREF)
–FS ERROR (ppm)
50
40
0
–3
–6
–12
2431 F18a
VCC = 5V
VREF + = 5V
VREF – = GND
VIN + = 1.25V
VIN – = 3.75V
FO = GND
TA = 25°C
6
3
–9
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
60
INL (ppm OF VREF)
+FS ERROR (ppm)
–10
RSOURCE = 1k
RSOURCE = 5k
RSOURCE = 10k
–15
–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5
VINDIF/VREFDIF
FO = GND
VCC = 5V
VREF + = 5V
CREF = 10µF
–
VREF = GND
TA = 25°C
VINCM = 0.5(VIN+ + VIN–) = 2.5V
2431 F19
Figure 19. INL vs Differential Input Voltage (VIN = IN + – IN –)
and Reference Source Resistance (RSOURCE at REF + and REF –)
for Large CREF Values (CREF ≥ 1µF)
CREF = 1µF, 10µF
30
CREF = 0.1µF
20
10
CREF = 0.01µF
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2431 F18b
Figure 18b. – FS Error vs RSOURCE at REF+ or REF– (Large CREF)
into about 0.11ppm additional INL error. When FO = HIGH
(internal oscillator and 50Hz notch), every 100Ω of source
resistance driving REF+ or REF– translates into about
0.092ppm additional INL error. When FO is driven by an
external oscillator with a frequency fEOSC, every 100Ω of
source resistance driving REF+ or REF– translates into
about 0.73 • 10–6 • fEOSCppm additional INL error. Figure␣ 19 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on the
two reference pins is additive with respect to this INL error.
In general, matching of source impedance for the REF+
and REF– pins does not help the gain or the INL error. The
user is thus advised to minimize the combined source
impedance driving the REF+ and REF– pins rather than to
try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
1%. Such a specification can also be easily achieved by an
external clock. When relatively stable resistors (50ppm/°C)
are used for the external source impedance seen by REF+
and REF–, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications, a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maximum full-scale error.
24301f
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Output Data Rate
When using the internal oscillator, the LTC2430/LTC2431
can produce up to 7.5 readings per second with a notch
frequency of 60Hz (FO = LOW) and 6.25 readings per
second with a notch frequency of 50Hz (FO = HIGH). The
actual output data rate will depend upon the length of the
sleep and data output phases which are controlled by the
user and which can be made insignificantly short. When
operated with an external conversion clock (FO connected
to an external oscillator), the LTC2430/LTC2431 output
data rate can be increased as desired. The duration of the
conversion phase is 20510/fEOSC. If fEOSC = 153600Hz, the
converter behaves as if the internal oscillator is used and
the notch is set at 60Hz. There is no significant difference
in the LTC2430/LTC2431 performance between these two
operation modes.
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is nevertheless
accompanied by three potential effects, which must be
carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2430/LTC2431’s exceptional common
mode rejection and by carefully eliminating common
mode to differential mode conversion sources in the input
circuit. The user should avoid single-ended input filters
and should maintain a very high degree of matching and
symmetry in the circuits driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2430/LTC2431
typical performance can be inferred from Figures 13, 14
and 17 in which the horizontal axis is scaled by
153600/fEOSC.
Third, an increase in the frequency of the external oscillator above 1.6MHz (a more than 10× increase in the output
data rate) will start to decrease the effectiveness of the
internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity.
Typical measured performance curves for output data rates
up to 100 readings per second are shown in Figures␣ 20 to
27. In order to obtain the highest possible level of accuracy
from this converter at output data rates above 50 readings
per second, the user is advised to maximize the power
supply voltage used and to limit the maximum ambient
operating temperature. The accuracy is also sensitive to the
clock signal levels and edge rate as discussed in the section Digital Signal Levels. In certain circumstances, a reduction of the differential reference voltage may be
beneficial.
Input Bandwidth
The combined effect of the internal sinc4 digital filter and
of the analog and digital autocalibration circuits determines the LTC2430/LTC2431 input bandwidth. When the
internal oscillator is used, the 3dB input bandwidth of the
LTC2430/LTC2431 is 3.63Hz for 60Hz notch frequency
(FO = LOW) and 3.02Hz for 50Hz notch frequency
(FO = HIGH). If an external conversion clock generator of
frequency fEOSC is connected to the FO pin, the 3dB input
bandwidth is 2.36 • 10–5 • fEOSC.
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled very
accurately by a first order filter with the pole located at the
3dB frequency. When the internal oscillator is used, the
shape of the LTC2430/LTC2431 input bandwidth is shown
in Figure␣ 28. When an external oscillator of frequency
fEOSC is used, the shape of the LTC2430/LTC2431 input
bandwidth can be derived from Figure␣ 28, FO = LOW curve
of the LTC2411 in which the horizontal axis is scaled by
fEOSC/153600.
The conversion noise (2.8µVRMS typical for VREF = 5V) can
be modeled as a white noise source connected to a noise
free converter. The noise spectral density is 67nV/√Hz for
24301f
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OFFSET ERROR (ppm OF VREF)
5
VINCM = VREFCM
VCC = VREF = 5V
VIN = 0V
FO = EXT OSC
9
8
7
6
5
4
TA = 85°C
3
TA = 25°C
2
TA = 85°C
–5
–10
–15
–20
VINCM = VREFCM
VCC = VREF = 5V
FO = EXT OSC
–25
1
0
TA = 25°C
0
+FS ERROR (ppm OF VREF)
10
–30
0
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2431 F21
2431 F20
Figure 20. Offset Error vs Output Data Rate and Temperature
Figure 21. + FS Error vs Output Data Rate and Temperature
30
22
TA = 25°C
21
TA = 85°C
20
RESOLUTION (BITS)
–FS ERROR (ppm OF VREF)
VINCM = VREFCM
V =V
= 5V
25 F CC= EXTREF
OSC
O
15
10
5
TA = 25°C
0
TA = 85°C
–5
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
20
19
18
VINCM = VREFCM
VCC = VREF = 5V
VIN = 0V
FO = EXT OSC
16 REF – = GND
RES = LOG2 (VREF/NOISERMS)
15
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
17
2431 F22
2431 F23
Figure 23. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 22. – FS Error vs Output Data Rate and Temperature
5
22
TA = 25°C
19
TA = 85°C
17 VINCM = VREFCM
VCC = VREF = 5V
F = EXT OSC
16 O –
REF = GND
RES = LOG2(VREF/INLMAX)
15
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2430 F24
Figure 24. Resolution (INLRMS ≤ 1LSB)
vs Output Data Rate and Temperature
28
OFFSET ERROR (ppm OF VREF)
RESOLUTION (BITS)
20
18
VINCM = VREFCM
VIN = 0V
REF – = GND
FO = EXT OSC
TA = 25°C
4
21
3
2
VCC = VREF = 5V
1
0
VCC = 2.7V
VREF = 2.5V
–1
–2
–3
–4
–5
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2431 F25
Figure 25. Offset Error vs Output
Data Rate and VCC
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VCC = VREF = 5V
21
20
19
VCC = 2.7V
VREF = 2.5V
18
VINCM = VREFCM
17 VIN = 0V
FO = EXT OSC
REF – = GND
16
TA = 25°C
RES = LOG2(VREF/NOISERMS)
15
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
RESOLUTION (BITS)
RESOLUTION (BITS)
21
22
20
VCC = VREF = 5V
19
18
VCC = 2.7V
VINCM = VREFCM
VREF = 2.5V
V
=
0V
17
IN
FO = EXT OSC
REF – = GND
16
TA = 25°C
RES = LOG2(VREF/INLMAX)
15
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2430 F26
2430 F27
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and VCC
1000
–1
–2
–3
FO = HIGH
FO = LOW
–4
–5
–6
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
INPUT SIGNAL ATTENUATION (dB)
0
Figure 27. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and VCC
100
FO = LOW
10
FO = HIGH
1
0.1
1
3
4
0
5
2
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2431 F28
Figure 28. Input Signal Bandwidth Using the Internal Oscillator
an infinite bandwidth source and 216nV/√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the
simultaneous requirements of very low bandwidth (just a
few Hz) in order to reduce the output referred noise and
relatively high bandwidth (at least 500kHz) necessary to
drive the input switched-capacitor network. A possible
solution is a high gain, low bandwidth amplifier stage
followed by a high bandwidth unity-gain buffer.
When external amplifiers are driving the LTC2430/
LTC2431, the ADC input referred system noise calculation
can be simplified by Figure 29. The noise of an amplifier
driving the LTC2430/LTC2431 input pin can be modeled
as a band-limited white noise source. Its bandwidth can be
0.1
10
100 1k
10k 100k
1
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
1M
2431 G29
Figure 29. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
approximated by the bandwidth of a single pole lowpass
filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure␣ 29, using fi as the x-axis
selector, we can find on the y-axis the noise equivalent
bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal
calibration and filtering. The noise of the driving amplifier
referred to the converter input and including all these
effects can be calculated as N␣ = ni • √freqi. The total system
noise (referred to the LTC2430/LTC2431 input) can now
be obtained by summing as square root of sum of squares
the three ADC input referred noise sources: the LTC2430/
LTC2431 internal noise (2.8µV), the noise of the IN +
driving amplifier and the noise of the IN – driving amplifier.
24301f
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If the FO pin is driven by an external oscillator of frequency
fEOSC, Figure 29 can still be used for noise calculation if the
x-axis is scaled by fEOSC/153600. For large values of the
ratio fEOSC/153600, the Figure 29 plot accuracy begins to
decrease, but in the same time the LTC2430/LTC2431
noise floor rises and the noise contribution of the driving
amplifiers lose significance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2430/LTC2431 significantly simplifies antialiasing filter requirements.
The sinc4 digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2430/LTC2431’s autocalibration circuits further simplify the antialiasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUTMAX where fN is the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode, fS = 12,800Hz with a 50Hz notch setting and fS =
15,360Hz with a 60Hz notch setting. In the external
oscillator mode, fS = fEOSC/10.
The combined normal mode rejection performance is
shown in Figure␣ 30 for the internal oscillator with 50Hz
notch setting (FO = HIGH) and in Figure␣ 31 for the internal
–30
–40
–50
–60
–70
–80
–90
–100
–110
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2431 F30
Figure 30. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch
30
As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front
of the LTC2430/LTC2431. If passive RC components are
placed in front of the LTC2430/LTC2431, the input dynamic current should be considered (see Input Current
section). In cases where large effective RC time constants
are used, an external buffer amplifier may be required to
minimize the effects of dynamic input current.
0
FO = HIGH
–20
–120
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demonstrated by Figures 34 to 36. Typical measured values of the
normal mode rejection of the LTC2430/LTC2431 operating with an internal oscillator and a 60Hz notch setting are
shown in Figure 34 superimposed over the theoretical
calculated curve. Similarly, typical measured values of the
normal mode rejection of the LTC2430/LTC2431 operating with an internal oscillator and a 50Hz notch setting are
shown in Figure 35 superimposed over the theoretical
calculated curve.
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
0
–10
oscillator with FO = LOW and for the external oscillator
mode. The regions of low rejection occurring at integer
multiples of fS have a very narrow bandwidth. Magnified
details of the normal mode rejection curves are shown in
Figure␣ 32 (rejection near DC) and Figure␣ 33 (rejection at
fS = 256fN) where fN represents the notch frequency.
These curves have been derived for the external oscillator
mode but they can be used in all operating modes by
appropriately selecting the fN value.
FO = LOW OR
FO = EXTERNAL OSCILLATOR,
fEOSC = 10 • fS
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2431 F31
Figure 31. Input Normal Mode Rejection, Internal
Oscillator and FO = LOW or External Oscillator
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INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
APPLICATIO S I FOR ATIO
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
2431 F32
2431 F33
Figure 32. Input Normal Mode Rejection
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN(P-P) = 5V
FO = GND
TA = 25°C
– 60
–80
–100
–120
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2431 F34
0
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
Figure 33. Input Normal Mode Rejection
MEASURED DATA
CALCULATED DATA
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN(P-P) = 5V
FO = 5V
TA = 25°C
–20
–40
– 60
–80
–100
–120
0
25
50
75
100
125
INPUT FREQUENCY (Hz)
150
175
200
2431 F35
Figure 34. Input Normal Mode Rejection vs Input Frequency
Figure 35. Input Normal Mode Rejection vs Input Frequency
Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The proprietary architecture used for the LTC2430/LTC2431 third
order modulator resolves this problem and guarantees a
predictable stable behavior at input signal levels of up to
150% of full scale. In many industrial applications, it is
not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and
LTC2430/LTC2431 are eminently suited for such tasks.
When the perturbation is differential, the specification of
interest is the normal mode rejection for large input signal levels. With a reference voltage VREF␣ =␣ 5V, the
LTC2430/LTC2431 have a full-scale differential input range
of 5V peak-to-peak. Figures 36 and 37 show measurement results for the LTC2430/LTC2431 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale)
input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peakto-peak (full scale) input signal. It is clear that the LTC2430/
LTC2431 rejection performance is maintained with no
compromises in this extreme situation. When operating
with large input signal levels, the user must observe that
such signals do not violate the device absolute maximum
ratings.
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VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
VCC = 5V
VREF = 5V
VINCM = 2.5V
FO = GND
TA = 25°C
– 60
–80
–100
–120
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
0
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
VCC = 5V
VREF = 5V
VINCM = 2.5V
FO = 5V
TA = 25°C
– 60
–80
–100
–120
0
25
50
75
100
125
INPUT FREQUENCY (Hz)
150
2431 F36
Typical strain gauge based bridges deliver only 2mV/Volt
of excitation. As the maximum reference voltage of the
LTC2430/LTC2431 is 5V, remote sensing of applied excitation without additional circuitry requires that excitation
be limited to 5V. This gives only 10mV full scale, which can
be resolved to 1 part in 3500 without averaging. For many
solid state sensors, this is comparable to the sensor. Averaging 128 samples however reduces the noise level by
a factor of eight, bringing the resolving power to 1 part in
40000, comparable to better weighing systems. Hysteresis
and creep effects in the load cells are typically much greater
than this. Most applications that require strain measurements to this level of accuracy are measuring slowly changing phenomena, hence the time required to average a large
number of readings is usually not an issue. For those systems that require accurate measurement of a small incremental change on a significant tare weight, the lack of history
effects in the LTC2400 family is of great benefit.
For those applications that cannot be fulfilled by the
LTC2430/LTC2431 alone, compensating for error in external amplification can be done effectively due to the “no
latency” feature of the LTC2430/LTC2431. No
latency operation allows samples of the amplifier offset
and gain to be interleaved with weighing measurements.
The use of correlated double sampling allows suppression
of 1/f noise, offset and thermocouple effects within the
bridge. Correlated double sampling involves alternating
200
2431 F37
Figure 36. Measured Input Normal Mode Rejection
vs Input Frequency
BRIDGE APPLICATIONS
175
Figure 37. Measured Input Normal Mode Rejection
vs Input Frequency
the polarity of excitation and dealing with the reversal of
input polarity mathematically. Alternatively, bridge excitation can be increased to as much as ±10V, if one of several
precision attenuation techniques is used to produce a
precision divide operation on the reference signal. Another option is the use of a reference within the 5V input
range of the LTC2430/LTC2431 and developing excitation
via fixed gain, or LTC1043 based voltage multiplication,
along with remote feedback in the excitation amplifiers, as
shown in Figures 43 and 45.
Figure 38 shows an example of a simple bridge connection. Note that it is suitable for any bridge application
+
R1
0.1µF
REF +
350Ω
BRIDGE
LT1019
10µF
0.1µF
VCC
SDO
REF –
SCK
IN +
CS
LTC2430/
LTC2431
IN –
GND
FO
R2
2431 F38
R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS
Figure 38. Simple Bridge Connection
24301f
32
LTC2430/LTC2431
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where measurement speed is not of the utmost importance. For many applications where large vessels are
weighed, the average weight over an extended period of
time is of concern and short term weight is not readily
determined due to movement of contents, or mechanical
resonance. Often, large weighing applications involve load
cells located at each load bearing point, the output of
which can be summed passively prior to the signal processing circuitry, actively with amplification prior to the
ADC, or can be digitized via multiple ADC channels and
summed mathematically. The mathematical summation
of the output of multiple LTC2430/LTC2431’s provide the
benefit of a root square reduction in noise. The low power
consumption of the LTC2430/LTC2431 make it attractive
for multidrop communication schemes where the ADC is
located within the load-cell housing.
thermal stability, as input offset voltages and currents,
temperature coefficient of gain settling resistors all become factors.
The circuit in Figure 39 shows an example of a simple
amplification scheme. This example produces a differential output with a common mode voltage of 2.5V, as
determined by the bridge. The use of a true three amplifier
instrumentation amplifier is not necessary, as the LTC2430/
LTC2431 have common mode rejection far beyond that of
most amplifiers. The LTC1051 is a dual autozero amplifier
that can be used to produce a gain of 10 before its input
referred noise dominates the LTC2430/LTC2431 noise.
This example shows a gain of 34, that is determined by a
feedback network built using a resistor array containing
eight individual resistors. The resistors are organized to
optimize temperature tracking in the presence of thermal
gradients. The second LTC1051 buffers the low noise
input stage from the transient load steps produced during
conversion.
A direct connection to a load cell is perhaps best incorporated into the load-cell body, as minimizing the distance to
the sensor largely eliminates the need for protection
devices, RFI suppression and wiring. The LTC2430/
LTC2431 exhibit extremely low temperature dependent
drift. As a result, exposure to external ambient temperature ranges does not compromise performance. The incorporation of any amplification considerably complicates
The gain stability and accuracy of this approach is very
good, due to a statistical improvement in resistor matching due to individual error contribution being reduced. A
gain of 34 may seem low, when compared to common
5VREF
0.1µF
5V
3
8
+
2
5V
–
2
4
350Ω
BRIDGE
–
8
U2A
15
1
RN1
16
6
11
14
7
2
6
4
8
3
5
12
3
+
REF +
VCC
SDO
REF –
4
SCK
IN +
13
U2B
5
CS
LTC2430/
LTC2431
–
7
+
1
9
6
–
U1B
5
10
0.1µF
0.1µF
1
U1A
7
+
RN1 = 5k × 8 RESISTOR ARRAY
U1A, U1B, U2A, U2B = 1/2 LTC1051
IN –
GND
FO
2431 F39
Figure 39. Using Autozero Amplifiers to Reduce Input Referred Noise
24301f
33
LTC2430/LTC2431
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practice in earlier generations of load-cell interfaces, however the accuracy of the LTC2430/LTC2431 changes the
rationale. Achieving high gain accuracy and linearity at
higher gains may prove difficult, while providing little
benefit in terms of noise reduction.
applications where the gain setting resistor can be made
to match the temperature coefficient of the strain gauges.
If the bridge is composed of precision resistors, with only
one or two variable elements, the reference arm of the
bridge can be made to act in conjunction with the feedback
resistor to determine the gain. If the feedback resistor is
incorporated into the design of the load cell, using resistors which match the temperature coefficient of the loadcell elements, good results can be achieved without the
need for resistors with a high degree of absolute accuracy.
The common mode voltage in this case, is again a function
of the bridge output. Differential gain as used with a 350Ω
bridge is:
At a gain of 100, the gain error that could result from
typical open-loop gain of 160dB is –1ppm, however,
worst-case is at the minimum gain of 116dB, giving a gain
error of –158ppm. Worst-case gain error at a gain of 34,
is –54ppm. The use of the LTC1051A reduces the worstcase gain error to –33ppm. The advantage of gain higher
than 34, then becomes dubious, as the input referred
noise sees little improvement and gain accuracy is potentially compromised.
A V = 9.95 =
Note that this 4-amplifier topology has advantages over
the typical integrated 3-amplifier instrumentation amplifier in that it does not have the high noise level common in
the output stage that usually dominates when an instrumentation amplifier is used at low gain. If this amplifier is
used at a gain of 10, the gain error is only 10ppm and input
referred noise is reduced to 0.28µVRMS. The buffer stages
can also be configured to provide gain of up to 50 with high
gain stability and linearity.
R1 + R2
R1 + 175Ω
Common mode gain is half the differential gain. The
maximum differential signal that can be used is 1/4 VREF,
as opposed to 1/2 VREF in the 2-amplifier topology above.
Remote Half Bridge Interface
As opposed to full bridge applications, typical half bridge
applications must contend with nonlinearity in the bridge
output, as signal swing is often much greater. Applications
include RTD’s, thermistors and other resistive elements
that undergo significant changes over their span. For
Figure 40 shows an example of a single amplifier used to
produce single-ended gain. This topology is best used in
5V
+
10µF
0.1µF
5V
350Ω
BRIDGE
3
+
7
LTC1050
2
+
–
0.1µV
6
REF +
175Ω
REF –
+
1µF
4
20k
1µF
R1
4.99k
VCC
IN +
R2
46.4k
LTC2430/
LTC2431
20k
IN –
GND
AV = 9.95 =
R1 + R2
R1 + 175Ω
2431 F40
Figure 40. Bridge Amplification Using a Single Amplifier
24301f
34
LTC2430/LTC2431
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single variable element bridges, the nonlinearity of the half
bridge output can be eliminated completely; if the reference arm of the bridge is used as the reference to the ADC,
as shown in Figure 41. The LTC2430/LTC2431 can accept
inputs up to 1/2 VREF. Hence, the reference resistor R1
must be at least 2× the highest value of the variable
resistor.
In the case of 100Ω platinum RTD’s, this would suggest a
value of 800Ω for R1. Such a low value for R1 is not
advisable due to self-heating effects. A value of 25.5k is
shown for R1, reducing self-heating effects to acceptable
levels for most sensors.
The basic circuit shown in Figure 41 shows connections
for a full 4-wire connection to the sensor, which may be
VS
2.7V TO 5.5V
REF +
R1
25.5k
0.1%
2 4
PLATINUM
100Ω
RTD 1
3
VCC
REF –
LTC2430/
LTC2431
+
IN
IN –
GND
located remotely. The differential input connections will
reject induced or coupled 60Hz interference, however, the
reference inputs do not have the same rejection. If 60Hz or
other noise is present on the RTD, a low pass filter is
recommended as shown in Figure 42. Note that you
cannot place a large capacitor directly at the junction of R1
and R2, as it will store charge from the sampling process.
A better approach is to produce a low pass filter decoupled
from the input lines with a high value resistor (R3).
The use of a third resistor in the half bridge, between the
variable and fixed elements gives essentially the same
result as the two resistor version, but has a few benefits.
If, for example, a 25k reference resistor is used to set the
excitation current with a 100Ω RTD, the negative
reference input is sampling the same external node as the
positive input, but may result in errors if used with a long
cable. For short cable applications, the errors may be
acceptably low. If instead the single 25k resistor is
replaced with a 10k 5% and a 10k 0.1% reference
resistor, the noise level introduced at the reference, at
least at higher frequencies, will be reduced. A filter can be
introduced into the network, in the form of one or more
capacitors, or ferrite beads, as long as the sampling
pulses are not translated into an error. The reference
voltage is also reduced, but this is not undesirable, as it
will decrease the value of the LSB, although, not the input
referred noise level.
2431 F41
Figure 41. Remote Half Bridge Interface
5V
R2
10k
0.1%
R1
10k, 5%
2 4
PLATINUM
100Ω
RTD 1
3
5V
R3
10k
5%
+
1µF
560Ω
LTC1050
–
REF +
VCC
REF –
LTC2430/
LTC2431
10k
10k
IN +
IN –
GND
2431 F42
Figure 42. Remote Half Bridge Sensing with Noise Supression on Reference
24301f
35
LTC2430/LTC2431
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The circuit shown in Figure 42 shows a more rigorous
example of Figure 41, with increased noise suppression
and more protection for remote applications.
drift translates into 0.05ppm/°C gain error. Simpler alternatives, with the amplifiers providing gain using resistor
arrays for feedback, can produce results that are similar to
bridge sensing schemes via attenuators. Note that the
amplifiers must have high open-loop gain or gain error will
be a source of error. The fact that input offset voltage has
relatively little effect on overall error may lead one to use
low performance amplifiers for this application. Note that
the gain of a device such as an LF156, (25V/mV over
Figure 43 shows an example of gain in the excitation circuit
and remote feedback from the bridge. The LTC1043s
provide voltage multiplication, providing ±10V from a 5V
reference with only 1ppm error. The amplifiers are used at
unity-gain and, hence, introduce a very little error due to
gain error or due to offset voltages. A 1µV/°C offset voltage
15V
7
20Ω
Q1
2N3904
15V
U1
4
LTC1043
15V
6
+
4
200Ω
2
10V
LT1236-5
+
47µF
11
0.1µF
12
14
13
+
10µF
0.1µF
1k
5V
7
1µF
–15V
33Ω
8
*
LTC1150
–
10V
3
17
350Ω 10V
BRIDGE
5V
0.1µF
VCC
LTC2430/
LTC2431
REF +
–10V
REF –
33Ω
IN +
IN –
U2
LTC1043
15V
7
Q2
2N3906
6
+
5
3
4
–15V
–
2
2
3
–15V
1k
6
*
LTC1150
20Ω
GND
15
18
0.1µF
*FLYING CAPACITORS ARE
1µF FILM (MKP OR EQUIVALENT)
5V
U2
4
LTC1043
8
7
SEE LTC1043 DATA SHEET FOR
DETAILS ON UNUSED HALF OF U1
*
11
1µF
FILM
12
200Ω
14
13
2431 F43
–10V
17
–10V
Figure 43. LTC1043 Provides Precise 4× Reference for Excitation Voltages
24301f
36
LTC2430/LTC2431
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temperature) will produce a worst-case error of –180ppm
at a noise gain of 3, such as would be encountered in an
inverting gain of 2, to produce –10V from a 5V reference.
of the A/D and multiplexer in normal operation, some
thought should be given to fault conditions that could
result in full excitation voltage at the inputs to the multiplexer or ADC. The use of amplification prior to the
multiplexer will largely eliminate errors associated with
channel leakage developing error voltages in the source
impedance.
The error associated with the 10V excitation would be
–80ppm. Hence, overall reference error could be as high
as 130ppm, the average of the two.
Figure 45 shows a similar scheme to provide excitation
using resistor arrays to produce precise gain. The circuit
is configured to provide 10V and –5V excitation to the
bridge, producing a common mode voltage at the input to
the LTC2430/LTC2431 of 2.5V, maximizing the AC input
range for applications where induced 60Hz could reach
amplitudes up to 2VRMS.
Complete 20-Bit Data Acquistion System in 0.1 Inch2
The LTC2430/LTC2431 provide 20-bit accuracy while
consuming a maximum of 300µA. The MS package of the
LTC2431 makes it especially attractive in applications
where very limited space is available. A complete 20-bit
data acquisition system in 0.1 inch2 is shown in Figure 46
where the LTC2431 is powered by the LT1790 reference
family in an S6 package. A supply voltage from 0.25V
above the LT1790 output level to 20V enables the LT1790
to source up to 1mA and ensure the solid performance of
the LT2431.
The circuits in Figures 43 and 45 could be used where
multiple bridge circuits are involved and bridge output can
be multiplexed onto a single LTC2430/LTC2431, via an
inexpensive multiplexer such as the 74HC4052.
Figure 44 shows the use of an LTC2430/LTC2431 with a
differential multiplexer. This is an inexpensive multiplexer
that will contribute some error due to leakage if used
directly with the output from the bridge, or if resistors are
inserted as a protection mechanism from overvoltage.
Although the bridge output may be within the input range
The 3V, 3.3V, 4.096V and 5V versions of the LT1790 can
power the LTC2430/LTC2431 directly. Lower voltage versions will require a separate VCC supply of 2.7V to 5.5V for
the LTC2430/LTC2431.
5V
5V
+
16
47µF
12
14
REF +
15
REF –
11
LTC2430/
LTC2431
74HC4052
1
5
TO OTHER
DEVICES
13
IN +
3
IN –
2
6
4
8
9
VCC
GND
10
A0
A1
2431 F44
Figure 44. Use a Differential Mulitplexer to Expand Channel Capability
24301f
37
LTC2430/LTC2431
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15V
+
20Ω
Q1
2N3904
1/2
LT1112
1
–
C1
0.1µF
22Ω
5V
3
+
2
LT1236-5
C3
47µF
C1
0.1µF
RN1
10k
10V
1
5V
2
RN1
10k
350Ω BRIDGE
TWO ELEMENTS
VARYING
3
VCC
LTC2430/
LTC2431
REF +
4
REF –
IN +
–5V
IN –
8
RN1
10k
5
7
C2
0.1µF
20Ω
7
15V
RN1 IS CADDOCK T914 10K-010-02
8
–
1/2
LT1112
4
–15V
GND
6
33Ω
×2
Q2, Q3
2N3906
×2
RN1
10k
–15V
+
6
5
2431 F45
Figure 45. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier
24301f
38
LTC2430/LTC2431
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PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
.053 – .068
(1.351 – 1.727)
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN16 (SSOP) 0502
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.90 ± 0.15
(1.93 ± .006)
DETAIL “A”
0.497 ± 0.076
(.0196 ± .003)
REF
0° – 6° TYP
GAUGE PLANE
1 2 3 4 5
0.53 ± 0.01
(.021 ± .006)
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.13 ± 0.076
(.005 ± .003)
MSOP (MS) 0802
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
24301f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
39
LTC2430/LTC2431
U
TYPICAL APPLICATIO
SUPPLY VOLTAGE RANGE:
(VOUT + 0.25V) TO 20V
LT1790
VOUT
4.7µF
6
4
LT1790
1
0.1µF
2
VCC
0.1µF
VCC
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
FO
LTC2431
REF +
SCK
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
Relative Size of Components
IN +
SDO
IN –
CS
3-WIRE
SPI INTERFACE
GND
24301 TA05
THE LT1790 IS AVAILABLE WITH 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V AND 5V OUTPUTS
THE LTC2431 MAY BE POWERED BY THE LT1790 3V, 3.3V, 4.096V AND 5V VERSIONS
Figure 46. Complete 20-Bit Data Acquisition System in 0.1 inch2
RELATED PARTS
PART NUMBER
LT®1019
LT1025
LTC1050
LT1236A-5
LT1460
LT1790
LTC2400
LTC2401/LTC2402
LTC2404/LTC2408
LTC2410
LTC2411
LTC2413
LTC2414/LTC2418
LTC2415
LTC2420
LTC2421/LTC2422
LTC2424/LTC2428
LTC2440
DESCRIPTION
Precision Bandgap Reference, 2.5V, 5V
Micropower Thermocouple Cold Junction Compensator
Precision Chopper Stabilized Op Amp
Precision Bandgap Reference, 5V
Micropower Series Reference
Micropower SOT23 Low Dropout Reference Family
24-Bit, No Latency ∆Σ ADC in SO-8
1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
24-Bit, Fully Differential, No Latency ∆Σ ADC
24-Bit, Fully Differential, No Latency ∆Σ ADC in MS10
24-Bit, Fully Differential, No Latency ∆Σ ADC
8-/16-Channel 24-Bit Differential, No Latency ∆Σ ADC
24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate
20-Bit, No Latency ∆Σ ADC in SO-8
1-/2-Channel, 20-Bit, No Latency ∆Σ ADC in MSOP-10
4-/8-Channel, 20-Bit, No Latency ∆Σ ADC
24-Bit, High Speed, Low Noise ∆Σ ADC
COMMENTS
3ppm/°C Drift, 0.05% Max Initial Accuracy
80µA Supply Current, 0.5°C Initial Accuracy
No External Components 5µV Offset, 1.6µVP-P Noise
0.05% Max Initial Accuracy, 5ppm/°C Drift
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
0.05% Max Initial Accuracy, 10ppm/°C Max Drift
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA
0.29ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA
Simultaneous 50Hz and 60Hz Rejection, 800nVRMS Noise
0.2ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error
Pin Compatible with the LTC2410
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
1.2ppm Noise, Low Power 2.7V to 5.5V Supply, 200µA
1.2ppm Noise, Pin Compatible with LTC2404/LTC2408
200nVRMS Noise, 4000Hz Output Rate
24301f
40
Linear Technology Corporation
LT/TP 0303 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
工商网监
湘ICP备2023018690号
