LTC2450
Easy-to-Use, Ultra-Tiny
16-Bit ΔΣ ADC
DESCRIPTION
FEATURES
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GND to VCC Single-Ended Input Range
0.02LSB RMS Noise
2LSB INL, No Missing Codes
2LSB Offset Error
4LSB Full-Scale Error
Single Conversion Settling Time for Multiplexed
Applications
Single Cycle Operation with Auto Shutdown
350μA Supply Current
50nA Sleep Current
30 Conversions Per Second
Internal Oscillator—No External Components
Required
Single Supply, 2.7V to 5.5V Operation
SPI Interface
Ultra-Tiny 2mm × 2mm DFN Package
APPLICATIONS
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System Monitoring
Environmental Monitoring
Direct Temperature Measurements
Instrumentation
Industrial Process Control
Data Acquisition
Embedded ADC Upgrades
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. East Drive
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 6208279, 6411242, 7088280, 7164378.
The LTC®2450 is an ultra-tiny 16-bit analog-to-digital
converter. The LTC2450 uses a single 2.7V to 5.5V supply,
accepts a single-ended analog input voltage, and communicates through an SPI interface. It includes an integrated
oscillator that does not require any external components.
It uses a delta-sigma modulator as a converter core and
provides single-cycle settling time for multiplexed applications. The converter is available in a 6-pin, 2mm × 2mm
DFN package. The internal oscillator does not require any
external components. The LTC2450 includes a proprietary
input sampling scheme that reduces the average input
sampling current several orders of magnitude.
The LTC2450 is capable of up to 30 conversions per second and, due to the very large oversampling ratio, has
extremely relaxed antialiasing requirements. The LTC2450
includes continuous internal offset and full-scale calibration algorithms which are transparent to the user, ensuring
accuracy over time and over the operating temperature
range. The converter uses its power supply voltage as the
reference voltage and the single-ended, rail-to-rail input
voltage range extends from GND to VCC.
Following a conversion, the LTC2450 can automatically
enter a sleep mode and reduce its power to less than
200nA. If the user samples the ADC once a second, the
LTC2450 consumes an average of less than 50μW from
a 2.7V supply.
TYPICAL APPLICATION
Integral Nonlinearity, VCC = 3V
3.0
VCC = VREF = 3V
2.5
2.0
0.1μF
1.5
10μF
1k
VCC
CLOSE TO
CHIP
VIN
SENSE
LTC2450
CS
SCK
SDO
0.1μF
GND
3-WIRE SPI
INTERFACE
INL (LSB)
1.0
0.5
TA = –45°C, 25°C, 90°C
0
–0.5
–1.0
–1.5
2450 TA01
–2.0
–2.5
–3.0
0
0.5
1.0
1.5
2.0
INPUT VOLTAGE (V)
2.5
3.0
2450 G02
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1
LTC2450
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VCC) ................................... –0.3V to 6V
Analog Input Voltage (VIN) ............–0.3V to (VCC + 0.3V)
Digital Input Voltage......................–0.3V to (VCC + 0.3V)
Digital Output Voltage ...................–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2450C ................................................ 0°C to 70°C
LTC2450I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10sec) ................... 300°C
TOP VIEW
6 SCK
VCC 1
7
VIN 2
5 SDO
4 CS
GND 3
DC PACKAGE
6-LEAD (2mm × 2mm) PLASTIC DFN
TJMAX = 125°C, θJA = 102°C/W
EXPOSED PAD (PIN7) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2450CDC#TRMPBF
LTC2450CDC#TRPBF
LCTR
6-Lead (2mm × 2mm) Plastic DFN
0°C to 70°C
LTC2450IDC#TRMPBF
LTC2450IDC#TRPBF
LCTR
6-Lead (2mm × 2mm) Plastic DFN
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
–40°C to 85°C
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
Resolution (No missing codes)
(Note 3)
l
MIN
Integral Nonlinearity
(Note 4)
l
2
10
LSB
l
2
8
LSB
Offset Error
TYP
MAX
Offset Error Drift
Bits
0.02
l
Gain Error
UNITS
16
0.01
LSB/°C
0.02
% of FS
Gain Error Drift
0.02
LSB/°C
Transition Noise
1.4
μVRMS
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range,otherwise
specifications are at TA = 25°C.
SYMBOL
PARAMETER
VIN
Input Voltage Range
CIN
IN Sampling Capacitance
IDC_LEAK (VIN)
IN DC Leakage Current
ICONV
Input Sampling Current (Note 9)
CONDITIONS
MIN
l
TYP
0
MAX
VCC
0.35
VIN = GND (Note 5)
VIN = VCC (Note 5)
l
l
–10
–10
UNITS
1
1
50
pF
10
10
nA
nA
nA
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LTC2450
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range,otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion
Sleep
CONDITIONS
MIN
l
CS = GND (Note 6)
CS = VCC (Note 6)
TYP
2.7
l
l
350
0.05
MAX
UNITS
5.5
V
600
0.5
μA
μA
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full
operating temperature range,otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
l
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IOZ
Hi-Z Output Leakage Current
TYP
MAX
UNITS
VCC – 0.3
V
–10
0.3
V
10
μA
10
IO = –800μA
l
IO = –1.6mA
l
l
pF
VCC – 0.5
V
–10
0.4
V
10
μA
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range,otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
29
33.3
42
ms
2
MHz
tCONV
Conversion Time
l
fSCK
SCK Frequency Range
l
tlSCK
SCK Low Period
l
250
ns
thSCK
SCK High Period
l
250
ns
t1
CS Falling Edge to SDO Low Z
(Notes 7, 8)
l
0
100
ns
t2
CS Rising Edge to SDO High Z
(Notes 7, 8)
l
0
100
ns
t3
CS Falling Edge to SCK Falling Edge
l
100
tKQ
SCK Falling Edge to SDO Valid
l
0
(Note 7)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND. VCC = 2.7V to 5.5V
unless otherwise specified.
Note 3: Guaranteed by design, not subject to test.
Note 4: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band. Guaranteed by design, test correlation and 3 point transfer curve
measurement.
ns
100
ns
Note 5: CS = VCC. A positive current is flowing into the DUT pin.
Note 6: SCK = VCC or GND. SDO is high impedance.
Note 7: See Figure 3.
Note 8: See Figure 4.
Note 9: Input sampling current is the average input current drawn from the
input sampling network while the LTC2450 is actively sampling the input.
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LTC2450
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity, VCC = 5V
3.0
VCC = VREF = 5V
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0
TA = –45°C, 25°C, 90°C
–0.5
VCC = VREF = 3V
2.5
INL (LSB)
INL (LSB)
2.5
Integral Nonlinearity, VCC = 3V
3.0
–1.0
0.5
TA = –45°C, 25°C, 90°C
0
–0.5
–1.0
–1.5
–1.5
–2.0
–2.0
–2.5
–2.5
–3.0
–3.0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
0
2.5
1.0
1.5
2.0
INPUT VOLTAGE (V)
0.5
2450 G01
2450 G02
Offset Error vs Temperature
Maximum INL vs Temperature
5.0
5.0
4.5
4.5
4.0
4.0
3.5
OFFSET (LSB)
INL (LSB)
3.5
3.0
2.5
VCC = 5V
2.0
VCC = 4.1V
1.5
VCC = 3V
3.0
2.5
VCC = 4.1V
2.0
1.5
VCC = 3V
1.0
VCC = 5V
1.0
0.5
0.5
0
–50
–25
75
50
25
0
TEMPERATURE (°C)
0
–50
100
50
25
0
TEMPERATURE (°C)
–25
75
Gain Error vs Temperature
Transition Noise vs Temperature
3.00
4.5
2.75
TRANSITION NOISE RMS (μV)
5.0
4.0
3.5
3.0
2.5
VCC = 4.1V
2.0
1.5
VCC = 5V
VCC = 3V
1.0
0.5
0
–50
100
2450 G04
2450 G03
GAIN ERROR (LSB)
3.0
2.50
2.25
2.00
1.75
VCC = 5V
1.50 VCC = 4.1V
1.25
1.00
VCC = 3V
0.50
0.75
0.25
–25
50
25
0
TEMPERATURE (°C)
75
100
2450 G05
0
–50 –30
50
–10 10 30
TEMPERATURE (°C)
70
90
2450 G06
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LTC2450
TYPICAL PERFORMANCE CHARACTERISTICS
Conversion Mode Power Supply
Current vs Temperature
Transition Noise vs Output Code
3.00
500
TA = 25°C
2.50
CONVERSION CURRENT (μA)
TRANSITION NOISE RMS (μV)
2.75
2.25
2.00
1.75
VCC = 5V
1.50
1.25
VCC = 3V
1.00
0.50
0.75
VCC = 5V
400
VCC = 3V
300
VCC = 4.1V
200
100
0.25
0
0
–45
0.80
1.00
0.40
0.60
0
0.20
OUTPUT CODE (NORMALIZED TO FULL SCALE)
35
15
–5
55
TEMPERATURE (°C)
–25
75
2450 G08
2450 G07
Sleep Mode Power Supply
Current vs Temperature
Average Power Dissipation
vs Temperature, VCC = 3V
10000
AVERAGE POWER DISSIPATION (μW)
200
VCC = 5V
VCC = 4.1V
100
50
VCC = 3V
–25
25Hz OUTPUT SAMPLE RATE
1000
150
35
15
–5
55
TEMPERATURE (°C)
75
10Hz OUTPUT SAMPLE RATE
100
1Hz OUTPUT SAMPLE RATE
10
–50
95
–25
0
25
50
TEMPERATURE (°C)
75
100
2450 G10
2450 G09
Conversion Period vs
Temperature
42
40
CONVERSION TIME (ms)
SLEEP MODE CURRENT (nA)
250
0
–45
95
38
VCC = 5V, 4.1V, 3V
36
34
32
30
–45 –25
35
15
55
–5
TEMPERATURE (°C)
75
95
2450 G11
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LTC2450
PIN FUNCTIONS
VCC (Pin 1): Positive Supply Voltage and Converter Reference Voltage. Bypass to GND (Pin 3) with a 10μF capacitor
in parallel with a low series inductance 0.1μF capacitor
located as close to the part as possible.
VIN (Pin 2): Analog Input Voltage.
GND (Pin 3): Ground. Connect to a ground plane through
a low impedance connection.
CS (Pin 4): Chip Select Active LOW Digital Input. A LOW on
this pin enables the SDO digital output. A HIGH on this pin
places the SDO output pin in a high impedance state.
SDO (Pin 5): Three-State Serial Data Output. SDO is used
for serial data output during the DATA OUTPUT state and
can be used to monitor the conversion status.
SCK (Pin 6): Serial Clock Input. SCK synchronizes the serial
data output. While digital data is available (the ADC is not
in CONVERT state) and CS is LOW (ADC is not in SLEEP
state) a new data bit is produced at the SDO output pin
following every falling edge applied to the SCK pin.
Exposed Pad (Pin 7): Ground. The Exposed Pad must be
soldered to the same point as Pin 3.
FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
VIN
GND
REF +
16 BIT ΔΣ
A/D
CONVERTER
REF –
CS
SDO
SCK
SPI
INTERFACE
INTERNAL
OSCILLATOR
2450 BD
Figure 1. Functional Block Diagram
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LTC2450
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2450 is a low power, delta-sigma analog-todigital converter with a simple 3-wire interface (see
Figure 1). Its operation is composed of three successive
states: CONVERT, SLEEP and DATA OUTPUT. The operating cycle begins with the CONVERT state, is followed
by the SLEEP state and ends with the DATA OUTPUT
state (see Figure 2). The 3-wire interface consists of
serial data output (SDO), serial clock input (SCK) and the
active low chip select input (CS).
The CONVERT state duration is determined by the LTC2450
conversion time (nominally 33.3 milliseconds). Once
started, this operation can not be aborted except by a low
power supply condition (VCC < 2.1V) which generates an
internal power-on reset signal.
After the completion of a conversion, the LTC2450 enters
the SLEEP state and remains here until both the chip
select and clock inputs are low (CS = SCK = LOW). Following this condition the ADC transitions into the DATA
OUTPUT state.
POWER-ON RESET
CONVERT
SLEEP
NO
The DATA OUTPUT state concludes in one of two different ways. First, the DATA OUTPUT state operation is
completed once all 16 data bits have been shifted out and
the clock then goes low, which corresponds to the 16th
falling edge of SCK. Second, the DATA OUTPUT state can
be aborted at any time by a LOW-to-HIGH transition on
the CS input. Following either one of these two actions,
the LTC2450 will enter the CONVERT state and initiate a
new conversion cycle.
When the power supply voltage VCC applied to the converter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
SCK = LOW
AND
CS = LOW?
DATA OUTPUT
16TH FALLING
EDGE OF SCK
OR
CS = HIGH?
Upon entering the DATA OUTPUT state, SDO outputs the
most significant bit (D15) of the conversion result. During
this state, the ADC shifts the conversion result serially
through the SDO output pin under the control of the SCK
input pin. There is no latency in generating this result and
it corresponds to the last completed conversion. A new
bit of data appears at the SDO pin following each falling
edge detected at the SCK input pin. The user can reliably
latch this data on every rising edge of the external serial
clock signal driving the SCK pin (see Figure 3).
Power-Up Sequence
YES
NO
While in the SLEEP state, whenever the chip select input
is pulled high (CS = HIGH), the LTC2450’s power supply
current is reduced to less than 200nA. When the chip select
input is pulled low (CS = LOW), and SCK is maintained
at a HIGH logic level, the LTC2450 will return to a normal
power consumption level. During the SLEEP state, the
result of the last conversion is held indefinitely in a static
register.
YES
2450 F02
Figure 2. LTC2450 State Transition Diagram
When VCC rises above this critical threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2450 starts
a conversion cycle and follows the succession of states
described in Figure 2. The first conversion result following POR is accurate within the specifications of the
device if the power supply voltage VCC is restored within
the operating range (2.7V to 5.5V) before the end of the
POR time interval.
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LTC2450
APPLICATIONS INFORMATION
Ease of Use
The LTC2450 data output has no latency, filter settling delay
or redundant results associated with the conversion cycle.
There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple
analog input voltages requires no special actions.
this range. Thus the converter resolution remains at 1LSB
independent of the reference voltage. INL, offset, and fullscale errors vary with the reference voltage as indicated
by the Typical Performance Characteristics graphs. These
error terms will decrease with an increase in the reference
voltage (as the LSB size in μV increases).
The LTC2450 performs offset and full-scale calibrations
every conversion. This calibration is transparent to the
user and has no effect upon the cyclic operation described
previously. The advantage of continuous calibration is
extreme stability of the ADC performance with respect to
time and temperature.
Input Voltage Range
The LTC2450 includes a proprietary input sampling scheme
that reduces the average input current several orders of
magnitude as compared to traditional delta sigma architectures. This allows external filter networks to interface
directly to the LTC2450. Since the average input sampling
current is 50nA, an external RC lowpass filter using a 1kΩ
and 0.1μF results in
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