LTC2631
Single 12-/10-/8-Bit I2C
VOUT DACs with
10ppm/°C Reference
Description
Features
Integrated Precision Reference
2.5V Full-Scale 10ppm/°C (LTC2631-L)
4.096V Full-Scale 10ppm/°C (LTC2631-H)
nn Maximum INL Error: 1LSB (LTC2631A-12)
nn Bidirectional Reference: Input or 10ppm/°C Output
nn 400kHz I2C Interface
nn Nine Selectable Addresses (LTC2631-Z)
nn Low Noise (0.7mV
P-P , 0.1Hz to 200kHz)
nn Guaranteed Monotonic Over Temperature
nn 2.7V to 5.5V Supply Range (LTC2631-L)
nn Low Power Operation: 180µA at 3V
nn Power Down to 1.8µA Maximum (C and I Grades)
nn Power-On Reset to Zero or Mid-Scale Options
nn Double-Buffered Data Latches
nn Guaranteed Operation from –40°C to 125°C (H-Grade)
nn 8-Lead TSOT-23 (ThinSOT™) Package
The LTC®2631 is a family of 12-, 10-, and 8-bit voltageoutput DACs with an integrated, high accuracy, low-drift
reference in an 8-lead TSOT-23 package. It has a rail-torail output buffer that is guaranteed monotonic.
nn
The LTC2631-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2631-H
has a full-scale output of 4.096V, and operates from a
4.5V to 5.5V supply. A 10ppm/°C reference output is available at the REF pin.
Each DAC can also operate in External Reference mode,
in which a voltage supplied to the REF pin sets the fullscale output.
The LTC2631 DACs use a 2-wire, I2C-compatible serial
interface. The LTC2631 operates in both the standard
mode (clock rate of 100kHz) and the fast mode (clock
rate of 400kHz).
Applications
The LTC2631 incorporates a power-on reset circuit.
Op-tions are available for reset to zero-scale or reset to
mid-scale after power-up.
Mobile Communications
nn Process Control and Industrial Automation
nn Automatic Test Equipment
nn Portable Equipment
nn Automotive
nn Optical Networking
nn
CA0
I2C
ADDRESS
DECODE
(LTC2631-M)
VCC
REF
INTERNAL
REFERENCE
RESISTOR
DIVIDER
I2C
INTERFACE
SDA
1.0
REF_SEL
VCC = 3V
VFS = 2.5V
0.5
CONTROL
DECODE LOGIC
SCL
SWITCH
Integral Nonlinearity (LTC2631A-LM12)
INL (LSB)
Block Diagram
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 5396245, 5859606, 6891433, 6937178
and 7414561.
0
DACREF
INPUT
REGISTER
DAC
REGISTER
DAC
VOUT
–0.5
–1.0
GND
0
1024
2048
3072
4095
CODE
2631 TA01
2631 TA01b
2631fd
For more information www.linear.com/LTC2631
1
LTC2631
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (VCC).................................... –0.3V to 6V
REF_SEL, SCL, SDA...................................... –0.3V to 6V
VOUT, CA0, CA1, REF..........–0.3V to Min(VCC + 0.3V, 6V)
Operating Temperature Range
LTC2631C................................................. 0°C to 70°C
LTC2631I.............................................. –40°C to 85°C
LTC2631H........................................... –40°C to 125°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
Pin Configuration
LTC2631-Z
LTC2631-M
TOP VIEW
CA0 1
SCL 2
SDA 3
GND 4
8 CA1
7 VOUT
6 REF
5 VCC
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
TJMAX = 150°C (NOTE 5), θJA = 195°C/W
2
TOP VIEW
CA0 1
SCL 2
SDA 3
GND 4
8 REF_SEL
7 VOUT
6 REF
5 VCC
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
TJMAX = 150°C (NOTE 5), θJA = 195°C/W
2631fd
For more information www.linear.com/LTC2631
LTC2631
Order Information
LTC2631 A
C
TS8 –L
M
12
http://www.linear.com/product/LTC2631#orderinfo
#TRM PBF
LEAD FREE DESIGNATOR
TAPE AND REEL
TR = 2,500-Piece Tape and Reel
TRM = 500-Piece Tape and Reel
RESOLUTION
12 = 12-Bit
10 = 10-Bit
8 = 8-Bit
POWER-ON RESET
M = Reset to Mid-Scale
Z = Reset to Zero-Scale
FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
TS8 = 8-Lead Plastic TSOT-23
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
H = Automotive Temperature Range (–40°C to 125°C)
ELECTRICAL GRADE (OPTIONAL)
A = ±1LSB Maximum INL (12-Bit)
PRODUCT PART NUMBER
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2631fd
For more information www.linear.com/LTC2631
3
LTC2631
Product Selection Guide
PART NUMBER
VFS WITH INTERNAL
PART MARKING* REFERENCE
POWER-ON RESET
TO CODE
PIN 8
RESOLUTION
VCC
MAXIMUM INL
LTC2631A-LM12
LTDHF
2.5V • (4095/4096)
Mid-Scale
REF_SEL
12-Bit
2.7V – 5.5V
±1LSB
LTC2631A-LZ12
LTDHG
2.5V • (4095/4096)
Zero
CA1
12-Bit
2.7V – 5.5V
±1LSB
LTC2631A-HM12 LTDHH
4.096V • (4095/4096)
Mid-Scale
REF_SEL
12-Bit
4.5V – 5.5V
±1LSB
LTC2631A-HZ12
LTDHJ
4.096V • (4095/4096)
Zero
CA1
12-Bit
4.5V – 5.5V
±1LSB
LTC2631-LM12
LTDHF
2.5V • (4095/4096)
Mid-Scale
REF_SEL
12-Bit
2.7V – 5.5V
±2.5LSB
LTC2631-LM10
LTDHK
2.5V • (1023/1024)
Mid-Scale
REF_SEL
10-Bit
2.7V – 5.5V
±1LSB
LTC2631-LM8
LTDHQ
2.5V • (255/256)
Mid-Scale
REF_SEL
8-Bit
2.7V – 5.5V
±0.5LSB
LTC2631-LZ12
LTDHG
2.5V • (4095/4096)
Zero
CA1
12-Bit
2.7V – 5.5V
±2.5LSB
LTC2631-LZ10
LTDHM
2.5V • (1023/1024)
Zero
CA1
10-Bit
2.7V – 5.5V
±1LSB
LTC2631-LZ8
LTDHR
2.5V • (255/256)
Zero
CA1
8-Bit
2.7V – 5.5V
±0.5LSB
LTC2631-HM12
LTDHH
4.096V • (4095/4096)
Mid-Scale
REF_SEL
12-Bit
4.5V – 5.5V
±2.5LSB
LTC2631-HM10
LTDHN
4.096V • (1023/1024)
Mid-Scale
REF_SEL
10-Bit
4.5V – 5.5V
±1LSB
LTC2631-HM8
LTDHS
4.096V • (255/256)
Mid-Scale
REF_SEL
8-Bit
4.5V – 5.5V
±0.5LSB
LTC2631-HZ12
LTDHJ
4.096V • (4095/4096)
Zero
CA1
12-Bit
4.5V – 5.5V
±2.5LSB
LTC2631-HZ10
LTDHP
4.096V • (1023/1024)
Zero
CA1
10-Bit
4.5V – 5.5V
±1LSB
LTC2631-HZ8
LTDHT
4.096V • (255/256)
Zero
CA1
8-Bit
4.5V – 5.5V
±0.5LSB
*The temperature grade is identified by a label on the shipping container.
4
2631fd
For more information www.linear.com/LTC2631
LTC2631
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
LTC2631-8
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
LTC2631-10
LTC2631-12
MAX MIN TYP MAX MIN TYP
LTC2631A-12
MAX MIN TYP MAX
UNITS
DC Performance
l
8
10
12
12
Bits
Monotonicity
VCC = 3V, Internal Ref. (Note 3) l
8
10
12
12
Bits
DNL
Differential
Nonlinearity
VCC = 3V, Internal Ref. (Note 3) l
±0.5
INL
Integral
Nonlinearity
VCC = 3V, Internal Ref. (Note 3) l
±0.05 ±0.5
ZSE
Zero-Scale Error VCC = 3V, Internal Ref.,
Code = 0
VOS
Offset Error
VOSTC
VOS Temperature VCC = 3V, Internal Ref. (Note 4)
Coefficient
FSE
Full-Scale Error
VCC = 3V, Internal Ref.
(Note 14)
VFSTC
Full-Scale
Voltage
Temperature
Coefficient
VCC = 3V, Internal Ref. (Note 9)
C-Grade
I-Grade
H-Grade
Resolution
DC Output
Impedance
±1
±1
LSB
±0.2
±1
±1
±2.5
±0.5
±1
LSB
mV
l
0.5
5
0.5
5
0.5
5
0.5
5
VCC = 3V, Internal Ref. (Note 4) l
±0.5
±5
±0.5
±5
±0.5
±5
±0.5
±5
±10
l
Load Regulation Internal Ref., Mid-Scale,
VCC = 3V ±10%,
–5mA ≤ IOUT ≤ 5mA,
VCC = 5V ±10%,
–10mA ≤ IOUT ≤ 10mA
ROUT
±0.5
Internal Ref., Mid-Scale,
VCC = 3V ±10%,
–5mA ≤ IOUT ≤ 5mA,
VCC = 5V ±10%,
–10mA ≤ IOUT ≤ 10mA
±0.08 ±0.4
±10
±10
±10
±10
±10
±0.08 ±0.4
±10
±0.08 ±0.4
±10
±10
±10
±0.08 ±0.4
±10
±10
±10
±10
±10
±10
mV
µV/°C
%FSR
ppm/°C
ppm/°C
ppm/°C
l
0.009 0.016
0.035 0.064
0.14 0.256
0.14 0.256 LSB/mA
l
0.009 0.016
0.035 0.064
0.14 0.256
0.14 0.256 LSB/mA
l
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
Ω
l
0.09 0.156
0.09 0.156
0.09 0.156
0.09 0.156
Ω
SYMBOL
PARAMETER
CONDITIONS
VOUT
DAC Output Span
External Reference
Internal Reference
MIN
PSR
Power Supply Rejection
VCC = 3V ±10% or 5V ±10%
ISC
Short-Circuit Output Current (Note 5)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero-Scale; VOUT shorted to VCC
Full-Scale; VOUT shorted to GND
l
l
VCC
Positive Supply Voltage
For Specified Performance
l
ICC
Supply Current (Note 6)
VCC = 3V, VREF = 2.5V, External Reference
VCC = 3V, Internal Reference
VCC = 5V, VREF = 2.5V, External Reference
VCC = 5V, Internal Reference
l
l
l
l
ISD
Supply Current in Power-Down Mode
(Note 6)
VCC = 5V, C-Grade, I-Grade
VCC = 5V, H-Grade
l
l
TYP
MAX
UNITS
0 to VREF
0 to 2.5
V
V
–80
dB
27
–28
48
–48
mA
mA
5.5
V
150
180
160
190
200
240
210
260
µA
µA
µA
µA
0.6
0.6
1.8
4
µA
µA
Power Supply
2.7
2631fd
For more information www.linear.com/LTC2631
5
LTC2631
The
l denotes the specifications which apply over the full operating
electrical
characteristics
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
V
220
kΩ
Reference Input
Input Voltage Range
l
0
Resistance
l
160
Capacitance
IREF
190
7.5
Reference Current, Power-Down Mode
DAC Powered Down
l
pF
0.005
0.1
µA
1.250
1.260
V
Reference Output
Output Voltage
l
1.240
Reference Temperature Coefficient
±10
ppm/°C
Output Impedance
0.5
kΩ
Capacitive Load Driving
10
µF
2.5
mA
Short-Circuit Current
VCC = 5.5V; REF Shorted to GND
VIL
Low Level Input Voltage (SDA and SCL)
(Note 13)
l
–0.5
VIH
High Level Input Voltage (SDA and SCL) (Note 10)
l
0.7VCC
VIL(CAn)
Low Level Input Voltage on CAn
(n = 0, 1)
See Test Circuit 1
l
VIH(CAn)
High Level Input Voltage on CAn
(n = 0, 1)
See Test Circuit 1
l
RINH
Resistance from CAn (n = 0, 1)
to VCC to Set CAn = VCC
See Test Circuit 2
l
10
kΩ
RINL
Resistance from CAn (n = 0, 1)
to GND to Set CAn = GND
See Test Circuit 2
l
10
kΩ
RINF
Resistance from CAn (n = 0, 1)
to VCC or GND to Set CAn = Float
See Test Circuit 2
l
2
VOL
Low Level Output Voltage
Sink Current = 3mA
l
0
0.4
V
tOF
Output Fall Time
VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 11)
l
20 + 0.1CB
250
ns
tSP
Pulse Width of Spikes Suppressed by
Input Filter
l
0
50
ns
IIN
Input Leakage
0.1VCC ≤ VIN ≤ 0.9VCC
l
±1
µA
CIN
I/O Pin Capacitance
(Note 7)
l
10
pF
CB
Capacitive Load for Each Bus Line
l
400
pF
CCAn
External Capacitive Load on Address
Pin CAn (n = 0, 1)
l
10
pF
Digital I/O
6
0.3VCC
V
V
0.15VCC
0.85VCC
V
V
MΩ
2631fd
For more information www.linear.com/LTC2631
LTC2631
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL
PARAMETER
CONDITIONS
Settling Time
VCC = 3V (Note 8)
±0.39% (±1LSB at 8-Bits)
±0.098% (±1LSB at 10-Bits)
±0.024% (±1LSB at 12-Bits)
MIN
TYP
MAX
UNITS
AC Performance
tS
en
3.2
3.8
4.1
µs
µs
µs
Voltage-Output Slew Rate
1
V/µs
Capacitance Load Driving
500
pF
Glitch Impulse
At Mid-Scale Transition
2.1
nV•s
Multiplying Bandwidth
External Reference
300
kHz
Output Voltage Noise Density
At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
140
130
160
150
nV√Hz
nV√Hz
nV√Hz
nV√Hz
Output Voltage Noise
0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference,
CREF = 0.33µF
20
20
650
670
µVP-P
µVP-P
µVP-P
µVP-P
Timing
Characteristics l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 12).
LTC2631-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2631A-LM12/-LZ12 (VFS = 2.5V)
SYMBOL
PARAMETER
fSCL
SCL Clock Frequency
CONDITIONS
l
MIN
0
TYP
MAX
UNITS
400
kHz
tHD(STA)
Hold Time (Repeated) Start Condition
l
0.6
µs
tLOW
Low Period of the SCL Clock Pin
l
1.3
µs
tHIGH
High Period of the SCL Clock Pin
l
0.6
µs
tSU(STA)
Set-Up Time for a Repeated Start Condition
l
0.6
µs
tHD(DAT)
Data Hold Time
l
0
tSU(DAT)
Data Set-Up Time
l
100
tr
Rise Time of Both SDA and SCL Signals
(Note 11)
l
20 + 0.1CB
300
ns
tf
Fall Time of Both SDA and SCL Signals
(Note 11)
l
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for Stop Condition
l
0.6
µs
tBUF
Bus Free Time Between a Stop and Start Condition
l
1.3
µs
0.9
µs
ns
2631fd
For more information www.linear.com/LTC2631
7
LTC2631
The
l denotes the specifications which apply over the full operating
electrical
characteristics
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
LTC2631-8
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
LTC2631-10
LTC2631-12
MAX MIN TYP MAX MIN TYP
LTC2631A-12
MAX MIN TYP MAX
UNITS
DC Performance
Resolution
l
8
8
10
12
Monotonicity
VCC = 5V, Internal Ref. (Note 3)
Differential
Nonlinearity
VCC = 5V, Internal Ref. (Note 3)
l
±0.5
INL
Integral
Nonlinearity
VCC = 5V, Internal Ref. (Note 3)
l
±0.05 ±0.5
ZSE
Zero-Scale Error VCC = 5V, Internal Ref., Code = 0 l
0.5
5
0.5
5
0.5
5
0.5
5
mV
VOS
Offset Error
±0.5
±5
±0.5
±5
±0.5
±5
±0.5
±5
mV
VOSTC
VOS Temperature VCC = 5V, Internal Ref. (Note 4)
Coefficient
FSE
Full-Scale Error
VCC = 5V, Internal Ref. (Note 14) l
VFSTC
Full-Scale
Voltage
Temperature
Coefficient
VCC = 5V, Internal Ref. (Note 9)
C-Grade
I-Grade
H-Grade
ROUT
l
±10
±0.08 ±0.4
±10
±10
±10
12
Bits
DNL
VCC = 5V, Internal Ref. (Note 4)
10
12
l
12
±0.5
±0.2
±1
±1
±10
±2.5
±0.5
±10
±0.08 ±0.4
±0.08 ±0.4
±10
±10
±10
0.022 0.04
0.09
DC Output
Impedance
0.09 0.156
0.09 0.156
0.09 0.156
CONDITIONS
MIN
VOUT
DAC Output Span
External Reference
Internal Reference
PSR
Power Supply Rejection
VCC = 5V ±10%
ISC
Short-Circuit Output Current (Note 5)
Sinking
Sourcing
VFS = VCC = 5.5V
Zero-Scale; VOUT shorted to VCC
Full-Scale; VOUT shorted to GND
l
l
VCC
Positive Supply Voltage
For Specified Performance
l
ICC
Supply Current (Note 6)
VCC = 5V, VREF = 4.096V, External Reference
VCC = 5V, Internal Reference
l
l
ISD
Supply Current in Power-Down Mode
(Note 6)
VCC = 5V, C-Grade, I-Grade
VCC = 5V, H-Grade
l
l
±1
LSB
µV/°C
±10
±10
±10
0.006 0.01
PARAMETER
LSB
±0.08 ±0.4
±10
±10
±10
SYMBOL
±1
±10
l
Load Regulation VCC = 5V ±10%, Internal Ref.
Mid-Scale, –10mA ≤ IOUT ≤ 10mA
l
VCC = 5V ±10%, Internal Ref.
Mid-Scale, –10mA ≤ IOUT ≤ 10mA
Bits
±1
0.16
%FSR
ppm/°C
ppm/°C
ppm/°C
0.09 0.16 LSB/mA
0.09 0.156
TYP
MAX
Ω
UNITS
0 to VREF
0 to 4.096
V
V
–80
dB
27
–28
48
–48
mA
mA
5.5
V
160
200
220
270
µA
µA
0.6
0.6
1.8
4
µA
µA
Power Supply
8
4.5
2631fd
For more information www.linear.com/LTC2631
LTC2631
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
V
190
220
kΩ
Reference Input
Input Voltage Range
l
0
Resistance
l
160
Capacitance
IREF
7.5
Reference Current, Power-Down Mode
DAC Powered Down
l
pF
0.005
0.1
2.048
2.064
µA
Reference Output
Output Voltage
l
2.032
V
Reference Temperature Coefficient
±10
ppm/°C
Output Impedance
0.5
kΩ
Capacitive Load Driving
10
µF
4.3
mA
Short-Circuit Current
VCC = 5.5V; REF Shorted to GND
VIL
Low Level Input Voltage (SDA and SCL)
(Note 13)
l
–0.5
VIH
High Level Input Voltage (SDA and SCL) (Note 10)
l
0.7VCC
VIL(CAn)
Low Level Input Voltage on CAn
(n = 0, 1)
See Test Circuit 1
l
VIH(CAn)
High Level Input Voltage on CAn
(n = 0, 1)
See Test Circuit 1
l
RINH
Resistance from CAn (n = 0, 1)
to VCC to Set CAn = VCC
See Test Circuit 2
l
10
kΩ
RINL
Resistance from CAn (n = 0, 1)
to GND to Set CAn = GND
See Test Circuit 2
l
10
kΩ
RINF
Resistance from CAn (n = 0, 1)
to VCC or GND to Set CAn = Float
See Test Circuit 2
l
2
VOL
Low Level Output Voltage
Sink Current = 3mA
l
0
0.4
V
tOF
Output Fall Time
VO = VIH(MIN) to VO = VIL(MAX),
CB = 10pF to 400pF (Note 11)
l
20 + 0.1CB
250
ns
tSP
Pulse Width of Spikes Suppressed by
Input Filter
l
0
50
ns
IIN
Input Leakage
0.1VCC ≤ VIN ≤ 0.9VCC
l
±1
µA
CIN
I/O Pin Capacitance
(Note 7)
l
10
pF
CB
Capacitive Load for Each Bus Line
l
400
pF
CCAn
External Capacitive Load on Address
Pin CAn (n = 0, 1)
l
10
pF
Digital I/O
0.3VCC
V
V
0.15VCC
0.85VCC
V
V
MΩ
2631fd
For more information www.linear.com/LTC2631
9
LTC2631
The
l denotes the specifications which apply over the full operating
electrical
characteristics
temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL
PARAMETER
CONDITIONS
Settling Time
VCC = 5V (Note 8)
±0.39% (±1LSB at 8-Bits)
±0.098% (±1LSB at 10-Bits)
±0.024% (±1LSB at 12-Bits)
MIN
TYP
MAX
UNITS
AC Performance
tS
en
10
3.7
4.2
4.6
µs
µs
µs
Voltage-Output Slew Rate
1
V/µs
Capacitance Load Driving
500
pF
Glitch Impulse
At Mid-Scale Transition
3.0
nV•s
Multiplying Bandwidth
External Reference
300
kHz
Output Voltage Noise Density
At f = 1kHz, External Reference
At f = 10kHz, External Reference
At f = 1kHz, Internal Reference
At f = 10kHz, Internal Reference
140
130
210
200
nV√Hz
nV√Hz
nV√Hz
nV√Hz
Output Voltage Noise
0.1Hz to 10Hz, External Reference
0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, External Reference
0.1Hz to 200kHz, Internal Reference,
CREF = 0.33µF
20
20
650
670
µVP-P
µVP-P
µVP-P
µVP-P
2631fd
For more information www.linear.com/LTC2631
LTC2631
TIMING
Characteristics l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 12).
LTC2631-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2631A-HM12/-HZ12 (VFS = 4.096V)
SYMBOL
PARAMETER
fSCL
SCL Clock Frequency
CONDITIONS
l
0
tHD(STA)
Hold Time (Repeated) Start Condition
l
0.6
µs
tLOW
Low Period of the SCL Clock Pin
l
1.3
µs
tHIGH
High Period of the SCL Clock Pin
l
0.6
µs
tSU(STA)
Set-Up Time for a Repeated Start Condition
l
0.6
tHD(DAT)
Data Hold Time
l
0
tSU(DAT)
Data Set-Up Time
l
100
tr
Rise Time of Both SDA and SCL Signals
(Note 11)
l
20 + 0.1CB
300
ns
tf
Fall Time of Both SDA and SCL Signals
(Note 11)
l
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for Stop Condition
l
0.6
µs
tBUF
Bus Free Time Between a Stop and Start Condition
l
1.3
µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages are with respect to GND.
Note 3: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS),
rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and
linearity is defined from code 26 to code 4,095. For VFS = 4.096V and
N = 12, kL = 16 and linearity is defined from code 16 to code 4,095.
Note 4: Inferred from measurement at code 16 (LTC2631-12), code 4
(LTC2631-10) or code 1 (LTC2631-8), and at full-scale.
Note 5: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
MIN
TYP
MAX
UNITS
400
kHz
µs
0.9
µs
ns
Note 6: Digital inputs at 0V or VCC.
Note 7: Guaranteed by design and not production tested.
Note 8: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND.
Note 9: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 10: Maximum VIH = VCC(MAX) + 0.5V
Note 11: CB = capacitance of one bus line in pF
Note 12: All values refer to VIH = VIH(MIN) and VIL = VIL(MAX) levels.
Note 13: Minimum VIL exceeds the Absolute Maximum rating. This
condition won’t damage the IC, but could degrade performance.
Note 14: Full-scale error is determined using the reference voltage
measured at the REF pin.
2631fd
For more information www.linear.com/LTC2631
11
LTC2631
Typical Performance Characteristics
LTC2631-L12 (Internal Reference, VFS = 2.5V)
Integral Nonlinearity (INL)
1.0
1.0
VCC = 3V
0
0
–0.5
0
1024
2048
3072
–1.0
4095
0
1024
2048
1.0
2.52
VCC = 3V
INL (NEG)
–0.5
FS OUTPUT VOLTAGE (V)
DNL (LSB)
0
DNL (POS)
0
DNL (NEG)
–0.5
25 50 75 100 125 150
TEMPERATURE (°C)
25 50 75 100 125 150
TEMPERATURE (°C)
Full-Scale Output Voltage
vs Temperature
0.5
INL (POS)
–1.0
–50 –25
0
VCC = 3V
2.51
2.50
2.49
2.48
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
2631 G04
0
25 50 75 100 125 150
TEMPERATURE (°C)
2631 G06
2631 G05
Settling to ±1LSB
SCL
2V/DIV
0
2631 G03
DNL vs Temperature
VCC = 3V
0
1.240
–50 –25
4095
2631 G02
INL vs Temperature
–1.0
–50 –25
3072
CODE
2631 G01
0.5
1.250
1.245
CODE
1.0
VCC = 3V
1.255
VREF (V)
DNL (LSB)
INL (LSB)
1.260
VCC = 3V
0.5
–0.5
INL (LSB)
Reference Output Voltage
vs Temperature
Differential Nonlinearity (DNL)
0.5
–1.0
TA = 25°C, unless otherwise noted.
Settling to ±1LSB
9th CLOCK OF
3rd DATA BYTE
3/4 SCALE TO 1/4 SCALE STEP
VCC = 3V, VFS = 2.5V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
VOUT
1LSB/DIV
4.1µs
3.6µs
VOUT
1LSB/DIV
1/4 SCALE TO 3/4 SCALE STEP
VCC = 3V, VFS = 2.5V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
2µs/DIV
12
9th CLOCK OF
3rd DATA BYTE
SCL
2V/DIV
2631 G07
2µs/DIV
2631 G08
2631fd
For more information www.linear.com/LTC2631
LTC2631
Typical Performance Characteristics
LTC2631-H12 (Internal Reference, VFS = 4.096V)
Integral Nonlinearity (INL)
1.0
1.0
VCC = 5V
–0.5
0
–0.5
0
1024
2048
3072
–1.0
4095
0
1024
2048
1.0
4.115
VCC = 5V
INL (NEG)
FS OUTPUT VOLTAGE (V)
DNL (LSB)
0
DNL (POS)
0
DNL (NEG)
–0.5
–0.5
25 50 75 100 125 150
TEMPERATURE (°C)
25 50 75 100 125 150
TEMPERATURE (°C)
Full-Scale Output Voltage
vs Temperature
0.5
INL (POS)
–1.0
–50 –25
0
VCC = 5V
4.105
4.095
4.085
4.075
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
25 50 75 100 125 150
TEMPERATURE (°C)
2631 G13
2631 G12
Settling to ±1LSB
SCL
5V/DIV
0
2631 G11
DNL vs Temperature
VCC = 5V
0
2.028
–50 –25
4095
2631 G10
INL vs Temperature
INL (LSB)
3072
CODE
2631 G09
–1.0
–50 –25
2.048
2.038
CODE
0.5
VCC = 5V
2.058
VREF (V)
DNL (LSB)
INL (LSB)
2.068
VCC = 5V
0.5
0
1.0
Reference Output Voltage
vs Temperature
Differential Nonlinearity (DNL)
0.5
–1.0
TA = 25°C, unless otherwise noted.
2631 G14
Settling to ±1LSB
9th CLOCK OF
3rd DATA BYTE
3/4 SCALE TO 1/4 SCALE STEP
VCC = 5V, VFS = 4.095V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
VOUT
1LSB/DIV
4.6µs
VOUT
1LSB/DIV
3.9µs
1/4 SCALE TO 3/4 SCALE STEP
VCC = 5V, VFS = 4.095V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
2µs/DIV
SCL
5V/DIV
9th CLOCK OF
3rd DATA BYTE
2631 G15
2µs/DIV
2631 G16
2631fd
For more information www.linear.com/LTC2631
13
LTC2631
Typical Performance Characteristics
LTC2631-10
Integral Nonlinearity (INL)
1.0
Differential Nonlinearity (DNL)
1.0
VCC = 5V
VFS = 4.096V
INTERNAL REF.
VCC = 5V
VFS = 4.096V
INTERNAL REF.
0.5
DNL (LSB)
INL (LSB)
0.5
0
–0.5
–1.0
TA = 25°C, unless otherwise noted.
0
–0.5
0
512
256
768
–1.0
1023
0
512
256
CODE
1023
2631 G17
LTC2631-8
2631 G18
Integral Nonlinearity (INL)
1.0
Differential Nonlinearity (DNL)
0.50
VCC = 3V
VFS = 2.5V
INTERNAL REF.
0
–0.5
–1.0
VCC = 3V
VFS = 2.5V
INTERNAL REF.
0.25
DNL (LSB)
INL (LSB)
0.5
0
–0.25
0
128
64
192
255
–0.50
0
128
64
CODE
192
255
CODE
2631 G19
LTC2631
2631 G20
Load Regulation
10
8
6
Current Limiting
0.20
VCC = 5V (LTC2631-H)
VCC = 5V (LTC2631-L)
VCC = 3V (LTC2631-L)
0.15
∆VOUT (V)
ΔVOUT (mV)
2
0
–2
0.05
0
–0.05
–4
–0.10
–6
–0.15
INTERNAL REF.
CODE = MIDSCALE
–8
–10
–30
VCC = 5V (LTC2631-H)
VCC = 5V (LTC2631-L)
VCC = 3V (LTC2631-L)
0.10
4
–20
–10
0
10
IOUT (mA)
20
30
–0.20
–30
INTERNAL REF.
CODE = MIDSCALE
–20
2631 G21
14
768
CODE
–10
0
10
IOUT (mA)
20
30
2631 G22
2631fd
For more information www.linear.com/LTC2631
LTC2631
Typical Performance Characteristics
TA = 25°C, unless otherwise noted.
LTC2631
Offset Error vs Temperature
Gain Error vs VCC
3
0
–1
–2
0.2
0.1
0.0
–0.1
–0.2
–0.3
–3
–50 –25
0
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
2.5
25 50 75 100 125 150
TEMPERATURE (°C)
EXTERNAL REF.
VREF = 2.5V
0.3
GAIN ERROR (%FSR)
GAIN ERROR (%FSR)
1
0.4
EXTERNAL REF.
VREF = 2.5V
0.3
2
OFFSET ERROR (mV)
Gain Error vs Temperature
0.4
3
3.5
4
4.5
5
5.5
–0.4
–50 –25
0
VCC (V)
2631 G23
25 50 75 100 125 150
TEMPERATURE (°C)
2631 G24
Large-Signal Response
2631 G25
Mid-Scale-Glitch Impulse
Power-On Reset Glitch
LTC2631-L
9th CLOCK OF
3rd DATA BYTE
VCC
2V/DIV
SCL
5V/DIV
VOUT
0.5V/DIV
LTC2631-H12, VCC = 5V:
3.0nV-s TYP
VOUT
5mV/DIV
ZERO-SCALE
LTC2631-L12, VCC = 3V:
2.1nV-s TYP
VFS = VCC = 5V
1/4 SCALE TO 3/4 SCALE
VOUT
2mV/DIV
2µs/DIV
2µs/DIV
200µs/DIV
2631 G27
2631 G26
Headroom at Rails
vs Output Current
2631 G28
Exiting Power-Down to Mid-Scale
5.0
5V SOURCING
4.5
SCL
5V/DIV
4.0
VOUT (V)
3.5
9TH CLOCK OF
3RD DATA BYTE
3V (LTC2631-L) SOURCING
3.0
2.5
VOUT
0.5V/DIV
2.0
1.5
5V SINKING
1.0
0.5
0
3V (LTC2631-L) SINKING
0
1
2
3
4 5 6
IOUT (mA)
LTC2631-H
7
8
9
10
4µs/DIV
2631 G30
2631 G29
2631fd
For more information www.linear.com/LTC2631
15
LTC2631
Typical Performance Characteristics
LTC2631
Supply Current
vs REF_SEL Voltage
Supply Current vs Logic Voltage
1.2
0.5
SWEEP SCL AND SDA
BETWEEN 0V AND VCC
1.0
TA = 25°C, unless otherwise noted.
SWEEP REF_SEL
BETWEEN 0V AND VCC
0.4
ICC (mA)
ICC (mA)
0.8
VCC = 5V
0.6
0.3
VCC = 5V
0.2
VCC = 3V
(LTC2631-L)
0.4
VCC = 3V
(LTC2631-L)
0.2
0.0
0
2
3
LOGIC VOLTAGE (V)
1
4
0.1
5
0
1
2
4
3
REF_SEL VOLTAGE (V)
5
2631 G32
2631 G31
Multiplying Bandwidth
0
–2
–4
dB
–6
–8
–10
–12
–14 VCC = 5V
VREF(DC) = 2V
–16 VREF(AC) = 0.2VP-P
CODE = FULL SCALE
–18
1k
10k
100k
FREQUENCY (Hz)
1000k
2631 G33
0.1Hz to 10Hz Voltage Noise
Noise Voltage vs Frequency
NOISE VOLTAGE (nV/√Hz)
500
INTERNAL REF.
CODE = MIDSCALE
LTC2631-L, VCC = 4V
INTERNAL REF.
CODE = MIDSCALE
400
300
LTC2631-H
(VCC = 5V)
200
LTC2631-L
(VCC = 4V)
100
0
100
10µV/DIV
1k
10k
100k
1M
1s/DIV
2631 G35
FREQUENCY (Hz)
2631 G34
16
2631fd
For more information www.linear.com/LTC2631
LTC2631
Pin Functions
CA0 (Pin 1): Chip Address Bit 0. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the
part (see Tables 1 and 2).
SCL (Pin 2): Serial Clock Input Pin. Data is shifted into the
SDA pin at the rising edges of the clock. This high impedance pin requires a pull-up resistor or current source to
VCC.
SDA (Pin 3): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in. Open-drain
N-channel output during acknowledgment. SDA requires
a pull-up resistor or current source to VCC.
GND (Pin 4): Ground.
VCC (Pin 5): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V
(LTC2631-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2631-H). Bypass
to GND with a 0.1µF capacitor.
REF (Pin 6): Reference Voltage Input or Output. When
External Reference mode is selected, REF is an input (0V
≤ VREF ≤ VCC) where the voltage supplied sets the fullscale voltage. When Internal Reference is selected, the
10ppm/°C 1.25V (LTC2631-L) or 2.048V (LTC2631-H)
internal reference is available at the pin. This output may
be bypassed to GND with up to 10µF (0.33µF is recommended), and must be buffered when driving external DC
load current.
VOUT (Pin 7): DAC Analog Voltage Output.
CA1 (Pin 8, LTC2631-Z): Chip Address Bit 1. Tie this
pin to VCC, GND or leave it floating to select an I2C slave
address for the part (see Table 1).
REF_SEL (Pin 8, LTC2631-M): Selects default Reference
at power up. Tie to VCC to select the Internal Reference,
or GND to select an External Reference. After power-up,
the logic state at this pin is ignored and the reference may
be changed only by software command.
2631fd
For more information www.linear.com/LTC2631
17
LTC2631
Block Diagrams
LTC2631-Z
CA1
I2C
ADDRESS
DECODE
CA0
VCC
REF
INTERNAL
REFERENCE
CONTROL
DECODE LOGIC
SCL
I2C
INTERFACE
SDA
SWITCH
RESISTOR
DIVIDER
DACREF
INPUT
REGISTER
DAC
REGISTER
VOUT
DAC
GND
LTC2631-M
I2C
ADDRESS
DECODE
CA0
VCC
REF
INTERNAL
REFERENCE
CONTROL
DECODE LOGIC
SCL
I2C
INTERFACE
SDA
SWITCH
REF_SEL
RESISTOR
DIVIDER
DACREF
INPUT
REGISTER
DAC
REGISTER
VOUT
DAC
GND
2631 BD
Test Circuits
Test Circuits for I2C Digital I/O (See Electrical Characteristics)
Test Circuit 1
Test Circuit 2
VCC
100Ω
RINH/RINL/RINF
CAn
CAn
VIH(CAn)/VIL(CAn)
GND
2631 TC
18
2631fd
For more information www.linear.com/LTC2631
A5
2
A6
1
SDA
SCL
START
3
A4
4
A3
5
A2
SLAVE ADDRESS
6
A1
tf
7
A0
SCL
SDA
tHD(STA)
tr
tHD(DAT)
tHIGH
tSU(DAT)
tf
tSU(STA)
8
W
9
ACK
1
C3
2
C2
3
C1
For more information www.linear.com/LTC2631
5
6
X
7
X
8
X
9
ACK
1
2
3
4
5
2ND DATA BYTE
6
tSU(STO)
tSP
Figure 2. Typical LTC2631 Write Transaction
4
X
1ST DATA BYTE
C0
S
tHD(STA)
Figure 1. Serial Interface Timing
ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS
S
tLOW
7
tr
P
8
9
ACK
tBUF
1
S
2
2631 F01
3
4
5
X
3RD DATA BYTE
6
X
7
X
8
X
9
ACK
2631 F02
LTC2631
Timing Diagrams
2631fd
19
LTC2631
Operation
The LTC2631 is a family of single voltage-output DACs
in 8-lead ThinSOT packages. Each DAC can operate railto-rail using an external reference, or with its full-scale
voltage set by an integrated reference. Twelve combinations of accuracy (12-, 10-, and 8-bit), power-on reset
value (zero or mid-scale), and full-scale voltage (2.5V or
4.096V) are available. The LTC2631 is controlled using a
2-wire I2C interface.
Power-On Reset
The LTC2631-HZ/LTC2631-LZ clear the output to zeroscale when power is first applied, making system initialization consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2631 contains circuitry to reduce the power-on glitch: the analog
output typically rises less than 5mV above zero-scale during power on if the power supply is ramped to 5V in 1ms
or more. In general, the glitch amplitude decreases as
the power supply ramp time is increased. See “Power-On
Reset Glitch” in the Typical Performance Characteristics
section.
The LTC2631-HM/LTC2631-LM provide an alternative
reset, setting the output to mid-scale when power is first
applied.
Default reference mode selection is described in the Reference Modes section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the
range – 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe
these limits during power supply turn-on and turn-off
sequences, when the voltage at VCC (Pin 5) is in transition.
Transfer Function
The digital-to-analog transfer function is
⎛k ⎞
VOUT(IDEAL) = ⎜ N ⎟ VREF
⎝2 ⎠
20
where k is the decimal equivalent of the binary DAC
input code, N is the resolution, and VREF is either 2.5V
(LTC2631-LM/LTC2631-LZ) or 4.096V (LTC2631-HM/
LTC2631-HZ) when in Internal Reference mode, and the
voltage at REF (Pin 6) when in External Reference mode.
I2C Serial Interface
The LTC2631 communicates with a host using the standard 2-wire I2C interface. The Timing Diagrams (Figures 1
and 2) show the timing relationship of the signals on the
bus. The two bus lines, SDA and SCL, must be high when
the bus is not in use. External pull-up resistors or current
sources are required on these lines. The value of these
pull-up resistors is dependent on the power supply and
can be obtained from the I2C specifications. For an I2C
bus operating in the fast mode, an active pull-up will be
necessary if the bus capacitance is greater than 200pF.
The LTC2631 is a receive-only (slave) device. The master
can write to the LTC2631. The LTC2631 does not respond
to a read from the master.
START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA
from high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I2C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the
latest byte of information was properly received. The
Acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the
Acknowledge clock pulse. The slave-receiver must pull
down the SDA bus line during the Acknowledge clock
2631fd
For more information www.linear.com/LTC2631
LTC2631
operation
pulse so that it remains a stable LOW during the HIGH
period of this clock pulse. The LTC2631 responds to a
write by a master in this manner but does not acknowledge a read operation; in that case, SDA is retained HIGH
during the period of the Acknowledge clock pulse.
a 7-bit hardwired address not selectable by CA0/CA1. If
another address is required, please consult the factory.
Chip Address
Write Word Protocol
The state of pins CA0 and CA1 (LTC2631-HZ/LTC2631-LZ)
determines the slave address of the part. These pins can
each be set to any one of three states: VCC, GND or float.
This results in nine (LTC2631-HZ/LTC2631-LZ) or three
(LTC2631-HM/LTC2631-LM) selectable addresses for the
part. The slave address assignments are shown in Tables
1 and 2.
Table 1. Slave Address Map (LTC2631-Z)
CA1
CA0
A6
A5
A4
A3
A2
A1
A0
GND
GND
0
0
1
0
0
0
0
GND
FLOAT
0
0
1
0
0
0
1
GND
VCC
0
0
1
0
0
1
0
FLOAT
GND
0
0
1
0
0
1
1
FLOAT
FLOAT
0
1
0
0
0
0
0
FLOAT
VCC
0
1
0
0
0
0
1
VCC
GND
0
1
0
0
0
1
0
VCC
FLOAT
0
1
0
0
0
1
1
VCC
VCC
0
1
1
0
0
0
0
1
1
1
0
0
1
1
GLOBAL ADDRESS
Table 2. Slave Address Map (LTC2631-M)
CA0
A6
A5
A4
A3
A2
A1
A0
GND
0
0
1
0
0
0
0
FLOAT
0
0
1
0
0
0
1
VCC
0
0
1
0
0
1
0
GLOBAL ADDRESS
1
1
1
0
0
1
1
In addition to the address selected by the address pins,
the part also responds to a global address. This address
allows a common write to all LTC2631 parts to be accomplished using one 3-byte write transaction on the I2C bus.
The global address, listed at the end of Tables 1 and 2, is
The maximum capacitive load allowed on the CA0/CA1
address pins is 10pF, as these pins are driven during address detection to determine if they are floating.
The master initiates communication with the LTC2631
with a START condition and a 7-bit slave address followed
by the Write bit (W) = 0. The LTC2631 acknowledges by
pulling the SDA pin low at the ninth clock if the 7-bit slave
address matches the address of the part (set by CA0/CA1)
or the global address. The master then transmits 3-bytes
of data. The LTC2631 acknowledges each byte of data by
pulling the SDA line low at the ninth clock of each data
byte transmission. After receiving three complete bytes
of data, the LTC2631 executes the command specified in
the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2631 does not acknowledge
the extra bytes of data (SDA is high during the 9th clock).
The format of the three data bytes is shown in Figure 3. The
first byte of the input word consists of the 4-bit command,
followed by four don’t-cares bits. The next two bytes contain the 16-bit data word, which consists of the 12-, 10- or
8-bit input code, MSB to LSB, followed by 4, 6 or 8 don’tcares bits (LTC2631-12, LTC2631-10 and LTC2631-8
respectively). A typical LTC2631 write transaction is
shown in Figure 4.
The command bit assignments (C3-C0) are shown in
Table 3. The first four commands in the table consist of
write and update operations. A write operation loads a
16-bit data word from the 32-bit shift register into the
input register. In an update operation, the data word is
copied from the input register to the DAC register and
converted to an analog voltage at the DAC output. The
update operation also powers up the DAC if it had been in
power-down mode. The data path and registers are shown
in the Block Diagram.
2631fd
For more information www.linear.com/LTC2631
21
LTC2631
Operation
Write Word Protocol for LTC2631
S
SLAVE ADDRESS
W
A
1ST DATA BYTE
A
2ND DATA BYTE
C2
C1 C0
X
X
3RD DATA BYTE
A
P
INPUT WORD
Input Word (LTC2631-12)
C3
A
X
X
D11 D10 D9
1ST DATA BYTE
D8
D7
D6
D5
D4 D3 D2 D1
2ND DATA BYTE
D0
X
X
X
X
X
X
X
X
3RD DATA BYTE
Input Word (LTC2631-10)
C3
C2
C1 C0
X
X
X
X
D9
D8
1ST DATA BYTE
D7
D6
D5
D4
D3
D2 D1 D0
X
2ND DATA BYTE
X
X
X
3RD DATA BYTE
Input Word (LTC2631-8)
C3
C2
C1 C0
X
X
X
X
D7
D6
1ST DATA BYTE
D5
D4
D3
D2
D1
D0
X
X
X
2ND DATA BYTE
X
X
X
3RD DATA BYTE
2631 F03
Figure 3. Command and Data Input Format
to the REF pin will improve noise performance; 0.33µF
is recommended, and up to 10µF can be driven without
oscillation. This output must be buffered when driving
external DC load current.
Table 3. Command Codes
COMMAND*
C3
C2
C1
C0
0
0
0
0
Write to Input Register
0
0
0
1
Update (Power Up) DAC Register
0
0
1
1
Write to and Update (Power Up) DAC Register
0
1
0
0
Power Down
0
1
1
0
Select Internal Reference
0
1
1
1
Select External Reference
*Command codes not shown are reserved and should not be used.
Reference Modes
For applications where an accurate external reference is
not available, the LTC2631 has a user-selectable, integrated reference. The LTC2631-LM/LTC2631-LZ provide
a full-scale output of 2.5V. The LTC2631-HM/LTC2631-HZ
provide a full-scale output of 4.096V. The internal reference can be useful in applications where the supply
voltage is poorly regulated. Internal Reference mode can
be selected by using command 0110, and is the poweron default for LTC2631-HZ/LTC2631-LZ, as well as for
LTC2631-HM/LTC2631-LM when REF_SEL is tied high.
The 10ppm/°C, 1.25V (LTC2631-LM/LTC2631-LZ) or
2.048V (LTC2631-HM/LTC2631-HZ) internal reference
is available at the REF pin. Adding bypass capacitance
22
Alternatively, the DAC can operate in External Reference
mode using command 0111. In this mode, an input voltage
supplied externally to the REF pin provides the reference
(0V ≤ VREF ≤ VCC) and the supply current is reduced.
External Reference mode is the power-on default for
LTC2631-HM/LTC2631-LM when REF_SEL is tied low.
The reference mode of LTC2631-HZ/LTC2631-LZ can be
changed only by software command. The same is true for
LTC2631-HM/LTC2631-LM after power-on, after which
the logic state on REF_SEL is ignored.
Power-Down Mode
For power-constrained applications, the LTC2631’s
power-down mode can be used to reduce the supply
current whenever the DAC output is not needed. When in
power down, the buffer amplifier, bias circuit, and reference circuit are disabled and draw essentially zero current.
The DAC output is put into a high-impedance state, and
the output pin is passively pulled to ground through a
200kΩ resistor. Input and DAC register contents are not
disturbed during power down.
2631fd
For more information www.linear.com/LTC2631
LTC2631
operation
The DAC can be put into power-down mode by using
command 0100. The supply current is reduced to 1.8µA
maximum (C and I grades) and the REF pin becomes high
impedance (typically > 1GΩ).
Normal operation resumes after executing any command
that includes a DAC update, as shown in Table 3. The DAC
is powered up and its voltage output is updated. Normal
settling is delayed while the bias, reference, and amplifier circuits are re-enabled. When the REF pin output is
bypassed to GND with 1nF or less, the power-up delay
time is 20µs for settling to 12-bits. This delay increases
to 200µs for 0.33µF, and 10ms for 10µF.
Voltage Output
The LTC2631’s integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifier’s DC output
impedance is 0.1Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
50Ω • 1mA, or 50mV). See the graph “Headroom at Rails
vs. Output Current” in the Typical Performance Characteristics section.
The amplifier is stable driving capacitive loads of up to
500pF.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage-output device, the output is limited to voltages within the supply range.
Since the analog output of the DAC cannot go below ground,
it may limit the lowest codes, as shown in Figure 5b.
Similarly, limiting can occur near full-scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits
at VCC , as shown in Figure 5c. No full-scale limiting can
occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Board Layout
The PC board should have separate areas for the analog
and digital sections of the circuit. A single, solid ground
plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps
digital signals away from sensitive analog signals and
minimizes the interaction between digital ground currents
and the analog section of the ground plane. The resistance
from the LTC2631 GND pin to the ground plane should
be as low as possible. Resistance here will add directly to
the effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2631 is no more susceptible to
this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements
to shine rather than limiting attainable performance with
excessive internal resistance.
Another technique for minimizing errors is to use a separate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2631 is sinking large currents, this current flows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
2631fd
For more information www.linear.com/LTC2631
23
24
X = DON’T CARE
2
1
SCL
3
4
A3
A3
5
A2
A2
SLAVE ADDRESS
A4
A4
6
A1
A1
7
A0
A0
9
ACK
1
C3
C3
2
C2
C2
3
C1
C1
4
C0
C0
5
X
X
COMMAND
6
X
X
7
X
X
8
X
X
9
ACK
1
D11
2
D10
3
D9
4
5
D7
MS DATA
D8
6
D6
7
D5
8
D4
9
ACK
1
D3
2
D2
3
D1
Figure 4. Typical LTC2631 Input Waveform—Programming 12-Bit DAC Output for Full-Scale
8
W
4
5
X
LS DATA
D0
6
X
7
X
8
X
9
ACK
ZERO-SCALE
VOLTAGE 2631 F04
FULL-SCALE
VOLTAGE
STOP
Operation
VOUT
A5
A6
A5
SDA
START
A6
LTC2631
2631fd
For more information www.linear.com/LTC2631
LTC2631
operation
VREF = VCC
POSITIVE
FSE
VREF = VCC
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
(c)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
0V
0
2,048
INPUT CODE
(a)
2631 F05
4,095
INPUT CODE
(b)
Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12-Bits)
(a) Overall Transfer Function
(b) Effect of Negative Offset for Codes Near Zero
(c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
2631fd
For more information www.linear.com/LTC2631
25
LTC2631
Package Description
Please refer to http://www.linear.com/product/LTC2631#packaging for the most recent package drawings.
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637 Rev A)
0.40
MAX
2.90 BSC
(NOTE 4)
0.65
REF
1.22 REF
1.4 MIN
3.85 MAX 2.62 REF
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
1.95 BSC
TS8 TSOT-23 0710 REV A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
26
2631fd
For more information www.linear.com/LTC2631
LTC2631
Revision History
(Revision history begins at Rev C)
REV
DATE
DESCRIPTION
C
11/13
Updated TS8 package drawing to Rev A
PAGE NUMBER
26
D
06/17
Removed Note 3
11
2631fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC2631
27
LTC2631
Typical Application
Programmable ±5V Output
5V
5V
4
0.1µF
3
1.7k
1.7k
I2C BUS
CA0
5 6
VCC REF
8
REF_SEL
3
SDA
LTC2631A VOUT 7
2
SCL -LM12
1
CA0
0.1µF
5
–
LTC2054
+
2
10V
1
8
M9
9 M3
10
M1
1
P1
2
P3
3
P9
GND
4
0.1µF
7
VCC
LT1991
VEE
4
REF
OUT
6
VOUT = ±5V
5
0.1µF
–10V
2631 TA03
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PART NUMBER
DESCRIPTION
COMMENTS
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28
180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
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2631fd
LT 0617 REV D • PRINTED IN USA
For more information www.linear.com/LTC2631
www.linear.com/LTC2631
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