LTC2632CTS8-LI12#TRPBF

LTC2632 Dual 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference FEATURES DESCRIPTION Integrated Precision Reference 2.5V Full-Scale 10ppm/°C (LTC2632-L) 4.096V Full-Scale 10ppm/°C (LTC2632-H) n Maximum INL Error: ±1.5LSB (LTC2632A-12) n Low Noise: 0.75mV P-P 0.1Hz to 200kHz n Guaranteed Monotonic –40°C to 125°C Automotive Temperature Range n Selectable Internal or External Reference n 2.7V to 5.5V Supply Range (LTC2632-L) n Low Power Operation 0.4mA at 3V n Power-On-Reset to Zero-Scale/Mid-Scale n Double-Buffered Data Latches n 8-Lead ThinSOT™ Package The LTC®2632 is a family of dual 12-, 10-, and 8-bit voltage-output DACs with an integrated, high-accuracy, low-drift reference in an 8-lead TSOT-23 package. It has rail-to-rail output buffers and is guaranteed monotonic. n APPLICATIONS Mobile Communications Process Control and Industrial Automation n Automatic Test Equipment n Portable Equipment n Automotive n n The LTC2632-L has a full-scale output of 2.5V, and operates from a single 2.7V to 5.5V supply. The LTC2632-H has a full-scale output of 4.096V, and operates from a 4.5V to 5.5V supply. Each DAC can also operate with an external reference, which sets the full-scale output to the external reference voltage. These DACs communicate via a simple SPI/MICROWIRE compatible 3-wire serial interface which operates at clock rates up to 50MHz. The LTC2632 incorporates a power-on reset circuit. Options are available for reset to zero-scale or reset to mid-scale in internal reference mode, or reset to mid-scale in external reference mode after power-up. All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 5396245, 5859606, 6891433, and 6937178. BLOCK DIAGRAM INTERNAL REFERENCE GND SWITCH Integral Nonlinearity (LTC2632A-LZ12) 2 VREF CS/LD CONTROL LOGIC DAC B SDI DECODE SCK 32-BIT SHIFT REGISTER POWER-ON RESET VCC = 3V INTERNAL REF. 1 VOUTB INL (LSB) REGISTER REGISTER REGISTER DAC A REGISTER VCC VOUTA REF 0 –1 –2 0 1024 2048 CODE 3072 4095 2632 TA01 2632 BD Rev. C Document Feedback For more information www.analog.com 1 LTC2632 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) TOP VIEW Supply Voltage (VCC).................................... –0.3V to 6V SCK, SDI....................................................... –0.3V to 6V CS/LD (Note 10)................–0.3V to Min (VCC + 0.3V, 6V) VOUTA, VOUTB....................–0.3V to Min (VCC + 0.3V, 6V) REF...................................–0.3V to Min (VCC + 0.3V, 6V) Operating Temperature Range LTC2632C................................................. 0°C to 70°C LTC2632H........................................... –40°C to 125°C Maximum Junction Temperature........................... 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec).................... 300°C SCK CS/LD REF GND 1 2 3 4 8 7 6 5 SDI VCC VOUTB VOUTA TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150°C (NOTE 6), θJA = 195°C/W ORDER INFORMATION LTC2632 A C TS8 –L Z 12 #TRM PBF LEAD FREE DESIGNATOR TAPE AND REEL TR = 2,500-Piece Tape and Reel TRM = 500-Piece Tape and Reel RESOLUTION 12 = 12-Bit 10 = 10-Bit 8 = 8-Bit POWER-ON RESET I = Reset to Mid-Scale in Internal Reference Mode X = Reset to Mid-Scale in External Reference Mode (2632-L Only) Z = Reset to Zero-Scale in Internal Reference Mode FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE TS8 = 8-Lead Plastic TSOT-23 TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) H = Automotive Temperature Range (–40°C to 125°C) ELECTRICAL GRADE (OPTIONAL) A = ±1.5LSB Maximum INL (12-Bit) PRODUCT PART NUMBER Contact the factory for parts specified with wider operating temperature ranges. Contact the factory for information on lead based finish parts. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev. C 2 For more information www.analog.com LTC2632 PRODUCT SELECTION GUIDE PART MARKING* VFS WITH INTERNAL REFERENCE LTC2632A-LI12 LTFSJ 2.5V • (4095/4096) Mid-Scale LTC2632A-LX12 LTFSH 2.5V • (4095/4096) Mid-Scale LTC2632A-LZ12 LTFSG 2.5V • (4095/4096) Zero LTC2632A-HI12 LTFSM 4.096V • (4095/4096) LTC2632A-HZ12 LTFSK 4.096V • (4095/4096) LTC2632-LI12 LTFSJ LTC2632-LI10 LTFSQ LTC2632-LI8 LTFSW 2.5V • (255/256) Mid-Scale Internal 8-Bit 2.7V to 5.5V ±0.5LSB LTC2632-LX12 LTFSH 2.5V • (4095/4096) Mid-Scale External 12-Bit 2.7V to 5.5V ±2.5LSB LTC2632-LX10 LTFSP 2.5V • (1023/1024) Mid-Scale External 10-Bit 2.7V to 5.5V ±1LSB LTC2632-LX8 LTFSV 2.5V • (255/256) Mid-Scale External 8-Bit 2.7V to 5.5V ±0.5LSB LTC2632-LZ12 LTFSG 2.5V • (4095/4096) Zero Internal 12-Bit 2.7V to 5.5V ±2.5LSB LTC2632-LZ10 LTFSN 2.5V • (1023/1024) Zero Internal 10-Bit 2.7V to 5.5V ±1LSB PART NUMBER POWER-ON POWER-ON RESET TO CODE REFERENCE MODE RESOLUTION VCC Internal 12-Bit 2.7V to 5.5V ±1.5LSB External 12-Bit 2.7V to 5.5V ±1.5LSB Internal 12-Bit 2.7V to 5.5V ±1.5LSB Mid-Scale Internal 12-Bit 4.5V to 5.5V ±1.5LSB Zero Internal 12-Bit 4.5V to 5.5V ±1.5LSB 2.5V • (4095/4096) Mid-Scale Internal 12-Bit 2.7V to 5.5V ±2.5LSB 2.5V • (1023/1024) Mid-Scale Internal 10-Bit 2.7V to 5.5V ±1LSB MAXIMUM INL LTC2632-LZ8 LTFST 2.5V • (255/256) Zero Internal 8-Bit 2.7V to 5.5V ±0.5LSB LTC2632-HI12 LTFSM 4.096V • (4095/4096) Mid-Scale Internal 12-Bit 4.5V to 5.5V ±2.5LSB LTC2632-HI10 LTFSS 4.096V • (1023/1024) Mid-Scale Internal 10-Bit 4.5V to 5.5V ±1LSB LTC2632-HI8 LTFSY 4.096V • (255/256) Mid-Scale Internal 8-Bit 4.5V to 5.5V ±0.5LSB LTC2632-HZ12 LTFSK 4.096V • (4095/4096) Zero Internal 12-Bit 4.5V to 5.5V ±2.5LSB LTC2632-HZ10 LTFSR 4.096V • (1023/1024) Zero Internal 10-Bit 4.5V to 5.5V ±1LSB LTC2632-HZ8 LTFSX 4.096V • (255/256) Zero Internal 8-Bit 4.5V to 5.5V ±0.5LSB * The temperature grade is identified by a label on the shipping container. Above options are available in an 8-lead TSOT package (LTC2632xTS8). Rev. C For more information www.analog.com 3 LTC2632 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2632-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8, LTC2632A-LI12/-LX12/-LZ12 (VFS = 2.5V) SYMBOL PARAMETER MIN CONDITIONS LTC2632-8 LTC2632-10 LTC2632-12 LTC2632A-12 TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS DC Performance Resolution l 8 10 12 12 Bits 8 10 12 12 Bits Monotonicity VCC = 3V, Internal Ref. (Note 3) l DNL Differential Nonlinearity VCC = 3V, Internal Ref. (Note 3) l INL Integral Nonlinearity VCC = 3V, Internal Ref. (Note 3) l ±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 ZSE Zero-Scale Error VCC = 3V, Internal Ref., Code = 0 l 0.5 5 0.5 5 0.5 VOS Offset Error VCC = 3V, Internal Ref. (Note 4) l ±0.5 ±5 ±0.5 ±5 ±0.5 VOSTC VOS Temperature Coefficient VCC = 3V, Internal Ref. GE Gain Error VCC = 3V, Internal Ref. GETC Gain Temperature Coefficient VCC = 3V, Internal Ref. (Note 9) C-Grade H-Grade Load Regulation Internal Ref., Mid-Scale, VCC = 3V±10%, –5mA ≤ IOUT ≤ 5mA VCC = 5V±10%, –10mA ≤ IOUT ≤ 10mA ROUT DC Output Impedance Internal Ref., Mid-Scale, VCC = 3V±10%, –5mA ≤ IOUT ≤ 5mA VCC = 5V±10%, –10mA ≤ IOUT ≤ 10mA ±0.5 ±10 ±1 ±10 0.2 l ±0.5 0.8 10 10 0.2 ±1 LSB ±0.5 ±1.5 LSB 5 0.5 5 mV ±5 ±0.5 ±5 mV ±10 0.8 0.2 10 10 ±10 0.8 µV/°C 0.2 10 10 0.8 10 10 %FSR ppm/°C ppm/°C l 0.009 0.016 0.035 0.064 0.14 0.256 0.14 0.256 LSB/mA l 0.009 0.016 0.035 0.064 0.14 0.256 0.14 0.256 LSB/mA l 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 Ω l 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 Ω SYMBOL PARAMETER CONDITIONS VOUT DAC Output Span External Reference Internal Reference MIN PSR Power Supply Rejection VCC = 3V±10% or 5V±10% ISC Short-Circuit Output Current (Note 5) Sinking Sourcing VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND l l TYP MAX UNITS 0 to VREF 0 to 2.5 V V –80 dB 27 –28 48 –48 mA mA 5.5 V Power Supply VCC Positive Supply Voltage For Specified Performance l 2.7 ICC Supply Current (Note 6) VCC = 3V, VREF = 2.5V, External Reference VCC = 3V, Internal Reference VCC = 5V VREF = 2.5V, External Reference VCC = 5V, Internal Reference l l l l 0.3 0.4 0.3 0.4 0.5 0.6 0.5 0.6 mA mA mA mA ISD Supply Current in Power-Down Mode (Note 6) VCC = 5V l 0.5 2 µA Rev. C 4 For more information www.analog.com LTC2632 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2632-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8, LTC2632A-LI12/-LX12/-LZ12 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC V 200 kΩ 0.005 5.0 µA 1.25 1.26 Reference Input Input Voltage Range l 1 Resistance l 120 Capacitance IREF Reference Current, Power-Down Mode 160 12 DAC Powered Down l pF Reference Output Output Voltage l 1.24 V Reference Temperature Coefficient ±10 ppm/°C Output Impedance 0.5 kΩ Capacitive Load Driving 10 µF 2.5 mA Short-Circuit Current VCC = 5.5V, REF Shorted to GND VIH Digital Input High Voltage VCC = 3.6V to 5.5V VCC = 2.7V to 3.6V l l VIL Digital Input Low Voltage VCC = 4.5V to 5.5V VCC = 2.7V to 4.5V l l 0.8 0.6 V V ILK Digital Input Leakage VIN = GND to VCC l ±1 µA CIN Digital Input Capacitance (Note 7) l 8 pF Digital I/O 2.4 2.0 V V AC Performance tS en Settling Time VCC = 3V (Note 8) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) 3.5 3.9 4.4 µs µs µs Voltage Output Slew Rate 1.0 V/µs Capacitive Load Driving 500 pF Glitch Impulse At Mid-Scale Transition 2.8 nV•s DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0 to FS 4.5 nV•s Multiplying Bandwidth External Reference 320 kHz Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 200 180 nV/√Hz nV/√Hz nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1µF 30 35 680 730 µVP-P µVP-P µVP-P µVP-P Rev. C For more information www.analog.com 5 LTC2632 TIMING CHARACTERISTICS l denotes the specifications which apply over the full operating temperature The range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified. LTC2632-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8, LTC2632A-LI12/-LX12/-LZ12 (VFS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX t1 SDI Valid to SCK Setup (Figure 1) l 4 ns t2 SDI Valid to SCK Hold (Figure 1) l 4 ns t3 SCK High Time (Figure 1) l 9 ns t4 SCK Low Time (Figure 1) l 9 ns t5 CS/LD Pulse Width (Figure 1) l 10 ns t6 LSB SCK High to CS/LD High (Figure 1) l 7 ns t7 CS/LD Low to SCK High (Figure 1) l 7 ns t10 CS/LD High to SCK Positive Edge (Figure 1) l 7 ns SCK Frequency 50% Duty Cycle l 50 UNITS MHz Rev. C 6 For more information www.analog.com LTC2632 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2632-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8, LTC2632A-HI12/-HZ12 (VFS = 4.096V) SYMBOL PARAMETER LTC2632-8 LTC2632-10 LTC2632-12 LTC2632A-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX CONDITIONS UNITS DC Performance Resolution l 8 8 10 Monotonicity VCC = 5V, Internal Ref. (Note 3) l DNL Differential Nonlinearity VCC = 5V, Internal Ref. (Note 3) l ±0.5 INL Integral Nonlinearity VCC = 5V, Internal Ref. (Note 3) l ±0.05 ±0.5 ZSE Zero-Scale Error VCC = 5V, Internal Ref., Code =0 l 0.5 VOS Offset Error VCC = 5V, Internal Ref. (Note 4) l ±0.5 VOSTC VOS Temperature Coefficient VCC = 5V, Internal Ref. 12 10 12 12 12 ±0.5 Bits ±1 ±1 ±0.2 ±1 ±1 ±2.5 5 0.5 5 0.5 ±5 ±0.5 ±5 ±0.5 ±10 Bits ±10 LSB ±0.5 ±1.5 LSB 5 0.5 5 mV ±5 ±0.5 ±5 ±10 ±10 mV µV/°C GE Gain Error VCC = 5V, Internal Ref. GETC Gain Temperature Coefficient VCC = 5V, Internal Ref. (Note 9) C-Grade H-Grade Load Regulation l VCC = 5V±10%, Internal Ref. Mid-Scale, –10mA ≤ IOUT ≤ 10mA 0.006 0.01 0.022 0.04 0.09 0.16 0.09 0.16 LSB/ mA DC Output Impedance l VCC = 5V±10%, Internal Ref. Mid-Scale, –10mA ≤ IOUT ≤ 10mA 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 Ω ROUT l 0.2 0.8 0.2 10 10 0.8 0.2 10 10 0.8 0.2 10 10 SYMBOL PARAMETER CONDITIONS MIN VOUT DAC Output Span External Reference Internal Reference PSR Power Supply Rejection VCC = 5V±10% ISC Short-Circuit Output Current (Note 5) Sinking Sourcing VFS = VCC = 5.5V Zero-Scale; VOUT Shorted to VCC Full-Scale; VOUT Shorted to GND l l 0.8 10 10 TYP %FSR ppm/°C ppm/°C MAX UNITS 0 to VREF 0 to 4.096 V V –80 dB 27 –28 48 –48 mA mA Power Supply VCC Positive Supply Voltage For Specified Performance l 5.5 V ICC Supply Current (Note 6) VCC = 5V, VREF = 4.096V, External Reference VCC = 5V, Internal Reference l l 4.5 0.4 0.5 0.6 0.7 mA mA ISD Supply Current in Power-Down Mode (Note 6) VCC = 5V l 0.5 2 µA Rev. C For more information www.analog.com 7 LTC2632 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2632-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8, LTC2632A-HI12/-HZ12 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC V 160 200 kΩ 0.005 5.0 µA 2.048 2.064 Reference Input Input Voltage Range l 1 Resistance l 120 Capacitance IREF Reference Current, Power-Down Mode 12 DAC Powered Down l pF Reference Output Output Voltage l 2.032 V Reference Temperature Coefficient ±10 ppm/°C Output Impedance 0.5 kΩ Capacitive Load Driving Short-Circuit Current VCC = 5.5V; REF Shorted to GND 10 µF 4 mA Digital I/O VIH Digital Input High Voltage l 2.4 V VIL Digital Input Low Voltage l 0.8 V ILK Digital Input Leakage VIN = GND to VCC l ±1 µA CIN Digital Input Capacitance (Note 7) l 8 pF AC Performance tS en Settling Time VCC = 5V (Note 8) ±0.39% (±1LSB at 8 Bits) ±0.098% (±1LSB at 10 Bits) ±0.024% (±1LSB at 12 Bits) 3.9 4.1 4.9 µs µs µs Voltage Output Slew Rate 1.0 V/µs Capacitive Load Driving 500 pF Glitch Impulse At Mid-Scale Transition 3.0 nV•s DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0 to FS 6.7 nV•s Multiplying Bandwidth External Reference 320 kHz Output Voltage Noise Density At f = 1kHz, External Reference At f = 10kHz, External Reference At f = 1kHz, Internal Reference At f = 10kHz, Internal Reference 180 160 250 230 nV/√Hz nV/√Hz nV/√Hz nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 0.1Hz to 10Hz, Internal Reference 0.1Hz to 200kHz, External Reference 0.1Hz to 200kHz, Internal Reference CREF = 0.1µF 30 40 680 750 µVP-P µVP-P µVP-P µVP-P Rev. C 8 For more information www.analog.com LTC2632 TIMING CHARACTERISTICS l denotes the specifications which apply over the full operating temperature The range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified. LTC2632-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8, LTC2632A-HI12/-HZ12 (VFS = 4.096V) SYMBOL PARAMETER CONDITIONS t1 SDI Valid to SCK Setup (Figure 1) l 4 ns t2 SDI Valid to SCK Hold (Figure 1) l 4 ns t3 SCK High Time (Figure 1) l 9 ns t4 SCK Low Time (Figure 1) l 9 ns t5 CS/LD Pulse Width (Figure 1) l 10 ns t6 LSB SCK High to CS/LD High (Figure 1) l 7 ns t7 CS/LD Low to SCK High (Figure 1) l 7 ns t10 CS/LD High to SCK Positive Edge (Figure 1) l 7 ns SCK Frequency 50% Duty Cycle l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND Note 3: Linearity and monotonicity are defined from code kL to code 2N–1, where N is the resolution and kL is given by kL = 0.016•(2N/VFS), rounded to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = 16 and linearity is defined from code 16 to code 4,095. Note 4: Inferred from measurement at code 16 (LTC2632-12), code 4 (LTC2632-10) or code 1 (LTC2632-8), and at full-scale. Note 5: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation MIN TYP MAX 50 UNITS MHz above the specified maximum operating junction temperature may impair device reliability. Note 6: Digital inputs at 0V or VCC. Note 7: Guaranteed by design and not production tested. Note 8: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND. Note 9: Temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. Note 10: CS/LD can be held at high voltage as VCC ramps upon power-up. Rev. C For more information www.analog.com 9 LTC2632 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2632-L12 (Internal Reference, VFS = 2.5V) Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 3V 0.5 DNL (LSB) INL (LSB) 0.5 0 0 –0.5 –0.5 –1.0 VCC = 3V 1024 0 2048 CODE 3072 –1.0 4095 1024 0 3072 2048 CODE 4095 2632 G02 2632 G01 INL vs Temperature 1.0 VCC = 3V INL (POS) 0 –0.5 –1.0 –50 –25 INL (NEG) 0 DNL (POS) 0 DNL (NEG) –1.0 –50 –25 2632 G03 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 25 50 75 100 125 150 TEMPERATURE (°C) 2632 G05 Settling to ±1LSB Falling VOUT 1LSB/DIV CS/LD 5V/DIV VOUT 1LSB/DIV 1.240 –50 –25 2632 G04 Settling to ±1LSB Rising 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 1.250 1.245 –0.5 25 50 75 100 125 150 TEMPERATURE (°C) VCC = 3V 1.255 0.5 DNL (LSB) INL (LSB) 0.5 1.260 VCC = 3V VREF (V) 1.0 Reference Output Voltage vs Temperature DNL vs Temperature 3/4 SCALE TO 1/4 SCALE STEP VCC = 3V, VFS = 2.5V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 4.4µs 3.3µs CS/LD 5V/DIV 2µs/DIV 2632 G06 2µs/DIV 2632 G07 Rev. C 10 For more information www.analog.com LTC2632 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2632-H12 (Internal Reference, VFS = 4.096V) Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 5V 0.5 DNL (LSB) INL (LSB) 0.5 0 0 –0.5 –0.5 –1.0 VCC = 5V 1024 0 2048 CODE 3072 –1.0 4095 1024 0 3072 2048 CODE 4095 2632 G09 2632 G08 INL vs Temperature 1.0 VCC = 5V INL (POS) 0.5 0 INL (NEG) 0 25 50 75 100 125 150 TEMPERATURE (°C) DNL (POS) 0 DNL (NEG) –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2.028 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2632 G11 Settling to ±1LSB Rising 2632 G12 Settling to ±1LSB Falling CS/LD 5V/DIV VOUT 1LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP VCC = 3V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2.048 2.038 2632 G10 VOUT 1LSB/DIV VCC = 5V 2.058 –0.5 –0.5 –1.0 –50 –25 2.068 VCC = 5V VREF (V) INL (LSB) 0.5 DNL (LSB) 1.0 Reference Output Voltage vs Temperature DNL vs Temperature 3/4 SCALE TO 1/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 4.9µs 4.1µs CS/LD 5V/DIV 2µs/DIV 2632 G13 2µs/DIV 2632 G14 Rev. C For more information www.analog.com 11 LTC2632 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2632-10 Integral Nonlinearity (INL) 1.0 Differential Nonlinearity (DNL) 1.0 VCC = 3V VFS = 2.5V INTERNAL REF 0.5 DNL (LSB) INL (LSB) 0.5 0 –0.5 –1.0 VCC = 3V VFS = 2.5V INTERNAL REF 0 –0.5 256 0 512 CODE 768 –1.0 1023 256 0 512 CODE 768 1023 2632 G15 2632 G16 LTC2632-8 Integral Nonlinearity (INL) 0.50 Differential Nonlinearity (DNL) 0.50 VCC = 3V VFS = 2.5V INTERNAL REF 0.25 DNL (LSB) INL (LSB) 0.25 0 0 –0.25 –0.25 –0.50 VCC = 3V VFS = 2.5V INTERNAL REF 64 0 128 CODE 192 –0.50 255 64 0 128 CODE 192 255 2632 G18 2632 G17 LTC2632 Load Regulation 8 6 Current Limiting 0.20 VCC = 5V (LTC2632-H) VCC = 5V (LTC2632-L) VCC = 3V (LTC2632-L) 0.15 2 ∆VOUT (V) ∆VOUT (mV) VCC = 5V (LTC2632-H) VCC = 5V (LTC2632-L) VCC = 3V (LTC2632-L) 2 0.10 4 0 –2 0.05 0 –0.05 –4 1 0 –1 –0.10 –6 INTERNAL REFERENCE CODE = MID-SCALE –8 –10 –30 Offset Error vs Temperature 3 OFFSET ERROR (mV) 10 –20 –10 0 10 IOUT (mA) 20 30 2632 G19 –2 –0.15 –0.20 –30 INTERNAL REFERENCE CODE = MID-SCALE –20 –10 0 10 IOUT (mA) 20 30 2632 G20 –3 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2632 G21 Rev. C 12 For more information www.analog.com LTC2632 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2632 Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch LTC2632-L CS/LD 5V/DIV VCC 2V/DIV VOUT 0.5V/DIV LTC2632-H12, VCC = 5V 3.0nV-s TYP VOUT 2mV/DIV LTC2632-L12, VCC = 3V 2.8nV-s TYP VFS = VCC = 5V 1/4 SCALE to 3/4 SCALE 2µs/DIV 2632 G23 2µs/DIV 2632 G22 Headroom at Rails vs Output Current 2632 G24 LTC2632-H 5V SOURCING 4.0 VCC = 5V INTERNAL REF CS/LD 5V/DIV 3.5 VOUT (V) 200µs/DIV Exiting Power-Down to Mid-Scale 5.0 4.5 ZERO-SCALE VOUT 10mV/DIV 3V (LTC2632-L) SOURCING 3.0 2.5 2.0 1.5 5V SINKING 1.0 3V (LTC2632-L) SINKING 0.5 0 0 1 2 3 4 5 6 IOUT (mA) 7 DAC B IN POWER-DOWN MODE VOUTA 0.5V/DIV 9 8 2632 G25 Power-On Reset to Mid-Scale Supply Current vs Logic Voltage 1.2 VCC 2V/DIV SWEEP SCK, SDI, CS/LD BETWEEN 0V AND VCC 1.0 ICC (mA) LTC2632-H VOUT 0.5V/DIV LTC2632-L 200µs/DIV 2632 G26 5µs/DIV 10 2632 G27 0.8 VCC = 5V 0.6 0.4 0.2 VCC = 3V (LTC2632-L) 0 1 3 2 LOGIC VOLTAGE (V) 4 5 2632 G28 Rev. C For more information www.analog.com 13 LTC2632 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. LTC2632 Multiplying Bandwidth Noise Voltage vs Frequency 500 2 0 NOISE VOLTAGE (nV/√Hz) –2 –4 dB –6 –8 –10 –12 VCC = 5V VREF(DC) = 2V VREF(AC) = 0.2VP-P CODE = FULL-SCALE –14 –16 –18 1k 10k 100k FREQUENCY (Hz) 400 VCC = 5V CODE = MID-SCALE INTERNAL REFERENCE 300 LTC2632-H 200 LTC2632-L 100 0 100 1M 1k 100k 10k FREQUENCY (Hz) 2632 G30 2632 G29 Gain Error vs Reference Input 0.8 GAIN ERROR (%FSR) 0.1Hz to 10Hz Voltage Noise VCC = 5V, VFS = 2.5V CODE = MID-SCALE INTERNAL REFERENCE VCC = 5.5V GAIN ERROR OF 2 CHANNELS 0.6 1M 0.4 0.2 10µV/DIV 0 –0.2 –0.4 –0.6 –0.8 1 1.5 2 2.5 3 3.5 4 4.5 REFERENCE VOLTAGE (V) 5 5.5 1s/DIV 2632 G32 2632 G31 DAC to DAC Crosstalk (Dynamic) Gain Error vs Temperature 1.0 GAIN ERROR (%FSR) CS/LD 5V/DIV 1 DAC SWITCH 0-FS 2V/DIV VOUT 2mV/DIV LTC2632-H12, VCC = 5V 6.7nV-s TYP 2µs/DIV 2632 G33 0.5 0 –0.5 –1.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2634 G34 Rev. C 14 For more information www.analog.com LTC2632 PIN FUNCTIONS SCK (Pin 1): Serial Interface Clock Input. CMOS and TTL compatible. GND (Pin 4): Ground. CS/LD (Pin 2): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. VCC (Pin 7): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V (LTC2632-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2632-H). Bypass to GND with a 0.1µF capacitor. REF (Pin 3): Reference Voltage Input or Output. When external reference mode is selected, REF is an input (1V ≤ VREF ≤ VCC) where the voltage supplied sets the full-scale DAC output voltage. When internal reference is selected, the 10ppm/°C 1.25V (LTC2632-L) or 2.048V (LTC2632-H) internal reference (half full-scale) is available at the pin. This output may be bypassed to GND with up to 10µF (0.1µF is recommended) and must be buffered when driving external DC load current. VOUT A, VOUT B (Pins 5, 6): DAC Analog Voltage Output. SDI (Pin 8): Serial Interface Data Input. Data on SDI is clocked into the DAC on the rising edge of SCK. The LTC2632 accepts input word lengths of either 24 or 32 bits. Rev. C For more information www.analog.com 15 LTC2632 BLOCK DIAGRAM INTERNAL REFERENCE GND SWITCH VREF CS/LD REGISTER REGISTER DAC A REGISTER REGISTER VCC VOUTA REF DAC B VOUTB SDI CONTROL LOGIC DECODE SCK POWER-ON RESET 32-BIT SHIFT REGISTER 2632 BD TIMING DIAGRAM t1 t2 SCK t3 1 2 t6 t4 3 23 24 t10 SDI t5 t7 CS/LD 2632 F01 Figure 1. Serial Interface Timing Rev. C 16 For more information www.analog.com LTC2632 OPERATION The LTC2632 is a family of dual voltage output DACs in an 8-lead TSOT package. Each DAC can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. Fifteen combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zeroscale, mid-scale in internal reference mode, or mid-scale in external reference mode), and full-scale voltage (2.5V or 4.096V) are available. The LTC2632 is controlled using a 3-wire SPI/MICROWIRE compatible interface. Power-On Reset The LTC2632-HZ/LTC2632-LZ clear the output to zeroscale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2632 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 10mV above zero-scale during power-on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See “Power-On Reset Glitch” in the Typical Performance Characteristics section. The LTC2632-HI/LTC2632-LI/LTC2632-LX provides an alternative reset, setting the output to mid-scale when power is first applied. The LTC2632-LI and LTC2632-HI power-up in internal reference mode, with the output set to a mid-scale voltage of 1.25V and 2.048V respectively. The LTC2632-LX powers up in external reference mode, with the output set to mid-scale of the external reference. Default reference mode selection is described in the Reference Modes section. Transfer Function The digital-to-analog transfer function is ⎛ k ⎞ VOUT(IDEAL) = ⎜ ⎟ • VREF ⎝ 2N ⎠ where k is the decimal equivalent of the binary DAC input code, N is the resolution, and VREF is either 2.5V (LTC2632-LI/LTC2632-LX/LTC2632-LZ) or 4.096V (LTC2632-HI/LTC2632-HZ) when in internal reference mode, and the voltage at REF when in external reference mode. Table 1. Command Codes COMMAND* C3 C2 C1 C0 0 0 0 0 Write to Input Register n 0 0 0 1 Update (Power-Up) DAC Register n 0 0 1 0 Write to Input Register n, Update (Power-Up) All 0 0 1 1 Write to and Update (Power-Up) DAC Register n 0 1 0 0 Power-Down n 0 1 0 1 Power-Down Chip (All DAC’s and Reference) 0 1 1 0 Select Internal Reference (Power-Up Reference) 0 1 1 1 Select External Reference (Power-Down Internal Reference) 1 1 1 1 No Operation *Command codes not shown are reserved and should not be used. Table 2. Address Codes ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 DAC A 0 0 0 1 DAC B 1 1 1 1 All DACs * Address codes not shown are reserved and should not be used. Power Supply Sequencing The voltage at REF (Pin 3) must be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see the Absolute Maximum Ratings section). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC is in transition. Rev. C For more information www.analog.com 17 LTC2632 OPERATION INPUT WORD (LTC2632-12) COMMAND C3 C2 C1 ADDRESS C0 A3 A2 A1 DATA (12 BITS + 4 DON’T-CARE BITS) A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 MSB D0 X X X X X X X X X X X X X X LSB INPUT WORD (LTC2632-10) COMMAND C3 C2 C1 ADDRESS C0 A3 A2 A1 DATA (10 BITS + 6 DON’T-CARE BITS) A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 MSB D0 X LSB INPUT WORD (LTC2632-8) COMMAND C3 C2 C1 ADDRESS C0 A3 A2 A1 DATA (8 BITS + 8 DON’T-CARE BITS) A0 D7 D6 D5 D4 D3 D2 D1 MSB D0 X X X LSB 2632 F02 Figure 2. Command and Data Input Format Serial Interface The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, enabling the SDI and SCK buffers and the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 12-, 10- or 8-bit input code, ordered MSB-to-LSB, followed by 4, 6 or 8 don’t-care bits (LTC2632-12, LTC2632-10 and LTC2632-8 respectively; see Figure 2). Data can only be transferred to the device when the CS/LD signal is low, beginning on the first rising edge of SCK. SCK may be high or low at the falling edge of CS/LD. The rising edge of CS/LD ends the data transfer and causes the device to execute the command specified in the 24-bit input sequence. The complete sequence is shown in Figure 3a. The command (C3-C0) and address (A3-A0) assignments are shown in Tables 1 and 2. The first four commands in Table 1 consist of write and update operation. A Write operation loads a 16-bit data word from the 24-bit shift register into the input register of the selected DAC, n. An Update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 12-, 10-, or 8-bit input code, and is converted to an analog voltage at the DAC output. Write to and Update combines the first two commands. The Update operation also powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. While the minimum input sequence is 24 bits, it may optionally be extended to 32 bits to accommodate microprocessors that have a minimum word width of 16 bits (2 bytes). To use the 32-bit width, 8 don’t-care bits are transferred to the device first, followed by the 24-bit sequence described. Figure 3b shows the 32-bit sequence. The 16-bit data word is ignored for all commands that do not include a Write operation. Rev. C 18 For more information www.analog.com LTC2632 OPERATION Reference Modes Power-Down Mode For applications where an accurate external reference is not available, nor desirable due to limited space, the LTC2632 has a user-selectable, integrated reference. The integrated reference voltage is internally amplified by 2x to provide the full-scale DAC output voltage range. The LTC2632-LI/LTC2632-LX/LTC2632-LZ provides a fullscale output of 2.5V. The LTC2632-HI/LTC2632-HZ provides a full-scale output of 4.096V. The internal reference can be useful in applications where the supply voltage is poorly regulated. Internal reference mode can be selected by using command 0110b, and is the power-on default for LTC2632-HZ/LTC2632-LZ, as well as for LTC2632-HI/ LTC2632-LI. For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than two DAC outputs are needed. When in power-down, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. The DAC outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 200k resistors. Input and DAC-register contents are not disturbed during power-down. The 10ppm/°C, 1.25V (LTC2632-LI/LTC2632-LX/ LTC2632-LZ) or 2.048V (LTC2632-HI/LTC2632-HZ) internal reference is available at the REF pin. Adding bypass capacitance to the REF pin will improve noise performance; 0.1µF is recommended, and up to 10µF can be driven without oscillation. This output must be buffered when driving an external DC load current. Alternatively, the DAC can operate in external reference mode using command 0111b. In this mode, an input voltage supplied externally to the REF pin provides the reference (1V ≤ VREF ≤ VCC) and the supply current is reduced. The external reference voltage supplied sets the full-scale DAC output voltage. External reference mode is the power-on default for the LTC2632-LX. The reference mode of LTC2632-HZ/LTC2632-LZ/ LTC2632-HI/LTC2632-LI (internal reference power-on default), can be changed by software command after power-up. The same is true for the LTC2632-LX (external reference power-on default). Either channel or both channels can be put into powerdown mode by using command 0100b in combination with the appropriate DAC address (n). The supply current is reduced approximately 30% for each DAC powered down. The integrated reference is automatically powered down when external reference is selected using command 0111b. In addition, all the DAC channels and the integrated reference together can be put into power-down mode using power-down chip command 0101b. When the integrated reference is in power-down mode, the REF pin becomes high impedance (typically > 1GΩ). For all power-down commands the 16-bit data word is ignored. Normal operation resumes after executing any command that includes a DAC update (as shown in Table 1). The selected DAC is powered up as its voltage output is updated. When a DAC which is in a powered-down state is powered up and updated, normal settling is delayed. If less than two DACs are in a powered-down state prior to the update command, the power-up delay time is 10µs. However, if both DACs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the DAC amplifiers and reference buffers. In this case, the power up delay time is 12µs. The power-up of the integrated reference depends on the command that powered it down. If the reference is powered down using the select external reference command (0111b), then it can only be powered back up using select internal reference command (0110b). However, if the reference was powered down using power-down chip command (0101b), then in addition to the select internal reference command (0110b), any command that powers up the DACs will also power-up the integrated reference. Rev. C For more information www.analog.com 19 LTC2632 OPERATION Voltage Output Board Layout The LTC2632’s integrated rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 10mA at 5V, and 5mA at 3V. The PC board should have separate areas for the analog and digital sections of the circuit. A single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. The resistance from the LTC2632 GND pin to the ground plane should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.1Ω). Note that the LTC2632 is no more susceptible to this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load current. The measured change in output voltage per change in forced load current is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to ohms. The amplifier’s DC output impedance is 0.1Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices (e.g., when sinking 1mA, the minimum output voltage is 50Ω • 1mA, or 50mV). See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifier is stable driving capacitive loads of up to 500pF. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog output of the DAC cannot go below ground, it may limit for the lowest codes as shown in Figure 4b. Similarly, limiting can occur near full-scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC, as shown in Figure 4c. No full-scale limiting can occur if VREF is less than VCC –FSE. Another technique for minimizing errors is to use a separate power ground return trace on another board layer. The trace should run between the point where the power supply is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When the LTC2632 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. It is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. Bypass capacitors should be placed as close to the pins as possible with a low impedance path to GND. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Rev. C 20 For more information www.analog.com For more information www.analog.com 2 X 1 X SCK SDI CS/LD 4 X X 5 6 X 8 DON’T CARE BITS X 3 C2 C3 SDI C1 3 X 7 4 X 8 C0 COMMAND WORD 2 1 SCK CS/LD A1 7 ADDRESS A2 6 A0 8 D11 9 D10 10 D9 D8 12 D7 13 D6 14 24-BIT INPUT WORD 11 D5 15 D3 17 DATA WORD D4 16 D2 18 D1 19 D0 20 C2 C3 C1 11 12 C0 A3 13 A1 15 A0 16 D11 17 D10 18 32-BIT INPUT WORD ADDRESS A2 14 D9 19 D8 20 D7 21 D6 22 D5 23 24 D3 25 X 21 DATA WORD D4 Figure 3b. LTC2632-12 32-Bit Load Sequence LTC2632-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits; LTC2632-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits COMMAND WORD 10 9 Figure 3a. . LTC2632-12 24-Bit Load Sequence (Minimum Input Word) LTC2632-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits; LTC2632-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits A3 5 D2 26 X 22 D1 27 X 23 D0 28 X 24 X 29 X 30 2632 F03a X 31 X 32 2632 F03b LTC2632 OPERATION Rev. C 21 LTC2632 OPERATION VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0V NEGATIVE OFFSET 0 2,048 INPUT CODE 2632 F04 4,095 (a) 0V INPUT CODE (b) Figure 4. Effects of Rail-to-Rail Operation On a DAC Transfer Curve (Shown for 12 Bits) (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale PACKAGE DESCRIPTION TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 0.40 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 – 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1.95 BSC TS8 TSOT-23 0710 REV A Rev. C 22 For more information www.analog.com LTC2632 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 03/11 Revised part numbering. 2 to 9, 17, 19, 24 B 06/17 Removed Note 3. C 07/19 Changed A-Grade INL from ±1LSB to ±1.5LSB. 9 1 to 4, 7 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 23 LTC2632 TYPICAL APPLICATION LTC2632 DACs Adjust LTC2755-16 Offset, Amplified with LT1991 PGA to ±5V 5V 15V VDD 0.1µF LTC2755 ROFSA 0.1µF 15V 30pF RIN1 RFBA + IOUT1A 1/2 LT1469 RCOM1 – 0.1µF DAC A 0.1µF – IOUT2A RVOSA 5V 30pF –15V –15V LT1634-1.25 REFA DAC D OUTA 1/2 LT1469 + 0.1µF – + DAC B LT6240 0.1µF 30k 10V 5V –15V DAC C 0.1µF REF GND VCC LTC2632TS8-LI12 DAC A 0.1µF 0.1µF DAC B M9 M3 VCC M1 OUT LT1991 P1 REF P3 VEE VOUT ±6V P9 SERIAL BUS CS/LD SCK GND SDI 0.1µF –10V 2632 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1662 Dual 10-Bit Ultralow Power VOUT DAC in 8-Lead MSOP with External Reference 1.5µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2602/LTC2612/ Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP LTC2622 with External Reference 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, SPI Serial Interface LTC2607/LTC2617/ Dual 16-/14-/12-Bit VOUT DACs in 12-Lead DFN LTC2627 with External Reference 260µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, I2C Serial Interface LTC2630 Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference in SC70 180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, Rail-to-Rail Output, SPI Serial Interface LTC2631 Single 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C Reference in ThinSOT 180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, I2C Interface LTC2634 Quad 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference 125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, SPI Interface LTC2636 Octal 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference 125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, SPI Interface LTC2640 Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference in ThinSOT 180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode, Rail-to-Rail Output, SPI Interface LTC2654 Quad 16-/12-Bit VOUT DACs with ±4 LSB INL, ±1 LSB DNL 4mm × 4mm QFN-20, SSOP-16 Packages, SPI Interface, Internal 10ppm/°C (Max) Reference Rev. C 24 07/19 www.analog.com For more information www.analog.com  ANALOG DEVICES, INC. 2011-2019