LTC2974
4-Channel PMBus Power System Manager
Featuring Accurate Output Current Measurement
Features
Description
Sequence, Trim, Margin and Supervise Four Power
Supplies
n Manage Faults, Monitor Telemetry and Create Fault Logs
n PMBus Compliant Command Set
n Supported by LTpowerPlayTM GUI
n Margin or Trim Supplies to 0.25% Accuracy
n Fast OV/UV Supervisors Per Channel
n Fast Output Current Supervisors Per Channel
n Coordinate Sequencing and Fault Management
Across Multiple Chips
n Automatic Fault Logging to Internal EEPROM
n Operate Autonomously without Additional Software
n External Temperature and Input Voltage Supervisors
n Accurate Monitoring of Four Output Voltages, Four
Output Currents, Four External Temperatures, Input
Voltage and Internal Die Temperature
n I2C/SMBus Serial Interface
n Can Be Powered from 3.3V, or 4.5V to 15V
n Available in 64-Lead 9mm × 9mm QFN Package
The LTC®2974 is a 4-channel Power System Manager used
to sequence, trim (servo), margin, supervise, manage
faults, provide telemetry and create fault logs. PMBus
commands support power supply sequencing, precision
point-of-load voltage adjustment and margining. DACs use
a proprietary soft-connect algorithm to minimize supply
disturbances. Supervisory functions include over and under
current, voltage and temperature threshold limits for four
power supply output channels as well as over and under
voltage threshold limits for a single power supply input
channel. Programmable fault responses can disable the
power supplies with optional retry after a fault is detected.
Faults that disable a power supply can automatically trigger
black box EEPROM storage of fault status and associated
telemetry. An internal 16-bit ADC monitors four output
voltages, four output currents, four external temperatures,
one input voltage and die temperature. Output power is
also calculated. A programmable watchdog timer monitors microprocessor activity for a stalled condition and
resets the microprocessor if necessary. A single wire bus
synchronizes power supplies across multiple LTC power
system management devices. Configuration EEPROM supports autonomous operation without additional software.
n
Applications
Computers and Network Servers
Industrial Test and Measurement
n High Reliability Systems
n Medical Imaging
n Video
n
n
L, LT, LTC, LTM, Linear Technology, the Linear logo, and PolyPhase are registered trademarks
and LTpowerPlay is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 7382303, 7420359 and
7940091.
Typical Application
ADC Total Unadjusted Error
vs Temperature
4-Channel PMBus Power System Manager
VIN
4.5V < VIBUS < 15V**
OV
AUXFAULTB
VDD33**
PMBus
INTERFACE
TO/FROM
OTHER
DEVICES
VIN_SNS
ISENSEP0
I–
I+
ISENSEM0
TG
FAULTB0
FAULTB1
SHARE_CLK
ASEL0
ASEL1
WP
GND
R30
VSENSEP0
VOUT_EN0
TSENSE0
PWRGD
WDI/RESETB
0.06
0.05
0.04
SW
VDAC0
SDA
LTC2974*
SCL
ALERTB
CONTROL0
VSENSEM0
0.07
DC/DC
CONVERTER
BG
R20
VFB
LOAD
MMBT3906
2974 TA01
0.03
0.02
0.01
0
R10
TO µP
RESETB
INPUT
0.1µF
WATCHDOG
TIMER INTERRUPT
ERROR (%)
VPWR**
SGND
RUN/SS
GND
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF FOUR CHANNELS SHOWN
–0.01
–0.02
THREE TYPICAL PARTS
–0.03
–25
0
25
–50
50
TEMPERATURE (°C)
75
100
2974 TA01b
**LTC2974 MAY BE POWERED FROM
3.3V OR 4.5V TO 14V
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1
LTC2974
Table of Contents
Features............................................................ 1
Applications....................................................... 1
Typical Application............................................... 1
Description........................................................ 1
Absolute Maximum Ratings..................................... 4
Order Information................................................. 4
Pin Configuration................................................. 4
Electrical Characteristics........................................ 5
PMBus Timing Diagram.......................................... 9
Typical Performance Characteristics......................... 10
Pin Functions..................................................... 13
Block Diagram.................................................... 15
Operation......................................................... 16
LTC2974 Operation Overview.......................................... 16
EEPROM..................................................................... 17
AUXFAULTB.................................................................... 17
RESETB........................................................................... 18
PMBus Serial Digital Interface........................................ 18
PMBus........................................................................ 18
Device Address........................................................... 18
Processing Commands.............................................. 19
PMBUS Command Summary................................... 22
Summary Table...........................................................22
Data Formats.............................................................. 27
PMBus Command Description................................. 28
Addressing and Write Protect......................................... 28
PAGE........................................................................... 28
WRITE_PROTECT....................................................... 28
WRITE-PROTECT Pin.................................................29
MFR_PAGE_FF_MASK...............................................29
MFR_I2C_BASE_ADDRESS.......................................29
On/Off Control, Margining and Configuration.................30
OPERATION................................................................30
ON_OFF_CONFIG........................................................ 31
MFR_CONFIG_LTC2974............................................. 32
Cascade Sequence ON with Time-Based
Sequence OFF.............................................................33
MFR_CONFIG2_LTC2974...........................................35
MFR_CONFIG3_LTC2974...........................................35
Tracking Supplies On and Off..................................... 37
Tracking Implementation............................................38
MFR_CONFIG_ALL_LTC2974..................................... 39
Programming User EEPROM Space................................40
STORE_USER_ALL and RESTORE_USER_ALL......... 41
Bulk Programming the User EEPROM Space............. 41
MFR_EE_UNLOCK...................................................... 41
MFR_EE_ERASE........................................................ 42
MFR_EE_DATA........................................................... 42
Response When Part Is Busy.....................................43
MFR_EE Erase and Write Programming Time............43
Input Voltage Commands and Limits..............................43
VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_OV_
WARN_LIMIT, VIN_UV_WARN_LIMIT and
VIN_UV_FAULT_LIMIT...............................................43
Output Voltage Commands and Limits...........................44
VOUT_MODE..............................................................44
VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_
HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_LIMIT,
VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT,
VOUT_UV_FAULT_LIMIT, POWER_GOOD_ON and
POWER_GOOD_OFF...................................................45
MFR_VOUT_DISCHARGE_THRESHOLD.....................45
MFR_DAC...................................................................45
Output Current Commands and Limits...........................46
IOUT_CAL_GAIN........................................................46
IOUT_OC_FAULT_LIMIT, IOUT_OC_WARN_LIMIT and
IOUT_UC_FAULT_LIMIT............................................. 47
MFR_IOUT_CAL_GAIN_TC......................................... 47
External Temperature Commands And Limits.................48
OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_
LIMIT and UT_FAULT_LIMIT......................................48
MFR_TEMP_1_GAIN and MFR_TEMP_1_OFFSET.......48
MFR_T_SELF_HEAT, MFR_IOUT_CAL_GAIN_TAU_INV
and MFR_IOUT_CAL_GAIN_THETA........................... 49
Sequencing Timing Limits and Clock Sharing................. 51
TON_DELAY, TON_RISE, TON_MAX_FAULT_LIMIT
and TOFF_DELAY........................................................ 51
MFR_RESTART_DELAY.............................................. 51
Watchdog Timer and Power Good.................................. 52
MFR_PWRGD_EN...................................................... 52
Clock Sharing............................................................. 52
MFR_POWERGOOD_ASSERTION_DELAY.................53
Watchdog Operation...................................................53
MFR_WATCHDOG_T_FIRST and
MFR_WATCHDOG_T...................................................53
Fault Responses..............................................................54
Clearing Latched Faults..............................................54
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_
RESPONSE.................................................................55
IOUT_OC_FAULT_RESPONSE and IOUT_UC_FAULT_
RESPONSE.................................................................56
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE,
VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_
RESPONSE................................................................. 57
TON_MAX_FAULT_RESPONSE..................................58
MFR_RETRY_DELAY..................................................58
MFR_RETRY_COUNT.................................................58
Shared External Faults.................................................... 59
MFR_FAULTB0_PROPAGATE and MFR_FAULTB1_
PROPAGATE............................................................... 59
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LTC2974
Table of Contents
MFR_FAULTB0_RESPONSE and MFR_FAULTB1_
RESPONSE.................................................................60
Fault Warning and Status................................................ 61
CLEAR_FAULTS.......................................................... 61
STATUS_BYTE............................................................ 61
STATUS_WORD.......................................................... 62
STATUS_VOUT........................................................... 62
STATUS_IOUT............................................................63
STATUS_INPUT..........................................................63
STATUS_TEMPERATURE............................................63
STATUS_CML.............................................................64
STATUS_MFR_SPECIFIC............................................64
MFR_PADS.................................................................65
MFR_COMMON..........................................................65
Telemetry........................................................................66
READ_VIN.................................................................. 67
READ_VOUT............................................................... 67
READ_IOUT................................................................ 67
READ_TEMPERATURE_1........................................... 67
READ_TEMPERATURE_2........................................... 67
READ_POUT............................................................... 67
MFR_READ_IOUT...................................................... 67
MFR_IOUT_SENSE_VOLTAGE....................................68
MFR_VIN_PEAK......................................................... 69
MFR_VOUT_PEAK...................................................... 69
MFR_IOUT_PEAK....................................................... 69
MFR_TEMPERATURE_1_PEAK.................................. 69
MFR_VIN_MIN........................................................... 69
MFR_VOUT_MIN........................................................ 69
MFR_IOUT_MIN......................................................... 69
MFR_TEMPERATURE_1_MIN.................................... 69
Fault Logging.................................................................. 70
Fault Log Operation.................................................... 70
MFR_FAULT_LOG_STORE......................................... 70
MFR_FAULT_LOG_RESTORE..................................... 70
MFR_FAULT_LOG_CLEAR......................................... 71
MFR_FAULT_LOG_STATUS........................................ 71
MFR_FAULT_LOG....................................................... 71
MFR_FAULT_LOG Read Example............................... 74
Identification/Information............................................... 78
CAPABILITY................................................................ 79
PMBus_REVISION...................................................... 79
MFR_SPECIAL_ID...................................................... 79
MFR_SPECIAL_LOT................................................... 79
User Scratchpad.............................................................. 79
USER_DATA_00, USER_DATA_01, USER_DATA_02,
USER_DATA_03, USER_DATA_04, MFR_LTC_
RESERVED_1 and MFR_LTC_RESERVED_2.............. 79
Applications Information....................................... 80
Overview.........................................................................80
Powering the LTC2974....................................................80
Setting Command Register Values..................................80
Sequence, Servo, Margin and Restart Operations..........80
Command Units On or Off..........................................80
On Sequencing...........................................................80
On State Operation..................................................... 81
Servo Modes.............................................................. 81
DAC Modes................................................................. 82
Margining................................................................... 82
Off Sequencing........................................................... 82
VOUT Off Threshold Voltage........................................ 82
Automatic Restart via MFR_RESTART_DELAY
Command and CONTROL pin..................................... 82
Fault Management........................................................... 82
Output Overvoltage, Undervoltage, Overcurrent, and
Undercurrent Faults.................................................... 82
Output Overvoltage, Undervoltage, and Overcurrent
Warnings....................................................................83
Configuring the AUXFAULTB Output...........................83
Multi-Channel Fault Management...............................84
Interconnect Between Multiple LTC2974’s......................84
Application Circuits.........................................................85
Trimming and Margining DC/DC Converters with
External Feedback Resistors......................................85
Four-Step Resistor Selection Procedure for DC/DC
Converters with External Feedback Resistors............85
Trimming and Margining DC/DC Converters with a
TRIM Pin.....................................................................86
Two-Step Resistor and DAC Full-Scale Voltage
Selection Procedure for DC/DC Converters with a
TRIM Pin..................................................................... 87
Measuring Current with a Sense Resistor.................. 87
Measuring Current with Inductor DCR....................... 87
Single Phase Design Example....................................88
Measuring Multiphase Currents.................................88
Multiphase Design Example....................................... 89
Anti-aliasing Filter Considerations.............................. 89
Sensing Negative Voltages......................................... 89
Connecting the DC1613 USB to I2C/SMBus/PMBus
Controller to the LTC2974 in System..........................90
Accurate DCR Temperature Compensation..................... 91
LTpowerPlay: An Interactive GUI for Power Managers....93
PCB Assembly and Layout Suggestions.........................94
Bypass Capacitor Placement......................................94
Exposed Pad Stencil Design.......................................94
Unused ADC Sense Inputs..........................................94
PCB Board Layout......................................................94
Package Description............................................ 95
Typical Application.............................................. 96
Related Parts..................................................... 96
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LTC2974
Absolute Maximum Ratings
Pin Configuration
(Note 1)
64 VSENSEM1
63 VSENSEP1
62 VSENSEM2
61 VSENSEP2
60 NC
59 NC
58 VDAC3
57 VDAC2
56 NC
55 NC
54 VDAC1
53 VDAC0
52 NC
51 NC
50 VSENSEM3
49 VSENSEP3
TOP VIEW
VSENSEP0 1
VSENSEM0 2
VOUT_EN0 3
VOUT_EN1 4
VOUT_EN2 5
VOUT_EN3 6
AUXFAULTB 7
DNC 8
VIN_SNS 9
VPWR 10
VDD33 11
VDD33 12
VDD25 13
VDD25 14
TSENSE0 15
TSENSE1 16
48 ISENSEM3
47 ISENSEP3
46 ISENSEM2
45 ISENSEP2
44 ISENSEM1
43 ISENSEP1
42 ISENSEM0
41 ISENSEP0
40 REFM
39 GND
38 REFP
37 GND
36 ASEL1
35 ASEL0
34 TSENSE3
33 CONTROL1
65
GND
PWRGD 17
SHARE_CLK 18
GND 19
GND 20
GND 21
CONTROL2 22
CONTROL3 23
WDI/RESETB 24
FAULTB0 25
FAULTB1 26
TSENSE2 27
WP 28
SDA 29
SCL 30
ALERTB 31
CONTROL0 32
Supply Voltages:
VPWR to GND.......................................... –0.3V to 15V
VDD33 to GND........................................ –0.3V to 3.6V
VDD25 to GND...................................... –0.3V to 2.75V
Digital Input/Output Voltages:
ALERTB, SDA, SCL, CONTROL0, CONTROL1,
CONTROL2, CONTROL3 to GND............ –0.3V to 3.6V
PWRGD, SHARE_CLK, WDI/RESETB, WP,
FAULTB0, FAULTB1 to GND.................. –0.3V to 3.6 V
ASEL0, ASEL1 to GND........................... –0.3V to 3.6V
Analog Voltages:
REFP.................................................... –0.3V to 1.35V
REFM to GND......................................... –0.3V to 0.3V
VIN_SNS to GND...................................... –0.3V to 15V
VSENSEP[3:0] to GND.................................. –0.3V to 6V
VSENSEM[3:0] to GND................................. –0.3V to 6V
ISENSEP[3:0] to GND................................... –0.3V to 6V
ISENSEM[3:0] to GND.................................. –0.3V to 6V
VOUT_EN[3:0], AUXFAULTB to GND........... –0.3V to 15V
VDAC[3:0] to GND....................................... –0.3V to 6V
TSENSE[3:0] to GND................................. –0.3V to 3.6V
Operating Junction Temperature Range:
LTC2974C................................................. 0°C to 70°C
LTC2974I...............................................–40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
Maximum Junction Temperature......................... 125°C*
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 125°C, θJCtop = 7°C/W, θJCbottom = 1°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
*See OPERATION section for detailed EEPROM derating information for junction temperatures in excess
of 85°C.
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2974CUP#PBF
LTC2974CUP#TRPBF
LTC2974UP
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2974IUP#PBF
LTC2974IUP#TRPBF
LTC2974UP
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2974
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
15
V
10
13
mA
10
13
mA
2.55
2.8
V
Power Supply Characteristics
VPWR
VPWR Supply Input Operating Range
VDD33 Floating (Note 2)
l
IPWR
VPWR Supply Current
4.5V ≤ VPWR ≤ 15V, VDD33 Floating (Note 2)
l
IVDD33
VDD33 Supply Current
3.13V ≤ VDD33 ≤ 3.47V, VPWR = VDD33
l
VUVLO_VDD33
VDD33 Undervoltage Lockout
VDD33 Ramping Up, VPWR = VDD33
l
4.5
2.25
VDD33 Undervoltage Lockout
Hysteresis
VDD33
120
Supply Input Operating Range
VPWR = VDD33
l
3.13
Regulator Output Voltage
4.5V ≤ VPWR ≤ 15V
l
3.13
mV
3.47
V
3.26
3.47
V
Regulator Output Short-Circuit Current VPWR = 4.5V, VDD33 = 0V
l
75
90
140
mA
VDD25
Regulator Output Voltage
l
2.35
2.5
2.6
V
l
30
55
80
mA
tINIT
Initialization Time
3.13V ≤ VDD33 ≤ 3.47V
Regulator Output Short-Circuit Current VPWR = VDD33 = 3.47V, VDD25 = 0V
Time from VIN applied until the TON_DELAY
timer starts
30
ms
Voltage Reference Characteristics
VREF
Output Voltage
VREF = VREFP – VREFM, 0 < IREFP < 100µA
l
1.220
Temperature Coefficient
Hysteresis
1.232
1.244
3
(Note 3)
V
ppm/°C
100
ppm
ADC Characteristics
VIN_ADC
Voltage Sense Input Range
Current Sense Input Range
Differential Voltage:
VIN_ADC = (VSENSEPn – VSENSEMn)
l
0
6
V
Single-Ended Voltage: VSENSEMn
l
–0.1
0.1
V
Single-Ended Voltage: ISENSEPn, ISENSEMn
l
–0.1
6
V
Differential Current Sense Voltage:
VIN_ADC = (ISENSEPn – ISENSEMn)
l
–170
170
mV
Voltage Sense Resolution
0V ≤ VIN_ADC ≤ 6V, READ_VOUT
Current Sense Resolution
0mV ≤ |VIN_ADC| < 16mV (Note 4)
16mV ≤ |VIN_ADC| < 32mV
32mV ≤ |VIN_ADC| < 63.9mV
63.9mV ≤ |VIN_ADC| < 127.9mV
127.9mV ≤ |VIN_ADC|
IOUT_CAL_GAIN = 1000mΩ
TUE_ADC_
VOLT_SNS
Total Unadjusted Error
Voltage Sense Inputs VIN_ADC ≥ 1V
l
±0.25
%
Voltage Sense Inputs 0 ≤ VIN_ADC ≤ 1V
l
±2.5
mV
TUE_ADC_
CURR_SNS
Total Unadjusted Error
Current Sense Inputs 20mV ≤ VIN_ADC ≤
170mV
l
±0.3
%
Current Sense Inputs VIN_ADC ≤ 20mV
l
60
µV
l
±35
µV
N_ADC
122
µV/LSB
15.625
31.25
62.5
125
250
µA/LSB
µA/LSB
µA/LSB
µA/LSB
µA/LSB
VOS_ADC
Offset Error
ISENSEPn and ISENSEMn Inputs, VOS • IOUT_
CAL_GAIN, IOUT_CAL_GAIN = 1Ω
tCONV_ADC
Conversion Time
VSENSEPn, VSENSEMn, VIN_SNS Inputs (Note 5)
6.15
ms
ISENSEPn and ISENSEMn Inputs (Note 5)
24.6
ms
Internal Temperature
(READ_TEMPERATURE_2) (Note 5)
24.6
ms
(Note 5)
160
ms
1
pF
tUPDATE_ADC
Maximum Update Time
CIN_ADC
Input Sampling Capacitance
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5
LTC2974
Electrical
Characteristics l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
fIN_ADC
Input Sampling Frequency
CONDITIONS
MIN
TYP
MAX
IIN_ADC
Input Leakage Current
ISENSEPn, ISENSEMn,VSENSEPn, and VSENSEMn
Inputs, VIN_ADC = 0V, 0V ≤ VCOMMONMODE ≤ 6V
Differential Input Current
VSENSEPn, and VSENSEMn Inputs, VIN_ADC = 6V l
10
15
µA
ISENSEPn, and ISENSEMn Inputs,
VIN_ADC = 0.17V
l
0.3
0.5
µA
62.5
kHz
±0.5
l
UNITS
µA
DAC Output Characteristics
N_VDAC
Resolution
VFS_VDAC
Full-Scale Output Voltage
(Programmable)
DAC Code = 0x3FF Buffer Gain Setting_0
DAC Polarity = 1
Buffer Gain Setting_1
l
l
10
INL_VDAC
Integral Nonlinearity
(Note 6)
l
±2
LSB
DNL_VDAC
Differential Nonlinearity
(Note 6)
l
±2.4
LSB
VOS_VDAC
Offset Voltage
(Note 6)
l
±12
mV
VDAC
Load Regulation
VDACn = 2.65V, IVDACn Sourcing = 2mA
100
ppm/mA
VDACn = 0.1V, IVDACn Sinking = 2mA
100
ppm/mA
1.3
2.5
1.38
2.65
Bits
1.44
2.77
V
V
PSRR
DC: 3.13V ≤ VDD33 ≤ 3.47V, VPWR = VDD33
Leakage Current
VDACn Hi-Z, 0V ≤ VDACn ≤ 6V
l
Short-Circuit Current Low
VDACn Shorted to GND
l
Short-Circuit Current High
VDACn Shorted to VDD33
l
COUT
Output Capacitance
VDACn Hi-Z
10
pF
tS_VDAC
DAC Output Update Rate
Fast Servo Mode
250
µs
60
dB
±100
nA
–12
–4
mA
4
12
mA
Voltage Supervisor Characteristics
VIN_VS
N_VS
TUE_VS
tS_VS
Input Voltage Range (Programmable)
Voltage Sensing Resolution
Total Unadjusted Error
VIN_VS = (VSENSEPn Low Resolution Mode
– VSENSEMn)
High Resolution Mode
l
l
0
0
6
3.8
V
V
Single-Ended Voltage: VSENSEMn
l
–0.1
0.1
V
0V to 3.8V Range: High Resolution Mode
4
mV/LSB
0V to 6V Range: Low Resolution Mode
8
mV/LSB
2V ≤ VIN_VS ≤ 6V, Low Resolution Mode
l
±1.25
%
1.5V < VIN_VS ≤ 3.8V, High Resolution Mode
l
±1.0
%
0.8V ≤ VIN_VS ≤ 1.5V, High Resolution Mode
l
±1.5
Update Rate
12.21
%
µs
Current Supervisor Characteristics
VIN_CS
Current Sense Input Range
Single-Ended Voltage: ISENSEPn, ISENSEMn
l
–0.1
6
Differential Voltage:
VIN_CS = (ISENSEPn – ISENSEMn)
l
–170
170
400
V
mV
N_CS
Current Sense Resolution
IOUT_OC_FAULT_LIMIT • IOUT_CAL_GAIN
IOUT_UC_FAULT_LIMIT • IOUT_CAL_GAIN
µV/LSB
TUE_CS
Total Unadjusted Error
50mV ≤ VIN_CS ≤ 170mV
l
±3
%
±1.5
mV
600
µV
VIN_CS < 50mV
l
VOS_CS
Offset Error
|VIN_CS| = 0.8mV
l
IOS_CS
Differential Input Offset Current
OC = Positive Full-Scale, UC = 0A,
VIN_CS = 0V
117
nA
OC = UC = Positive Full-Scale, VIN_CS = 0V
244
nA
0
nA
OC = 0A, UC < 0A, VIN_CS = 0V
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LTC2974
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
tS_CS
Update Rate
CONDITIONS
MIN
TYP
MAX
12.21
UNITS
µs
VIN_SNS Input Characteristics
VIN_SNS
VIN_SNS Input Voltage Range
l
0
RVIN_SNS
VIN_SNS Input Resistance
l
70
TUEVIN_SNS
VIN_ON, VIN_OFF Threshold Total
Unadjusted Error
3V ≤ VVIN_SNS ≤ 8V
l
VVIN_SNS > 8V
l
±1.0
%
READ_VIN Total Unadjusted Error
3V ≤ VVIN_SNS ≤ 8V
l
±1.5
%
VVIN_SNS > 8V
l
±1.0
%
VDACPn = 0.2V
l
±1
±18
mV
VDACPn = 1.3V
l
±2
±26
mV
VDACPn = 2.65V
l
±3
±52
mV
90
15
V
110
kΩ
±2.0
%
DAC Soft-Connect Comparator Characteristics
VOS_CMP
Offset Voltage
External Temperature Sensor Characteristics (READ_TEMPERATURE_1)
tCONV_TSENSE Conversion Time
For One Channel, (Total Latency For All
Channels Is 4 • 66ms)
66
ms
ITSENSE_HI
TSENSE High Level Current
l
–90
–64
–40
µA
ITSENSE_LOW
TSENSE Low Level Current
l
–5.5
–4
–2.5
µA
TUE_TS
Total Unadjusted Error
Ideal Diode Assumed
N_TS
Maximum Ideality Factor
READ_TEMPERATURE_1 = 175°C
MFR_TEMP1_GAIN = 1/N_TS
l
±3
°C
1.10
NA
Internal Temperature Sensor Characteristics (READ_TEMPERATURE_2)
TUE_TS2
Total Unadjusted Error
±1
°C
VOUT Enable Output (VOUT_EN[3:0]) Characteristics
VVOUT_ENn
Output High Voltage
IVOUT_ENn = –5µA, VDD33 = 3.13V
l
10
13
14.7
V
IVOUT_ENn
Output Sourcing Current
VVOUT_ENn Pull-Up Enabled, VVOUT_ENn = 1V
l
–5
–7
–9
µA
Output Sinking Current
Strong Pull-Down Enabled,
VVOUT_ENn = 0.4V
l
3
5
8
mA
Weak Pull-Down Enabled, VVOUT_ENn = 0.4V
l
33
50
Internal Pull-Up Disabled,
0V ≤ VVOUT_ENn ≤ 15V
l
Output Leakage Current
65
µA
±1
µA
General Purpose Output (AUXFAULTB) Characteristics
VAUXFAULTB
Output High Voltage
IAUXFAULTB = –5µA, VDD33 = 3.13V
l
10
13
14.7
V
IAUXFAULTB
Output Sourcing Current
AUXFAULTB Pull-Up Enabled, VAUXFAULTB =
1V
l
–5
–7
–9
µA
Output Sinking Current
Strong Pull-Down Enabled, VAUXFAULTB = 0.4V l
3
5
8
mA
Output Leakage Current
Internal Pull-Up Disabled, 0V ≤ VAUXFAULTB
≤ 15V
l
±1
µA
EEPROM Characteristics
Endurance
(Note 7)
0°C < TJ < 85°C During EEPROM Write
Operations
l
10,000
Retention
(Note 7)
TJ < 85°C
l
10
tMASS_WRITE
Mass Write Operation Time (Note 8)
STORE_USER_ALL, 0°C < TJ < 85°C During
EEPROM Write Operations
l
Cycles
Years
440
4100
ms
2974fc
For more information www.linear.com/LTC2974
7
LTC2974
Electrical
Characteristics l denotes the specifications which apply over the full operating
The
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Inputs SCL, SDA, CONTROL0, CONTROL1, CONTROL2, CONTROL3, WDI/RESETB, FAULTB0, FAULTB1, WP
VIH
High Level Input Voltage
FAULTB0, FAULTB1, SDA, SCL, WDI/RESETB, l
WP
2.1
V
CONTROLn
1.85
V
l
VIL
Low Level Input Voltage
VHYST
Input Hysteresis
ILEAK
Input Leakage Current
0V ≤ VPIN ≤ 3.6V
tSP
Pulse Width of Spike Suppressed
FAULTB0, FAULTB1, CONTROLn
10
µs
SDA, SCL
98
ns
FAULTB0, FAULTB1, SDA, SCL, WDI/RESETB, l
WP
CONTROLn
1.5
1.6
l
20
tFAULT_MIN
Minimum Low Pulse Width for
Externally Generated Faults
tRESETB
Pulse Width to Assert Reset
VWDI/RESETB ≤ 1.5V
l
300
tWDI
Pulse Width to Reset Watchdog Timer
VWDI/RESETB ≤ 1.5V
l
0.3
fWDI
Watchdog Timer Interrupt Input
Frequency
CIN
Input Capacitance
V
mV
±2
l
V
180
µA
ms
µs
200
1
l
10
µs
MHz
pF
Digital Input SHARE_CLK
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
fSHARE_CLK_IN Input Frequency Operating Range
1.6
V
0.8
V
l
90
110
kHz
tLOW
Assertion Low Time
VSHARE_CLK < 0.8V
l
0.825
1.11
µs
tRISE
Rise Time
VSHARE_CLK < 0.8V to VSHARE_CLK > 1.6V
l
450
ns
ILEAK
Input Leakage Current
0V ≤ VSHARE_CLK ≤ VDD33 + 0.3V
l
±1
µA
CIN
Input Capacitance
10
pF
Digital Outputs SDA, ALERTB, SHARE_CLK, FAULTB0, FAULTB1, PWRGD
VOL
Digital Output Low Voltage
fSHARE_CLK_OUT Output Frequency Operating Range
ISINK = 3mA
l
5.49kΩ Pull-Up to VDD33
l
90
100
0.4
V
110
kHz
Digital Inputs ASEL0,ASEL1
VIH
Input High Threshold Voltage
VIL
Input Low Threshold Voltage
IIH,IL
High, Low Input Current
IIH,Z
Hi-Z Input Current
CIN
Input Capacitance
l VDD33 – 0.5
ASEL[1:0] = 0, VDD33
V
l
0.5
V
l
±95
µA
±24
µA
l
10
pF
Serial Bus Timing Characteristics
fSCL
Serial Clock Frequency (Note 9)
l
10
tLOW
Serial Clock Low Period (Note 9)
l
1.3
µs
tHIGH
Serial Clock High Period (Note 9)
l
0.6
µs
tBUF
Bus Free Time Between Stop and Start
(Note 10)
l
1.3
µs
tHD,STA
Start Condition Hold Time (Note 9)
l
600
ns
tSU,STA
Start Condition Setup Time (Note 9)
l
600
ns
400
kHz
2974fc
8
For more information www.linear.com/LTC2974
LTC2974
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25, REFP and REFM pins floating,
unless otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSU,STO
Stop Condition Setup Time (Note 9)
l
600
ns
tHD,DAT
Data Hold Time (LTC2974 Receiving
Data) (Note 9)
l
0
ns
Data Hold Time (LTC2974 Transmitting
Data) (Note 9)
l
300
tSU,DAT
Data Setup Time (Note 9)
l
100
tSP
Pulse Width of Spike Suppressed
(Note 9)
tTIMEOUT_BUS
Time Allowed to Complete any PMBus Longer Timeout = 0
Command After Which Time SDA Will Longer Timeout = 1
Be Released and Command Terminated
900
ns
ns
98
ns
25
200
l
l
35
280
ms
ms
Additional Digital Timing Characteristics
tOFF_MIN
Minimum Off Time for Any Channel
100
ms
the resolution for 1LSB in this range is 2–2mA = 250µA. Each successively
lower range improves resolution by cutting the LSB size in half.
Note 5: The nominal time between successive ADC conversions (latency of
the ADC) for any given channel is tUPDATE_ADC.
Note 6: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to full-scale code, 1023.
Note 7: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 8: The LTC2974 will not acknowledge any PMBus commands,
except for MFR_COMMON, when a STORE_USER_ALL command is being
executed. See also OPERATION section.
Note 9: Maximum capacitive load, CB, for SCL and SDA is 400pF. Data and
clock risetime (tr) and falltime (tf) are: (20 + 0.1• CB) (ns) < tr < 300ns and
(20 + 0.1 • CB) (ns) < tf < 300ns. CB = capacitance of one bus line in pF.
SCL and SDA external pull-up voltage, VIO, is 3.13V < VIO < 3.6V.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified. If power is supplied to the chip via the VDD33 pin only, connect
VPWR and VDD33 pins together.
Note 3: Hysteresis in the output voltage is created by package stress
that differs depending on whether IC was previously at a higher or lower
temperature. Output voltage is always measured at 25°C, but the IC is
cycled to 85°C or –40°C before successive measurements. Hysteresis is
roughly proportional to the square of the temperature change.
Note 4: The current sense resolution is determined by the L11 format and
the mV units of the returned value. For example, a full-scale value of 170mV
returns a L11 value of 0xF2A8 = 680 • 2–2 = 170. This is the lowest range
that can represent this value without overflowing the L11 mantissa and
PMBus Timing Diagram
SDA
tf
tLOW
tr
tSU(DAT)
tHD(STA)
tf
tSP
tr
tBUF
SCL
tHD(STA)
START
CONDITION
tHD(DAT)
tHIGH
tSU(STA)
tSU(STO)
2974 TD
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
2974fc
For more information www.linear.com/LTC2974
9
LTC2974
Typical Performance Characteristics
Reference Voltage vs
Temperature
ADC READ_VOUT Total Unadjusted
Error vs Temperature
ADC READ_IOUT Input Referred
Offset Voltage vs Temperature
5
1.2320
0.06
4
1.2318
0.05
3
0.04
2
0.03
1
ERROR (%)
1.2316
1.2314
1.2312
1.2310
OFFSET (µV)
0.07
REFERENCE OUTPUT VOLTAGE (V)
1.2322
0.02
0.01
0
–1
0.00
–2
1.2308
–0.01
–3
1.2306
–0.02
THREE TYPICAL PARTS
1.2304
–50
–25
0
25
50
TEMPERATURE (°C)
100
75
–4
THREE TYPICAL PARTS
–0.03
–50
–25
0
25
50
TEMPERATURE (°C)
75
2974 G01
3
2
2
0
0
–1
–2
–3
–3
–4
–4
0
1
2
3
4
READ_VOUT (V)
5
–5
6
0
1
2
3
4
READ_VOUT (V)
5
3.75
3.50
3.25
3.00
2.75
0
25
50
TEMPERATURE (°C)
75
–25
–75
0.001
6
100
2974 G07
0.01
10
100
Input Sampling Current vs
Differential Input Voltage: Current
Sense Inputs
400
6
350
5
4
3
2
1
0
1
2974 G06
7
0
0.1
READ_IOUT (A)
DIFFERENTIAL INPUT CURRENT (nA)
DIFFERENTIAL INPUT CURRENT (µA)
NOISE (µVRMS)
4.00
–25
0
2974 G05
4.50
2.50
–50
25
Input Sampling Current vs
Differential Input Voltage:
Voltage Sense Inputs
4.25
IOUT_CAL_GAIN = 2.1875mΩ
–50
2974 G04
ADC READ_IOUT Input Referred
Noise vs Temperature
100
75
50
1
–2
–5
75
READ_IOUT ERROR (mA)
3
–1
0
25
50
TEMPERATURE (°C)
ADC READ_IOUT Error
vs READ_IOUT
122µV/LSB
4
ERROR (LSBs)
ERROR (LSBs)
5
1
–25
2974 G03
ADC READ_VOUT-DNL
122µV/LSB
4
–5
–50
100
2974 G02
ADC READ_VOUT-INL
5
THREE TYPICAL PARTS
1
2
3
4
5
DIFFERENTIAL INPUT VOLTAGE (V)
6
2974 G08
VCM = 2.5V
300
250
200
150
100
50
0
0
25
50
75 100 125 150
DIFFERENTIAL INPUT VOLTAGE (mV)
175
2974 G09
2974fc
10
For more information www.linear.com/LTC2974
LTC2974
Typical Performance Characteristics
Voltage Supervisor Total
Unadjusted Error vs Temperature
1.400
1.2
0.15
SUPERVISOR ERROR (%)
SUPERVISOR ERROR (%)
1.405
1.4
HIGH RES MODE
VIN = 1.5V
0.20
DAC Full-Scale Voltage
vs Temperature, Gain = 0
0.10
0.05
0
–0.05
–0.10
DAC OUTPUT VOLTAGE (V)
0.25
Current Supervisor Total
Unadjusted Error vs Temperature
1.0
50mV
0.8
0.6
0.4
20mV
0.2
–0.15
THREE TYPICAL PARTS
–0.20
–50
–25
0
25
50
TEMPERATURE (°C)
75
–25
0
25
50
TEMPERATURE (°C)
75
DAC Full-Scale Voltage
vs Temperature, Gain = 1
1.380
1.375
1.370
100
0.0025
GAIN SETTING = 1
100
75
2974 G12
DAC Offset Voltage
vs Temperature, Gain = 0
DAC Offset Voltage
vs Temperature, Gain = 1
0.0040
GAIN SETTING = 0
GAIN SETTING = 1
0.0035
2.67
2.66
2.65
2.64
0.0020
DAC OUTPUT VOLTAGE (V)
2.68
DAC OUTPUT VOLTAGE (V)
DAC OUTPUT VOLTAGE (V)
1.385
THREE TYPICAL PARTS
1.360
–25
0
25
–50
50
TEMPERATURE (°C)
2.69
0.0015
0.0010
0.0005
2.63
0.0030
0.0025
0.0020
0.0015
0.0010
0.0005
THREE TYPICAL PARTS
2.62
–50
–25
THREE TYPICAL PARTS
0
25
50
TEMPERATURE (°C)
75
0
–50
100
–25
0
25
50
TEMPERATURE (°C)
2974 G13
75
THREE TYPICAL PARTS
0
–25
0
25
–50
50
TEMPERATURE (°C)
100
2974 G15
VDD33 Regulator Output Voltage
vs Temperature
DAC-DNL
1.00
3.285
0.75
0.75
3.280
0.50
0.50
0
–0.25
0.25
0
–0.25
–0.50
–0.50
–0.75
–0.75
–1.00
–1.00
0
256
512
DAC CODE
768
1024
2974 G16
3.275
OUTPUT VOLTAGE (V)
ERROR (LSBs)
1.00
0.25
100
75
2974 G14
DAC-INL
ERROR (LSBs)
1.390
2974 G11
2974 G10
2.70
1.395
1.365
0
–50
100
GAIN SETTING = 0
3.270
3.265
3.260
3.255
3.250
3.245
0
256
512
DAC CODE
768
1024
2974 G17
THREE TYPICAL PARTS
3.240
–25
0
25
–50
50
TEMPERATURE (°C)
75
100
2974 G18
2974fc
For more information www.linear.com/LTC2974
11
LTC2974
Typical Performance Characteristics
0
VVOUT_ENn and VAUXFAULTB Output
VOH vs Current Sourcing
14.0
OUTPUT HIGH VOLTAGE (V)
OUTPUT VOLTAGE DELTA (ppm)
13.5
–1000
–2000
–3000
1.4
12.5
25°C
12.0
–40°C
1.0
11.5
11.0
10.5
0
10
20
30
40
LOAD CURRENT SOURCING (mA)
10.0
1
0
2
3
6
4
5
CURRENT SOURCING (µA)
7
2974 G19
1.6
1.4
1.4
1.2
1.2
1.0
1.0
VOL (V)
VOL (V)
1.6
0.8
0.6
0
0
2
8
6
10
4
CURRENT SINKING (mA)
12
2974 G21
ALERTB VOL vs Current Sinking
0.8
0
20
15
5
10
CURRENT SINKING (mA)
0
85°C
25°C
–40°C
0.2
0
15
5
10
CURRENT SINKING (mA)
2974 G22
External Temperature READ_
TEMPERATURE_1 Error vs
Temperature
2974 G23
READ_TEMPERATURE_2 Error vs
Temperature
1.00
MMBT3906 DIODE CONNECTED BJTS
MFR_TEMP_1_GAIN_ADJ = 0.987
MFR_EXT_TEMP_1_ADC_OFF = –2°C
VDD33 = VPWR = 3.3V
0.75
0.50
0.50
0.25
0.25
ERROR (%)
ERROR (%)
8
0.4
85°C
25°C
–40°C
0.2
0.75
–40°C
0.6
0.4
1.00
0.6
2974 G20
PWRGD and FAULTBn VOL vs
Current Sinking
0
25°C
0.2
9.0
50
85°C
0.8
0.4
9.5
–4000
VVOUT_ENn and VAUXFAULTB Output
VOL vs Current Sinking
1.2
85°C
13.0
VOL (V)
VDD33 Regulator Load Regulation
0
–0.25
–0.50
0
–0.25
–0.50
–0.75
–0.75
THREE TYPICAL PARTS
–1.00
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
THREE TYPICAL PARTS
–1.00
–25
0
25
–50
50
TEMPERATURE (°C)
2974 G24
75
100
2974 G25
2974fc
12
For more information www.linear.com/LTC2974
LTC2974
Pin Functions
PIN NAME
PIN NUMBER
PIN TYPE
DESCRIPTION
VSENSEP0
1*
In
DC/DC Converter Differential (+) Output Voltage-0 Sensing Pin
VSENSEM0
2*
In
DC/DC Converter Differential (–) Output Voltage-0 Sensing Pin
VOUT_EN0
3
Out
DC/DC Converter Enable-0 Pin. Output High Voltage Optionally Pulled-Up to 12V by 5µA
VOUT_EN1
4
Out
DC/DC Converter Enable-1 Pin. Output High Voltage Optionally Pulled-Up to 12V by 5µA
VOUT_EN2
5
Out
DC/DC Converter Enable-2 Pin. Output High Voltage Optionally Pulled-Up to 12V by 5µA
VOUT_EN3
6
Out
DC/DC Converter Enable-3 Pin. Output High Voltage Optionally Pulled-Up to 12V by 5µA
AUXFAULTB
7
Out
Auxillary Fault Output Pin. Output High Voltage Optionally Pulled-Up to 12V by 5µA. Can Be
Configured to Pull Low When OV/UV/OC/UC Detected
DNC
8
VIN_SNS
9
In
VIN SENSE Input. This Voltage is Compared Against the VIN On and Off Voltage Thresholds In Order to
Determine When to Enable and Disable, Respectively, the Downstream DC/DC Converters
VPWR
10
In
VPWR Serves as the Unregulated Power Supply Input to the Chip (4.5 to 15V). If a 4.5V to 15V Supply
Voltage Is Unavailable, Short VPWR to VDD33 and Power the Chip Directly from a 3.3V Supply. Bypass
to GND with 0.1µF Capacitor.
VDD33
11
In/Out
VDD33
12
In
VDD25
13
In/Out
Do Not Connect Do Not Connect to this Pin
If Shorted to VPWR, It Serves as 3.13 to 3.47V Supply Input Pin. Otherwise It Is a 3.3V Internally
Regulated Voltage Output (Use 0.1µF Decoupling Capacitor to GND)
Input for Internal 2.5V Sub-Regulator. Short this Pin to Pin 11
2.5V Internally Regulated Voltage Output. Bypass to GND with a 0.1µF Capacitor
VDD25
14
In
TSENSE0
15*
In/Out
External Temperature Current Output and Voltage Input for Channel 0. Maximum allowed capacitance
is 1µF
2.5V Supply Voltage Input. Short this Pin to Pin 13
TSENSE1
16*
In/Out
External Temperature Current Output and Voltage Input for Channel 1. Maximum allowed capacitance
is 1µF
PWRGD
17
Out
Power-Good Open Drain Output. Indicates When Selected Outputs Are Power Good. Can be Used as
System Power-on Reset
SHARE_CLK
18
In/Out
Bidirectional Clock Sharing Pin. Connect a 5.49kΩ Pull-Up Resistor to VDD33
GND
19
Ground
Chip Ground. Must Be Soldered to PCB
GND
20
Ground
Chip Ground. Must Be Soldered to PCB
GND
21
Ground
Chip Ground. Must Be Soldered to PCB
CONTROL2
22
In
Control Pin 2 Input
CONTROL3
23
In
Control Pin 3 Input
WDI/RESETB
24
In
Watchdog Timer Interrupt and Chip Reset Input. Connect a 10kΩ Pull-Up Resistor to VDD33. Rising
Edge Resets Watchdog Counter. Holding this Pin Low for More than tRESETB Resets the Chip
FAULTB0
25
In/Out
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-0. Connect a 10kΩ
Pull-Up Resistor to VDD33
FAULTB1
26
In/Out
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-1. Connect a 10kΩ
Pull-Up Resistor to VDD33
TSENSE2
27*
In/Out
External Temperature Current Output and Voltage Input for Channel 2. Maximum allowed capacitance
is 1µF
WP
28
In
SDA
29
In/Out
SCL
30
In
PMBus Serial Clock Input Pin (400kHz Maximum)
ALERTB
31
Out
Open-Drain Output. Generates an Interrupt Request in a Fault/Warning Situation
CONTROL0
32
In
Control Pin 0 Input
CONTROL1
33
In
Control Pin 1 Input
Digital Input. Write-Protect Input Pin, Active High
PMBus Bidirectional Serial Data Pin
2974fc
For more information www.linear.com/LTC2974
13
LTC2974
Pin Functions
PIN NAME
PIN NUMBER
PIN TYPE
DESCRIPTION
TSENSE3
34*
In/Out
ASEL0
35
In
Ternary Address Select Pin 0 Input. Connect to VDD33, GND or Float to Encode 1 of 3 Logic States
ASEL1
36
In
Ternary Address Select Pin 1 Input. Connect to VDD33, GND or Float to Encode 1 of 3 Logic States
GND
37
Ground
REFP
38
Out
GND
39
Ground
REFM
40
Out
Reference Return Pin. Needs 0.1µF Decoupling Capacitor to REFP
ISENSEP0
41*
In
DC/DC Converter Differential (+) Output Current-0 Sensing Pin
ISENSEM0
42*
In
DC/DC Converter Differential (–) Output Current-0 Sensing Pin
ISENSEP1
43*
In
DC/DC Converter Differential (+) Output Current-1 Sensing Pin
ISENSEM1
44*
In
DC/DC Converter Differential (–) Output Current-1 Sensing Pin
ISENSEP2
45*
In
DC/DC Converter Differential (+) Output Current-2 Sensing Pin
ISENSEM2
46*
In
DC/DC Converter Differential (–) Output Current-2 Sensing Pin
ISENSEP3
47*
In
DC/DC Converter Differential (+) Output Current-3 Sensing Pin
ISENSEM3
48*
In
DC/DC Converter Differential (–) Output Current-3 Sensing Pin
VSENSEP3
49*
In
DC/DC Converter Differential (+) Output Voltage-3 Sensing Pin
VSENSEM3
50*
In
DC/DC Converter Differential (–) Output Voltage-3 Sensing Pin
NC
51
No Connect
NC
52
No Connect
No Connect
VDAC0
53
Out
DAC0 Output
VDAC1
54
Out
DAC1 Output
NC
55
No Connect
No Connect
NC
56
No Connect
No Connect
VDAC2
57
Out
DAC2 Output
VDAC3
58
Out
DAC3 Output
NC
59
No Connect
No Connect
NC
60
No Connect
No Connect
VSENSEP2
61*
In
DC/DC Converter Differential (+) Output Voltage-2 Sensing Pin
VSENSEM2
62*
In
DC/DC Converter Differential (–) Output Voltage-2 Sensing Pin
VSENSEP1
63*
In
DC/DC Converter Differential (+) Output Voltage-1 Sensing Pin
VSENSEM1
64*
In
DC/DC Converter Differential (–) Output Voltage-1 Sensing Pin
External Temperature Current Output and Voltage Input for Channel 3. Maximum allowed capacitance
is 1µF
Chip Ground. Must Be Soldered to PCB
Reference Voltage Output. Needs 0.1µF Decoupling Capacitor to REFM
Chip Ground. Must Be Soldered to PCB
No Connect
GND
65
Ground
Exposed Pad. Must Be Soldered to PCB
*Any unused VSENSEPn /ISENSEPn , VSENSEMn /ISENSEMn or TSENSEn pins should be tied to GND.
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LTC2974
Block Diagram
3.3V REGULATOR
VOUT
VIN
VPWR 10
VDD33
VDD33(OUT) 11
2.5V REGULATOR
VIN
VDD33(IN) 12
VOUT
VDD25(OUT) 13
VDD25
3R
VIN_SNS 9
20Ω
VSENSEP0
VSENSEM0
R
ISENSEP0
DNC 8
1 VSENSEP0
ISENSEM0
2 VSENSEM0
VSENSEM1
41 ISENSEP0
ISENSEP1
42 ISENSEM0
ISENSEM1
63 VSENSEP1
VSENSEP2
MUX
ICMP
VSENSEM2
ISENSEP2
ISENSEM2
VSENSEP3
GND 19
VSENSEM3
GND 20
ISENSEP3
VCMP
–
+
+
–
INTERNAL
TEMP
SENSOR
VSENSEP1
–
+
+
–
VDD25(IN) 14
+
–
64 VSENSEM1
10-BIT
VDAC
43 ISENSEP1
44 ISENSEM1
61 VSENSEP2
+
–
62 VSENSEM2
10-BIT
VDAC
45 ISENSEP2
46 ISENSEM2
ISENSEM3
GND 21
49 VSENSEP3
50 VSENSEM3
+ 16-BIT
– ∆∑ ADC
GND 37
GND 39
GND 65
47 ISENSEP3
48 ISENSEM3
ADC
CLOCKS
VDD33
10-BIT
DAC
53 VDAC0
VBUF
54 VDAC1
57 VDAC2
REFERENCE
1.232V
(TYP)
REFP 38
58 VDAC3
REFM 40
51 NC
52 NC
ALERTB 31
SCL 30
SDA 29
ASEL0 35
PMBus
INTERFACE
(400kHz I2C
COMPATIBLE)
ASEL1 36
PAGE 0
PAGE 1
PAGE 2
PAGE 3
EEPROM
RAM
ADC_RESULTS
MONITOR LIMITS
SERVO TARGETS
OSCILLATOR
PWRGD 17
SHARE_CLK 18
WDI/RESETB 24
4 PAGES
FAULTB0 25
FAULTB1 26
CONTROL0 32
CONTROLLER
PMBus ALGORITHM
FAULT PROCESSOR
WATCHDOG
SEQUENCER
56 NC
59 NC
60 NC
3 VOUT_EN0
WP 28
4 PAGES
55 NC
CLOCK
GENERATION
MASKING
5 VOUT_EN2
6 VOUT_EN3
VDD
PORB
4 VOUT_EN1
7 AUXFAULTB
UVLO
15 TSENSE0
EXTERNAL
TEMPERATURE
SENSOR
CONTROL1 33
CONTROL2 22
16 TSENSE1
27 TSENSE2
34 TSENSE3
CONTROL3 23
2974 BD
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15
LTC2974
Operation
LTC2974 Operation Overview
The LTC2974 is a PMBus programmable power supply
controller, monitor, sequencer and voltage and current
supervisor that can perform the following operations:
• Accept PMBus compatible programming commands.
• Provide DC/DC converter input voltage, output voltage,
output current, output temperature, and internal junction
temperature readback through the PMBus interface.
• Optionally stop trimming the DC/DC converter output
voltage after it reaches the initial margin or nominal
target. Optionally allow servo to resume if target drifts
outside of VOUT warning limits.
• Store command register contents with CRC to EEPROM
through PMBus programming.
• Restore EEPROM contents through PMBus programming or when VDD33 is applied on power-up.
• Control the output of DC/DC converters that set the
output voltage with a trim pin or DC/DC converters
that set the output voltage using an external resistor
feedback network.
• Report the DC/DC converter output voltage status
through the power good output.
• Sequence the startup of DC/DC converters via PMBus
programming and the CONTROL input pins. The LTC
2974 supports time-based sequencing and tracking
sequencing. Cascade sequence on with time based
sequence off is also supported.
• Coordinate system wide fault responses for all DC/DC
converters connected to the LTC2974 FAULTB0 and
FAULTB1 pins.
• Trim the DC/DC converter output voltage (typically in
0.02% steps), in closed-loop servo operating mode,
autonomously or through PMBus programming.
• Margin the DC/DC converter output voltage to PMBus
programmed limits.
• Trim or margin the DC/DC converter output voltage with
direct access to the margin DAC.
• Supervise the DC/DC converter input voltage, output
voltage, load current and the inductor temperatures
for overvalue/undervalue conditions with respect to
PMBus programmed limits and generate appropriate
faults and warnings.
• Accurately handle inductor self-heating transients using
a proprietary algorithm. These self-heating effects are
combined with external temperature sensor readings
to improve accuracy of current supervisors and ADC
current measurement.
• Respond to a fault condition by continuing operation
indefinitely, latching-off after a programmable deglitch
period, latching-off immediately or sequencing off
after TOFF_DELAY. Use retry mode to automatically
recover from a latched-off condition. With retry enabled,
MFR_RETRY_COUNT programs the number of retries
(0 to 6 or infinite) for all pages.
• Generate interrupt requests by asserting the ALERTB pin
in response to supported PMBus faults and warnings.
• Synchronize sequencing delays or shutdown for multiple
devices using the SHARE_CLK pin.
• Software and hardware write protect the command
registers.
• Disable the input voltage to the supervised DC/DC
converters in response to output OV, UV, OC and UC
faults.
• Log telemetry and status data to EEPROM in response
to a faulted-off condition.
• Supervise an external microcontroller’s activity for a
stalled condition with a programmable watchdog timer
and reset it if necessary.
• Prevent a DC/DC converter from re-entering the on
state after a power cycle until a programmable interval
(MFR_RESTART_DELAY) has elapsed and its output
has decayed below a programmable threshold voltage
(MFR_VOUT_DISCHARGE_THRESHOLD).
• Record minimum and maximum observed values of
input voltage, output voltages, output currents and
output temperatures.
• Access user EEPROM data directly, without altering RAM space (Mfr_ee_unlock, Mfr_ee_erase, and
Mfr_ee_data). Facilitates in-house bulk programming.
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LTC2974
Operation
EEPROM
The LTC2974 contains internal EEPROM (Non-Volatile
Memory) to store configuration settings and fault log
information. EEPROM endurance, retention and mass
write operation time are specified over the operating temperature range. See Electrical Characteristics and Absolute
Maximum Ratings sections.
Non destructive operation above TJ = 85°C is possible
although the Electrical Characteristics are not guaranteed
and the EEPROM will be degraded.
Operating the EEPROM above 85°C may result in a degradation of retention characteristics. The fault logging
function, which is useful in debugging system problems
that may occur at high temperatures, only writes to fault
log EEPROM locations. If occasional writes to these registers occur above 85°C, a slight degradation in the data
retention characteristics of the fault log may occur.
It is recommended that the EEPROM not be written using
STORE_USER_ALL or bulk programming when TJ > 85°C.
The degradation in EEPROM retention for temperatures
>85°C can be approximated by calculating the dimensionless acceleration factor using the following equation.
Ea
1
1
–
•
k TUSE +273 TSTRESS +273
AF = e
So the overall rentention of the EEPROM was degraded by
34 hours as a result of operation at a junction temperature
of 95°C for 10 hours. Note that the effect of this overstress
is negligible when compared to the overall EEPROM
rentention rating of 87,600 hours at a maximum junction
temperature of 85°C.
AUXFAULTB
The AUXFAULTB pin can be commanded to one of two
output levels at any time via the PMBUS. If desired, the
AUXFAULTB pin can also be configured to indicate when
some fault conditions have been detected, using a third
output level. See Figure 1 for a conceptual view of this
multiplexing.
PMBUS
COMMAND
HI-Z
WEAK 12V PULL-UP
OV/UV/OC/UC
(MASKABLE)
AUXFAULTB
FAST
PULL-DOWN
SET
RESET
Q
fault_seen
2974 F01
OFF_THEN_ON
OR
FAULT_RETRY
FOR ANY CHANNEL
Figure 1: AUXFAULTB MUX
Where:
AF = acceleration factor
Ea = activation energy = 1.4eV
k = 8.625 • 10–5eV/°K
TUSE = 85°C specified junction temperature
TSTRESS = actual junction temperature °C
Example: Calculate the effect on retention when operating
at a junction temperature of 95°C for 10 hours.
TSTRESS = 95°C
The MFR_CONFIG2_LTC2974 and MFR_CONFIG3_
LTC2974 commands can be used on a per channel basis
to select which, if any, fault conditions will cause the
AUXFAULTB pin to be driven to its third output level (fast
pull-down to GND). The only fault types which can be
propagated to the AUXFAULTB pin are over/under voltage
faults and over/under current faults.
Mfr_config_all_auxfaultb_wpu selects whether the
AUXFAULTB pin is in the hi-Z state, or weakly pulled-up
to approximately 12V, using a 5µA current. As shown in
Figure 1, the pulldown to GND overrides if any enabled
faults are detected.
TUSE = 85°C
AF = 3.4
Equivalent operating time at 85°C = 34 hours.
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LTC2974
Operation
RESETB
Holding the WDI/RESETB pin low for more than tRESETB
will cause the LTC2974 to enter the power-on reset state.
While in the power-on reset state, the device will not
communicate on the I2C bus. Following the subsequent
rising-edge of the WDI/RESETB pin, the LTC2974 will
execute its power-on sequence per the user configuration
stored in EEPROM. Connect WDI/RESETB to VDD33 with
a 10k resistor. WDI/RESETB includes an internal 256μs
deglitch filter so additional filter capacitance on this pin
is not recommended.
PMBus Serial Digital Interface
The LTC2974 communicates with a host (master) using the
standard PMBus serial bus interface. The PMBus Timing
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
The LTC2974 is a slave device. The master can communicate
with the LTC2974 using the following formats:
• Master transmitter, slave receiver
• Master receiver, slave transmitter
The following SMBus commands are supported:
• Write Byte, Write Word, Send Byte
The PMBus two wire interface is an incremental extension
of the SMBus. SMBus is built upon I2C with some minor
differences in timing, DC parameters and protocol. The
SMBus protocols are more robust than simple I2C byte
commands because they provide timeouts to prevent
bus hangs and optional Packet Error Checking (PEC) to
ensure data integrity. In general, a master device that
can be configured for I2C communication can be used
for PMBus communication with little or no change to
hardware or firmware.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification Part
1 Revision 1.1: Section 5: Transport. This can be found at:
www.pmbus.org
For a description of the differences between SMBus and I2C,
refer to System Management Bus (SMBus) Specification
Version 2.0: Appendix B – Differences between SMBus
and I2C. This can be found at:
www.smbus.org
When using an I2C controller to communicate with a PMBus
part it is important that the controller be able to write a
byte of data without generating a stop. This will allow the
controller to properly form the repeated start of a PMBus
read command by concatenating a start command byte
write with an I2C read.
Device Address
• Read Byte, Read Word, Block Read
• Alert Response Address
Figures 1 to 12 illustrate the aforementioned SMBus protocols. All transactions support PEC (parity error check) and
GCP (group command protocol). The Block Read supports
255 bytes of returned data. For this reason, the SMBus
timeout may be extended using the Mfr_config_all_longer_pmbus_timeout setting.
PMBus
PMBus is an industry standard that defines a means
of communication with power conversion devices. It is
comprised of an industry standard SMBus serial interface
and the PMBus command language.
The I2C/SMBus address of the LTC2974 equals the base
address + N where N is a number from 0 to 8. N can be
configured by setting the ASEL0 and ASEL1 pins to VDD33,
GND or FLOAT. See Table 1. Using one base address and
the nine values of N, nine LTC2974s can be connected
together to control thirty six outputs. The base address is
stored in the MFR_I2C_BASE_ADDRESS register. The base
address can be written to any value, but generally should
not be changed unless the desired range of addresses
overlap existing addresses. Watch that the address range
does not overlap with other I2C/SMBus device or global
addresses, including I2C/SMBus multiplexers and bus
buffers. This will bring you great happiness.
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LTC2974
Operation
The LTC2974 always responds to its global address and the
SMBus Alert Response address regardless of the state of
its ASEL pins and the MFR_I2C_BASE_ADDRESS register.
Processing Commands
The LTC2974 uses a dedicated processing block to ensure
quick response to all of its commands. There are a few
exceptions where the part will NACK a subsequent command because it is still processing the previous command.
These are summarized in the following tables. MFR_COMMON is a special command that may always be read even
when the part is busy. This provides an alternate method
for a host to determine if the LTC2974 is busy.
EEPROM Related Commands
COMMAND
TYPICAL DELAY* COMMENT
tMASS_WRITE
See Electrical Characterization table. The LTC2974 will not accept any commands while it is transferring
register contents to the EEPROM. The command byte will be NACKed. MFR_COMMON may always be
read.
RESTORE_USER_ALL
30ms
The LTC2974 will not accept any commands while it is transferring EEPROM data to command registers.
The command byte will be NACKed. MFR_COMMON may always be read.
MFR_FAULT_LOG_CLEAR
175ms
The LTC2974 will not accept any commands while it is initializing the fault log EEPROM space. The
command byte will be NACKed. MFR_COMMON may always be read.
MFR_FAULT_LOG_STORE
20ms
The LTC2974 will not accept any commands while it is transferring fault log RAM buffer to EEPROM
space. The command byte will be NACKed. MFR_COMMON may always be read.
Internal Fault log
20ms
An internal fault log event is a one time event that uploads the contents of the fault log to EEPROM in
response to a fault. Internal fault logging may be disabled. Commands received during this EEPROM
write are NACKed. MFR_COMMON may always be read.
MFR_FAULT_LOG_RESTORE
2ms
The LTC2974 will not accept any commands while it is transferring EEPROM data to the fault log RAM
buffer. The command byte will be NACKed. MFR_COMMON may always be read.
STORE_USER_ALL
*The typical delay is measured from the command’s stop to the next command’s start.
Other Commands
COMMAND
DELAY*
COMMENT
MFR_CONFIG
time for master supply to fall.
The system response to a control pin toggle is illustrated in Figure 18.
The system response to a UV fault on a slave channel is illustrated in Figure 19.
MFR_CONFIG_ALL_LTC2974
This command is used to configure parameters that are common to all channels on the IC. They may be set or reviewed
from any PAGE setting.
MFR_CONFIG_ALL_LTC2974 Data Contents
BIT(S)
SYMBOL
b[15:12] Reserved
b[11]
Mfr_config_all_pwrgd_off_uses_uv
OPERATION
Don’t care. Always returns 0.
Selects PWRGD de-assertion source for all channels.
0: PWRGD is de-asserted based on VOUT being below or equal to POWER_GOOD_OFF. This option
uses the ADC. Response time is approximately 100ms to 200ms.
1: PWRGD is de-asserted based on VOUT being below or equal to VOUT_UV_LIMIT. This option uses
the high speed supervisor. Response time is approximately 12µs.
b[10]
Mfr_config_all_fast_fault_log
Controls number of ADC readings completed before transferring fault log memory to EEPROM.
0: All ADC telemetry values will be updated before transferring fault log to EEPROM. Slower.
1: Telemetry values will be transferred from fault log to EEPROM within 24ms after detecting fault.
Faster.
b[9]
Mfr_config_all_control3_pol
Selects active polarity of CONTROL3 pin
0: Active low (pull pin low to start unit).
1: Active high (pull pin high to start unit).
b[8]
Mfr_config_all_control2_pol
Selects active polarity of CONTROL2 pin
0: Active low (pull pin low to start unit).
1: Active high (pull pin high to start unit).
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LTC2974
PMBus Command Description
MFR_CONFIG_ALL_LTC2974 Data Contents
BIT(S)
b[7]
SYMBOL
OPERATION
Mfr_config_all_fault_log_enable
Enable fault logging to EEPROM in response to Fault.
0: Fault logging to EEPROM is disabled.
1: Fault logging to EEPROM is enabled.
b[6]
Mfr_config_all_vin_on_clr_faults_en
Allow VIN rising above VIN_ON to clear all latched faults.
0: VIN_ON clear faults feature is disabled.
1: VIN_ON clear faults feature is enabled.
b[5]
Mfr_config_all_control1_pol
Selects active polarity of CONTROL1 pin
0: Active low (pull pin low to start unit).
1: Active high (pull pin high to start unit).
b[4]
Mfr_config_all_control0_pol
Selects active polarity of CONTROL0 pin
0: Active low (pull pin low to start unit).
1: Active high (pull pin high to start unit).
b[3]
Mfr_config_all_vin_share_enable
Allow this unit to hold SHARE_CLK pin low when VIN has not risen above VIN_ON or has fallen
below VIN_OFF. When enabled this unit will also turn all channels off in response to Share-clock
being held low.
0: SHARE_CLK inhibit is disabled.
1: SHARE_CLK inhibit is enabled.
b[2]
Mfr_config_all_pec_en
PMBus packet error checking enable.
0: PEC is accepted but not required.
1: PEC is enabled.
b[1]
Mfr_config_all_longer_pmbus_timeout Increase PMBus timeout interval by a factor of 8. Recommended for fault logging.
0: PMBus timeout is multiplied by a factor of 8.
1: PMBus timeout is not multiplied by a factor of 8.
b[0]
Mfr_config_all_auxfaultb_wpu_dis
AUXFAULTB charge-pumped, current-limited pull-up disable.
0: Use weak current-limited pull-up on AUXFAULTB after power-up, as long as no faults have forced
AUXFAULTB off.
1: Disable weak pull-up. AUXFAULTB driver is tri-stated after power-up as long as no faults have
forced AUXFAULTB off.
Programming User EEPROM Space
COMMAND NAME
CMD
CODE
STORE_USER_ALL
0x15
Store entire operating memory to
EEPROM.
Send Byte
N
NA
41
RESTORE_USER_ALL
0x16
Restore entire operating memory from
EEPROM.
Send Byte
N
NA
41
MFR_EE_UNLOCK
0xBD
Unlock user EEPROM for access by
MFR_EE_ERASE and MFR_EE_DATA
commands.
R/W Byte
N
Reg
NA
41
MFR_EE_ERASE
0xBE
Initialize user EEPROM for bulk
programming by MFR_EE_DATA.
R/W Byte
N
Reg
NA
42
MFR_EE_DATA
0xBF
Data transferred to and from EEPROM
using sequential PMBus word reads or
writes. Supports bulk programming.
R/W Word
N
Reg
NA
42
DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
DEFAULT REF
VALUE PAGE
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LTC2974
PMBus Command Description
STORE_USER_ALL and RESTORE_USER_ALL
STORE_USER_ALL, RESTORE_USER_ALL commands provide access to User EEPROM space. Once a command is
stored in User EEPROM, it will be restored with explicit restore command or when the part emerges from power-on
reset after power is applied. While either of these commands is being processed, the part will indicate it is busy, see
Response When Part Is Busy on page 43.
STORE_USER_ALL. Issuing this command will store all operating memory commands with a corresponding EEPROM
memory location.
RESTORE_USER_ALL. Issuing this command will restore all commands from EEPROM Memory. It is recommended
that this command not be executed while a unit is enabled since all monitoring is suspended while the EEPROM is
transferred to operating memory, and intermediate values from EEPROM may not be compatible with the values initially
stored in operating memory.
Bulk Programming the User EEPROM Space
The MFR_EE_UNLOCK, MFR_EE_ERASE and MFR_EE_DATA commands provide a method for 3rd party EEPROM
programming houses and end users to easily program the LTC2974 independent of any order dependencies or delays
between PMBus commands. All data transfers are directly to and from the EEPROM and do not affect the volatile RAM
space currently configuring the device.
The first step is to program a master reference part with the desired configuration. MFR_EE_UNLOCK and MFR_EE_DATA
are then used to read back all the data in User EEPROM space as sequential words. This information is stored to the
master programming HEX file. Subsequent parts may be cloned to match the master part using MFR_EE_UNLOCK,
MFR_EE_ERASE and MFR_EE_DATA to transfer data from the master HEX file. These commands operate directly on
the EEPROM independent of the part configurations stored in RAM space. During EEPROM access the part will indicate
that it is busy as described below.
In order to support simple programming fixtures the bulk programming features only uses PMBus word and byte commands. The MFR_UNLOCK configures the appropriate access mode and resets an internal address pointer allowing
a series of word commands to behave as a block read or write with the address pointer being incremented after each
operation. PEC use is optional and is configured by the MFR_EE_UNLOCK operation.
MFR_EE_UNLOCK
The MFR_EE_UNLOCK command prevents accidental EEPROM access in normal operation and configures the required
EEPROM bulk programming mode for bulk initialization, sequential writes, or reads. MFR_EE_UNLOCK augments the
protection provided by write protect. Upon unlocking the part for the required operation, an internal address pointer is
reset allowing a series of MFR_EE_DATA reads or writes to sequentially transfer data, similar to a block read or block
write. The MFR_EE_UNLOCK command can clear or set PEC mode based on the desired level of error protection. An
MFR_EE_UNLOCK sequence consists of writing two unlock codes using two byte-write commands. The following
table documents the allowed sequences. Writing a non-supported sequence locks the part. Reading MFR_EE_UNLOCK
returns the last byte written or zero if the part is locked.
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LTC2974
PMBus Command Description
MFR_EE_UNLOCK Data Contents
BIT(S) SYMBOL
OPERATION
b[7:0] Mfr_ee_unlock[7:0] To unlock user EEPROM space for Mfr_ee_erase and Mfr_ee_data read or write operations with PEC allowed:
Write 0x2b followed by 0xd4.
To unlock user EEPROM space for Mfr_ee_erase and Mfr_ee_data read or write operations with PEC required:
Write 0x2b followed by 0xd5.
To unlock user and manufacturer EEPROM space for Mfr_ee_data read only operations with PEC allowed:
Write 0x2b, followed by 0x91 followed by 0xe4.
To unlock user and manufacturer EEPROM space for Mfr_ee_data read only operations with PEC required:
Write 0x2b, followed by 0x91 followed by 0xe5.
MFR_EE_ERASE
The MFR_EE_ERASE command is used to erase the entire contents of the user EEPROM space and configures this
space to accept new program data. Writing values other than 0x2B will lock the part. Reads return the last value written.
MFR_EE_ERASE Data contents
BIT(S) SYMBOL
OPERATION
b[7:0] Mfr_ee_erase[7:0] To erase the user EEPROM space and configure to accept new data:
1) Use the appropriate Mfr_ee_unlock sequence to configure for Mfr_ee_erase commands with or without PEC.
2) Write 0x2B to Mfr_ee_erase.
The part will indicate it is busy erasing the EEPROM by the mechanism detailed below.
MFR_EE_DATA
The MFR_EE_DATA command allows the user to transfer data directly to or from the EEPROM without affecting RAM
space.
To read the user EEPROM space issue the appropriate Mfr_ee_unlock command and perform Mfr_ee_data reads until
the EEPROM has been completely read. Extra reads will lock the part and return zero. The first read returns the 16-bit
EEPROM packing revision ID that is stored in ROM. The second read returns the number of 16-bit words available;
this is the number of reads or writes to access all memory locations. Subsequent reads return EEPROM data starting
with lowest address.
To write to the user EEPROM space issue the appropriate Mfr_ee_unlock and Mfr_ee_erase commands followed by
successive Mfr_ee_data word writes until the EEPROM is full. Extra writes will lock the part. The first write is to the
lowest address.
Mfr_ee_data reads and writes must not be mixed.
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LTC2974
PMBus Command Description
MFR_EE_DATA Data Contents
BIT(S) SYMBOL
OPERATION
b[7:0] Mfr_ee_data[7:0] To read user space
1) Use the appropriate Mfr_ee_unlock sequence to configure for Mfr_ee_data commands with or without PEC.
2) Read Mfr_ee_data[0] = PackingId (MFR Specific ID).
3) Read Mfr_ee_data[1] = NumberOfUserWords (total number of 16-bit word available).
4) Read Mfr_ee_data[2] through Mfr_ee_data[NumberOfWord+1] (User EEPROM data contents)
To write user space
1) Initialize the user memory using the sequence described for the MFR_EE_ERASE command.
2) Use the appropriate Mfr_ee_unlock sequence to configure for Mfr_ee_data commands with or without PEC.
3) Write Mfr_ee_data[0] through Mfr_ee_data[NumberOfWord-1] (User EEPROM data content to be wriiten)
The part will indicate it is busy erasing the EEPROM by the mechanism detailed below.
Response When Part Is Busy
The part will indicate it is busy accessing the EEPROM by the following mechanism:
1) Clearing Mfr_common_busyb of the MFR_COMMON register. This byte can always be read and will never NACK a
byte read request even if the part is busy.
2) NACKing commands other than MFR_COMMON.
MFR_EE Erase and Write Programming Time
The program time per word is typically 0.17ms and will require spacing the I2C/SMBus writes at greater than 0.17ms
to guarantee the write has completed. The Mfr_ee_erase command takes approximately 400ms. We recommend using
MFR_COMMON for handshaking.
Input Voltage Commands and Limits
COMMAND NAME
CMD
CODE
VIN_ON
0x35
Input voltage (VIN_SNS) above which power
conversion can be enabled.
R/W Word
N
L11
V
Y
10.0
0xD280
43
VIN_OFF
0x36
Input voltage (VIN_SNS) below which power
conversion is disabled. All VOUT_EN pins go
off immediately or sequence off after TOFF_
DELAY (See Mfr_config_track_enn).
R/W Word
N
L11
V
Y
9.0
0xD240
43
VIN_OV_FAULT_LIMIT
0x55
Input overvoltage fault limit measured at
VIN_SNS pin.
R/W Word
N
L11
V
Y
15.0
0xD3C0
43
VIN_OV_WARN_LIMIT
0x57
Input overvoltage warning limit measured at
VIN_SNS pin.
R/W Word
N
L11
V
Y
14.0
0xD380
43
VIN_UV_WARN_LIMIT
0x58
Input undervoltage warning limit measured at
VIN_SNS pin.
R/W Word
N
L11
V
Y
0
0x8000
43
VIN_UV_FAULT_LIMIT
0x59
Input undervoltage fault limit measured at
VIN_SNS pin.
R/W Word
N
L11
V
Y
0
0x8000
43
DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
DEFAULT REF
VALUE PAGE
VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_OV_WARN_LIMIT, VIN_UV_WARN_LIMIT and
VIN_UV_FAULT_LIMIT
These commands provide voltage supervising limits for the input voltage VIN_SNS.
For more information www.linear.com/LTC2974
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LTC2974
PMBus Command Description
Output Voltage Commands and Limits
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
VOUT_MODE
0x20 Output voltage data format and mantissa
exponent (2–13).
R Byte
Y
Reg
VOUT_COMMAND
0x21 Servo target. Nominal DC/DC converter
output voltage setpoint.
R/W Word
Y
L16
V
VOUT_MAX
0x24 Upper limit on the output voltage the unit
can command regardless of any other
commands.
R/W Word
Y
L16
VOUT_MARGIN_HIGH
0x25 Margin high DC/DC converter output voltage R/W Word
setting.
Y
VOUT_MARGIN_LOW
0x26 Margin low DC/DC converter output voltage
setting.
R/W Word
VOUT_OV_FAULT_LIMIT
0x40 Output overvoltage fault limit.
VOUT_OV_WARN_LIMIT
DEFAULT REF
VALUE PAGE
0x13
44
Y
1.0
0x2000
45
V
Y
4.0
0x8000
45
L16
V
Y
1.05
0x219A
45
Y
L16
V
Y
0.95
0x1E66
45
R/W Word
Y
L16
V
Y
1.1
0x2333
45
0x42 Output overvoltage warning limit.
R/W Word
Y
L16
V
Y
1.075
0x2266
45
VOUT_UV_WARN_LIMIT
0x43 Output undervoltage warning limit.
R/W Word
Y
L16
V
Y
0.925
0x1D9A
45
VOUT_UV_FAULT_LIMIT
0x44 Output undervoltage fault limit. Used for
Ton_max_fault and power good deassertion.
R/W Word
Y
L16
V
Y
0.9
0x1CCD
45
POWER_GOOD_ON
0x5E Output voltage at or above which a power
good should be asserted.
R/W Word
Y
L16
V
Y
0.96
0x1EB8
45
POWER_GOOD_OFF
0x5F
Output voltage at or below which a power
good should be de-asserted when Mfr_
config_all_pwrgd_off_uses_uv is clear.
R/W Word
Y
L16
V
Y
0.94
0x1E14
45
MFR_VOUT_DISCHARGE_
THRESHOLD
0xE9 Coefficient used to multiply VOUT_
COMMAND in order to determine VOUT off
threshold voltage.
R/W Word
Y
L11
Y
2.0
0xC200
45
MFR_DAC
0xE0 Manufacturer register that contains the code R/W Word
of the 10-bit DAC.
Y
Reg
N
0x0000
45
VOUT_MODE
This command is read only and specifies the mode and exponent for all commands with a L16 data format. See
Data Formats on page 27.
VOUT_MODE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:5] Vout_mode_type
Reports linear mode. Hard-wired to 000b.
b[4:0] Vout_mode_parameter Linear mode exponent. 5-bit two’s complement integer. Hardwired to 0x13 (–13 decimal).
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LTC2974
PMBus Command Description
VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_LIMIT,
VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT, VOUT_UV_FAULT_LIMIT, POWER_GOOD_ON and
POWER_GOOD_OFF
These commands provide various servo, margining and supervising limits for a channel’s output voltage.
MFR_VOUT_DISCHARGE_THRESHOLD
This register contains the coefficient that multiplies VOUT_COMMAND in order to determine the OFF threshold voltage for the associated output. If the output voltage has not decayed below MFR_VOUT_DISCHARGE_THRESHOLD •
VOUT_COMMAND prior to the channel being commanded to enter/re-enter the ON state, the Status_mfr_discharge bit
in the STATUS_MFR_SPECIFIC register will be set and the ALERTB pin will be asserted low. In addition, the channel
will not enter the ON state until the output has decayed below its off-threshold voltage. Setting this to a value greater
than 1.0 effectively disables DISCHARGE_THRESHOLD checking, allowing the channel to turn back on even if it has
not decayed at all.
Other channels can be held-off if a particular output has failed to discharge by using the bidirectional FAULTBn pins
(refer to the MFR_FAULTBn_RESPONSE and MFR_FAULTBn_PROPOGATE registers).
MFR_DAC
This command register allows the user to directly program the 10-bit DAC. Manual DAC writes require the channel
to be in the ON state,TON_RISE to have expired and MFR_CONFIG_LTC2974 b[5:4] = 10b or 11b. Writing MFR_
CONFIG_LTC2974 b[5:4] = 10b commands the DAC to hard connect with the value in Mfr_dac_direct_val. Writing
b[5:4] = 11b commands the DAC to soft-connect. Once the DAC has soft-connected, Mfr_dac_direct_val returns the
value that allowed the DAC to be connected without perturbing the power supply. MFR_DAC writes are ignored when
MFR_CONFIG_LTC2974 b[5:4] = 00b or 01b.
MFR_DAC Data Contents
BIT(S)
SYMBOL
b[15:10] Reserved
b[9:0]
OPERATION
Read only, always returns 0.
Mfr_dac_direct_val DAC code value.
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45
LTC2974
PMBus Command Description
Output Current Commands and Limits
CMD
CODE DESCRIPTION
COMMAND NAME
TYPE
PAGED FORMAT UNITS EEPROM
DEFAULT REF
VALUE PAGE
IOUT_CAL_GAIN
0x38 The nominal resistance of the current sense
element in mΩ.
R/W Word
Y
L11
mΩ
Y
1.0
0xBA00
46
IOUT_OC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
R/W Word
Y
L11
A
Y
10.0
0xD280
47
IOUT_OC_WARN_LIMIT
0x4A Output overcurrent warning limit.
R/W Word
Y
L11
A
Y
5.0
0xCA80
47
IOUT_UC_FAULT_LIMIT
0x4B Output undercurrent fault limit. Used to
detect a reverse current and must be a
negative value.
R/W Word
Y
L11
A
Y
-1.0
0xBE00
47
MFR_IOUT_CAL_GAIN_TC
0xF6
R/W Word
Y
CF
ppm
Y
0x0
47
Temperature coefficient applied to IOUT_
CAL_GAIN.
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the ratio of the voltage at the current sense pins to the sensed current.
For devices using a fixed current sense resistor, it is the same value as the resistance of the resistor (units are expressed
in mΩ). IOUT_CAL_GAIN is internally limited to values between 0.01mΩ to 1,000mΩ. The register readback value
always returns what was last written and does not reflect internal limiting.
Calculations using IOUT_CAL_GAIN are:
VIOUT_OC_FAULT_LIMIT = IOUT_OC_FAULT_LIMIT • IOUT_CAL_GAIN • TCORRECTION
VIOUT_UC_FAULT_LIMIT = IOUT_UC_FAULT_LIMIT • IOUT_CAL_GAIN • TCORRECTION
Where:
TCORRECTION = (1 + MFR_IOUT_CAL_GAIN_TC • 1E-6 • (READ_TEMPERATURE_1 + MFR_T_SELF_HEAT – 25.0))
READ_IOUT =
VIOUT _ SNSPn – VIOUT _ SNSMn
(IOUT _CAL _GAIN)• TCORRECTION
Note:
TCORRECTION is limited by hardware to a value between 0.25 and 4.0.
READ_TEMPERATURE_2 is substituted for READ_TEMPERATURE_1 if the associated TSENSE network fails to detect
a valid temperature. See READ_TEMPERATURE_1 for more information.
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LTC2974
PMBus Command Description
IOUT_OC_FAULT_LIMIT, IOUT_OC_WARN_LIMIT and IOUT_UC_FAULT_LIMIT
IOUT supervisor fault and warning limits.
IOUT_OC_FAULT_LIMITED is internally limited to values greater or equal to zero. The register readback value always
returns what was last written and does not reflect internal limiting.
IOUT_UC_FAULT_LIMITED is internally limited to values less than zero. The register readback value always returns
what was last written and does not reflect internal limiting.
MFR_IOUT_CAL_GAIN_TC
The MFR_IOUT_CAL_GAIN_TC is a paged command that sets the temperature coefficient of the IOUT_CAL_GAIN
register value in ppm/°C. This command uses the temperature measured by the external temperature diode for the
associated page.
Refer to IOUT_CAL_GAIN for details on proper usage.
MFR_IOUT_CAL_GAIN_TC Data Contents
BIT(S) SYMBOL
b[15:0] Mfr_iout_cal_gain_tc
OPERATION
16-bit twos complement integer representing the temperature coefficient.
Value = Y where Y = b[15:0] is a twos complement.
Example:
Mfr_iout_cal_gain_tc = 3900ppm
For b[15:0] = 0x0F3C
Value = 3900
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47
LTC2974
PMBus Command Description
External Temperature Commands And Limits
COMMAND NAME
CMD
CODE DESCRIPTION
OT_FAULT_LIMIT
0x4F
Overtemperature fault limit setting for
the external temperature sensor.
R/W Word
Y
L11
°C
Y
65.0
0xEA08
48
OT_WARN_LIMIT
0x51 Overtemperature warning limit for the
external temperature sensor
R/W Word
Y
L11
°C
Y
60.0
0xE3C0
48
UT_WARN_LIMIT
0x52 Undertemperature warning limit for
the external temperature sensor.
R/W Word
Y
L11
°C
Y
0
0x8000
48
UT_FAULT_LIMIT
0x53 Undertemperature fault limit for the
external temperature sensor.
R/W Word
Y
L11
°C
Y
–5.0
0xCD80
48
MFR_TEMP_1_GAIN
0xF8
Inverse of external diode temperature
non ideality factor. One LSB = 2–14.
R/W Word
Y
CF
Y
1
0x4000
48
MFR_TEMP_1_OFFSET
0xF9
Offset value for the external
temperature.
R/W Word
Y
L11
°C
Y
0
0x8000
48
MFR_T_SELF_HEAT
0xB8 Calculated temperature rise due to
self-heating of output current sense
device above value measured by
external temperature sensor.
R Word
Y
L11
°C
NA
49
MFR_IOUT_CAL_GAIN_TAU_INV
0xB9 Inverse of time constant for Mfr_t_
self_heat changes scaled by 4 •
tCONV_SENSE.
R/W Word
Y
L11
Y
0.0
0x8000
49
MFR_IOUT_CAL_GAIN_THETA
0xBA Thermal resistance from inductor
core to point measured by external
temperature sensor.
R/W Word
Y
L11
Y
0.0
0x8000
49
TYPE
PAGED FORMAT UNITS EEPROM
°C/W
DEFAULT REF
VALUE PAGE
OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_LIMIT and UT_FAULT_LIMIT
These commands provide supervising limits for temperature as measured by the external diode.
MFR_TEMP_1_GAIN and MFR_TEMP_1_OFFSET
The MFR_TEMP_1_GAIN command specifies the inverse of the temperature sensor ideality factor. The MFR_TEMP_1_
OFFSET allows an offset to be applied to the measured temperature.
Calculations using these paged commands are:
READ_TEMPERATURE_1 = TEXT • MFR_TEMP_1_GAIN – 273.15 + MFR_TEMP_1_OFFSET
Where:
TEXT = Measured external temperature in degrees Kelvin.
READ_TEMPERATURE_2 is substituted for READ_TEMPERATURE_1 if the associated TSENSE network fails to detect
a valid temperature. Under these conditions MFR_TEMP1_GAIN and MFR_TEMP1_OFFSET will have no effect. See
READ_TEMPERATURE_1 for more information.
MFR_TEMP_1_GAIN Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_temp_1_gain[15:0]
16-bit integer representing inverse of temperature non-ideality factor. Value = Y • 214 where Y = b[15:0] is an
unsigned integer. Example:
MFR_TEMP_1_GAIN = 1.0
For b[15:0] = 0x4000
Value = 16384 • 2–14 = 1.0
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LTC2974
PMBus Command Description
MFR_T_SELF_HEAT, MFR_IOUT_CAL_GAIN_TAU_INV and MFR_IOUT_CAL_GAIN_THETA
The LTC2974 uses an innovative (patent pending) algorithm to dynamically model the temperature rise from the external
temperature sensor to the inductor core. This temperature rise is called MFR_T_SELF_HEAT and is used to calculate the
final temperature correction required by IOUT_CAL_GAIN. The temperature rise is a function of the power dissipated
in the inductor DCR, the thermal resistance from the inductor core to the remote temperature sensor and the thermal
time constant of the inductor to board system. The algorithm simplifies the placement requirements for the external
temperature sensor and compensates for the significant steady state and transient temperature error from the inductor
core to the primary inductor heat sink.
I = PI
PI = CURRENT REPRESENTING THE POWER DISSIPATED BY THE INDUCTOR
(VDCR • READ_IOUT WHERE VDCR = (VISENSEP – VISENSM))
Cτ = CAPACITANCE REPRESENTING THERMAL HEAT CAPACITY OF THE INDUCTOR
(INCLUDED IN MFR_IOUT_CAL_GAIN_TAU_INV)
VI = TI
TI =
R = θIS
C = Cτ
VOLTAGE REPRESENTING THE TEMPERATURE OF THE INDUCTOR
θIS = RESISTANCE REPRESENTING THE THERMAL RESISTANCE FROM THE DCR
TO THE REMOTE TEMPERATURE SENSOR (MFR_IOUT_CAL_GAIN_THETA)
TS = VOLTAGE REPRESENTING THE TEMPERATURE AT THE REMOTE
TEMPERATURE SENSOR
VS = TS
2974 F21
Figure 21. Electronic Analogy for Inductor Temperature Model
The best way to understand the self-heating effect inside the inductor is to model the system using the circuit analogy
of Figure 21. The 1st order differential equation for the above model may be approximated by the following difference
equation:
PI – TI/θIS = Cτ ∆TI/∆t (Eq1) (when TS = 0)
from which:
∆TI = ∆t (PI θIS – TI)/(θIS Cτ) (Eq2) or
∆TI = (PI θIS – TI) • τINV (Eq3)
where
τINV = ∆t/(θIS Cτ) (Eq4)
and ∆t is the sample period of the external temperature ADC.
The LTC2974 implements the self-heating algorithm using Eq3 and Eq4 where:
∆TI =∆MFR_T_SELF_HEAT
PI = READ_IOUT • (VISENSEP – VISENSEM)
TS = READ_TEMPERATURE_1
TI = MFR_T_SELF_HEAT + TS
∆t = 4 • tCONV_SENSE. (One complete external temperature loop period)
τINV = MFR_IOUT_CAL_GAIN_TAU_INV
θIS = MFR_IOUT_CAL_GAIN_THETA
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LTC2974
PMBus Command Description
Initially self heat is set to zero. After each temperature measurement self heat is updated to be the previous value of
self heat incremented or decremented by ∆MFR_T_SELF_HEAT.
The actual value of Cτ is not required. The important quantity is the thermal time constant τINV = (θIS Cτ). For example,
if an inductor has a thermal time constant τINV = 5 seconds then:
MFR_IOUT_CAL_GAIN_TAU_INV = (4 • tCONV_SENSE)/5 = 4 • 66ms/5s = 0.0528
Refer to the application section for more information on calibrating θIS and τINV.
READ_TEMPERATURE_2 is substituted for READ_TEMPERATURE_1 if the associated TSENSE network fails to detect
a valid temperature. Under these conditions TS = READ_TEMPERATURE_2 and the self-heating correction is applied
using the internal die temperature. See READ_TEMPERATURE_1 for more information.
MFR_T_SELF_HEAT Data Content
Bit(s)
Symbol
b[15:0] Mfr_t_self_heat
Operation
Values are limited to the range 0°C to 50°C.
MFR_IOUT_CAL_GAIN_THETA Data Content
Bit(s)
Symbol
b[15:0] Mfr_iout_cal_gain_theta
Operation
Values ≤ 0 set MFR_T_SELF_HEAT to zero.
MFR_IOUT_CAL_GAIN_TAU_INV Data Content
Bit(s)
Symbol
b[15:0] Mfr_iout_cal_gain_tau_inv
Operation
Values ≤ 0 set MFR_T_SELF_HEAT to zero.
Values ≥ 1 set MFR_T_SELF_HEAT to MFR_IOUT_CAL_GAIN_THETA • READ_IOUT • (VISENSEP – VISENSEM).
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LTC2974
PMBus Command Description
Sequencing Timing Limits and Clock Sharing
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
DEFAULT REF
VALUE PAGE
TON_DELAY
0x60 Time from CONTROL pin and/or OPERATION
command = ON to VOUT_EN pin = ON.
R/W Word
Y
L11
ms
Y
1.0
0xBA00
51
TON_RISE
0x61 Time from when the VOUT_ENn pin goes high
until the LTC2974 optionally soft-connects its
DAC and begins to servo the output voltage to
the desired value.
R/W Word
Y
L11
ms
Y
10.0
0xD280
51
TON_MAX_FAULT_LIMIT
0x62 Maximum time from VOUT_EN pin on assertion
that an UV condition will be tolerated before a
TON_MAX_FAULT condition results.
R/W Word
Y
L11
ms
Y
15.0
0xD3C0
51
TOFF_DELAY
0x64 Time from CONTROL pin and/or OPERATION
command = OFF to VOUT_EN pin = OFF.
R/W Word
Y
L11
ms
Y
1.0
0xBA00
51
MFR_RESTART_DELAY
0xDC Delay from actual CONTROL active edge to
virtual CONTROL active edge.
R/W Word
N
L11
ms
Y
400
0xFB20
51
TON_DELAY, TON_RISE, TON_MAX_FAULT_LIMIT and TOFF_DELAY
These commands share the same format and provide sequencing and timer fault and warning delays in ms.
TON_DELAY sets the amount of time in milliseconds that a channel waits following the start of an ON sequence before
its VOUT_EN pin enables a DC/DC converter. This delay is counted using SHARE_CLK only.
TON_RISE sets the amount of time in ms that elapses after the power supply has been enabled until the LTC2974’s
DAC soft-connects and servos the output voltage to the desired level if Mfr_dac_mode = 00b. This delay is counted
using SHARE_CLK only.
TON_MAX_FAULT_LIMIT is the maximum amount of time that the power supply being controlled by the LTC2974 can
attempt to power up the output without reaching the VOUT_UV_FAULT_LIMIT. If it does not, then a TON_MAX_FAULT
is declared. If the output reaches VOUT_UV_FAULT_LIMIT prior to TON_MAX_FAULT_LIMIT, the LTC2974 unmasks the
VOUT_UV_FAULT_LIMIT threshold. (Note that a value of zero means there is no limit to how long the power supply
can attempt to bring up its output voltage.) This delay is counted using SHARE_CLK only.
TOFF_DELAY is the amount of time that elapses after the CONTROL pin and/or OPERATION command is de-asserted
until the channel is disabled (soft-off). This delay is counted using SHARE_CLK if available, otherwise the internal
oscillator is used.
All of the above TON and TOFF delays are internally limited to 655ms, and rounded to the nearest 10µs. The read value
of these commands always returns what was last written and does not reflect internal limiting.
MFR_RESTART_DELAY
This command essentially sets the off time of a CONTROL pin initiated restart. If the CONTROL pin is toggled off for at
least 10µs then on, all dependent channels are disabled, held off for a time = Mfr_restart_delay, then sequenced back
on. CONTROL pin transitions whose OFF time exceeds Mfr_restart_delay are not affected by this command. A value
of all zeros disables this feature. This delay is counted using SHARE_CLK only.
This delay is internally limited to 13.1 seconds, and rounded to the nearest 200µs. The read value of this command
always returns what was last written and does not reflect internal limiting.
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LTC2974
PMBus Command Description
Clock Sharing
Multiple LTC PMBus devices can synchronize their clocks in an application by connecting together the open-drain
SHARE_CLK input/outputs to a pull-up resistor as a wired OR. In this case the fastest clock will take over and synchronize all other chips to its falling edge.
SHARE_CLK can optionally be used to synchronize ON/OFF dependency on VIN across multiple chips by setting the
Mfr_config_all_vin_share_enable bit of the MFR_CONFIG_ALL register. When configured this way the chip will hold
SHARE_CLK low when the unit is off for insufficient input voltage, and upon detecting that SHARE_CLK is held low
the chip will disable all channels after a brief deglitch period. When the SHARE_CLK pin is allowed to rise, the chip
will respond by beginning a start sequence. In this case the slowest VIN_ON detection will take over and synchronize
other chips to its start sequence.
Watchdog Timer and Power Good
CMD
CODE DESCRIPTION
COMMAND NAME
MFR_PWRGD_EN
0xD4 Configuration that maps WDI/
RESETB status and individual
channel power good to the
PWRGD pin.
TYPE
PAGED FORMAT UNITS EEPROM
DEFAULT REF
VALUE PAGE
Y
0x0000
52
ms
Y
100
0xEB20
53
L11
ms
Y
0
0x8000
53
L11
ms
Y
0
0x8000
53
R/W Word
N
Reg
MFR_POWERGOOD_ASSERTION_DELAY 0xE1 Power-good output assertion
delay.
R/W Word
N
L11
MFR_WATCHDOG_T_FIRST
0xE2 First watchdog timer interval.
R/W Word
N
MFR_WATCHDOG_T
0xE3 Watchdog timer interval.
R/W Word
N
MFR_PWRGD_EN
This command register controls the mapping of the watchdog and channel power good status to the PWRGD pin.
MFR_PWRGD_EN Data Contents
BIT(S) SYMBOL
OPERATION
b[15:9] Reserved
Read only, always returns 0s.
b[8]
Mfr_pwrgd_en_wdog Watchdog.
1 = Watchdog timer not-expired status is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = Watchdog timer does not affect the PWRGD pin.
b[7:4] Reserved
b[3]
Always returns 0000b.
Mfr_pwrgd_en_chan3 Channel 3.
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when
the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
b[2]
Mfr_pwrgd_en_chan2 Channel 2.
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when
the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
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LTC2974
PMBus Command Description
b[1]
Mfr_pwrgd_en_chan1 Channel 1.
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when
the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
b[0]
Mfr_pwrgd_en_chan0 Channel 0.
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when
the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
MFR_POWERGOOD_ASSERTION_DELAY
This command register allows the user to program the delay from when the internal power-good signal becomes valid
until the power-good output is asserted. This delay is counted using SHARE_CLK if available, otherwise the internal
oscillator is used. This delay is internally limited to 13.1 seconds, and rounded to the nearest 200µs. The read value
of this command always returns what was last written and does not reflect internal limiting.
The power good de-assertion delay and threshold source is controlled by Mfr_config_all_pwrgd_off_uses_uv. Systems that require a fast power good de-assertion should set Mfr_config_all_pwrgd_off_uses_uv=1. This uses the
VOUT_UV_FAULT_LIMIT and the high speed comparator to de-assert the PWRGD pin. Systems that require a separate
power good off threshold should set Mfr_config_all_pwrgd_off_uses_uv=0. This uses the slower ADC polling loop
and POWER_GOOD_OFF to de-assert the PWRGD pin.
Watchdog Operation
A non-zero write to the MFR_WATCHDOG_T register will reset the watchdog timer. Low-to-high transitions on the
WDI/RESETB pin also reset the watchdog timer. If the timer expires, ALERTB is asserted and the PWRGD output
is optionally de-asserted and then reasserted after MFR_PWRGD_ASSERTION_DELAY ms. Writing 0 to either the
MFR_WATCH_DOG_T or MFR_WATCHDOG_T_FIRST registers will disable the timer.
MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T
The MFR_WATCHDOG_T_FIRST register allows the user to program the duration of the first watchdog timer interval
following assertion of the PWRGD pin, assuming the PWRGD pin reflects the status of the watchdog timer. If assertion of PWRGD is not conditioned by the watchdog timer’s status, then MFR_WATCHDOG_T_FIRST applies to the first
timing interval after the timer is enabled. Writing a value of 0ms to the MFR_WATCHDOG_T_FIRST register disables
the watchdog timer. This delay is internally limited to 65 seconds and rounded to the nearest 1ms.
The MFR_WATCHDOG_T register allows the user to program watchdog timer intervals subsequent to the MFR_WATCHDOG_T_FIRST timing interval. Writing a value of 0ms to the MFR_WATCHDOG_T register disables the watchdog timer.
This delay is internally limited to 655ms and rounded to the nearest 10µs.
Both timers operate on an internal clock independent of SHARE_CLK. The read value of both commands always returns
what was last written and does not reflect internal limiting.
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LTC2974
PMBus Command Description
Fault Responses
COMMAND NAME
CMD
CODE DESCRIPTION
VOUT_OV_FAULT_RESPONSE
0x41
Action to be taken by the device when an
output overvoltage fault is detected.
R/W Byte
Y
Reg
Y
0x80
55
VOUT_UV_FAULT_RESPONSE
0x45
Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte
Y
Reg
Y
0x7F
55
IOUT_OC_FAULT_RESPONSE
0x47
Action to be taken by the device when an
output overcurrent fault is detected.
R/W Byte
Y
Reg
Y
0x00
56
IOUT_UC_FAULT_RESPONSE
0x4C Action to be taken by the device when an
output undercurrent fault is detected.
R/W Byte
Y
Reg
Y
0x00
56
OT_FAULT_RESPONSE
0x50
Action to be taken by the device when an
overtemperature fault is detected on the
external temperature sensor.
R/W Byte
Y
Reg
Y
0xB8
57
UT_FAULT_RESPONSE
0x54
Action to be taken by the device when an R/W Byte
undertemperature fault is detected on the
external temperature sensor.
Y
Reg
Y
0xB8
57
VIN_OV_FAULT_RESPONSE
0x56
Action to be taken by the device when an
input overvoltage fault is detected.
R/W Byte
N
Reg
Y
0x80
57
VIN_UV_FAULT_RESPONSE
0x5A Action to be taken by the device when an
input undervoltage fault is detected.
R/W Byte
N
Reg
Y
0x00
57
TON_MAX_FAULT_RESPONSE
0x63
Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte
Y
Reg
Y
0xB8
58
MFR_RETRY_DELAY
0xDB Retry interval during FAULT retry mode.
R/W Word
N
L11
Y
200
0xF320
58
MFR_RETRY_COUNT
0xF7
R/W Byte
N
Reg
Y
0x00
58
Retry count for all faulted off conditions
that enable retry.
TYPE
PAGED FORMAT UNITS EEPROM
ms
DEFAULT REF
VALUE PAGE
Clearing Latched Faults
Latched faults are reset by toggling the CONTROL pin, using the OPERATION command, or removing and reapplying
the bias voltage to the VIN_SNS pin. All fault and warning conditions result in the ALERTB pin being asserted low and
the corresponding bits being set in the status registers. The CLEAR_FAULTS command resets the contents of the
status registers and de-asserts the ALERTB output. The CLEAR_FAULTS does not clear a faulted off state nor allow a
channel to turn back on.
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LTC2974
PMBus Command Description
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE
The fault response documented here is for voltages that are measured by the high speed supervisor. These voltages
are measured over a short period of time and may require a deglitch period. Note that in addition to the response
described by these commands, the LTC2974 will also:
• Set the appropriate bit(s) in the STATUS_BYTE.
• Set the appropriate bit(s) in the STATUS_WORD.
• Set the appropriate bit in the corresponding STATUS_VOUT register, and
• Notify the host by pulling the ALERTB pin low.
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Vout_ov_fault_response_action, Response action:
Vout_uv_fault_response_action 00b: The unit continues operation without interruption.
01b: The unit continues operating for the delay time specified by bits[2:0] in increments of tS_VS. See
Electrical Characteristics Table. If the fault is still present at the end of the delay time, the unit shuts down
immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn). After shutting down, the device
responds according to the retry settings in bits [5:3].
10b-11b: The unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn).
After shutting down, the device responds according to the retry settings in bits [5:3].
b[5:3] Vout_ov_fault_response_retry,
Vout_uv_fault_response_retry
Response retry behavior:
000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001b-111b: The PMBus device attempts to restart the number of times specified by the global Mfr_retry_
count[2:0] until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down.
Changing the value might not take effect until the next off-then-on sequence on that channel.
b[2:0] Vout_ov_fault_response_delay,
Vout_uv_fault_response_delay
This sample count determines the amount of time a unit is to ignore a fault after it is first detected. Use this
delay to deglitch fast faults.
000b: There is no additional deglitch delay applied to fault detection.
001b-111b: The fault is deglitched for deglitch period of b[2:0] samples at a sampling period of tS_VS
(12.2µs typical).
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LTC2974
PMBus Command Description
IOUT_OC_FAULT_RESPONSE and IOUT_UC_FAULT_RESPONSE
The fault response documented here is for currents that are measured by the high speed supervisor. These currents
are measured over a short period of time and may require a deglitch period. Note that in addition to the response
described by these commands, the LTC2974 will also:
• Set the appropriate bit in the STATUS_BYTE.
• Set the appropriate bit in the STATUS_WORD.
• Set the appropriate bit in the corresponding STATUS_IOUT register, and
• Notify the host by pulling the ALERTB pin low.
IOUT_OC_FAULT_RESONSE and IOUT_UC_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Iout_oc_fault_response_action, Response action:
Iout_uc_fault_response_action 00b and 01b: The unit continues operation without interruption. Note that the current will not be limited to the
value of Iout_oc_fault_limit or Iout_uc_fault_limit.
10b: The unit continues operating for the delay time specified by bits [2:0]. If the fault is still present at the
end of the delay time, the unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_
track_enn). After shutting down, the device responds according to the retry settings in bits [5:3]. Note that
the current will not be limited to the value of Iout_oc_fault_limit or Iout_uc_fault_limit.
11b: The unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn). After
shutting down, the device responds according to the retry settings in bits [5:3].
b[5:3] Iout_oc_fault_response_retry,
Iout_uc_fault_response_retry
Response retry behavior:
000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001-111b: The PMBus device attempts to restart the number of times specified by the global Mfr_retry_
count[2:0] until it is commanded off (by the control pin or operation command or both), bias power is
removed, or another fault condition causes the unit to shut down.
Changing the value might not take effect until the next off-then-on sequence on that channel.
b[2:0] Iout_oc_fault_response_delay,
Iout_uc_fault_response_delay
This sample count determines the amount of time a unit is to ignore a fault after it is first detected. Use this
delay to deglitch fast faults.
000b: There is no additional deglitch delay applied to fault detection.
001b-111b: The fault is deglitched for the interval selected by b[2:0] as follows.
b[2:0]
Deglitch interval
001b
100µs
010b
1ms
011b
5ms
100b
10ms
101b
20ms
110b
50ms
111b
100ms
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LTC2974
PMBus Command Description
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_RESPONSE
The fault response documented here is for values that are measured by the ADC. Note that in addition to the response
described by these commands, the LTC2974 will also:
• Set the appropriate bit(s) in the STATUS_BYTE.
• Set the appropriate bit(s) in the STATUS_WORD.
• Set the appropriate bit in the corresponding STATUS_VIN or STATUS_TEMPERATURE register, and
• Notify the host by pulling the ALERTB pin low.
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE, VIN_UV_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Ot_fault_response_action,
Response action:
Ut_fault_response_action,
00b: The unit continues operation without interruption.
Vin_ov_fault_response_action,
Vin_uv_fault_response_action 01b-11b: The unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn).
After shutting down, the device responds according to the retry settings in bits [5:3].
b[5:3] Ot_fault_response_retry,
Ut_fault_response_retry,
Vin_ov_fault_response_retry,
Vin_uv_fault_response_retry
Response retry behavior:
000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001b-111b: The PMBus device attempts to restart the number of times specified by the global Mfr_retry_
count[2:0] until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down.
Changing the value might not take effect until the next off-then-on sequence on that channel.
b[2:0] Ot_fault_response_delay,
Ut_fault_response_delay,
Vin_ov_fault_response_delay,
Vin_uv_fault_response_delay
Hard coded to 000b: There is no additional deglitch delay applied to fault detection.
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LTC2974
PMBus Command Description
TON_MAX_FAULT_RESPONSE
This command defines the LTC2974 response to a TON_MAX_FAULT. It may be used to protect against a short-circuited
output at startup. After startup use VOUT_UV_FAULT_RESPONSE to protect against a short-circuited output.
The device also:
• Sets the HIGH_BYTE bit in the STATUS_BYTE,
• Sets the VOUT bit in the STATUS_WORD,
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT register, and
• Notifies the host by asserting ALERTB.
TON_MAX_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Ton_max_fault_response_action Response action:
00b: The unit continues operation without interruption.
01b-11b: The unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn).
After shutting down, the device responds according to the retry settings in bits [5:3].
b[5:3] Ton_max_fault_response_retry
Response retry behavior:
000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001b-111b: The PMBus device attempts to restart the number of times specified by the global Mfr_retry_
count[2:0] until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down.
Changing the value might not take effect until the next off-then-on sequence on that channel.
b[2:0] Ton_max_fault_response_delay Hard coded to 000b: There is no additional deglitch delay applied to fault detection.
MFR_RETRY_DELAY
This command determines the retry interval when the LTC2974 is in retry mode in response to a fault condition. This
delay is counted using SHARE_CLK only. This delay is internally limited to 13.1 seconds, and rounded to the nearest
200µs. The read value of this command always returns what was last written and does not reflect internal limiting.
MFR_RETRY_COUNT
The MFR_RETRY_COUNT is a global command that sets the number of retries attempted when any channel faults off
with its fault response retry field set to a non zero value.
In the event of multiple or recurring retry faults on the same channel the total number of retries equals MFR_RETRY_
COUNT. If a channel has not been faulted off for 6 seconds, its retry counter is cleared. Toggling a channel’s CONTROL
pin off then on or issuing OPERATION off then on commands will synchronously clear the retry count.
MFR_RETRY_COUNT Data Contents
BIT(S) SYMBOL
OPERATION
b[7:3] Reserved
Always returns zero.
b[2:0] Mfr_retry_count [2:0]
0: No retries:
1-6: Number of retries.
7: Infinite retries.
Changing the value might not take effect until the next off-then-on sequence on that channel.
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LTC2974
PMBus Command Description
Shared External Faults
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
DEFAULT REF
VALUE PAGE
MFR_FAULTB0_PROPAGATE
0xD2 Configuration that determines if a channels
faulted off state is propagated to the
FAULTB0 pin.
R/W Byte
Y
Reg
Y
0x00
59
MFR_FAULTB1_PROPAGATE
0xD3 Configuration that determines if a channels
faulted off state is propagated to the
FAULTB1 pin.
R/W Byte
Y
Reg
Y
0x00
59
MFR_FAULTB0_RESPONSE
0xD5 Action to be taken by the device when the
FAULTB0 pin is asserted low.
R/W Byte
N
Reg
Y
0x00
60
MFR_FAULTB1_RESPONSE
0xD6 Action to be taken by the device when the
FAULTB1 pin is asserted low.
R/W Byte
N
Reg
Y
0x00
60
MFR_FAULTB0_PROPAGATE and MFR_FAULTB1_PROPAGATE
These manufacturer specific commands enable channels that have faulted off to propagate that state to the appropriate fault pin. MFR_FAULTB0_PROPAGATE allows any channel’s faulted off state to propagate to the FAULTB0 pin.
MFR_FAULTB1_PROPAGATE allows any channel’s faulted off state to propagate to the FAULTB1 pin.
Note that pulling a fault pin low will have no effect for channels that have MFR_FAULTBn_RESPONSE set to 0. The
channel continues operation without interruption. This fault response is called Ignore (0x0) in LTpowerPlay.
MFR_FAULTB0_PROPAGATE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:1] Reserved
Don’t care. Always returns 0.
b[0]
Mfr_faultb0_propagate
Enable fault propagation.
0: Channel’s faulted off state does not assert FAULTB0 low.
1 :Channel’s faulted off state asserts FAULTB0 low.
MFR_FAULTB1_PROPAGATE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:1] Reserved
Don’t care. Always returns 0.
b[0]
Mfr_faultb1_propagate
Enable fault propagation.
0: Channel’s faulted off state does not assert FAULTB1 low.
1: Channel’s faulted off state asserts FAULTB1 low.
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LTC2974
PMBus Command Description
MFR_FAULTB0_RESPONSE and MFR_FAULTB1_RESPONSE
These manufacturer specific commands share the same format and specify the response to assertions of the FAULTB
pins. MFR_FAULTB0_RESPONSE determines which channels shut off when the FAULTB0 pin is asserted low and
MFR_FAULTB1_RESPONSE determines which channels shut off when the FAULTB1 pin is asserted low.When a channel shuts off in response to a FAULTBn pin, the ALERTB pin is asserted low and the appropriate bit is set in the STATUS_MFR_SPECIFIC register. For a graphical explanation, see the switches on the left hand side of Figure 28: Channel
Fault Management Block Diagram.
Faults will not propagate for channels that have MFR_FAULTBn_RESPONSE set to 0: The channel continues operation
without interruption. Note that this fault response is called No Action in LTpowerPlay.
MFR_FAULTB0_RESPONSE and MFR_FAULTB1_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:4] Reserved
Read only, always returns 0000b.
b[3]
Mfr_faultb0_response_chan3, Channel 3 response.
Mfr_faultb1_response_chan3 0: The channel continues operation without interruption
1: The channel shuts down if the corresponding FAULTB pin is still asserted after 10µs. When the FAULTB pin
subsequently de-asserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[2]
Mfr_faultb0_response_chan2, Channel 2 response.
Mfr_faultb1_response_chan2 0: The channel continues operation without interruption
1: The channel shuts down if the corresponding FAULTB pin is still asserted after 10µs. When the FAULTB pin
subsequently de-asserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[1]
Mfr_faultb0_response_chan1, Channel 1 response.
Mfr_faultb1_response_chan1 0: The channel continues operation without interruption
1: The channel shuts down if the corresponding FAULTB pin is still asserted after 10µs. When the FAULTB pin
subsequently de-asserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[0]
Mfr_faultb0_response_chan0, Channel 0 response.
Mfr_faultb1_response_chan0 0: The channel continues operation without interruption
1: The channel shuts down if the corresponding FAULTB pin is still asserted after 10µs. When the FAULTB pin
subsequently de-asserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
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LTC2974
PMBus Command Description
Fault Warning and Status
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
DEFAULT REF
VALUE PAGE
CLEAR_FAULTS
0x03 Clear any fault bits that have been set.
Send Byte
Y
NA
61
STATUS_BYTE
0x78 One byte summary of the unit’s fault condition.
R Byte
Y
Reg
NA
61
STATUS_WORD
0x79 Two byte summary of the unit’s fault condition.
R Word
Y
Reg
NA
62
STATUS_VOUT
0x7A Output voltage fault and warning status.
R Byte
Y
Reg
NA
62
STATUS_IOUT
0x7B Output current fault and warning status.
R Byte
Y
Reg
NA
63
STATUS_INPUT
0x7C Input supply fault and warning status.
R Byte
N
Reg
NA
63
STATUS_TEMPERATURE
0x7D External temperature fault and warning status
for READ_TEMPERATURE_1.
R Byte
Y
Reg
NA
63
STATUS_CML
0x7E Communication and memory fault and warning
status.
R Byte
N
Reg
NA
64
STATUS_MFR_SPECIFIC
0x80 Manufacturer specific fault and state
information.
R Byte
Y
Reg
NA
64
MFR_PADS
0xE5 Current state of selected digital I/O pads.
R/W Word
N
Reg
NA
65
MFR_COMMON
0xEF Manufacturer status bits that are common
across multiple LTC chips.
R Byte
N
Reg
NA
65
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear status bits that have been set. This command clears all fault and warning bits in all unpaged status registers, and paged status registers selected by the current PAGE setting. At the same
time, the device negates (clears, releases) its contribution to ALERTB.
The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. See Clearing
Latched Faults for more information.
If the fault is present after the fault is cleared, the fault status bit shall be set again and the host notified by the usual
means.
Note: this command responds to the global page command. (PAGE=0xFF)
STATUS_BYTE
The STATUS_BYTE command returns the summary of the most critical faults or warnings which have occurred, as
shown in the following table. STATUS_BYTE is a subset of STATUS_WORD and duplicates the same information.
STATUS_BYTE Data Contents
BIT(S) SYMBOL
OPERATION
b[7]
Status_byte_busy
Same as Status_word_busy.
b[6]
Status_byte_off
Same as Status_word_off.
b[5]
Status_byte_vout_ov
Same as Status_word_vout_ov.
b[4]
Status_byte_iout_oc
Same as Status_word_iout_oc.
b[3]
Status_byte_vin_uv
Same as Status_word_vin_uv.
b[2]
Status_byte_temp
Same as Status_word_temp.
b[1]
Status_byte_cml
Same as Status_word_cml.
b[0]
Status_byte_high_byte Same as Status_word_high_byte.
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LTC2974
PMBus Command Description
STATUS_WORD
The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based on
the information in these bytes, the host can get more information by reading the appropriate detailed status register.
The low byte of the STATUS_WORD is the same register as the STATUS_BYTE command.
STATUS_WORD Data Contents
BIT(S) SYMBOL
OPERATION
b[15] Status_word_vout
An output voltage fault or warning has occurred. See STATUS_VOUT.
b[14] Status_word_iout
An output current fault or warning has occurred. See STATUS_IOUT.
b[13] Status_word_input
An input voltage fault or warning has occurred. See STATUS_INPUT.
b[12] Status_word_mfr
A manufacturer specific fault has occurred. See STATUS_MFR._SPECIFIC.
b[11] Status_word_power_not_good The PWRGD pin, if enabled, is negated. Power is not good.
b[10] Status_word_fans
Not supported. Always
returns 0.
b[9]
Status_word_other
Not supported. Always
returns 0.
b[8]
Status_word_unknown
Not supported. Always
returns 0.
b[7]
Status_word_busy
Device busy when PMBus command received. See OPERATION: Processing Commands.
b[6]
Status_word_off
This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply
not being enabled. The off-bit is clear if unit is allowed to provide power to the output.
b[5]
Status_word_vout_ov
An output overvoltage fault has occurred.
b[4]
Status_word_iout_oc
An output overcurrent fault has occurred.
b[3]
Status_word_vin_uv
A VIN undervoltage fault has occurred.
b[2]
Status_word_temp
A temperature fault or warning has occurred. See STATUS_TEMPERATURE.
b[1]
Status_word_cml
A communication, memory or logic fault has occurred. See STATUS_CML.
b[0]
Status_word_high_byte
A fault/warning not listed in b[7:1] has occurred.
STATUS_VOUT
The STATUS_VOUT command returns the summary of the output voltage faults or warnings which have occurred, as
shown in the following table:
STATUS_VOUT Data Contents
BIT(S) SYMBOL
OPERATION
b[7]
Status_vout_ov_fault
Overvoltage fault.
b[6]
Status_vout_ov_warn
Overvoltage warning.
b[5]
Status_vout_uv_warn
Undervoltage warning
b[4]
Status_vout_uv_fault
Undervoltage fault.
b[3]
Status_vout_max_fault
VOUT_MAX fault. An attempt has been made to set the output voltage to a value higher than allowed by the
VOUT_MAX command. After being cleared, Status_vout_max_fault will not report additional faults until a channel
state transition (off-then-on) has been performed or a valid output voltage, lower than allowed by VOUT_MAX, has
been set.
b[2]
Status_vout_ton_max_fault TON_MAX_FAULT sequencing fault.
b[1]
Status_vout_toff_max_warn Not supported. Always returns 0.
b[0]
Status_vout_tracking_error Not supported. Always returns 0.
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LTC2974
PMBus Command Description
STATUS_IOUT
The STATUS_IOUT command returns the summary of the output current faults or warnings which have occurred, as
shown in the following table:
STATUS_IOUT Data Contents
BIT(S) SYMBOL
OPERATION
b[7]
Status_iout_oc_fault
Overcurrent fault.
b[6]
Status_iout_oc_uv_fault
Not Supported. Always returns 0.
b[5]
Status_iout_oc_warn
Overcurrent warning
b[4]
Status_iout_uc_fault
Undercurrent fault.
b[3]
Status_iout_curr_share_fault
Not Supported. Always returns 0.
b[2]
Status_pout_power_limiting
Not Supported. Always returns 0.
b[1]
Status_pout_overpower_fault Not Supported. Always returns 0.
b[0]
Status_pout_overpower_warn Not Supported. Always returns 0.
STATUS_INPUT
The STATUS_INPUT command returns the summary of the VIN faults or warnings which have occurred, as shown in
the following table:
STATUS_INPUT Data Contents
BIT(S) SYMBOL
OPERATION
b[7]
Status_input_ov_fault
VIN overvoltage fault
b[6]
Status_input_ov_warn
VIN overvoltage warning
b[5]
Status_input_uv_warn
VIN undervoltage warning
b[4]
Status_input_uv_fault
VIN undervoltage fault
b[3]
Status_input_off
Unit is off for insufficient input voltage.
b[2]
IIN overcurrent fault
Not supported. Always returns 0.
b[1]
IIN overcurrent warn
Not supported. Always returns 0.
b[0]
PIN overpower warn
Not supported. Always returns 0.
STATUS_TEMPERATURE
The STATUS_TEMPERATURE command returns the summary of the temperature faults or warnings which have occurred, as shown in the following table. Note that this information is paged and refers to the temperature of the associated external diode.
STATUS_TEMPERATURE Data Contents
BIT(S) SYMBOL
OPERATION
b[7]
Status_temperature_ot_fault
Overtemperature fault.
b[6]
Status_temperature_ot_warn
Overtemperature warning.
b[5]
Status_temperature_ut_warn
Undertemperature warning.
b[4]
Status_temperature_ut_fault
Undertemperature fault.
b[3]
Reserved
Reserved. Always returns 0.
b[2]
Reserved
Reserved. Always returns 0.
b[1]
Reserved
Reserved. Always returns 0.
b[0]
Reserved
Reserved. Always returns 0.
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LTC2974
PMBus Command Description
STATUS_CML
The STATUS_CML command returns the summary of the communication, memory and logic faults or warnings which
have occurred, as shown in the following table:
STATUS_CML Data Contents
BIT(S) SYMBOL
b[7]
Status_cml_cmd_fault
OPERATION
1 = An illegal or unsupported command fault has occurred.
0 = No fault has occurred.
b[6]
Status_cml_data_fault
1 = Illegal or unsupported data received.
0 = No fault has occurred.
b[5]
Status_cml_pec_fault
1 = A packet error check fault has occurred. Note: PEC checking is always active in the LTC2974. Any extra byte
received before a STOP will set Status_cml_pec_fault unless the extra byte is a matching PEC byte.
b[4]
Status_cml_memory_fault
b[3]
Status_cml_processor_fault Not supported, always returns 0.
b[2]
Reserved
Reserved, always returns 0.
b[1]
Status_cml_pmbus_fault
1 = A communication fault other than ones listed in this table has occurred. This is a catch all category for illegally
formed I2C/SMBus commands (Example: An address byte with read =1 received immediately after a START).
b[0]
Status_cml_unknown_fault
0 = No fault has occurred.
1 = A fault has occurred in the EEPROM.
0 = No fault has occurred.
0 = No fault has occurred.
Not supported, always returns 0.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC command returns manufacturer specific status flags. Bits marked CHANNEL = All are
not paged. Bits marked STICKY = Yes stay set until a CLEAR_FAULTS is issued or the channel is commanded on by
the user. Bits marked ALERT = Yes pull ALERTB low when the bit is set. Bits marked OFF = Yes indicate that the event
can be configured elsewhere to turn the channel off.
STATUS_MFR_SPECIFIC Data Contents
BIT(S) SYMBOL
b[7]
Status_mfr_discharge
OPERATION
CHANNEL
1 = A VOUT discharge fault occurred while attempting to enter the ON Current Page
state.
STICKY ALERT OFF
Yes
Yes
Yes
0 = No VOUT discharge fault has occurred.
b[6]
Status_mfr_fault1_in
This channel attempted to turn on while the FAULTB1 pin was
asserted low, or this channel has shut down at least once in
response to a FAULTB1 pin asserting low since the last CONTROL
pin toggle, OPERATION command ON/OFF cycle or CLEAR_FAULTS
command. If Mfr_track_en_chann is set, Status_mfr_fault1_in may
also be set for the channel causing the fault.
Current Page
Yes
Yes
Yes
b[5]
Status_mfr_fault0_in
This channel attempted to turn on while the FAULTB0 pin was
asserted low, or this channel has shut down at least once in
response to a FAULTB0 pin asserting low since the last CONTROL
pin toggle, OPERATION command ON/OFF cycle or CLEAR_FAULTS
command. If Mfr_track_en_chann is set, Status_mfr_fault0_in may
also be set for the channel causing the fault.
Current Page
Yes
Yes
Yes
b[4]
Status_mfr_servo_target_reached Servo target has been reached.
Current Page
No
No
No
b[3]
Status_mfr_dac_connected
Current Page
No
No
No
DAC is connected and driving VDAC pin.
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LTC2974
PMBus Command Description
b[2]
Status_mfr_dac_saturated
A previous servo operation terminated with maximum or minimum
DAC value.
Current Page
Yes
No
No
b[1]
Status_mfr_auxfaultb_faulted_off
AUXFAULTB has been de-asserted due to a VOUT or IOUT fault.
All
No
No
No
b[0]
Status_mfr_watchdog_fault
1 = A watchdog fault has occurred.
All
Yes
Yes
No
0 = No watchdog fault has occurred.
MFR_PADS
The MFR_PADS command provides read-only access of digital pads (pins). The input values are before any deglitching logic.
MFR_PADS Data Contents
BIT(S)
SYMBOL
b[15]
Mfr_pads_pwrgd_drive
OPERATION
0 = PWRGD pad is being driven low by this chip.
1 = PWRGD pad is not being driven low by this chip.
b[14]
Mfr_pads_alertb_drive
0 = ALERTB pad is being driven low by this chip.
1 = ALERTB pad is not being driven low by this chip.
b[13:12] Mfr_pads_faultb_drive[1:0]
bit[1] used for FAULTB0 pad, bit[0] used for FAULTB1 pad as follows:
0 = FAULTB pad is being driven low by this chip.
1 = FAULTB pad is not being driven low by this chip.
b[11:10] Reserved[1:0]
b[9:8]
Mfr_pads_asel1[1:0]
Always returns 00b.
11: Logic high detected on ASEL1 input pad.
10: ASEL1 input pad is floating.
01: Reserved.
00: Logic low detected on ASEL1 input pad.
b[7:6]
Mfr_pads_asel0[1:0]
11: Logic high detected on ASEL0 input pad.
10: ASEL0 input pad is floating.
01: Reserved.
00: Logic low detected on ASEL0 input pad.
b[5]
Mfr_pads_control1
1: Logic high detected on CONTROL1 pad.
0: Logic low detected on CONTROL1 pad.
b[4]
Mfr_pads_control0
1: Logic high detected on CONTROL0 pad.
0: Logic low detected on CONTROL0 pad.
b[3:2]
Mfr_pads_faultb[1:0]
bit[1] used for FAULTB0 pad, bit[0] used for FAULTB1 pad as follows:
1: Logic high detected on FAULTB pad.
0: Logic low detected on FAULTB pad.
b[1]
Mfr_pads_control2
b[0]
Mfr_pads_control3
1: Logic high detected on CONTROL2 pad.
0: Logic low detected on CONTROL2 pad.
1: Logic high detected on CONTROL3 pad.
0: Logic low detected on CONTROL3 pad.
MFR_COMMON
This command returns status information for the alert, device busy, share-clock pin (SHARE_CLK) and the write-protect
pin (WP).
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LTC2974
PMBus Command Description
This is the only command that may still be read when the LTC2974 is busy processing an EEPROM or other command.
It may be polled by the host to determine when the LTC2974 is available to process a PMBus command. A busy device
will always acknowledge its address but will NACK the command byte and set Status_byte_busy and Status_word_busy
when it receives a command that it cannot immediately process. ALERTB will not be asserted low in this case.
MFR_COMMON Data Contents
BIT(S) SYMBOL
b[7]
OPERATION
Mfr_common_alertb
Returns alert status.
1: ALERTB is de-asserted high.
0: ALERTB is asserted low.
b[6]
Mfr_common_busyb
Returns device busy status.
1: The device is available to process PMBus commands.
0: The device is busy and will NACK PMBus commands.
b[5:2] Reserved
b[1]
Read only, always returns 1s.
Mfr_common_share_clk
Returns the status of the share-clock pin.
1: Share-clock pin is being held low.
0: Share-clock pin is active.
b[0]
Mfr_common_write_protect Returns the status of the write-protect pin.
1: Write-protect pin is high.
0: Write-protect pin is low.
Telemetry
COMMAND NAME
CMD
CODE DESCRIPTION
READ_VIN
0x88 Input supply voltage.
R Word
N
L11
V
NA
67
READ_VOUT
0x8B DC/DC converter output voltage.
R Word
Y
L16
V
NA
67
TYPE
PAGED FORMAT UNITS EEPROM
DEFAULT REF
VALUE PAGE
READ_IOUT
0x8C DC/DC converter output current.
R Word
Y
L11
A
NA
67
READ_TEMPERATURE_1
0x8D External diode junction temperature. This
is the value used for all temperature related
processing, including IOUT_CAL_GAIN.
R Word
Y
L11
°C
NA
67
READ_TEMPERATURE_2
0x8E Internal junction temperature.
R Word
N
L11
°C
NA
67
READ_POUT
0x96 DC/DC converter output power.
R Word
Y
L11
W
NA
67
MFR_READ_IOUT
0xBB Alternate data format for READ_IOUT. One
LSB = 2.5mA.
R Word
Y
CF
2.5mA
NA
67
MFR_IOUT_SENSE_VOLTAGE
0xFA Absolute value of VISENSEP – VISENSEM.
One LSB = 3.05µV.
R Word
Y
CF
3.05µV
NA
68
MFR_VIN_PEAK
0xDE Maximum measured value of READ_VIN.
R Word
N
L11
V
NA
69
MFR_VOUT_PEAK
0xDD Maximum measured value of READ_VOUT.
R Word
Y
L16
V
NA
69
MFR_IOUT_PEAK
0xD7 Maximum measured value of READ_IOUT.
R Word
Y
L11
A
NA
69
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of READ_
TEMPERATURE_1.
R Word
Y
L11
°C
NA
69
MFR_VIN_MIN
R Word
N
L11
V
NA
69
0xFC Minimum measured value of READ_VIN.
MFR_VOUT_MIN
0xFB Minimum measured value of READ_VOUT.
R Word
Y
L16
V
NA
69
MFR_IOUT_MIN
0xD8 Minimum measured value of READ_IOUT.
R Word
Y
L11
A
NA
69
MFR_TEMPERATURE_1_MIN
0xFD Minimum measured value of READ_
TEMPERATURE_1.
R Word
Y
L11
°C
NA
69
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LTC2974
PMBus Command Description
READ_VIN
This command returns the most recent ADC measured value of the input voltage at the VIN_SNS pin.
READ_VOUT
This command returns the most recent ADC measured value of the channel’s output voltage.
READ_IOUT
This command returns the most recent ADC measured value of the channel’s output current.
READ_TEMPERATURE_1
This command returns the most recent measured value of the external diode temperature in °C. This value is used for
all temperature related operations and calculations. This command is paged. READ_TEMPERATURE_2 is substituted
for READ_TEMPERATURE_1 if the associated TSENSE network fails to detect a valid temperature.
The TSENSE network will fail to detect a valid temperature under the following conditions:
The TSENSE pin is shorted to a constant voltage.
The sense diode has an ideality factor greater than N_TS max.
Floating the TSENSE pin is not recommended and may return unpredictable temperature values.
READ_TEMPERATURE_2
This command returns the most recent ADC measured value of junction temperature in °C as determined by the
LTC2974’s internal temperature sensor. This register is for information purposes and does not generate any faults,
warnings, or affect any other registers or internal calculations unless it is used as READ_TEMPERATURE_1. This
command is not paged.
READ_TEMPERATURE_2 is substituted for READ_TEMPERATURE_1 if a channel’s TSENSE network fails to detect a
valid temperature.
READ_POUT
This command returns the most recent ADC measured value of the channel’s output power in watts.
MFR_READ_IOUT
This command returns the most recent ADC measured value of the channel’s output current, using a custom format
that provides better numeric representation granularity than the READ_IOUT command for currents whose absolute
value is between 2A and 82A.
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LTC2974
PMBus Command Description
MFR_READ_IOUT Data Contents
BIT(S) SYMBOL
b[15:0] Mfr_read_iout[15:0]
OPERATION
Channel output current expressed in custom format for improved resolution at high currents.
Value = Y • 2.5 where Y = b[15:0] is a signed two’s-complement number.
Example:
MFR_READ_IOUT = 5mA
For b[15:0] = 0x0002
Value = 2 • 2.5 = 5mA
The granularity of the returned value is always 2.5mA, and the return value is limited to ±81.92A. Use the READ_IOUT
command for larger currents. Note that the accuracy of the returned value is always limited by the ADC Characteristics
listed in the Electrical Characteristics section.
Comparison of Granularity Due to Numeric Format
READ_IOUT
GRANULARITY
MFR_READ_IOUT
GRANULARITY
31.25mA ≤ IOUT < 62.5mA
61µA
2.5mA
62.5mA ≤ IOUT < 125mA
122µA
2.5mA
125mA ≤ IOUT < 250mA
244µA
2.5mA
250mA ≤ IOUT < 500mA
488µA
2.5mA
0.5A ≤ IOUT < 1A
977µA
2.5mA
1A ≤ IOUT < 2A
1.95mA
2.5mA
2A ≤ IOUT < 4A
3.9mA
2.5mA
4A ≤ IOUT < 8A
7.8mA
2.5mA
8A ≤ IOUT < 16A
15.6mA
2.5mA
16A ≤ IOUT < 32A
31.3mA
2.5mA
32A ≤ IOUT < 64A
62.5mA
2.5mA
64A ≤ IOUT < 82A
125mA
2.5mA
82A ≤ IOUT < 128A
125mA
Saturated
128A ≤ IOUT < 256A
250mA
Saturated
CURRENT RANGE
MFR_IOUT_SENSE_VOLTAGE
This command returns the absolute value of the voltage measured between ISENSEPn and ISENSEMn during the last
READ_IOUT ADC conversion without any temperature correction.
MFR_IOUT_SENSE_VOLTAGE Data Contents
BIT(S) SYMBOL
OPERATION
b[15:0] Mfr_iout_sense_voltage Absolute value of raw voltage conversion measured between ISENSEPn and ISENSEMn.
Value = Y • 0.025 • 2–13 where Y = b[15:0] is an unsigned integer.
Example:
MFR_IOUT_SENSE_VOLTAGE = 1.544mV
For b[15:0] = 0x1FA=506
Value = 506 • 0.025 • 2–13 = 1.544mV
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LTC2974
PMBus Command Description
MFR_VIN_PEAK
This command returns the maximum ADC measured value of the input voltage. This register is reset to 0x7C00
(–225) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VOUT_PEAK
This command returns the maximum ADC measured value of the channel’s output voltage. This register is reset to
0xF800 (0.0) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_IOUT_PEAK
This commands returns the maximum ADC measured value of the channel’s output current. This register is reset to
0x7C00 (–225) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_TEMPERATURE_1_PEAK
This command returns the maximum measured value of the external diode temperature in °C. This register is reset
to 0x7C00 (–225) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VIN_MIN
This command returns the minimum ADC measured value of the input voltage. This register is reset to 0x7BFF (approximately 225) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VOUT_MIN
This command returns the minimum ADC measured value of the channel’s output voltage. This register is reset to
0xFFFF (7.9999) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
Updates are disabled when Margin Low (Ignore Faults and Warnings) is enabled.
MFR_IOUT_MIN
This command returns the minimum ADC measured values of the channel’s output current. This register is reset to
0x7BFF (approximately 225) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command
is executed.
MFR_TEMPERATURE_1_MIN
This command returns the minimum measured value of the external diode temperature in °C. This register is reset to
0x7BFF (approximately 225) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command
is executed.
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LTC2974
PMBus Command Description
Fault Logging
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
DEFAULT REF
VALUE PAGE
Send Byte
N
NA
70
MFR_FAULT_LOG_RESTORE 0xEB Command a transfer of the fault log
previously stored in EEPROM back to RAM.
Send Byte
N
NA
70
MFR_FAULT_LOG_CLEAR
0xEC Initialize the EEPROM block reserved for
fault logging and clear any previous fault
logging locks.
Send Byte
N
NA
71
MFR_FAULT_LOG_STATUS
0xED Fault logging status.
R Byte
N
Reg
Y
NA
71
MFR_FAULT_LOG
0xEE Fault log data bytes. This sequentially
retrieved data is used to assemble a
complete fault log.
R Block
N
Reg
Y
NA
71
MFR_FAULT_LOG_STORE
0xEA Command a transfer of the fault log from
RAM to EEPROM.
Fault Log Operation
A conceptual diagram of the fault log is shown in Figure 22. The fault log provides black box capability for the LTC2974.
During normal operation the contents of the status registers, the output voltage/current/temperature readings, the
input voltage readings, as well as peak and min values of these quantities, are stored in a continuously updated buffer
in RAM. You can think of the operation as being similar to a strip chart recorder. When a fault occurs, the contents are
written into EEPROM for non volatile storage. The EEPROM fault log is then locked. The part can be powered down
with the fault log available for reading at a later time.
RAM 255 BYTES
EEPROM 255 BYTES
8
ADC READINGS
CONTINUOUSLY
FILL BUFFER
TIME OF FAULT
TRANSFER TO
EEPROM AND
LOCK
...
...
AFTER FAULT
READ FROM
EEPROM AND
LOCK BUFFER
2974 F22
Figure 22: Fault Logging
MFR_FAULT_LOG_STORE
This command allows the user to transfer data from the RAM buffer to EEPROM.
MFR_FAULT_LOG_RESTORE
This command allows the user to transfer a copy of the fault-log data from the EEPROM to the RAM buffer. After a
restore the RAM buffer is locked until a successful MFR_FAULT_LOG read.
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LTC2974
PMBus Command Description
MFR_FAULT_LOG_CLEAR
This command initializes the EEPROM block reserved for fault logging. Any previous fault log stored in EEPROM will
be erased by this operation and logging of the fault log RAM to EEPROM will be enabled. Make sure that Mfr_fault_
log_status_ram = 0 before issuing the MFR_FAULT_LOG_CLEAR command.
MFR_FAULT_LOG_STATUS
This register is used to manage fault log events. The Mfr_fault_log_status_eeprom bit is set after a MFR_FAULT_LOG_
STORE command or a faulted-off event triggers a transfer of the fault log from RAM to EEPROM. This bit is cleared
by a MFR_FAULT_LOG_CLEAR command.
Mfr_fault_log_status_ram is set after a MFR_FAULT_ LOG_RESTORE to indicate that the data in the RAM has been
restored from EEPROM and not yet read using a MFR_FAULT_LOG command. This bit is cleared only by a successful
execution of an MFR_FAULT_LOG command.
MFR_FAULT_LOG_STATUS Data Contents
BIT(S) SYMBOL
OPERATION
b[7:2] Reserved
Read only, always returns 0s.
b[1]
Mfr_fault_log_status_ram
Fault log RAM status:
0: The fault log RAM allows updates.
1: The fault log RAM is locked until the next MFR_FAULT_LOG read.
b[0]
Mfr_fault_log_status_eeprom Fault log EEPROM status:
0: The transfer of the fault log RAM to the EEPROM is enabled.
1: The transfer of the fault log RAM to the EEPROM is inhibited.
MFR_FAULT_LOG
Read only. This 2040-bit (255 byte) data block contains a copy of the RAM buffer fault log. The RAM buffer is continuously updated after each ADC conversion as long as Mfr_fault_log_status_ram is clear.
With Mfr_config_all_fault_log_enable = 1 and Mfr_fault_log_status_eeprom = 0, the RAM buffer is transferred to EEPROM whenever an LTC2974 fault causes a channel to latch off or a MFR_FAULT_LOG_STORE command is received.
This transfer is delayed until the ADC has updated its READ values for all channels when Mfr_config_all_fast_fault_log
is clear, otherwise it happens within 24ms. This optional delay can be used to ensure that the slower ADC monitored
values are all updated for the case where a fast supervisor detected fault initiates the transfer to EEPROM.
Mfr_fault_log_status_eeprom is set high after the RAM buffer is transferred to EEPROM and not cleared until a
MFR_FAULT_LOG_CLEAR is received, even if the LTC2974 is reset or powered down. Fault log EEPROM transfers are
not initiated as a result of Status_mfr_discharge events.
During a MFR_FAULT_LOG read, data is returned one byte at a time as defined in Table 2. The fault log data is partitioned into two sections. The first section is referred to as the preamble and contains the Position_last pointer, time
information and peak and min values. The second section contains a chronological record of telemetry and requires
Position_last for proper interpretation. The fault log stores approximately 300ms of telemetry. To prevent timeouts
during block reads, it is recommended that Mfr_config_all_longer_pmbus_timeout be set to 1.
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LTC2974
PMBus Command Description
Table 2. Data Block Contents
Table 2. Data Block Contents
DATA
DATA
Position_last[7:0]
SharedTime[7:0]
BYTE* DESCRIPTION
0
1
BYTE* DESCRIPTION
Position of fault log pointer when
fault occurred.
Mfr_temperature_peak2[7:0]
39
41-bit share-clock counter value
when fault occurred. Counter
LSB is in 200μs increments.
Mfr_temperature_peak2[15:8]
40
Mfr_temperature_min2[7:0]
41
Mfr_temperature_min2[15:8]
42
43
SharedTime[15:8]
2
Mfr_iout_peak2[7:0]
SharedTime[23:16]
3
Mfr_iout_peak2[15:8]
44
SharedTime[31:24]
4
Mfr_iout_min2[7:0]
45
SharedTime[39:32]
5
Mfr_iout_min2[15:8]
46
SharedTime[40]
6
Mfr_vout_peak3[7:0]
47
Mfr_vout_peak0[7:0]
7
Mfr_vout_peak3[15:8]
48
Mfr_vout_peak0[15:8]
8
Mfr_vout_min3[7:0]
49
Mfr_vout_min0[7:0]
9
Mfr_vout_min3[15:8]
50
Mfr_vout_min0[15:8]
10
Mfr_temperature_peak3[7:0]
51
Mfr_temperature_peak0[7:0]
11
Mfr_temperature_peak3[15:8]
52
Mfr_temperature_peak0[15:8]
12
Mfr_temperature_min3[7:0]
53
Mfr_temperature_min0[7:0]
13
Mfr_temperature_min3[15:8]
54
Mfr_temperature_min0[15:8]
14
Mfr_iout_peak3[7:0]
55
Mfr_iout_peak0[7:0]
15
Mfr_iout_peak3[15:8]
56
Mfr_iout_peak0[15:8]
16
Mfr_iout_min3[7:0]
57
Mfr_iout_min0[7:0]
17
Mfr_iout_min3[15:8]
58
Mfr_iout_min0[15:8]
18
Status_vout0[7:0]
59
Mfr_vin_peak[7:0]
19
Status_iout0[7:0]
60
Mfr_vin_peak[15:8]
20
Status_mfr_specific0[7:0]
61
Mfr_vin_min[7:0]
21
Status_vout1[7:0]
62
Mfr_vin_min[15:8]
22
Status_iout1[7:0]
63
Mfr_vout_peak1[7:0]
23
Status_mfr_specific1[7:0]
64
Mfr_vout_peak1[15:8]
24
Status_vout2[7:0]
65
Mfr_vout_min1[7:0]
25
Status_iout2[7:0]
66
Mfr_vout_min1[15:8]
26
Status_mfr_specific2[7:0]
67
Mfr_temperature_peak1[7:0]
27
Status_vout3[7:0]
68
Mfr_temperature_peak1[15:8]
28
Status_iout3[7:0]
69
Mfr_temperature_min1[7:0]
29
Status_mfr_specific3[7:0]
70
Mfr_temperature_min1[15:8]
30
Mfr_iout_peak1[7:0]
31
Fault_log [Position_last]
71
Mfr_iout_peak1[15:8]
32
Fault_log [Position_last-1]
72
Mfr_iout_min1[7:0]
33
.
Mfr_iout_min1[15:8]
34
.
Mfr_vout_peak2[7:0]
35
.
Mfr_vout_peak2[15:8]
36
Fault_log [Position_last-170]
237
Mfr_vout_min2[7:0]
37
Reserved
Mfr_vout_min2[15:8]
38
238254
71 bytes for preamble
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LTC2974
PMBus Command Description
Table 2. Data Block Contents
DATA
POSITION
BYTE* DESCRIPTION
DATA
19
Read_vout1[15:8]
20
Status_vout1[7:0]
21
Status_mfr_specific1[7:0]
22
Read_temperature_1_1[7:0]
23
Read_temperature_1_1[15:8]
24
Status_temperature1[7:0]
25
Status_iout1[7:0]
26
Read_iout1[7:0]
27
Read_iout1[15:8]
28
Read_pout1[7:0]
29
Read_pout1[15:8]
30
Read_vout2[7:0]
31
Read_vout2[15:8]
32
Status_vout2[7:0]
33
Status_mfr_specific2[7:0]
34
Read_temperature_1_2[7:0]
DATA
35
Read_temperature_1_2[15:8]
0
Read_temperature_2[7:0]
36
Status_temperature2[7:0]
1
Read_temperature_2[15:8]
37
Status_iout2[7:0]
2
Read_vout0[7:0]
38
Read_iout2[7:0]
3
Read_vout0[15:8]
39
Read_iout2[15:8]
4
Status_vout0[7:0]
40
Read_pout2[7:0]
5
Status_mfr_specific0[7:0]
41
Read_pout2[15:8]
6
Read_temperature_1_0[7:0]
42
Read_vout3[7:0]
7
Read_temperature_1_0[15:8]
43
Read_vout3[15:8]
8
Status_temperature0[7:0]
44
Status_vout3[7:0]
9
Status_iout0[7:0]
45
Status_mfr_specific3[7:0]
10
Read_iout0[7:0]
46
Read_temperature_1_3[7:0]
11
Read_iout0[15:8]
47
Read_temperature_1_3[15:8]
12
Read_pout0[7:0]
48
Status_temperature3[7:0]
13
Read_pout0[15:8]
49
Status_iout3[7:0]
14
Read_vin[7:0]
50
Read_iout3[7:0]
15
Read_vin[15:8]
51
Read_iout3[15:8]
16
Status_input[7:0]
52
Read_pout3[7:0]
17
0x0
53
Read_pout3[15:8]
18
Read_vout1[7:0]
Number of loops: (238 – 71)/54
= 3.1
*Note that PMBus data byte numbers start at 1 rather than 0.
See Figure 13 Block Read.
The data returned between bytes 71 and 237 of the
previous table is interpreted using Position_last and the
following table. The key to identifying the data located in
byte 71 is to locate the DATA corresponding to POSITION
= Position_last in the next table. Subsequent bytes are
identified by decrementing the value of POSITION. For
example: If Position_last = 8 then the first data returned
in a block read is Status_temperature of page 0 followed
by Read_temperature_1[15:8] of page 0 followed by
Read_temperature_1[7:0] of page 0 and so on. See Table 3.
Table 3. Interpreting Cyclical Loop Data
POSITION
Total Bytes = 54
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LTC2974
PMBus Command Description
MFR_FAULT_LOG Read Example
PREAMBLE INFORMATION
The following table fully decodes a sample fault log read
with Position_last = 13 to help clarify the cyclical nature
of the operation.
Data Block Contents
PREAMBLE INFORMATION
BYTE
BYTE
NUMBER NUMBER
DECIMAL HEX
0
00
DATA
DESCRIPTION
Position_last[7:0] = 13 Position of faultlog pointer when
fault occurred.
1
01
SharedTime[7:0]
2
02
SharedTime[15:8]
3
03
SharedTime[23:16]
4
04
SharedTime[31:24]
5
05
SharedTime[39:32]
6
06
SharedTime[40]
7
07
Mfr_vout_peak0[7:0]
8
08
Mfr_vout_peak0[15:8]
41-bit shareclock counter
value when fault
occurred. Counter
LSB is in 200µs
increments.
BYTE
BYTE
NUMBER NUMBER
DECIMAL HEX
DATA
28
1C
Mfr_temperature_
peak1[15:8]
29
1D
Mfr_temperature_
min1[7:0]
30
1E
Mfr_temperature_
min1[15:8]
31
1F
Mfr_iout_peak1[7:0]
32
20
Mfr_iout_peak1[15:8]
33
21
Mfr_iout_min1[7:0]
34
22
Mfr_iout_min1[15:8]
35
23
Mfr_vout_peak2[7:0]
36
24
Mfr_vout_peak2[15:8]
37
25
Mfr_vout_min2[7:0]
38
26
Mfr_vout_min2[15:8]
39
27
Mfr_temperature_
peak2[7:0]
40
28
Mfr_temperature_
peak2[15:8]
41
29
Mfr_temperature_
min2[7:0]
9
09
Mfr_vout_min0[7:0]
10
0A
Mfr_vout_min0[15:8]
11
0B
Mfr_temperature_
peak0[7:0]
42
2A
Mfr_temperature_
min2[15:8]
12
0C
Mfr_temperature_
peak0[15:8]
43
2B
Mfr_iout_peak2[7:0]
13
0D
Mfr_temperature_
min0[7:0]
44
2C
Mfr_iout_peak2[15:8]
45
2D
Mfr_iout_min2[7:0]
46
2E
Mfr_iout_min2[15:8]
14
0E
Mfr_temperature_
min0[15:8]
47
2F
Mfr_vout_peak3[7:0]
15
0F
Mfr_iout_peak0[7:0]
48
30
Mfr_vout_peak3[15:8]
16
10
Mfr_iout_peak0[15:8]
49
31
Mfr_vout_min3[7:0]
17
11
Mfr_iout_min0[7:0]
50
32
Mfr_vout_min3[15:8]
18
12
Mfr_iout_min0[15:8]
51
33
19
13
Mfr_vin_peak_[7:0]
Mfr_temperature_
peak3[7:0]
20
14
Mfr_vin_peak_[15:8]
52
34
21
15
Mfr_vin_min_[7:0]
Mfr_temperature_
peak3[15:8]
22
16
Mfr_vin_min_[15:8]
53
35
Mfr_temperature_
min3[7:0]
23
17
Mfr_vout_peak1[7:0]
54
36
24
18
Mfr_vout_peak1[15:8]
Mfr_temperature_
min3[15:8]
25
19
Mfr_vout_min1[7:0]
55
37
Mfr_iout_peak3[7:0]
26
1A
Mfr_vout_min1[15:8]
56
38
Mfr_iout_peak3[15:8]
27
1B
Mfr_temperature_
peak1[7:0]
57
39
Mfr_iout_min3[7:0]
58
3A
Mfr_iout_min3[15:8]
59
3B
Status_vout0[7:0]
DESCRIPTION
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LTC2974
PMBus Command Description
PREAMBLE INFORMATION
CYCLICAL MUX LOOP DATA
BYTE
BYTE
NUMBER NUMBER
DECIMAL HEX
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
DECIMAL HEX DECIMAL
DATA
DESCRIPTION
MUX LOOP 1
60
3C
Status_iout0[7:0]
61
3D
Status_
temperature0[7:0]
85
55
53
Read_pout3[15:8]
86
56
52
Read_pout3[7:0]
62
3E
Status_vout1[7:0]
87
57
51
Read_iout3[15:8]
63
3F
Status_iout1[7:0]
88
58
50
Read_iout3[7:0]
64
40
Status_
temperature1[7:0]
89
59
49
Status_iout3[7:0]
90
5A
48
Status_
temperature3[7:0]
65
41
Status_vout2[7:0]
66
42
Status_iout2[7:0]
91
5B
47
67
43
Status_
temperature2[7:0]
Read_
temperature_1_3[15:8]
92
5C
46
68
44
Status_vout3[7:0]
Read_
temperature_1_3[7:0]
69
45
Status_iout3[7:0]
93
5D
45
70
46
Status_
temperature3[7:0]
Status_mfr_
specific3[7:0]
94
5E
44
Status_vout3[7:0]
95
5F
43
Read_vout3[15:8]
96
60
42
Read_vout3[7:0]
97
61
41
Read_pout2[15:8]
98
62
40
Read_pout2[7:0]
99
63
39
Read_iout2[15:8]
100
64
38
Read_iout2[7:0]
101
65
37
Status_iout2[7:0]
102
66
36
Status_
temperature2[7:0]
103
67
35
Read_
temperature_1_2[15:8]
104
78
34
Read_
temperature_1_2[7:0]
105
69
33
Status_mfr_
specific2[7:0]
106
6A
32
Status_vout2[7:0]
107
6B
31
Read_vout2[15:8]
108
6C
30
Read_vout2[7:0]
109
6D
29
Read_pout1[15:8]
110
6E
28
Read_pout1[7:0]
111
6F
27
Read_iout1[15:8]
112
70
26
Read_iout1[7:0]
113
71
25
Status_iout1[7:0]
114
72
24
Status_
temperature2[7:0]
115
73
23
Read_
temperature_1_1[15:8]
End of Preamble
CYCLICAL MUX LOOP DATA
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
DECIMAL HEX DECIMAL
MUX LOOP 0
71
47
13
Read_pout0[15:8]
72
48
12
Read_pout0[7:0]
73
49
11
Read_iout0[15:8]
74
4A
10
Read_iout0[7:0]
75
4B
9
Status_iout0[7:0]
76
4C
8
Status_
temperature0[7:0]
77
4D
7
Read_
temperature_1_0[15:8]
78
4E
6
Read_
temperature_1_0[7:0]
79
4F
5
Status_mfr_
specific0[7:0]
80
50
4
Status_vout0[7:0]
81
51
3
Read_vout0[15:8]
82
52
2
Read_vout0[7:0]
83
53
1
Read_
temperature_2[15:8]
84
54
0
Read_
temperature_2[7:0]
54 BYTES PER
LOOP
Position_last
54 BYTES PER
LOOP
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LTC2974
PMBus Command Description
CYCLICAL MUX LOOP DATA
CYCLICAL MUX LOOP DATA
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
DECIMAL HEX DECIMAL
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
DECIMAL HEX DECIMAL
MUX LOOP 1
54 BYTES PER
LOOP
MUX LOOP 2
116
74
22
Read_
temperature_1_1[7:0]
144
90
48
Status_
temperature3[7:0]
117
75
21
Status_mfr_
specific1[7:0]
145
91
47
Read_
temperature_1_3[15:8]
118
76
20
Status_vout1[7:0]
146
92
46
119
77
19
Read_vout1[15:8]
Read_
temperature_1_3[7:0]
120
78
18
Read_vout1[7:0]
147
93
45
121
79
17
0x0
Status_mfr_
specific3[7:0]
122
7A
16
Status_input[7:0]
148
94
44
Status_vout3[7:0]
123
7B
15
Read_vin[15:8]
149
95
43
Read_vout3[15:8]
124
7C
14
Read_vin[7:0]
150
96
42
Read_vout3[7:0]
125
7D
13
Read_pout0[15:8]
151
97
41
Read_pout2[15:8]
126
7E
12
Read_pout0[7:0]
152
98
40
Read_pout2[7:0]
127
7F
11
Read_iout0[15:8]
153
99
39
Read_iout2[15:8]
128
80
10
Read_iout0[7:0]
154
9A
38
Read_iout2[7:0]
129
81
9
Status_iout0[7:0]
155
9B
37
Status_iout2[7:0]
130
82
8
Status_
temperature0[7:0]
156
9C
36
Status_
temperature2[7:0]
131
83
7
Read_
temperature_1_0[15:8]
157
9D
35
Read_
temperature_1_2[15:8]
132
84
6
Read_
temperature_1_0[7:0]
158
9E
34
Read_
temperature_1_2[7:0]
133
85
5
Status_mfr_
specific0[7:0]
159
9F
33
Status_mfr_
specific2[7:0]
134
86
4
Status_vout0[7:0]
160
A0
32
Status_vout2[7:0]
135
87
3
Read_vout0[15:8]
161
A1
31
Read_vout2[15:8]
136
88
2
Read_vout0[7:0]
162
A2
30
Read_vout2[7:0]
137
89
1
Read_
temperature_2[15:8]
163
A3
29
Read_pout1[15:8]
164
A4
28
Read_pout1[7:0]
165
A5
27
Read_iout1[15:8]
138
8A
0
Read_
temperature_2[7:0]
166
A6
26
Read_iout1[7:0]
CYCLICAL MUX LOOP DATA
167
A7
25
Status_iout1[7:0]
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
DECIMAL HEX DECIMAL
168
A8
24
Status_
temperature2[7:0]
169
A9
23
Read_
temperature_1_1[15:8]
170
AA
22
Read_
temperature_1_1[7:0]
171
AB
21
Status_mfr_
specific1[7:0]
MUX LOOP 2
139
8B
53
Read_pout3[15:8]
140
8C
52
Read_pout3[7:0]
141
8D
51
Read_iout3[15:8]
142
8E
50
Read_iout3[7:0]
143
8F
49
Status_iout3[7:0]
54 BYTES PER
LOOP
172
AC
20
Status_vout1[7:0]
173
AD
19
Read_vout1[15:8]
54 BYTES PER
LOOP
2974fc
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LTC2974
PMBus Command Description
CYCLICAL MUX LOOP DATA
CYCLICAL MUX LOOP DATA
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
DECIMAL HEX DECIMAL
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
DECIMAL HEX DECIMAL
174
MUX LOOP 2
AE
18
Read_vout1[7:0]
175
AF
17
0x0
176
B0
16
Status_input[7:0]
177
B1
15
Read_vin[15:8]
178
B2
14
Read_vin[7:0]
179
B3
13
Read_pout0[15:8]
180
B4
12
Read_pout0[7:0]
181
B5
11
Read_iout0[15:8]
182
B6
10
Read_iout0[7:0]
183
B7
9
Status_iout0[7:0]
184
B8
8
Status_
temperature0[7:0]
185
B9
7
Read_
temperature_1_0[15:8]
186
BA
6
Read_
temperature_1_0[7:0]
187
BB
5
Status_mfr_
specific0[7:0]
188
BC
4
Status_vout0[7:0]
189
BD
3
Read_vout0[15:8]
190
BE
2
191
BF
192
C0
54 BYTES PER
LOOP
MUX LOOP 3
201
C9
45
Status_mfr_
specific3[7:0]
202
CA
44
Status_vout3[7:0]
203
CB
43
Read_vout3[15:8]
204
CC
42
Read_vout3[7:0]
205
CD
41
Read_pout2[15:8]
206
CE
40
Read_pout2[7:0]
207
CF
39
Read_iout2[15:8]
208
D0
38
Read_iout2[7:0]
209
D1
37
Status_iout2[7:0]
210
D2
36
Status_
temperature2[7:0]
211
D3
35
Read_
temperature_1_2[15:8]
212
D4
34
Read_
temperature_1_2[7:0]
213
D5
33
Status_mfr_
specific2[7:0]
214
D6
32
Status_vout2[7:0]
215
D7
31
Read_vout2[15:8]
Read_vout0[7:0]
216
D8
30
Read_vout2[7:0]
1
Read_
temperature_2[15:8]
217
D9
29
Read_pout1[15:8]
218
DA
28
Read_pout1[7:0]
0
Read_
temperature_2[7:0]
219
DB
27
Read_iout1[15:8]
220
DC
26
Read_iout1[7:0]
221
DD
25
Status_iout1[7:0]
222
DE
24
Status_
temperature2[7:0]
223
DF
23
Read_
temperature_1_1[15:8]
224
E0
22
Read_
temperature_1_1[7:0]
225
E1
21
Status_mfr_
specific1[7:0]
CYCLICAL MUX LOOP DATA
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
DECIMAL HEX DECIMAL
MUX LOOP 3
54 BYTES PER
LOOP
193
C1
53
Read_pout3[15:8]
194
C2
52
Read_pout3[7:0]
195
C3
51
Read_iout3[15:8]
196
C4
50
Read_iout3[7:0]
197
C5
49
Status_iout3[7:0]
226
E2
20
Status_vout1[7:0]
198
C6
48
Status_
temperature_3[7:0]
227
E3
19
Read_vout1[15:8]
228
E4
18
Read_vout1[7:0]
229
E5
17
0x0
230
E6
16
Status_input[7:0]
231
E7
15
Read_vin[15:8]
232
E8
14
Read_vin[7:0]
199
C7
47
Read_
temperature_1_3[15:8]
200
C8
46
Read_
temperature_1_3[7:0]
54 BYTES PER
LOOP
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LTC2974
PMBus Command Description
CYCLICAL MUX LOOP DATA
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
DECIMAL HEX DECIMAL
MUX LOOP 3
54 BYTES PER
LOOP
233
E9
13
Read_pout0[15:8]
234
EA
12
Read_pout0[7:0]
235
EB
11
Read_iout0[15:8]
236
EC
10
Read_iout0[7:0]
237
ED
9
Status_iout0[7:0]
Last valid fault
log byte
238
EE
0x00
Bytes EE - FE
return 0x00
239
EF
0x00
240
F0
0x00
241
F1
0x00
242
F2
0x00
243
F3
0x00
244
F4
0x00
245
F5
0x00
246
F6
0x00
247
F7
0x00
248
F8
0x00
249
F9
0x00
250
FA
0x00
251
FB
0x00
252
FC
0x00
253
FD
0x00
254
FE
0x00
This is PMBUS
byte 255. It must
be read to clear
Mfr_fault_log_
status_ram.
Identification/Information
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
DEFAULT REF
VALUE PAGE
CAPABILITY
0x19 Summary of PMBus optional communication
protocols supported by this device.
R Byte
N
Reg
0xB0
79
PMBUS_REVISION
0x98 PMBus revision supported by this device.
Current revision is 1.1.
R Byte
N
Reg
0x11
79
MFR_SPECIAL_ID
0xE7 Manufacturer code for identifying the LTC2974.
R Word
N
Reg
Y
0x0213
79
MFR_SPECIAL_LOT
0xE8 Customer dependent codes that identify the
factory programmed user configuration stored
in EEPROM. Contact factory for default value.
R Byte
Y
Reg
Y
79
2974fc
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LTC2974
PMBus Command Description
CAPABILITY
The CAPABILITY command provides a way for a host system to determine some key capabilities of the LTC2974.
CAPABILITY Data Contents
BIT(S) SYMBOL
b[7]
Capability_pec
b[6:5] Capability_scl_max
b[4]
OPERATION
Hard coded to 1 indicating Packet Error Checking is supported. Reading the Mfr_config_all_pec_en bit will indicate
whether PEC is currently required.
Hard coded to 01b indicating the maximum supported bus speed is 400kHz.
Capability_smb_alert Hard coded to 1 indicating this device does have an ALERTB pin and does support the SMBus Alert Response Protocol.
b[3:0] Reserved
Always returns 0.
PMBus_REVISION
PMBus_REVISION Data Contents
BIT(S) SYMBOL
OPERATION
b[7:0] PMBus_rev
Reports the PMBus standard revision compliance. This is hard-coded to 0x11 for revision 1.1.
MFR_SPECIAL_ID
This register contains the manufacturer ID for the LTC2974. Always returns 0x0213.
MFR_SPECIAL_LOT
These paged registers contain information that identifies the user configuration that was programmed at the factory.
Contact the factory to request a custom factory programmed user configuration and special lot number.
User Scratchpad
COMMAND NAME
CMD
CODE
DESCRIPTION
USER_DATA_00
0xB0
Manufacturer reserved for LTpowerPlay.
R/W Word
N
Reg
Y
N/A
79
USER_DATA_01
0xB1
Manufacturer reserved for LTpowerPlay.
R/W Word
Y
Reg
Y
N/A
79
USER_DATA_02
0xB2
OEM Reserved.
R/W Word
N
Reg
Y
N/A
79
USER_DATA_03
0xB3
Scratchpad location.
R/W Word
Y
Reg
Y
0x00
79
USER_DATA_04
0xB4
Scratchpad location.
R/W Word
N
Reg
Y
0x00
79
MFR_LTC_RESERVED_1
0xB5
Manufacturer reserved.
R/W Word
Y
Reg
Y
NA
79
MFR_LTC_RESERVED_2
0xBC
Manufacturer reserved.
R/W Word
Y
Reg
NA
79
TYPE
PAGED FORMAT UNITS EEPROM
DEFAULT REF
VALUE PAGE
USER_DATA_00, USER_DATA_01, USER_DATA_02, USER_DATA_03, USER_DATA_04, MFR_LTC_RESERVED_1
and MFR_LTC_RESERVED_2
These registers are provided as user scratchpad and additional manufacturer reserved locations.
USER_DATA_03 and USER_DATA_04 are available for user scratch pad use. These 10 bytes (1 unpaged word plus
4 paged words) might be used for traceability or revision information such as serial number, board model number,
assembly location, or assembly date.
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LTC2974
Applications Information
Overview
The LTC2974 is a power management IC that is capable
of sequencing, margining, trimming, supervising output
voltage for OV/UV conditions, supervising output current
for OC/UC conditions, fault management, and voltage/
current/temperature readback for four DC/DC converter
channels. Input voltage and LTC2974 junction temperature
readback are also available. Linear Technology Power
System Managers can coordinate operation among multiple devices using common SHARE_CLK, FAULTB, and
CONTROL pins. The LTC2974 utilizes a PMBus compliant
interface and command set.
Powering the LTC2974
The LTC2974 can be powered two ways. The first method
requires that a voltage between 4.5V and 15V be applied
to the VPWR pin. See Figure 23. An internal linear regulator converts VPWR down to 3.3V which drives all of the
internal circuitry of the LTC2974.
Alternatively, power from an external 3.3V supply may be
applied directly to the VDD33 pins 11 and 12 using a voltage
between 3.13V and 3.47V. See Figure 24. Tie VPWR to the
4.5V < VPWR < 15V
0.1µF
0.1µF
VPWR
VIN_SNS
VDD33
VDD33
VDD25
0.1µF
LTC2974*
2978 F23
*SOME DETAILS
OMITTED FOR CLARITY
Figure 23. Powering LTC2974 Directly from an Intermediate Bus
VDD33
LTC2974*
VDD25
0.1µF
The command register settings described herein are intended as a reference and for the purpose of understanding
the registers in a software development environment. In
actual practice, the LTC2974 can be completely configured
for stand-alone operation with the LTC USB to I2C/SMBus/
PMBus controller (DC1613) and software GUI using intuitive menu driven objects.
Sequence, Servo, Margin and Restart
Operations
Command Units On or Off
Three control parameters determine how a particular channel is turned on and off: The CONTROL pins, the OPERATION
command and the value of the input voltage measured at the
VIN_SNS pin (VIN). In all cases, VIN must exceed VIN_ON in
order to enable the device to respond to the CONTROL pins
or OPERATION commands. When VIN drops below VIN_OFF
an immediate OFF or sequence off after TOFF_DELAY of all
channels will result (See Mfr_config_track_enn). Refer
to the OPERATION section in the data sheet for a detailed
description of the ON_OFF_CONFIG command.
1. A DC/DC converter may be configured to turn on any
time VIN exceeds VIN_ON.
2. A DC/DC converter may be configured to turn on only
when it receives an OPERATION command.
3. A DC/DC converter may be configured to turn on only
via the CONTROL pin.
VPWR
VDD33
Setting Command Register Values
Some examples of typical ON/OFF configurations are:
VDD25
GND
EXTERNAL 3.3V
0.1µF
VDD33 pins. All functionality is available when using this
alternate power method. The higher voltages needed for
the VOUT_EN pins and bias for the VSENSE pins are charge
pumped from VDD33.
VDD25
GND
2978 F24
*SOME DETAILS
OMITTED FOR CLARITY
Figure 24. Powering LTC2974 from External 3.3V Supply
4. A DC/DC converter may be configured to turn on only
when it receives an OPERATION command and the
CONTROL pin is asserted.
On Sequencing
The TON_DELAY command sets the amount of time that
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a channel will wait following the start of an ON sequence
before its VOUT_EN pin will enable a DC/DC converter. Once
the DC/DC converter has been enabled, the TON_RISE value
determines the time at which the device soft-connects
the DAC and servos the DC/DC converter output to the
VOUT_COMMAND value. The TON_MAX_FAULT_LIMIT
value determines the time at which the device checks
for an undervoltage condition. If a TON_MAX_FAULT occurs, the channel can be configured to disable the DC/DC
converter and propagate the fault to other channels using
the bidirectional FAULTB pins. Figure 25 shows a typical
on-sequence using the CONTROL pin. Note that overvoltage faults are checked against the VOUT_OV_FAULT_LIMIT
value at all times the device is powered up and not in a
reset state nor margining while ignoring OVs.
On State Operation
Once a channel has reached the ON state, the OPERATION command can be used to command the DC/DC
converter’s output to margin high, margin low, or return to
a nominal output voltage indicated by VOUT_COMMAND.
The user also has the option of configuring a channel to
continuously trim the output of the DC/DC converter to the
VOUT_COMMAND voltage, or the channel’s VDACn output
can be placed in a high impedance state thus allowing the
DC/DC converter output voltage to go to its nominal value,
VDCn(NOM). Refer to the MFR_CONFIG_LTC2974 command
for details on how to configure the output voltage servo.
Servo Modes
The ADC, DAC and internal processor comprise a digital
servo loop that can be configured to operate in several
useful modes. The servo target refers to the desired output
voltage.
Continuous/non-continuous trim mode: MFR_
CONFIG_LTC2974 b[7]. In continuous trim mode, the
servo will update the DAC in a closed loop fashion each
time it takes a VOUT reading. The update rate is determined
by the time it takes to step through the ADC MUX which is
no more than tUPDATE_ADC. See Electrical Characteristics
table Note 5. In non-continuous trim mode, the servo will
drive the DAC until the ADC measures the output voltage
desired and then stop updating the DAC.
Non-continuous servo on warn mode: MFR_CONFIG_
LTC2974 b[7] = 0, b[6] = 1. When in non-continuous
mode, the LTC2974 will re-trim (re-servo) the output if
the output drifts beyond the OV or UV warn limits.
VCONTROL
VOUT_EN
VOUT_OV_FAULT_LIMIT
VOUT_COMMAND
VDC(NOM)
VOUT_UV_FAULT_LIMIT
VOUT
2974 F25
TON_DELAY
TON_RISE
TON_MAX_FAULT_LIMIT
Figure 25. Typical ON Sequence Using Control Pin
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LTC2974
Applications Information
DAC Modes
VOUT Off Threshold Voltage
The DACs that drive the VDACn pins can operate in several
useful modes. See MFR_CONFIG_LTC2974.
The MFR_VOUT_DISCHARGE_THRESHOLD command
register allows the user to specify the OFF threshold that
the output voltage must decay below before the channel
can enter/re-enter the ON state. The OFF threshold voltage
is specified by multiplying MFR_VOUT_DISCHARGE_
THRESHOLD and VOUT_COMMAND. In the event that an
output voltage has not decayed below its OFF threshold
before attempting to enter the ON state, the channel will
continue to be held off, the appropriate bit is set in the
STATUS_MFR_SPECIFIC register, and the ALERTB pin will
be asserted low. When the output voltage has decayed
below its OFF threshold, the channel can enter the ON state.
• Soft-connect. Using the LTC patented soft-connect
feature, the DAC output is driven to within 1 LSB of
the voltage at the DC/DC’s feedback node before connecting, to avoid introducing transients on the output.
This mode is used when servoing the output voltage.
During startup, the LTC2974 waits until TON_RISE has
expired before connecting the DAC. This is the most
common operating mode.
• Disconnected. DAC output is high Z.
• DAC manual with soft-connect. Non servo mode. The
DAC soft-connects to the feedback node. Soft-connect
drives the DAC code to match the voltage at the feedback
node. After connection, the DAC is moved by writing
DAC codes to the MFR_DAC register.
• DAC manual with hard connect. Non servo mode. The
DAC hard connects to the feedback node using the current value in MFR_DAC. After connection, the DAC is
moved by writing DAC codes to the MFR_DAC register.
Margining
The LTC2974 margins and trims the output of a DC/DC
converter by forcing a voltage across an external resistor
connected between the DAC output and the feedback node
or the trim pin. Preset limits for margining are stored in
the VOUT_MARGIN_HIGH/LOW registers. Margining is
actuated by writing the appropriate bits to the OPERATION register.
Margining requires the DAC to be connected. Margin
requests that occur when the DAC is disconnected will
be ignored.
Off Sequencing
An off sequence is initiated using the CONTROL pin or the
OPERATION command. The TOFF_DELAY value determines
the amount of time that elapses from the beginning of the
off sequence until each channel’s VOUT_EN pin is pulled
low, thus disabling its DC/DC converter.
Automatic Restart via MFR_RESTART_DELAY
Command and CONTROL pin
An automatic restart sequence can be initiated by driving
the CONTROL pin to the off state for >10μs and then releasing it. The automatic restart disables all VOUT_EN pins
that are mapped to a particular CONTROL pin for a time
period = MFR_RESTART_DELAY and then starts all DC/
DC Converters according to their respective TON_DELAYs.
(see Figure 26). VOUT_EN pins are mapped to one of the
CONTROL pins by the MFR_CONFIG_LTC2974 command.
This feature allows a host that is about to reset to restart
the power in a controlled manner after it has recovered.
CONTROL
PIN BOUNCE
VCONTROL
VOUT_EN0
2974 F26
TOFF_DELAY0
MFR_RESTART_DELAY
TON_DELAY0
Figure 26. Off Sequence with Automatic Restart
Fault Management
Output Overvoltage, Undervoltage, Overcurrent, and
Undercurrent Faults
The high-speed voltage supervisor OV and UV fault thresholds are configured using the VOUT_OV_FAULT_LIMIT
and VOUT_UV_FAULT_LIMIT commands, respectively.
The VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_
RESPONSE registers determine the responses to
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OV/UV faults. In addition, the high-speed current supervisor OC and UC fault thresholds are configured using the
IOUT_OC_FAULT_LIMIT and IOUT_UC_FAULT_LIMIT commands, respectively. The IOUT_OC_FAULT_RESPONSE
and IOUT_UC_FAULT_RESPONSE commands determine
the responses to OC/UC faults. Fault responses can range
from disabling the DC/DC converter immediately, waiting
to see if the fault condition persists for some interval before disabling the DC/DC converter, or allowing the DC/DC
converter to continue operating in spite of the fault. If a
DC/DC converter is disabled, the LTC2974 can be configured to retry one to six times, retry continuously without
limitation, or latch-off. The retry interval is specified using
the MFR_RETRY_DELAY command. Latched faults are
reset by toggling the CONTROL pin, using the OPERATION
command, or removing and reapplying the bias voltage to
the VIN_SNS pin. All fault and warning conditions result in
the ALERTB pin being asserted low and the corresponding
bits being set in the status registers. The CLEAR_FAULTS
command resets the contents of the status registers and
de-asserts the ALERTB output.
VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT, and
IOUT_OC_WARN_LIMIT registers, respectively. Note that
there is no IOUT UC warning threshold. If a warning occurs,
the corresponding bits are set in the status registers and
the ALERTB output is asserted low. Note that a warning
will never cause a VOUT_EN output pin to disable a DC/DC
converter.
Output Overvoltage, Undervoltage, and Overcurrent
Warnings
Figure 27 shows an application circuit where the AUXFAULTB output is used to trigger a SCR crowbar on the
intermediate bus in order to protect the DC/DC converter’s
load from a catastrophic fault such as a stuck top-gate.
OV, UV, and OC warning thresholds are processed by
the LTC2974’s ADC. These thresholds are set by the
RSENSE
0.007Ω
4.5V < VIBUS < 15V
Configuring the AUXFAULTB Output
The AUXFAULTB output may be used to indicate an output
OV, OC, or UC fault. Use the MFR_CONFIG2_LTC2974
and MFR_CONFIG3_LTC2974 registers to configure the
AUXFAULTB pin to assert low in response to VOUT_OV,
IOUT_OC or IOUT_UC fault conditions. The AUXFAULTB
output will stop pulling low when the LTC2974 is commanded to re-enter the ON state following a faulted-off
condition.
A charge-pumped 5µA pull-up to 12V is also available on
the AUXFAULTB output. Refer to the MFR_CONFIG_ALL_
LTC2974 register description in the PMBUS COMMAND
DESCRIPTION section for more information.
Q1
Si4894BDY
VIN
CBYPASS
VIN_SNS
VPWR
VCC
GATE
LTC4210-1
24.3k
10k
SENSE
ON
TIMER GND
0.22µF
100Ω
68Ω
0.01µF
LTC2974*
10k
MMBT2907
4.99k
DC/DC
CONVERTER
VSENSEP0
0.1µF
0.01µF
VOUT
VDAC0
MCR12DC
LOAD
VSENSEM0
VOUT_EN0
220Ω
SGND
0.01µF
RUN/SS
GND
2974 F27
REFP
AUXFAULTB
VFB
REFM
GND
VDD33 VDD33
0.1µF
VDD25 VDD25
0.1µF
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF FOUR CHANNELS SHOWN
Figure 27. Application Circuit with Crowbar Protection on Intermediate Bus
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LTC2974
Applications Information
Multi-Channel Fault Management
Multi-channel fault management is handled using the
bidirectional FAULTB pins. Figure 28 illustrates the connections between channels and the FAULTB pins.
• The MFR_FAULTBn_PROPAGATE register acts like a
programmable switch that allows faulted_off conditions
from a particular channel (PAGE) to propagate to either
FAULTB output. The MFR_FAULTBn_RESPONSE register
controls similar switches on the inputs to each channel
that allow any channel to shut down in response to any
combination of the FAULTB pins. Channels responding
to a FAULTB pin pulling low will attempt a new start
sequence when the FAULTB pin in question is released
by the faulted channel.
• A FAULTB pin can also be asserted low by an external
driver in order to initiate an immediate off-sequence
after a 10μs deglitch delay.
Interconnect Between Multiple LTC2974’s
Figure 29 shows how to interconnect the pins in a typical
multi-LTC2974 array.
• All VIN_SNS lines should be tied together in a star
type connection at the point where VIN is to be sensed.
This will minimize timing errors for the case where the
ON_OFF_CONFIG is configured to start the LTC2974 based
on VIN and ignore the CONTROL line and the OPERATION
Mfr_faultb0_response, page = 0
Mfr_faultb1_response, page = 0
CHANNEL 0
EVENT PROCESSOR
PAGE = 0
Mfr_faultb0_response, page = 1
Mfr_faultb1_response, page = 1
CHANNEL 1
EVENT PROCESSOR
PAGE = 1
Mfr_faultb0_response, page = 2
Mfr_faultb1_response, page = 2
CHANNEL 2
EVENT PROCESSOR
PAGE = 2
Mfr_faultb0_response, page = 3
Mfr_faultb1_response, page = 3
CHANNEL 3
EVENT PROCESSOR
PAGE = 3
command. In multi-part applications that are sensitive to
timing differences, it is recommended that the Vin_share_
enable bit of the MFR_CONFIG_ALL_LTC2974 register be
set high in order to allow SHARE_CLK to synchronize on/
off sequencing in response to the VIN_ON and VIN_OFF
thresholds.
• Connecting all AUXFAULTB lines together will allow
selected faults on any DC/DC converter’s output in the
array to shut off a common input switch.
• ALERTB is typically one line in an array of PMBus converters. The LTC2974 allows a rich combination of faults
and warnings to be propagated to the ALERTB pin.
• WDI/RESETB can be used to put the LTC2974 in the
power-on reset state. Pull WDI/RESETB low for at least
tRESETB to enter this state.
• The FAULTB lines can be connected together to create
fault dependencies. Figure 29 shows a configuration
where a fault on any FAULTB will pull all others low.
This is useful for arrays where it is desired to abort
a startup sequence in the event any channel does not
come up (see Figure 30).
• PWRGD reflects the status of the outputs that are
mapped to it by the MFR_PWRGD_EN command. Figure 29 shows all the PWRGD pins connected together,
but any combination may be used.
FAULTED_OFF
Mfr_faultb0_propagate_chan0
Mfr_faultb1_propagate_chan0
FAULTED_OFF
FAULTB0
Mfr_faultb0_propagate_chan1
Mfr_faultb1_propagate_chan1
FAULTED_OFF
Mfr_faultb0_propagate_chan2
FAULTB1
Mfr_faultb1_propagate_chan2
FAULTED_OFF
Mfr_faultb0_propagate_chan3
Mfr_faultb1_propagate_chan3
2974 F28
Figure 28. Channel Fault Management Block Diagram
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TO VIN OF
DC/DCs TO HOST CONTROLLER
TO INPUT
SWITCH
LTC2974 #1
VIN_SNS
AUXFAULTB
LTC2974 #n
VIN_SNS
AUXFAULTB
SDA
SCL
ALERTB
CONTROL0
SDA
SCL
ALERTB
CONTROL0
WDI/RESETB
FAULTB0
WDI/RESETB
FAULTB0
SHARE_CLK
PWRGD
SHARE_CLK
PWRGD
GND
GND
TO OTHER LTC2974s–10k EQUIVALENT PULL-UP RECOMMENDED
ON EACH LINE EXCEPT SHARE_CLK (USE 5.49k)
2974 F29
Figure 29. Typical Connections between Multiple LTC2974s
VCONTROL
VOUT0
VOUT1
VOUT2
VOUTn
BUSSED
VFAULTBn PINS
TON_DELAY0
TON_DELAY1
TON_DELAY2
•
•
•
•
•
•
TON_DELAYn
2974 F30
TON_MAX_FAULT1
Figure 30. Aborted On-Sequence Due to Channel 1 Short
Application Circuits
Trimming and Margining DC/DC Converters with
External Feedback Resistors
Figure 31 shows a typical application circuit for trimming/
margining a power supply with an external feedback
network. The VSENSEP0 and VSENSEM0 differential inputs
sense the load voltage directly, and a correction voltage
is developed on the VDAC0 pin by the closed-loop servo
algorithm. The VDAC0 output is connected to the DC/DC
converter’s feedback node through resistor R30. For this
configuration, set Mfr_config_dac_pol to 0.
Four-Step Resistor Selection Procedure for DC/DC
Converters with External Feedback Resistors
The following four-step procedure should be used to
calculate the resistor values required for the application
circuit shown in Figure 31.
1. Assume values for feedback resistor R20 and the nominal
DC/DC converter output voltage VDC(NOM), and solve
for R10.
VDC(NOM) is the output voltage of the DC/DC converter
when the LTC2974’s VDAC0 pin is in a high impedance
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Applications Information
VIN
4.5V < VIBUS < 15V
VPWR
0.1µF
VIN_SNS
VOUT
VDAC0
VDD33
VDD33
VDD25
LTC2974*
R20
VFB
LOAD
R10
VDD25
0.1µF
DC/DC
CONVERTER
R30
VSENSEP0
VSENSEM0
SGND
VOUT_EN0
RUN/SS
GND
GND
2974 F31
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF FOUR CHANNELS SHOWN
Figure 31. Application Circuit for DC/DC Converters with External Feedback Resistors
state. R10 is a function of R20, VDC(NOM), the voltage at
the feedback node (VFB) when the loop is in regulation,
and the feedback node’s input current (IFB).
R10 =
R20 • VFB
VDC(NOM) – IFB • R20 – VFB
(1)
2. Solve for the value of R30 that yields the maximum
required DC/DC converter output voltage VDC(MAX).
When VDAC0 is at 0V, the output of the DC/DC converter
is at its maximum voltage.
R30 ≤
R20 • VFB
VDC(MAX) – VDC(NOM)
(2)
3. Solve for the minimum value of VDAC0 that is needed
to yield the minimum required DC/DC converter output
voltage VDC(MIN).
The DAC has two full-scale settings, 1.38V and 2.65V. In
order to select the appropriate full-scale setting, calculate
the minimum required VDAC0(F/S) output voltage:
(
)
VDAC0(F/S) > VDC(NOM) – VDC(MIN) •
R30
+ VFB (3)
R20
4. Re-calculate the minimum, nominal, and maximum
DC/DC converter output voltages and the resulting
margining resolution.
R20
VDC(NOM) = VFB • 1+
+ I • R20
R10 FB
R20
• VDAC0(F /S) – VFB
R30
R20
VDC(MAX) = VDC(NOM) +
• VFB
R30
R20
• VDAC0(F /S)
VRES = R30
V/DAC LSB
1024
VDC(MIN) = VDC(NOM) –
(
(4)
)
(5)
(6)
(7)
Trimming and Margining DC/DC Converters with a
TRIM Pin
Figure 32 illustrates a typical application circuit for trimming/margining the output voltage of a DC/DC converter
with a TRIM Pin. The LTC2974’s VDAC0 pin connects to
the TRIM pin through resistor R30. For this configuration,
set the DAC polarity bit Mfr_config_dac_pol in MFR_CONFIG_LTC2974 to 1.
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VIN
4.5V < VIBUS < 15V
0.1µF
VPWR
VIN_SNS
VDD33
VSENSEP0
VDAC0
VDD33
VDD25
0.1µF
R30
LTC2974*
LOAD
VDD25
VO+
TRIM
VSENSE+
DC/DC
CONVERTER
VSENSEM0
VSENSE–
VOUT_EN0
ON/OFFB
VO–
GND
2974 F32
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF FOUR CHANNELS SHOWN
Figure 32. Application Circuit for DC/DC Converters with Trim Pin
DC/DC converters with a TRIM pin may be margined
high or low by connecting an external resistor between
the TRIM pin and either the VSENSEP or VSENSEM pin. The
relationships between these resistors and the Δ% change
in the output voltage of the DC/DC converter are typically
expressed as:
RTRIM _ DOWN
R
• 50
= TRIM
– RTRIM
∆DOWN %
(8)
RTRIM _ UP =
RTRIM
V • (100 + ∆UP %) 50
• DC
–
– 1 (9)
∆UP %
2 • VREF • ∆UP %
where RTRIM is the resistance looking into the TRIM pin,
VREF is the TRIM pin’s open-circuit output voltage and
VDC is the DC/DC converter’s nominal output voltage.
ΔUP% and ΔDOWN% denote the percentage change in the
converter’s output voltage when margining up or down,
respectively.
Two-Step Resistor and DAC Full-Scale Voltage Selection
Procedure for DC/DC Converters with a TRIM Pin
The following two-step procedure should be used to calculate the resistor value for R30 and the required full-scale
DAC voltage (refer to Figure 32).
1. Solve for R30:
50 – ∆DOWN %
R30 ≤ RTRIM •
∆DOWN %
(10)
2. Calculate the maximum required output voltage for
VDAC0:
∆UP %
VDAC0 ≥ 1+
• VREF
%
∆
DOWN
(11)
Note: Not all DC/DC converters follow these trim equations,
especially newer bricks. Consult LTC Field Application
Engineering.
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Measuring Current with a Sense Resistor
A circuit for measuring current with a sense resistor is
shown in Figure 33. The balanced filter rejects both common mode and differential mode noise from the output
of the DC/DC converter. The filter is placed directly across
the sense resistor in series with the DC/DC converter’s inductor. Note that the current sense inputs must be limited
to less than 6V with respect to ground. Select RCM and
CCM such that the filter’s corner frequency is < 1/10 the
DC/DC converter’s switching frequency. This will result in
a current sense waveform that offers a good compromise
between the voltage ripple and the delay through the filter.
A value 1kΩ for RCM is suggested in order to minimize gain
errors due to the current sense inputs’ internal resistance.
Measuring Current with Inductor DCR
Figure 34 shows the circuit for applications that require
DCR current sense. A second order R-C filter is required
in these applications in order to minimize the ripple voltage seen at the current sense inputs. A value of 1kΩ
is suggested for RCM1 and RCM2 in order to minimize
gain errors due the current sense inputs’ internal resistance. CCM1 should be selected to provide cancellation
of the zero created by the DCR and inductance, i.e.
CCM
RCM
CCM
RSNS
ISENSEP
LTC2974
ISENSEM
2974 F33
LOAD CURRENT
Figure 33.Sense Resistor Current Sensing Circuits
RCM2
CCM1
CCM1
CCM2
RCM2
CCM2
ISENSEP
LTC2974
ISENSEM
2974 F34
RCM1
SWX0
L
Single Phase Design Example
As a design example for a DCR current sense application,
assume L = 2.2μH, DCR = 10mΩ, and FSW = 500kHz.
Let RCM1 = 1kΩ and solve for CCM1:
CCM1 ≥
2.2µH
= 220nF
10mΩ •1kΩ
Let RCM2 = 1kΩ. In order to get a second pole at
FSW/10 = 50kHz:
CCM2 ≅
1
= 3.18nF
2π • 50kHz •1kΩ
Let CCM2 = 3.3nF. Note that since CCM2 is much less than
CCM1 the loading effects of the second stage filter on the
matched first stage are not significant. Consequently, the
delay time constant through the filter for the current sense
waveform will be approximately 3μs.
Measuring Multiphase Currents
RCM
L
CCM1 = L/(DCR • RCM1). CCM2 should be selected to provide
a second stage corner frequency at < 1/10 of the DC/DC
converter’s switching frequency. In addition, CCM2 needs to
be much smaller than CCM1 in order to prevent significant
loading of the filter’s first stage.
RCM1
DCR
Figure 34. DCR Current Sensing Circuits
For current sense applications with more than one phase,
R-C averaging may be employed. Figure 35 shows an
example of this approach for a 3-phase system with DCR
current sensing. The current sense waveforms are averaged together prior to being applied to the second stage of
the filter consisting of RCM2 and CCM2. Because the RCM1
resistors for the three phases are in parallel, the value of
RCM1 must be multiplied by the number of phases. Also
note that since the DCRs are effectively in parallel, the
value for IOUT_CAL_GAIN will be equal to the inductor’s
DCR divided by the number of phases. Care should be
taken in the layout of the multiphase inductors to keep the
PCB trace resistance from the DC side of each inductor to
the summing node balanced in order to provide the most
accurate results.
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LTC2974
Applications Information
SWX1
RCM1
RCM1
RCM2
CCM2
RCM1
L
CCM2
ISENSEP
LTC2974
ISENSEM
DCR
2974 F35
RCM1/3
RCM2
CCM1
DCR
L
CCM2
DCR
L
TO LOAD
SWX2
SWX3
Figure 35. Multiphase DCR Current Sensing Circuits
Multiphase Design Example
Sensing Negative Voltages
Using the same values for inductance and DCR from
the previous design example, the value for RCM1 will be
3kΩ for a three phase DC/DC converter if CCM1 is left at
220nF. Similarly, the value for IOUT_CAL_GAIN will be
DCR/3 = 3.33mΩ.
Figure 37 shows the LTC2974 sensing a negative power
supply (VEE). The R1/R2 resistor divider translates the
negative supply voltage to the LTC2974’s VSENSEM1 input
while the VSENSEP1 input is tied to the REFP pin which has
a typical output voltage of 1.23V. Read_vout is determined
from the following equation:
Anti-aliasing Filter Considerations
Noisy environments require an anti-aliasing filter on
the input to the LTC2974’s ADC. The R-C circuit shown
in Figure 36 is adequate for most situations. Keep
R40 = R50 ≤ 200Ω to minimize ADC gain errors, and select
a value for capacitors C10 and C20 that does not add too
much additional response time to the OV/UV supervisor,
e.g. τ = 10μs (R = 100Ω, C = 0.10μF).
R2
VEE = VREFP – (READ_ VOUT ) •
+1 –
R1
1µA • R2
Where READ_VOUT returns VSENSEP – VSENSEM
The voltage divider should be configured in order to present
about 0.5V to the voltage sense inputs when the negative
supply reaches its POWER_GOOD_ON threshold so that
VIN
4.5V < VIBUS < 15V
0.1µF
VPWR
VIN_SNS
VOUT
VDAC0
VDD33
VDD33
VDD25
0.1µF
(14)
VSENSEP0
C10
LTC2974*
R30
R40
R20
VFB
LOAD
C20
VDD25
VSENSEM0
R50
R10
VOUT_EN0
GND
DC/DC
CONVERTER
SGND
RUN/SS
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF FOUR CHANNELS SHOWN
GND
2974 F36
Figure 36. Anti-Aliasing Filter on VSENSE Lines
2974fc
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89
LTC2974
Applications Information
4.5V < VIBUS < 15V
VIN_SNS
VPWR
LTC2974
1.23V TYP
REFP
0.1µF
SDA
PMBus
INTERFACE
SCL
ALERTB
CONTROL
REFM
VSENSEP1
1µA AT 0.5V
0.1µF
R1 = 4.99k
VSENSEM1
R2 = 120k
WDI/RESETB
VEE = –12V
FAULTB
SHARE_CLK
ASEL0
PWRGD
ASEL1
WP GND
WDI/RESETB
2974 F37
POWER_GOOD_ON = 0.5V FOR VEE POWER_GOOD = –11.414V
WHERE VEE POWER_GOOD =
VREFP – POWER_GOOD_ON (R2/R1 + 1) – 1µA • R2
ONLY ONE OF FOUR CHANNELS SHOWN,
SOME DETAILS OMITTED FOR CLARITY
Figure 37. Sensing Negative Voltages
the current flowing out of the VSENSEMn pin is minimized
to ~1µA. The relationship between the POWER_GOOD_ON
register value and the corresponding negative supply value
can be determined using equation 14.
Figure 39 shows the recommended schematic to use when
the LTC2974 is powered by the system 3.3V through its
VDD33 and VPWR pins. The LTC4412 ideal OR’ing circuit
allows either the controller or system to power the LTC2974.
Connecting the DC1613 USB to I2C/SMBus/PMBus
Controller to the LTC2974 in System
Because of the controller’s limited current sourcing capability, only the LTC2974s, their associated pull up resistors
and the I2C/SMBus pull-up resistors should be powered
from the ORed 3.3V supply. In addition, any device sharing
I2C/SMBus bus connections with the LTC2974 should not
have body diodes between the SDA/SCL pins and its VDD
node because this will interfere with bus communication
in the absence of system power.
The DC1613 USB to I2C/SMBus/PMBus Controller can
be interfaced to the LTC2974s on the user’s board for
programming, telemetry and system debug. The controller, when used in conjunction with LTpowerPlay software,
provides a powerful way to debug an entire power system.
Failures are quickly diagnosed using telemetry, fault status
registers and the fault log. The final configuration can be
quickly developed and stored to the LTC2974’s EEPROM.
Figure 38 and Figure 39 illustrate application schematics
for powering, programming and communicating with one
or more LTC2974’s via the DC1613 I2C/SMBus/PMBus
controller regardless of whether or not system power is
present.
The DC1613 controller’s I2C/SMBus connections are optoisolated from the PC’s USB port. The 3.3V supply from the
controller and the LTC2974’s VDD33 pin can be paralleled
because the LTC LDOs that generate these voltages can be
backdriven and draw
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