LTC3553EUD-2#PBF

LTC3553-2 Micropower USB Power Manager with Li-Ion Charger, Always-On LDO and Buck Regulator DESCRIPTION FEATURES n n n n n n n n n n The LTC ®3553-2 is a micropower, highly integrated power management and battery charger IC for single-cell Li-Ion/Polymer battery applications. It includes a PowerPath manager with automatic load prioritization, a battery charger, an ideal diode and numerous internal protection features. Designed specifically for USB applications, the LTC3553-2 power manager automatically limits input current to a maximum of either 100mA or 500mA. Battery charge current is automatically reduced such that the sum of the load current and the charge current does not exceed the selected input current limit. The LTC3553-2 also includes a synchronous buck regulator, an always-on low dropout linear regulator (LDO), and a pushbutton controller. With all supplies enabled in standby mode, the quiescent current drawn from the battery is only 12μA. The LTC3553-2 is available in a 3mm × 3mm × 0.75mm 20-pin QFN package. 12μA Standby Mode Quiescent Current (All Outputs On) Seamless Transition Between Input Power Sources: Li-Ion/Polymer Battery and USB 240mΩ Internal Ideal Diode Provides Low Loss PowerPath™ High Efficiency 200mA Buck Regulator Always-On 150mA Low Dropout (LDO) Linear Regulator Pushbutton On/Off Control With System Reset Full Featured Li-Ion/Polymer Battery Charger Programmable Charge Current With Thermal Limiting Instant-On Operation With Discharged Battery 3mm × 3mm × 0.75mm 20-Pin QFN Package APPLICATIONS n n n n USB-Based Handheld Products Portable Li-Ion/Polymer Based Electronic Devices Wearable Electronics Low Power Medical Devices L, LT, LTC, LTM, Linear Technology, the Linear logo, and Burst Mode are registered trademarks and PowerPath, Hot Swap, and Bat-Track are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6522118, 6700364, 5481178, 6304066, 6570372, 6580258, 7511390 and other patents pending. TYPICAL APPLICATION 100k 10μF LTC3553-2 NTC 100k PROG T 18 CHRG BAT + 1.87k Li-Ion BATTERY BVIN 2.2μF VINLDO PGOOD HPWR DIGITAL CONTROL 3.3V 150mA 4.7μF LDO 2.05M SUSP BUCK_ON Battery Drain Current vs Temperature SYSTEM LOAD VOUT VBUS 10μF 649k PBSTAT 10μH 1.2V 200mA SW 10pF ON VBAT = 3.8V 16 STBY = 3.8V REGULATORS LOAD = 0mA 14 BUCK AND LDO ON 12 10 ONLY LDO ON 8 6 4 2 HARD RESET 0 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) LDO_FB STBY BATTERY DRAIN CURRENT (μA) 4.35V TO 5.5V USB INPUT 332k 35532 TA01b 10μF BUCK_FB ON/OFF 649k 35532 TA01a 35532f 1 LTC3553-2 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2, 3) VBUS, VOUT t < 1ms and Duty Cycle < 1% .................. –0.3V to 7V Steady State............................................. –0.3V to 6V BAT, NTC, CHRG, SUSP, PBSTAT, ON, BUCK_FB, LDO_FB................................ –0.3V to 6V BUCK_ON, STBY, HPWR, PGOOD, BVIN, VINLDO, LDO (Note 4)....................................–0.3V to VCC + 0.3V IBAT .............................................................................1A ISW (Continuous) .................................................300mA ILDO (Continuous) ................................................175mA ICHRG, IPBSTAT, IPGOOD ............................................75mA Operating Temperature Range.................. –40°C to 85°C Junction Temperature ........................................... 110°C Storage Temperature Range................... –65°C to 125°C PROG BAT VOUT SUSP VBUS TOP VIEW 20 19 18 17 16 15 NTC HPWR 1 14 CHRG PGOOD 2 21 GND PBSTAT 3 13 SW ON 4 12 BVIN 11 VINLDO 7 8 9 10 STBY BUCK_FB LDO_FB LDO 6 BUCK_ON GND 5 UD PACKAGE 20-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 110°C, θJA = 58.7°C/W EXPOSED PAD (PIN 21) IS GND, AND MUST BE SOLDERED TO PCB GND ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3553EUD-2#PBF LTC3553EUD-2#TRPBF LGFJ 20-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ LTC3553 Options PART NUMBER LDO PGOOD HARD RESET TIME LTC3553 ON/OFF Control No 5 seconds LTC3553-2 Always On Yes 14 seconds POWER MANAGER ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VBUS = 5V, VBAT = 3.8V, HPWR = SUSP = BUCK_ON = 0V, RPROG = 1.87k, STBY = high, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.2 8 8 2 16 16 μA μA μA 5 8 μA 300 150 15 500 350 30 μA μA μA No-Load Quiescent Currents IBATQ Battery Drain Current (Note 5) Buck and LDO Shutdown, Hard Reset Buck and LDO Enabled LDO Enabled, Buck Shutdown IOUT = ISW = ILDO = 0 VBUS = 0V, Hard Reset VBUS = 0V, BUCK_ON = STBY = 3.8V VBUS = 0V, BUCK_ON = 0V IBATQC Battery Drain Current, VBUS Available VBAT = VFLOAT, Timer Timed Out IBUSQ VBUS Input Current 100mA, 500mA Modes Charger On Timer Timed Out SUSP = 5V (Suspend Mode) 35532f 2 LTC3553-2 POWER MANAGER ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VBUS = 5V, VBAT = 3.8V, HPWR = SUSP = BUCK_ON = 0V, RPROG = 1.87k, STBY = high, unless otherwise noted. SYMBOL PARAMETER CONDITIONS IBVINQ BVIN Input Current Buck Shutdown Buck Enabled, Standby Mode Buck Enabled VBUS = 0V, VBVIN = 3.8V, ISW = 0 (Note 8) BUCK_ON = 0V BUCK_ON = STBY = 3.8V BUCK_ON = 3.8V, STBY = 0V VINLDO Input Current LDO Shutdown (Hard Reset) LDO Enabled VBUS = 0V, VINLDO = 3.8V, ILDO = 0 (Note 10) IVINLDOQ MIN TYP MAX UNITS 0.01 1.5 22 1 3 38 μA μA μA 0.01 0.1 1 1 μA μA 5.5 V 80 400 90 450 100 500 mA mA Input Power Supply VBUS Input Supply Voltage IBUS(LIM) Total Input Current HPWR = 0V (100mA) HPWR = 5V (500mA) VUVLO VBUS Undervoltage Lockout Rising Threshold Falling Threshold 3.8 3.6 3.9 3.5 V mV Rising Threshold Falling Threshold 200 50 300 0 mV mV VDUVLO RON_ILIM VBUS to BAT Differential Undervoltage Lockout 4.35 l l Input Current Limit Power FET On-Resistance (Between VBUS and VOUT ) 350 mΩ Battery Charger VFLOAT VBAT Regulated Output Voltage 0 ≤ TA ≤ 85°C ICHG Constant-Current Mode Charge Current RPROG = 1.87k, 0 ≤ TA ≤ 85°C 4.179 4.165 4.2 4.2 4.221 4.235 380 400 420 V V mA PROG Pin Servo Voltage VPROG VPROG,TRKL PROG Pin Servo Voltage in Trickle Charge VBAT < V TRKL 1 0.1 V V hPROG Ratio of IBAT to PROG Pin Current 750 mA/mA ITRKL Trickle Charge Current VBAT < V TRKL 30 40 50 mA V TRKL Trickle Charge Threshold Voltage VBAT Rising VBAT Falling 2.9 2.75 3 2.6 V V Threshold Voltage Relative to VFLOAT –75 –100 –125 ΔVRECHRG Recharge Battery Threshold Voltage mV tTERM Safety Timer Termination Period Timer Starts when VBAT = VFLOAT – 50mV 3.2 4 5 Hour tBADBAT Bad Battery Termination Time VBAT < V TRKL 0.4 0.5 0.63 Hour hC/10 End-of-Charge Indication Current Ratio (Note 6) 0.085 0.1 0.115 mA/mA RON_CHG Battery Charger Power FET On-Resistance (Between VOUT and BAT) IBAT = 200mA TLIM Junction Temperature in Constant Temperature Mode 220 mΩ 110 °C NTC VCOLD Cold Temperature Fault Threshold Voltage Rising NTC Voltage Hysteresis 75 76 1.3 77 %VBUS %VBUS VHOT Hot Temperature Fault Threshold Voltage Falling NTC Voltage Hysteresis 34 35 1.3 36 %VBUS %VBUS VDIS NTC Disable Threshold Voltage Falling NTC Voltage Hysteresis 1.2 1.7 50 2.2 %VBUS mV INTC NTC Leakage Current VNTC = VBUS = 5V 50 nA l –50 35532f 3 LTC3553-2 POWER MANAGER ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VBUS = 5V, VBAT = 3.8V, HPWR = SUSP = BUCK_ON = 0V, RPROG = 1.87k, STBY = high, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VFWD Forward Voltage Detection (Note 12) 15 mV RDROPOUT Diode On-Resistance, Dropout IOUT = 200mA, VBUS = 0V 240 mΩ IMAX Diode Current Limit (Note 7) Ideal Diode 1 A Logic Inputs (HPWR, SUSP) VIL Input Low Voltage VIH Input High Voltage RPD Internal Pull-Down Resistance 0.4 1.2 V V 4 MΩ Logic Output (CHRG) VOL Output Low Voltage I CHRG = 5mA 65 250 mV I CHRG Output Hi-Z Leakage Current VBAT = 4.5V, VCHRG = 5V 0 1 μA BUCK REGULATOR ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). BUCK_ON = VOUT = BVIN = 3.8V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS BVIN Input Supply Voltage (Note 9) VOUT UVLO VOUT Undervoltage Lockout fOSC Oscillator Frequency IBUCK_FB BUCK_FB Input Current (Note 8) RSW_PD SW Pull-Down in Shutdown MIN l VOUT Falling VOUT Rising TYP 2.7 MAX UNITS 5.5 V 2.5 2.6 2.8 2.9 V V 0.955 1.125 1.295 –0.05 BUCK_ON = 0V 0.05 10 MHz μA kΩ Logic Input Pin (STBY) Input High Voltage 1.2 V Input Low Voltage Input Current –1 0.4 V 1 μA Buck Regulator in Normal Operation (STBY Low) ILIM Peak PMOS Current Limit BUCK_ON = 3.8V (Note 7) BUCK_ON = 3.8V l 300 500 650 mA 780 800 820 mV VBUCK_FB Regulated Feedback Voltage DMAX Max Duty Cycle RP RDS(ON) of PMOS ISW = 100mA 1.1 Ω RN RDS(ON) of NMOS ISW = –100mA 0.7 Ω 100 % Buck Regulator in Standby Mode (STBY High) Feedback Voltage Threshold BUCK_ON = 3.8V, VBUCK_FB Falling Short-Circuit Current Standby Mode Dropout Voltage BUCK_ON = 2.9V, ISW = 10mA, VBUCK_FB = 0.76V, VOUT = 2.9V, BVIN = 2.9V l 770 800 820 mV 30 50 100 mA 50 100 mV 35532f 4 LTC3553-2 LDO REGULATOR ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VOUT = VINLDO = 3.8V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS VINLDO Input Voltage Range (Note 9) VOUT UVLO VOUT Undervoltage Lockout VLDO_FB ILDO = 1mA (Note 10) VLDO_FB Line Regulation ILDO = 1mA, VINLDO = 1.65V to 5.5V (Note 10) VLDO_FB Load Regulation ILDO = 1mA to 150mA (Note 10) ILDO_FB Feedback Pin Input Current Available Output Current l VOUT Falling VOUT Rising Regulated Feedback Voltage ILDO_OC MIN 1.65 2.5 l TYP 780 MAX 5.5 V 2.6 2.8 2.9 V V 800 820 0.7 –50 mV mV/V 0.025 l UNITS mV/mA 50 150 nA mA ILDO_SC Short-Circuit Output Current (Note 7) 300 VDROP Dropout Voltage (Note 13) ILDO = 150mA, VINLDO = 3.8V ILDO = 150mA, VINLDO = 2.5V ILDO = 75mA, VINLDO = 1.8V 160 220 180 mA tLDO_SS Soft-Start Time 0.2 ms RLDO_PD Output Pull-Down Resistance in Hard Reset 10 kΩ 260 350 280 mV mV mV PUSHBUTTON INTERFACE ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VBAT = 3.8V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Pushbutton Pin (ON) (Notes 4 , 9) l VCC_PB Pushbutton Operating Supply Range VON_TH ON Threshold Rising ON Threshold Falling 2.7 I ON ON Input Current VON = VCC (Note 4) –1 RPB_PU Pushbutton Pull-Up Resistance Pull-Up to VCC (Note 4) 200 5.5 V 1.2 V V 1 μA 650 kΩ 0.4 V V 0.4 400 Logic Input Pins (BUCK_ON) Input High Voltage Input Low Voltage 1.2 Input Current –1 1 μA –1 1 μA 0.1 0.4 V 1 μA 0.4 V Status Output Pins (PBSTAT, PGOOD) IPBSTAT PBSTAT Output High Leakage Current VPBSTAT = 3V VPBSTAT PBSTAT Output Low Voltage IPBSTAT = 3mA IPGOOD PGOOD Output High Leakage Current VPGOOD = 3V VPGOOD PGOOD Output Low Voltage IPGOOD = 3mA 0.1 V THPGOOD PGOOD Threshold Voltage (Note 14) –8 –1 % 35532f 5 LTC3553-2 PUSHBUTTON INTERFACE ELECTRICAL CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VBAT = 3.8V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Pushbutton Timing Parameters (Note 11) t ON_PBSTATL Minimum ON Low Time to Cause PBSTAT Low ON Brought Low During Power-On (PON) or Power-Up (PUP1, PUP2) States 50 ms t ON_PBSTATH Delay from ON High to PBSTAT High Power-On (PON) State, After PBSTAT Has Been Low for at Least tPBSTAT_PW 900 μs t ON_PUP Minimum ON Low Time to Enter Power-Up (PUP1 or PUP2) State Starting in the Hard Reset (HR) or Power-Off (POFF) States 400 ms t ON_HR Minimum ON Low Time to Hard Reset ON Brought Low During the Power-On (PON) or Power-Up (PUP1, PUP2) States 11 14 tPBSTAT_PW PBSTAT Minimum Pulse Width Power-On (PON) or Power-Up (PUP1, PUP2) States 40 50 ms tEXTPWR Power-Up from USB Present to Power-Up (PUP1 or PUP2) State Starting in the Hard Reset (HR) or Power-Off (POFF) States 100 ms tPON_UP BUCK_ON High to Power-On State Starting with BUCK_ON Low in the Power-Off (POFF) State 900 μs tPON_DIS_BUCK BUCK_ON Low to Buck Disabled 17 s 1 μs tPUP Power-Up (PUP1 or PUP2) State Duration 5 s tPDN Power-Down (PDN1 or PDN2) State Duration 1 s tPGOODH Regulators in Regulation to PGOOD High All Enabled Regulators within PGOOD Threshold Voltage tPGOODL Regulator Out of Regulation to PGOOD Low Any Enabled Regulator Below PGOOD Threshold Voltage Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3553-2E is tested under pulsed load conditions such that TJ ≈ TA . The LTC3553-2E is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 85°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA , in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal impedance. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperatures will exceed 110°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. Note 4: VCC is the greater of VBUS or BAT. Note 5: Total battery drain current represents the load a battery will see in application due to quiescent currents drawn by the BAT pin (IBATQ) plus any current drawn from the VOUT pin. In applications where the buck input (BVIN pin) and LDO input (VINLDO pin) are connected to the 1 1.8 ms 3 μs PowerPath output (VOUT pin), the quiescent currents on BVIN and VINLDO must be added to IBATQ to get the actual battery drain current that will be seen in application. Note 6: hC/10 is expressed as a fraction of programmed full charge current with specified PROG resistor. Note 7: The current limit features of this part are intended to protect the IC from short term or intermittent fault conditions. Continuous operation above the absolute maximum specified pin current rating may result in device degradation or failure. Note 8: BUCK_FB High, Not Switching Note 9: VOUT not in UVLO. Note 10: Measured with the LDO operating in unity-gain, with its output and feedback pins tied together. Note 11: See the Operation section of this data sheet for detailed explanation of the pushbutton state machine and the effects of each state on regulator and power manager operation. Note 12: If VBUS < VUVLO then VFWD = 0 and the forward voltage across the ideal diode is equal to its current times RDROPOUT. Note 13: Dropout voltage is the minimum input to output voltage differential needed for the LDO to maintain regulation at a specified output current. When the LDO is in dropout, its output voltage will be equal to: VINLDO – VDROP. Note 14: PGOOD threshold is expressed as a percentage difference from the buck or LDO regulation voltage. The threshold is measured with the feedback pin voltage rising. 35532f 6 LTC3553-2 TYPICAL PERFORMANCE CHARACTERISTICS 400 VBUS Supply Current vs Temperature (Suspend Mode) 25 VBUS = 5V HPWR = L 15 IBUS (μA) IBUS (μA) 18 VBUS = 5V 20 350 300 Battery Drain Current vs Temperature BATTERY DRAIN CURRENT (μA) VBUS Supply Current vs Temperature TA = 25°C, unless otherwise specified. 10 250 5 VBAT = 3.8V 16 STBY = 3.8V REGULATORS LOAD = 0mA 14 BUCK AND LDO ON 12 ONLY LDO ON 10 8 6 4 2 200 –75 –50 –25 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 25 50 75 100 125 150 TEMPERATURE (°C) 35532 G01 35532 G03 35532 G02 VBUS Current Limit vs Temperature Battery Drain Current vs Temperature (Suspend Mode) 5 HARD RESET 0 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 500 VBUS = 5V VBAT = 3.8V 4 VBUS and Battery Current vs Load Current 600 VBUS = 5V 400 RPROG = 1.87k 500 HPWR = H IVBUS 3 2 300 200 0 –75 –50 –25 100 125 0 BATTERY CURRENT (mA) IBAT (mA) 240 80 VBUS = 5V HPWR = H RPROG = 1.87k 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 35532 G08 CHRG 5 VBAT 400 4 300 3 SAFETY TIMER TERMINATION 200 VOLTAGE (V) 35532 G07 6 920mAhr CELL VBUS = 5V 500 RPROG = 1.87k 160 0 25 50 75 100 125 150 TEMPERATURE (°C) 500 600 320 0.40 0.20 –75 –50 –25 200 300 400 LOAD CURRENT (mA) Battery Charge Current and Voltage vs Time 400 0.25 100 35532 G06 480 0.30 IBAT (DISCHARGING) –100 0 25 50 75 TEMPERATURE (°C) IOUT = 200mA 0.45 RON (Ω) 100 Charge Current vs Temperature (Thermal Regulation) RON from VBUS to VOUT vs Temperature 0.35 IBAT (CHARGING) 35532 G05 35532 G04 0.50 200 0 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 300 HPWR = L 100 1 ILOAD CURRENT (mA) IVBUS (mA) IBAT (μA) 400 2 100 1 C/10 IBAT 0 0 1 2 3 5 4 TIME (hour) 6 7 0 8 35532 G09 35532f 7 LTC3553-2 TYPICAL PERFORMANCE CHARACTERISTICS Battery Regulation (Float) Voltage vs Temperature VFLOAT Load Regulation 4.204 TA = 25°C, unless otherwise specified. 4.250 VBUS = 5V HPWR = H Battery Charge Current vs Battery Voltage 500 VBUS = 5V IBAT = 2mA 4.202 VBUS = 5V HPWR = H RPROG = 1.87k 400 4.225 4.198 IBAT (mA) VFLOAT (V) VFLOAT (V) 4.200 4.200 300 200 4.196 4.175 100 4.194 4.192 0 50 100 150 200 250 300 350 400 450 IBAT (mA) 4.150 –75 –50 –25 0 0 25 50 75 TEMPERATURE (°C) 2 100 125 35532 G10 2.4 2.8 3.2 3.6 VBAT (V) 35532 G11 Forward Voltage vs Ideal Diode Current 4.4 4 35532 G12 VBUS Connect Waveform VBUS Disconnect Waveform 300 250 5V VOUT 200 VFWD (mV) VBUS 5V VBUS = 5V VBUS VOUT 3.8V VOUT 3.8V LDO (3.3V) LDO (3.3V) 150 VBUS = 0V BUCK (1.2V) BUCK (1.2V) 100 0V 50 20μs/DIV 0 200 400 600 800 IBAT (mA) 1000 35532 G14 100μs/DIV VBAT = 3.8V ILDO = 100mA IBUCK = 100mA HPWR = HIGH SUSP = LOW STBY = LOW 0 1200 35532 G13 Oscillator Frequency vs Temperature 1.30 HPWR 0 0 5V VOUT IBUS 0.5A/DIV 0 IBUS 0A 0.5A/DIV 0A IBAT 0.5A/DIV 0A IBAT 0A 0.5A/DIV 1ms/DIV VBAT = 3.75V IOUT = 50mA RPROG = 2k SUSP = LOW 1ms/DIV 35532 G16 VBAT = 3.75V IOUT = 50mA RPROG = 2k HPWR = HIGH 35532 G17 OSCILLATOR FREQUENCY (MHz) SUSP 5V 5V 35532 G15 VBAT = 3.8V ILDO = 100mA IBUCK = 100mA HPWR = HIGH SUSP = LOW STBY = LOW Switching from Suspend Mode to 500mA Mode Switching from 100mA Mode to 500mA Mode VBUS 0V 1.25 2.7V 3.8V 5.5V 1.20 1.15 1.10 1.05 1.00 0.95 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 35532 G18 35532f 8 LTC3553-2 TYPICAL PERFORMANCE CHARACTERISTICS Buck Switching Regulator 2.5V Output Efficiency vs Load Buck Regulator 3.3V Output Efficiency vs Load 100 100 STBY = L 100 STBY = L 90 80 80 80 70 70 70 60 50 40 60 50 40 30 30 20 20 3.8V 5V 0.1 1 10 BUCK LOAD (mA) 100 0 0.01 0.1 1 10 BUCK LOAD (mA) 100 35 STBY = L 90 30 BVIN SUPPLY CURRENT (μA) EFFICIENCY (%) 80 70 60 50 40 30 20 3.8V 5V 1 10 BUCK LOAD (mA) 100 1000 20 15 10 0 2.5 3 3.5 4 4.5 5 BVIN SUPPLY VOLTAGE (V) 5.5 1000 –45°C 25°C 90°C 2.0 1.5 1.0 0 2.5 3 3.5 4 4.5 5 BVIN SUPPLY VOLTAGE (V) 5.5 35532 G24 35532 G23 Buck Regulator Output Transient (STBY = Low) VOUT 50mV/DIV (AC) BUCK (1.2V) 10mV/DIV (AC) 440 100 0.5 5 VOUT 50mV/DIV (AC) 460 NO LOAD STBY = H 2.5 Buck Regulator Output Transient (STBY = High) 480 1 10 BUCK LOAD (mA) 35532 G21 3.0 25 Buck Regulator Short-Circuit Current vs Temperature STBY = L 0.1 Buck Regulator Standby Mode BVIN Supply Current –45°C 25°C 90°C NO LOAD STBY = L 35532 G22 500 3.8V 5V 0 0.01 Buck Regulator Burst Mode ® Operation BVIN Supply Current 100 0.1 40 35532 G20 Buck Regulator 1.2V Output Efficiency vs ILOAD 0 0.01 50 10 1000 35532 G19 10 60 20 3.8V 5V 10 1000 STBY = L 30 BVIN SUPPLY CURRENT (μA) 0 0.01 EFFICIENCY (%) 90 10 SHORT CIRCUIT CURRENT (mA) Buck Switching Regulator 1.8V Output Efficiency vs Load 90 EFFICIENCY (%) EFFICIENCY (%) TA = 25°C, unless otherwise specified. BUCK (1.2V) 50mV/DIV (AC) 5mA IBUCK 100μA 100mA IBUCK 1mA 420 50μs/DIV 400 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) VBUS = 0V VBAT = 3.8V STBY = HIGH 35532 G26 100μs/DIV 35532 G27 VBUS = 0V VBAT = 3.8V STBY = LOW 35532 G25 35532f 9 LTC3553-2 TYPICAL PERFORMANCE CHARACTERISTICS Buck Regulator Feedback Voltage vs Output Current Buck Regulator Switch Impedance vs Temperature 1.6 1.2 1.0 NMOS 0.8 0.6 0.4 0.2 Regulator Output Transient During STBY Transition 3.8V 5V STBY = L 0.815 PMOS FEEDBACK VOLTAGE (V) SWITCH IMPEDANCE (Ω) 0.820 BVIN = 3.2V STBY = L 1.4 TA = 25°C, unless otherwise specified. BUCK OUTPUT 1.2V AT 10mA 20mV/DIV (AC) 0.810 0.805 LDO OUTPUT 3.3V AT 10mA 20mV/DIV (AC) 0.800 0.795 HIGH STBY LOW 0.790 0.785 0 –75 –50 –25 0.780 0.1 0 25 50 75 100 125 150 TEMPERATURE (°C) 1 10 100 OUTPUT CURRENT (mA) 1000 35532 G29 35532 G28 Regulated LDO Feedback Voltage vs Temperature Power-Up Sequencing from Hard Reset Buck Regulator Dropout Voltage in Standby Mode vs Load Current 820 140 0V 120 LDO OUTPUT 1V/DIV 100 80 0V 60 100μA LDO LOAD VINLDO = 2.9V VINLDO = 3.8V VINLDO = 5V 815 BUCK OUTPUT 0.5V/DIV FEEDBACK VOLTAGE (mV) DROPOUT VOLTAGE (mV) 200 BVIN = 2.9V –45°C 180 25°C 160 90°C 35532 G30 50μs/DIV VBUS = 0V VBAT = 3.8V 810 805 800 795 790 40 35532 G32 100μs/DIV 20 785 FRONT PAGE APPLICATION CIRCUIT 0 0 5 10 15 20 LOAD CURRENT (mA) 25 780 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) 30 35532 G33 35532 G31 LDO Load Regulation 800 799 798 797 400 300 350 LDO DROPOUT VOLTAGE (mV) LDO IN UNITY GAIN VINLDO = 3.8V VOUT = VBAT = 3.8V VBUS = 0V LDO SHORT-CIRCUIT CURRENT (mA) LDO OUTPUT VOLTAGE (mV) 801 LDO Dropout Voltage at VINLDO = 3.8V LDO Short-Circuit Current 300 250 200 150 100 50 0 796 0 25 50 75 100 LDO LOAD (mA) 125 150 1 2 3 4 5 VINLDO (V) 35532 G34 35532 G35 –45°C 25°C 90°C 250 200 150 100 50 0 0 25 50 75 100 LDO LOAD (mA) 125 150 35532 G36 35532f 10 LTC3553-2 TYPICAL PERFORMANCE CHARACTERISTICS LDO Dropout Voltage at VINLDO = 2.5V LDO Dropout Voltage at VINLDO = 1.8V 300 LDO Output Transient 300 –45°C 25°C 90°C 250 LDO DROPOUT VOLTAGE (mV) LDO DROPOUT VOLTAGE (mV) TA = 25°C, unless otherwise specified. 200 150 100 50 0 –45°C 25°C 90°C 250 VOUT 50mV/DIV (AC) LDO (3.3V) 100mV/DIV (AC) 200 150 100 100mA ILDO 1mA 50 50μs/DIV 0 0 25 50 75 100 LDO LOAD (mA) 125 150 35532 G37 0 15 30 45 LDO LOAD (mA) 60 75 35532 G39 VBUS = 0V VBAT = 3.8V 35532 G38 35532f 11 LTC3553-2 PIN FUNCTIONS HPWR (Pin 1): High Power Logic Input. When this pin is low the input current limit is set to 100mA and when this pin is driven high it is set to 500mA. The SUSP pin needs to be low for the input current limit circuit to be enabled. This pin has a conditional internal pull-down resistor when power is applied to the VBUS pin. PGOOD (Pin 2): Power Good. This open-drain output indicates that all enabled regulators have been in regulation for at least 1.8ms. PBSTAT (Pin 3): Pushbutton Status. This open-drain output is a debounced and buffered version of the ON pushbutton input. It may be used to interrupt a microprocessor. ON (Pin 4): Pushbutton Input. Weak internal pull-up forces a high state if ON is left floating. A normally open pushbutton is connected from ON to ground to force a low state on this pin. GND (Pin 5, Exposed Pad Pin 21): Ground. The exposed package pad is ground and must be soldered to the PC board for proper functionality and for maximum heat transfer. STBY (Pin 6): Standby Mode. When this pin is driven high, the buck regulator quiescent current is reduced to very low levels, while still maintaining output voltage regulation. In this mode, the buck regulator is limited to 10mA maximum load current. This pin must be driven to a valid logic level. Do not float this pin. BUCK_ON (Pin 7): Logic Input Enables the Buck Regulator. This pin must be driven to a valid logic level. Do not float this pin. BUCK_FB (Pin 8): Feedback Input for the Buck Regulator. This pin servos to a fixed voltage of 0.8V when the control loop is complete. LDO_FB (Pin 9): Feedback Input for the Low Dropout Regulator. This pin servos to a fixed voltage of 0.8V when the control loop is complete. LDO (Pin 10): Low Dropout (LDO) Linear Regulator Output. This pin should be bypassed with a low impedance multilayer ceramic capacitor. VINLDO (Pin 11): Power Input Pin for the LDO Regulator. This pin is to be connected to VOUT or any supply voltage below VOUT, such as the buck regulator output. This pin should be bypassed with a low impedance multilayer ceramic capacitor. BVIN (Pin 12): Power Input for the Buck Regulator. It is recommended that this pin be connected to the VOUT pin. It should be bypassed with a low impedance multilayer ceramic capacitor. SW (Pin 13): Power Transmission (Switch) Pin for the Buck Regulator. CHRG (Pin 14): Open-Drain Charge Status Output. This pin indicates the status of the battery charger. It is internally pulled low while charging. Once the battery charge current reduces to less than one-tenth of the programmed charge current, this pin goes into a high impedance state. An external pull-up resistor and/or LED is required to provide indication. NTC (Pin 15): The NTC pin connects to a battery’s thermistor to determine if the battery is too hot or too cold to charge. If the battery’s temperature is out of range, charging is paused until it drops back into range. A low drift bias resistor is required from VBUS to NTC and a thermistor is required from NTC to ground. If the NTC function is not desired, the NTC pin should be grounded. PROG (Pin 16): Charge Current Program and Charge Current Monitor Pin. Connecting a resistor from PROG to ground programs the charge current as given by: I CHG (A)= 750V RPROG If sufficient input power is available in constant-current mode, this pin servos to 1V. The voltage on this pin always represents the actual charge current. BAT (Pin 17): Single-Cell Li-Ion Battery Pin. Depending on available power and load, a Li-Ion battery on BAT will either deliver system power to VOUT through the ideal diode or be charged from the battery charger. 35532f 12 LTC3553-2 PIN FUNCTIONS VOUT (Pin 18): Output Voltage of the PowerPath Controller and Input Voltage of the Battery Charger. The majority of the portable products should be powered from VOUT. The LTC3553-2 will partition the available power between the external load on VOUT and the internal battery charger. Priority is given to the external load and any extra power is used to charge the battery. An ideal diode from BAT to VOUT ensures that VOUT is powered even if the load exceeds the allotted input current from VBUS or if the VBUS power source is removed. VOUT should be bypassed with a low impedance multilayer ceramic capacitor. SUSP (Pin 19): Suspend Mode Logic Input. If this pin is driven high the input current limit path is disabled. In this state the circuit draws negligible power from the VBUS pin. Any load at the VOUT pin is provided by the battery through the internal ideal diode. When this input is grounded, the input current limit will be set to desired value as determined by the state of the HPWR pin. This pin has a conditional internal pull-down resistor when power is applied to the VBUS pin. VBUS (Pin 20): USB Input Voltage. VBUS will usually be connected to the USB port of a computer or a DC output wall adapter. VBUS should be bypassed with a low impedance multilayer ceramic capacitor. 35532f 13 LTC3553-2 BLOCK DIAGRAM 18 VOUT VBUS 20 HPWR INPUT CURRENT LIMIT 1 SUSP 19 CC/CV CHARGER 17 BAT 16 PROG EXTPWR UVLO 12 BVIN NTC 15 BATTERY TEMP MONITOR 1.125MHz OSCILLATOR OSC 0.8V CHRG 14 ÷ 2048 CHARGE STATUS 13 SW EN STBY 8 BUCK_FB 200mA BUCK DC/DC 11 VINLDO 0.8V 10 LDO EN STBY 6 BUCK_ON 7 PBSTAT 3 ON 4 STBY 9 LDO_FB 2 PGOOD 150mA LDO PUSHBUTTON INTERFACE AND SEQUENCE LOGIC POWER GOOD COMPARATORS 5, 21 35532 BD1 GND 35532f 14 LTC3553-2 OPERATION Introduction The LTC3553-2 is a highly integrated power management IC that includes the following features: The buck regulator includes a low power standby mode which can be used to power essential keep-alive circuitry while draining ultralow current from the battery for extended battery life. PowerPath controller Battery charger USB PowerPath Controller Ideal diode The input current limit and charger control circuits of the LTC3553-2 are designed to limit input current as well as control battery charge current as a function of IVOUT. VOUT drives the combination of the external load, the buck and LDO regulators and the battery charger. Pushbutton controller 200mA buck regulator Always-on 150mA low dropout (LDO) linear regulator Designed specifically for USB applications, the PowerPath controller incorporates a precision input current limit which communicates with the battery charger to ensure that input current never violates the USB specifications. The ideal diode from BAT to VOUT guarantees that ample power is always available to VOUT even if there is insufficient or absent power at VBUS. The LTC3553-2 also includes a pushbutton input to control the two regulators and system reset. The constant-frequency current mode step-down switching regulator provides 200mA and supports 100% duty cycle operation as well as Burst Mode operation for high efficiency at light load. No external compensation components are required for the switching regulator. The LDO can deliver up to 150mA, and is stable with a ceramic output capacitor of at least 1μF. For application flexibility, the LDO’s power input pin, VINLDO, is independent of the buck’s BVIN pin. Either regulator can be programmed for a minimum output voltage of 0.8V and can be used to power a microcontroller core, microcontroller I/O, memory or other logic circuitry. The buck regulator operates at 1.125MHz. Simplified PowerPath Block Diagram VBUS 20 18 VOUT IDEAL CC/CV CHARGER + – 100mA/500mA INPUT CURRENT LIMIT 15mV 17 BAT If the combined load does not exceed the programmed input current limit, VOUT will be connected to VBUS through an internal 350mΩ P-channel MOSFET. If the combined load at VOUT exceeds the programmed input current limit, the battery charger will reduce its charge current by the amount necessary to enable the external load to be satisfied while maintaining the programmed input current. Even if the battery charge current is set to exceed the allowable USB current, the average input current USB specification will not be violated. Furthermore, load current at VOUT will always be prioritized and only excess available current will be used to charge the battery. The input current limit is programmed by the HPWR and SUSP pins. If SUSP pin set high, the input current limit is disabled. If SUSP pin is low, the input current limit is enabled. HPWR pin selects between 100mA input current limit when it is low and 500mA input current limit when it is high. Ideal Diode From BAT to VOUT The LTC3553-2 has an internal ideal diode from BAT to VOUT designed to respond quickly whenever VOUT drops below BAT. If the load increases beyond the input current limit, additional current will be pulled from the battery via the ideal diode. Furthermore, if power to VBUS (USB) is removed, then all of the application power will be provided by the battery via the ideal diode. The ideal diode is fast enough to keep VOUT from dropping significantly with just the recommended output capacitor. The ideal diode consists of a precision amplifier that enables an on-chip 35532 F01a 35532f 15 LTC3553-2 OPERATION P-channel MOSFET whenever the voltage at VOUT is approximately 15mV (VFWD) below the voltage at BAT. The resistance of the internal ideal diode is approximately 240mΩ. prioritized over the battery charge current. The USB current limit programming will always be observed and only additional current will be available to charge the battery. When system loads are light, battery charge current will be maximized. Suspend Mode When the SUSP pin is pulled high the LTC3553-2 enters suspend mode to comply with the USB specification. In this mode, the power path between VBUS and VOUT is put in a high impedance state to reduce the VBUS input current to 15μA. The system load connected to VOUT is supplied through the ideal diode connected to BAT. VBUS Undervoltage Lockout (UVLO) and Undervoltage Current Limit (UVCL) An internal undervoltage lockout circuit monitors VBUS and keeps the input current limit circuitry off until VBUS rises above the rising UVLO threshold (3.8V) and at least 200mV above VBAT. Hysteresis on the UVLO turns off the input current limit circuitry if VBUS drops below 3.6V or within 50mV of VBAT. When this happens, system power at VOUT will be drawn from the battery via the ideal diode. To minimize the possibility of oscillation in and out of UVLO when using resistive input supplies, the input current limit is reduced as VBUS falls below 4.45V typical. Battery Charger The LTC3553-2 includes a constant-current/constant-voltage battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out of temperature charge pausing. When a battery charge cycle begins, the battery charger first determines if the battery is deeply discharged. If the battery voltage is below V TRKL, typically 2.9V, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. If the low voltage persists for more than 1/2 hour, the battery charger automatically terminates. Once the battery voltage is above 2.9V, the battery charger begins charging in full power constant current mode. The current delivered to the battery will try to reach 750V/RPROG. Depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed current. The external load will always be Charge Termination The battery charger has a built-in safety timer. When the battery voltage approaches the float voltage, the charge current begins to decrease as the LTC3553-2 enters constant-voltage mode. Once the battery charger detects that it has entered constant-voltage mode, the four hour safety timer is started. After the safety timer expires, charging of the battery will terminate and no more current will be delivered to the battery. Automatic Recharge After the battery charger terminates, it will remain off drawing only microamperes of current from the battery. If the portable product remains in this state long enough, the battery will eventually self discharge. To ensure that the battery is always topped off, a charge cycle will automatically begin when the battery voltage falls below VRECHRG (typically 4.1V). In the event that the safety timer is running when the battery voltage falls below VRECHRG, the timer will reset back to zero. To prevent brief excursions below VRECHRG from resetting the safety timer, the battery voltage must be below VRECHRG for approximately 2ms. The charge cycle and safety timer will also restart if the VBUS UVLO cycles low and then high (e.g., VBUS, is removed and then replaced). Charge Current The charge current is programmed using a single resistor from PROG to ground. 1/750th of the battery charge current is delivered to PROG which will attempt to servo to 1.000V. Thus, the battery charge current will try to reach 750 times the current in the PROG pin. The program resistor and the charge current are calculated using the following equations: R PROG = 750V 750V ,I CHG = I CHG R PROG 35532f 16 LTC3553-2 OPERATION In either the constant-current or constant-voltage charging modes, the PROG pin voltage will be proportional to the actual charge current delivered to the battery. Therefore, the actual charge current can be determined at any time by monitoring the PROG pin voltage and using the following equation: I BAT = V PROG • 750 R PROG In many cases, the actual battery charge current, IBAT, will be lower than ICHG due to limited input current available and prioritization with the system load drawn from VOUT. Thermal Regulation To prevent thermal damage to the IC or surrounding components, an internal thermal feedback loop will automatically decrease the programmed charge current if the die temperature rises to approximately 110°C. Thermal regulation protects the LTC3553-2 from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the LTC3553-2 or external components. The benefit of the LTC3553-2 thermal regulation loop is that charge current can be set according to the desired charge rate rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. Charge Status Indication The CHRG pin indicates the status of the battery charger. An open-drain output, the CHRG pin can drive an indicator LED through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. When charging begins, CHRG is pulled low and remains low for the duration of a normal charge cycle. When charging is complete, i.e., the charger enters constant-voltage mode and the charge current has dropped to one-tenth of the programmed value, the CHRG pin is released (high impedance). The CHRG pin does not respond to the C/10 threshold if the LTC3553-2 reduces the charge current due to excess load on the VOUT pin. This prevents false end of charge indications due to insufficient power available to the battery charger. Even though charging is stopped during an NTC fault the CHRG pin will stay low indicating that charging is not complete. Battery Charger Stability Considerations The LTC3553-2’s battery charger contains both a constantvoltage and a constant-current control loop. The constantvoltage loop is stable without any compensation when a battery is connected with low impedance leads. Excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1μF from BAT to GND. Furthermore, a 100μF 1210 ceramic capacitor in series with a 0.3Ω resistor from BAT to GND is required to keep ripple voltage low if operation with the battery disconnected is allowed. High value, low ESR multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. Ceramic capacitors up to 22μF may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2Ω to 1Ω of series resistance. In constant-current mode, the PROG pin is in the feedback loop rather than the battery voltage. Because of the additional pole created by any PROG pin capacitance, capacitance on this pin must be kept to a minimum. With no additional capacitance on the PROG pin, the battery charger is stable with program resistor values as high as 25k. However, additional capacitance on this node reduces the maximum allowed program resistor. The pole frequency at the PROG pin should be kept above 100kHz. Therefore, if the PROG pin has a parasitic capacitance, CPROG, the following equation should be used to calculate the maximum resistance value for RPROG: R PROG ≤ 1 2π • 100kHz • C PROG 35532f 17 LTC3553-2 OPERATION NTC Thermistor Alternate NTC Thermistors and Biasing The battery temperature is measured by placing a negative temperature coefficient (NTC) thermistor close to the battery pack. To use this feature connect the NTC thermistor, RNTC, between the NTC pin and ground and a bias resistor, RNOM, from VBUS to NTC, as shown in Figure 1. RNOM should be a 1% resistor with a value equal to the value of the chosen NTC thermistor at 25°C (R25). The LTC3553-2 will pause charging when the resistance of the NTC thermistor drops to 0.54 times the value of R25 or approximately 54k (for a Vishay curve 1 thermistor, this corresponds to approximately 40°C). If the battery charger is in constant-voltage mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. As the temperature drops, the resistance of the NTC thermistor rises. The LTC3553-2 is also designed to pause charging when the value of the NTC thermistor increases to 3.17 times the value of R25. For a Vishay curve 1 thermistor this resistance, 317k, corresponds to approximately 0°C. The hot and cold comparators each have approximately 3°C of hysteresis to prevent oscillation about the trip point. The LTC3553-2 provides temperature qualified charging if a grounded thermistor and a bias resistor are connected to NTC. By using a bias resistor whose value is equal to the room temperature resistance of the thermistor (R25) the upper and lower temperatures are preprogrammed to approximately 40°C and 0°C, respectively (assuming a Vishay curve 1 thermistor). 20 NTC BLOCK VBUS 
t
7BUS (NTC RISING) RNOM 100k – TOO_COLD 15 NTC + The upper and lower temperature thresholds can be adjusted by either a modification of the bias resistor value or by adding a second adjustment resistor to the circuit. If only the bias resistor is adjusted, then either the upper or the lower threshold can be modified but not both. The other trip point will be determined by the characteristics of the thermistor. Using the bias resistor in addition to an adjustment resistor, both the upper and the lower temperature trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. Examples of each technique are given below. NTC thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. The Vishay-Dale thermistor NTHS0603N011-N1003F, used in the following examples, has a nominal value of 100k and follows the Vishay curve 1 resistance-temperature characteristic. In the explanation below, the following notation is used. R25 = Value of the thermistor at 25°C RNTC 100k RNTC|COLD = Value of thermistor at the cold trip point – 
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7BUS (NTC FALLING) TOO_HOT + RNTC|HOT = Value of the thermistor at the hot trip point rCOLD = Ratio of RNTC|COLD to R25 rHOT = Ratio of RNTC|HOT to R25 + NTC_ENABLE 
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7BUS (NTC FALLING) – 35532 F01 RNOM = Primary thermistor bias resistor (see Figure 2) R1 = Optional temperature range adjustment resistor (see Figure 2) Figure 1. Typical NTC Thermistor Circuit 35532f 18 LTC3553-2 OPERATION 20 VBUS 
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7BUS (NTC RISING) RNOM 105k – TOO_COLD 15 NTC + R1 12.7k RNTC 100k – 
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7BUS (NTC FALLING) TOO_HOT + + NTC_ENABLE 
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7BUS (NTC FALLING) – By using a bias resistor, RNOM, different in value from R25, the hot and cold trip points can be moved in either direction. The temperature span will change somewhat due to the nonlinear behavior of the thermistor. The following equations can be used to easily calculate a new value for the bias resistor: r R NOM = HOT • R25 0.538 r R NOM = COLD • R25 3.17 where rHOT and rCOLD are the resistance ratios at the desired hot and cold trip points. Note that these equations are linked. Therefore, only one of the two trip points can be independently set, the other is determined by the default ratios designed in the IC. 35532 F02 Figure 2. NTC Thermistor Circuit With Additional Bias Resistor The trip points for the LTC3553-2’s temperature qualification are internally programmed at 0.35 • VBUS for the hot threshold and 0.76 • VBUS for the cold threshold. Therefore, the hot trip point is set when: R NTC|HOT R NOM +R NTC|HOT • VBUS = 0.35 • VBUS and the cold trip point is set when: R NTC|COLD R NOM +R NTC|COLD • V BUS = 0.76 • V BUS Solving these equations for RNTC|COLD and RNTC|HOT results in the following: RNTC|HOT = 0.538 • RNOM and RNTC|COLD = 3.17 • RNOM By setting RNOM equal to R25, the above equations result in rHOT = 0.538 and rCOLD = 3.17. Referencing these ratios to the Vishay Resistance-Temperature Curve 1 chart gives a hot trip point of about 40°C and a cold trip point of about 0°C. The difference between the hot and cold trip points is approximately 40°C. Consider an example where a 60°C hot trip point is desired. From the Vishay curve 1 R-T characteristics, rHOT is 0.2488 at 60°C. Using the above equation, RNOM should be set to 46.4k. With this value of RNOM, the cold trip point is about 16°C. Notice that the span is now 44°C rather than the previous 40°C. This is due to the decrease in temperature gain of the thermistor as absolute temperature increases. The upper and lower temperature trip points can be independently programmed by using an additional bias resistor as shown in Figure 2. The following formulas can be used to compute the values of RNOM and R1: r COLD – r HOT R NOM = • R25 2.714 R1 = 0.536 • R NOM – r HOT • R25 For example, to set the trip points to 0°C and 45°C with a Vishay curve 1 thermistor choose: 3.266 – 0.4368 R NOM = • 100k =104.2k 2.714 the nearest 1% value is 105k: R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k The nearest 1% value is 12.7k. The final solution is shown in Figure 2 and results in an upper trip point of 45°C and a lower trip point of 0°C. 35532f 19 LTC3553-2 OPERATION BUCK REGULATOR Introduction The LTC3553-2 includes a constant-frequency currentmode 200mA buck regulator. At light loads, the regulator automatically enters Burst Mode operation to maintain high efficiency. Applications with a near-zero-current sleep or memory keep-alive mode can command the LTC3553-2 buck regulator into a standby mode that maintains output regulation while drawing only 1.5μA quiescent current. Load capability drops to 10mA in this mode. The buck regulator is enabled, disabled and sequenced through the pushbutton interface (see the Pushbutton Interface section for more information). It is recommended that the buck regulator input supply (BVIN) be connected to the system supply pin (VOUT). This is recommended because the undervoltage lockout circuit on the VOUT pin (VOUT UVLO) disables the buck regulator when the VOUT voltage drops below the VOUT UVLO threshold. If driving the buck regulator input supply from a voltage other than VOUT, the regulator should not be operated outside its specified operating voltage range as operation is not guaranteed beyond this range. Output Voltage Programming Figure 3 shows the buck regulator application circuit. The output voltage for the buck regulator is programmed using a resistor divider from the buck regulator output connected to the feedback pin (BUCK_FB) such that: ⎛ R1 ⎞ VBUCK = 0.8V • ⎜ +1⎟ ⎝ R2 ⎠ Typical values for R1 can be as high as 2.2MΩ. (R1 + R2) can be as high as 3MΩ. The capacitor CFB cancels the pole created by feedback resistors and the input capacitance of the BUCK_FB pin and also helps to improve transient response for output voltages much greater than 0.8V. A variety of capacitor sizes can be used VIN MP EN SW PWM STBY CONTROL L VBUCK MN CFB R1 COUT BUCK_FB GND 0.8V R2 35532 F03 Figure 3. Buck Regulator Application Circuit for CFB but a value of 10pF is recommended for most applications. Experimentation with capacitor sizes between 2pF and 22pF may yield improved transient response. Normal Buck Operating Mode (STBY Pin Low) In normal mode (STBY pin low), the buck regulator performs as a traditional constant-frequency current mode switching regulator. Switching frequency is determined by an internal oscillator which operates at 1.125MHz. An internal latch is set at the start of every oscillator cycle, turning on the main P-channel MOSFET switch. During each cycle, a current comparator compares the inductor current to the output of an error amplifier. The output of the current comparator resets the internal latch, which causes the main P-channel MOSFET switch to turn off and the N-channel MOSFET synchronous rectifier to turn on. The N-channel MOSFET synchronous rectifier turns off at the end of the clock cycle, or when the current through the N-channel MOSFET synchronous rectifier drops to zero, whichever happens first. Via this mechanism, the error amplifier adjusts the peak inductor current to deliver the required output power. All necessary compensation is internal to the buck regulator requiring only a single ceramic output capacitor for stability. At light load and no-load conditions, the buck automatically switches to a power-saving hysteretic control algorithm that operates the switches intermittently to minimize switching losses. Known as Burst Mode operation, the buck cycles 35532f 20 LTC3553-2 OPERATION the power switches enough times to charge the output capacitor to a voltage slightly higher than the regulation point. The buck then goes into a reduced quiescent current sleep mode. In this state, power loss is minimized while the load current is supplied by the output capacitor. Whenever the output voltage drops below a predetermined value, the buck wakes from sleep and cycles the switches again until the output capacitor voltage is once again slightly above the regulation point. Sleep time thus depends on load current, since the load current determines the discharge rate of the output capacitor. load current, Burst Mode operation yields the best overall conversion efficiency. Standby Mode Buck Operation (STBY Pin High) It is possible for the buck regulator’s input voltage to fall near or below its programmed output voltage (e.g., a battery voltage of 3.4V with a programmed output voltage of 3.3V). When this happens, the PMOS switch duty cycle increases to 100%, keeping the switch on continuously. Known as dropout operation, the output voltage equals the regulator’s input voltage minus the voltage drops across the internal P-channel MOSFET and the inductor. There are situations where even the low quiescent current of Burst Mode operation is not low enough. For instance, in a static memory keep alive situation, load current may fall well below 1μA. In this case, the 22μA typical BVIN quiescent current in Burst Mode operation becomes the main factor determining battery run time. Standby mode cuts BVIN quiescent current down to just 1.5μA, greatly extending battery run time in this essentially no-load region of operation. The application circuit commands the LTC3553-2 into and out of standby mode via the STBY pin logic input. Bringing the STBY pin high places the regulator into standby mode, while bringing it low returns it to Burst Mode operation. In standby mode, buck load capability drops to 10mA. In standby mode, the buck regulator operates hysteretically. When the BUCK_FB pin voltage falls below the internal 0.8V reference, a current source from BVIN to SW turns on, delivering current through the inductor to the switching regulator output capacitor and load. When the FB pin voltage rises above the reference plus a small hysteresis voltage, that current is shut off. In this way, output regulation is maintained. Since the power transfer from BVIN to SW is through a high impedance current source rather than through a low impedance MOSFET switch, power loss scales with load current as in a linear low dropout (LDO) regulator, rather than as in a switching regulator. For near-zero load conditions where regulator quiescent current is the dominant power loss, standby mode is ideal. But at any appreciable Shutdown The buck regulator is shut down and enabled via the pushbutton interface. In shutdown, it draws only a few nanoamps of leakage current from the BVIN pin. It also pulls down on its output with a 10k resistor from its switch pin to ground. Dropout Operation Soft-Start Operation In normal operating mode, soft-start works by gradually increasing the maximum allowed peak inductor current for the buck regulator over a 500μs period. This allows the output to rise slowly, helping minimize the inrush current needed to charge up the output capacitor. A soft-start cycle occurs whenever the buck is enabled. Soft-start occurs only in normal operation, but not in standby mode. Standby mode operation is already inherently current-limited, since the regulator works by intermittently turning on a current source from BVIN to SW. Changing the state of the STBY pin while the regulators are operating doesn’t trigger a new soft-start cycle, to avoid glitching the outputs. Inductor Selection Many different sizes and shapes of inductors are available from numerous manufacturers. Choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. 35532f 21 LTC3553-2 OPERATION Inductor value should be chosen based on the desired output voltage. See Table 1. Table 3 shows several inductors that work well with the step-down switching buck regulator. These inductors offer a good compromise in current rating, DCR and physical size. Consult each manufacturer for detailed information on their entire selection of inductors. Larger value inductors reduce ripple current, which improves output ripple voltage. Lower value inductors result in higher ripple current and improved transient response time, but will reduce the available output current. To maximize efficiency, choose an inductor with a low DC resistance. Choose an inductor with a DC current rating at least 1.5 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. If output short circuit is a possible condition, the inductor should be rated to handle the maximum peak current specified for the buck converter. Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. Inductors that are very thin or have a very small volume typically have much higher core and DCR losses, and will not give the best efficiency. The choice of which style inductor to use often depends more on the price versus size, performance and any radiated EMI requirements than on what the buck requires to operate. The inductor value also has an effect on Burst Mode operation. Lower inductor values will cause Burst Mode switching frequency to increase. Input/Output Capacitor Selection Low ESR (equivalent series resistance) ceramic capacitors should be used at the buck output as well as at the buck input supply. Only X5R or X7R ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. For good transient response and stability the output capacitor should retain at least 4μF of capacitance over operating temperature and bias voltage. Generally, a good starting point is to use a 10μF output capacitor. Table 1. Choosing the Inductor Value Table 2. Ceramic Capacitor Manufacturers DESIRED OUTPUT VOLTAGE RECOMMENDED INDUCTOR VALUE AVX www.avxcorp.com 1.8V or Less 10μH Murata www.murata.com 1.8V to 2.5V 6.8μH Taiyo Yuden www.t-yuden.com 2.5V to 3.3V 4.7μH Vishay Siliconix www.vishay.com TDK www.tdk.com Table 3. Recommended Inductors for the Buck Regulator INDUCTOR PART NO. SIZE (L × W × H) (mm) L (μH) MAX IDC (A) MAX DCR (Ω) 1117AS-4R7M 1117AS-6R8M 1117AS-100M 4.7 6.8 10 0.64 0.54 0.45 0.18* 0.250* 0.380* 3.0 × 2.8 × 1.0 Toko www.toko.com MANUFACTURER CDRH2D11BNP-4R7N CDRH2D11BNP-6R8N CDRH2D11BNP-100N 4.7 6.8 10 0.7 0.6 0.48 0.248 0.284 0.428 3.0 × 3.0 × 1.2 Sumida www.sumida.com SD3112-4R7-R SD3112-6R8-R SD3112-100-R 4.7 6.8 10 0.8 0.68 0.55 0.246* 0.291* 0.446* 3.1 × 3.1 × 1.2 Cooper www.cooperet.com EPL2014-472ML_ EPL2014-682ML_ EPL2014-103ML_ 4.7 6.8 10 0.88 0.8 0.6 0.254 0.316 0.459 2.0 × 1.8 × 1.4 Coilcraft www.coilcraft.com * = Typical DCR 35532f 22 LTC3553-2 OPERATION The switching regulator input supply should be bypassed with a 2.2μF capacitor. Consult with capacitor manufacturers for detailed information on their selection and specifications of ceramic capacitors. Many manufacturers now offer very thin ( VUVLO and VBUS – VBAT > VDUVLO), the pushbutton circuity immediately enters the PUP1 state. For this to work reliably, the BAT pin voltage must be kept well-behaved when no battery is connected. Ensure this by bypassing the BAT pin to GND with an RC network consisting of a 100μF ceramic capacitor in series with 0.3Ω. 1 BAT 0 1 VBUS 0 1 ON (PB) 0 1 PBSTAT 0 100ms 1 BUCK 0 1 LDO 0 1.8ms 1 PGOOD 0 5s 1 BUCK_ON 0 STATE POFF PUP2 PON 35532 F07 Figure 7. Power-Up via Applying External Power 35532f 26 LTC3553-2 OPERATION Power-Up Via Asserting the BUCK_ON Pin Power-Down by De-Asserting BUCK_ON Figure 8 shows the LTC3553-2 powering up by driving BUCK_ON high. For this example the pushbutton circuitry starts in the HR state with a battery connected. Once BUCK_ON goes high, the pushbutton circuitry enters the PON state and the buck powers up. Also, as the part exits the hard reset state the LDO will power up simultaneously. The PGOOD is initially low and will go high once both regulators are within 8% of their regulation voltage for 1.8ms. Figure 9 shows the LTC3553-2 powering down by μC/ μP control. For this example the pushbutton circuitry starts in the PON state with a battery connected and both regulators enabled. The user presses the pushbutton (ON low) for at least 50ms, which generates a debounced, low impedance pulse on the PBSTAT output. After receiving the PBSTAT signal, the μC/μP software decides to drive the BUCK_ON input low in order to power down. After the BUCK_ON input goes low, the pushbutton circuitry will enter the PDN2 state. In the PDN2 state a one second wait time is initiated after which the pushbutton circuitry enters the POFF state. During this one second time, the ON, and BUCK_ON inputs as well as external power application are ignored. Though the above assumes a battery Powering up via asserting the BUCK_ON pin is useful for applications containing an always-on μC that’s not powered by the LTC3553-2 regulators. That μC can power the application up and down for housekeeping and other activities not needing the user’s control. 1 1 BAT BAT 0 0 1 1 VBUS VBUS 0 0 1 1 1s ON (PB) ON (PB) 0 0 1 1 PBSTAT PBSTAT 0 0 1 1 PGOOD BUCK_ON 0 0 1 1 μC/μP CONTROL BUCK_ON BUCK 0 0 1 1 BUCK LDO 0 0 1.8ms 1 1 LDO PGOOD 0 0 STATE 50ms HR PON STATE 35532 F08 Figure 8. Power-Up via Asserting the BUCK_ON Pin PON PDN2 POFF 35532 F09 Figure 9. Power-Down via De-Assertion of BUCK_ON 35532f 27 LTC3553-2 OPERATION present, the same operation would take place with a valid external supply (VBUS) with or without a battery present. threshold temporarily. This VOUT UVLO condition causes the pushbutton circuitry to transition from the PON state to the PDN2 state. Upon entering the PDN2 state the buck regulator powers down. The VOUT UVLO condition also disables the LDO causing the PGOOD to go low. Once the LDO powers back up and is in regulation for 1.8ms, the PGOOD will go high impedance. The PGOOD remains asserted through this state transition as the LDO stays on. Holding ON low through the one second power-down period will not cause a power-up event at end of the one second period. The ON pin must be brought high following the power-down event and then go low again to establish a valid power-up event. In the typical case where the BUCK_ON pin is driven by logic powered by the buck regulator, the BUCK_ON pin would also go low, as depicted in Figure 10. If the external supply recovers after entering the PDN2 state such that VOUT is no longer in UVLO, then the LTC3553-2 will transition back into the PUP2 state once the PDN2 one second delay is complete. Following the state diagram, the transition from PDN2 to PUP2 in this case actually occurs via a brief visit to the POFF state. During the brief UVLO Minimum Off-Time Timing (Low Battery) Figure 10 assumes the battery is either missing or at a voltage below the VOUT UVLO threshold, and the application is running via external power (VBUS). A glitch on the external supply causes VOUT to drop below the VOUT UVLO 1 BAT 0 1 VBUS 0 1 ON (PB) 0 1 PBSTAT 0 5s 1 BUCK_ON 0 1s, BUCK POWERS UP 1 BUCK 0 LDO POWERS UP 1 LDO 0 1.8ms 1 PGOOD 0 STATE PON PDN2 PUP2 PON 35532 F10 Figure 10. UVLO Minimum Off-Time Timing 35532f 28 LTC3553-2 OPERATION POFF state, the state machine immediately recognizes that valid external power is available and transitions into the PUP2 state. Entering the PUP2 state will cause the buck to power up as described previously in the power-up sections. Not depicted here, but in cases where the BUCK_ON pin is driven by a supply that remains high when entering the POFF state, then as per the state diagram in Figure 7, the pushbutton circuitry will enter the PON state once VOUT is no longer in UVLO. Upon entering the PON state, the buck regulator will power up. Note: If VOUT drops too low (below about 1.9V) the LTC3553-2 will see this as a POR condition and will enter the PDN1 state rather than the PDN2 state. One second later the part will transition to the HR state. Under these conditions an explicit power-up event (such as a pushbutton press) may be required to bring the LTC3553-2 out of hard reset. Hard Reset Timing HARD RESET provides an ultralow power-down state for shipping or long term storage as well as a way to power down the application in case of a software lockup. In the case of software lockup, the user can hold the pushbutton (ON low) for 14 seconds and a hard reset event (HRST) will occur, placing the pushbutton circuitry in the power-down (PDN1) state. At this point the buck regulator will be shut down. Following a one second power-down period the pushbutton circuitry will enter the hard reset state (HR). At this point the LDO regulator will be shut down. Holding ON low through the one second power-down period will not cause a power-up event at end of the one second period. ON must be brought high following the power-down event and then go low again for 400ms to establish a valid power-up event, as shown in Figure 11. 1 BAT 0 1 VBUS 0 14s 1 ON (PB) 0 50ms 1 PBSTAT 0 400ms 1 LDO 0 1 BUCK 0 1s 1 BUCK_ON 0 1.8ms 1 PGOOD 0 STATE PON PDN1 HR PUP1 35532 F11 Figure 11. Hard Reset via Holding ON Low for 14 Seconds 35532f 29 LTC3553-2 OPERATION Power-Up Sequencing LAYOUT AND THERMAL CONSIDERATIONS Figure 12 shows the actual power-up sequencing of the LTC3553-2. The regulators are both initially disabled (0V). Starting in hard reset state, if the pushbutton has been applied (ON low) for 400ms, the LDO is enabled. The LDO slews up and enters regulation. The actual slew rate is controlled by the soft start function of the LDO in conjunction with output capacitance and load (see the LDO Regulator Operation section for more information). When the LDO is within about 8% of final regulation, the buck is enabled and slews up into regulation. 1.8ms after the buck is within 8% of final regulation, the PGOOD output will go high impedance. The regulators in Figure 12 are slewing up with nominal output capacitors and no-load. Adding a load or increasing output capacitance on any of the outputs will reduce the slew rate and lengthen the time it takes the regulator to achieve regulation. Printed Circuit Board Power Dissipation In order to be able to deliver maximum charge current under all conditions, it is critical that the Exposed Pad on the backside of the LTC3553-2 package is soldered to a ground plane on the board. Correctly soldered to a 2500mm2 ground plane on a double-sided 1oz copper board, the LTC3553-2 has a thermal resistance (θJA) of approximately 70°C/W. Failure to make good thermal contact between the Exposed Pad on the backside of the package and an adequately sized ground plane will result in thermal resistances far greater than 70°C/W. The conditions that cause the LTC3553-2 to reduce charge current due to the thermal protection feedback can be approximated by considering the power dissipated in the BUCK OUTPUT 0.5V/DIV 0V LDO OUTPUT 1V/DIV 0V 100μs/DIV 35532 F12 Figure 12. Power-Up Sequencing, Front Page Application Circuit 35532f 30 LTC3553-2 OPERATION part. For high charge currents the LTC3553-2 power dissipation is approximately: PD = (VBUS –BAT) • IBAT + PD(REGS) where PD is the total power dissipated, VBUS is the supply voltage, BAT is the battery voltage, and IBAT is the battery charge current. PD(REGS) is the sum of power dissipated on chip by the step-down switching regulators. The power dissipated by the buck regulator can be estimated as follows: PD(BUCK) = (BOUTx • IOUT) • (100 - Eff)/100 Where BOUTx is the programmed output voltage, IOUT is the load current and Eff is the % efficiency which can be measured or looked up on an efficiency table for the programmed output voltage. The power dissipated by the LDO regulator can be estimated using: PD(LDO) = (VINLDO – VLDO) • ILDO where VINLDO is the LDO input supply voltage, VLDO is the LDO regulated output voltage, and ILDO is the LDO load current. Thus the power dissipated by all regulators is: PD(REGS) = PD(BUCK) + PD(LDO) It is not necessary to perform any worst-case power dissipation scenarios because the LTC3553-2 will automatically reduce the charge current to maintain the die temperature at approximately 110°C. However, the approximate ambi- ent temperature at which the thermal feedback begins to protect the IC is: TA = 110°C – PD • θJA Example: Consider the LTC3553-2 operating from a wall adapter with 5V (VBUS) providing 400mA (IBAT) to charge a Li-Ion battery at 3.3V (BAT). Also assume PD(REGS) = 0.3W, so the total power dissipation is: PD = (5V – 3.3V) • 400mA + 0.3W = 0.98W The ambient temperature above which the LTC3553-2 will begin to reduce the 400mA charge current, is approximately: TA = 110°C – 0.98W • 70°C/W = 41.4°C The LTC3553-2 can be used above 41.4°C, but the charge current will be reduced below 400mA. The charge current at a given ambient temperature can be approximated by: PD = (110°C – TA) / θJA = (VBUS – BAT) • IBAT + PD(REGS) Thus: IBAT = [(110°C – TA) / θJA –PD(REGS)] (VBUS –BAT) Consider the above example with an ambient temperature of 60°C. The charge current will be reduced to approximately: IBAT = [(110°C – 60°C) / 70°C/W – 0.3W] / (5V – 3.3V) IBAT = (0.71W – 0.3W) / 1.7V = 241mA 35532f 31 LTC3553-2 OPERATION Printed Circuit Board Layout When laying out the printed circuit board, the following list should be followed to ensure proper operation of the LTC3553-2: 1. The Exposed Pad of the package (Pin 21) should connect directly to a large ground plane to minimize thermal and electrical impedance. 2. The traces connecting the regulator input supply pins (BVIN and VINLDO) and their respective decoupling capacitors should be kept as short as possible. The GND side of each capacitor should connect directly to the ground plane of the part. This capacitor provides the AC current to the internal power MOSFETs and their drivers. It is important to minimize inductance from this capacitor to the pin of the LTC3553-2. Connect BVIN to VOUT and VINLDO to its input supply through short low impedance traces. 3. The switching power trace connecting the SW pin to its inductor should be minimized to reduce radiated EMI and parasitic coupling. Due to the large voltage swing of the switching node, sensitive nodes such as the feedback nodes should be kept far away or shielded from the switching nodes or poor performance could result. 4. Connections between the buck regulator inductor and its output capacitor should be kept as short as possible. The GND side of the output capacitor should connect directly to the thermal ground plane of the part. 5. Keep the feedback pin traces (BUCK_FB and LDO_FB) as short as possible. Minimize any parasitic capacitance between the feedback traces and any switching node (i.e., SW and logic signals). If necessary, shield the feedback nodes with a GND trace. 6. Connections between the LTC3553-2 PowerPath pins (VBUS and VOUT) and their respective decoupling capacitors should be kept as short as possible. The GND side of these capacitors should connect directly to the ground plane of the part. 35532f 32 LTC3553-2 TYPICAL APPLICATIONS USB PowerPath With Li-Ion Battery (NTC Qualified Charging) 4.35V TO 5.5V USB INPUT 20 C3 10μF 15 R1 100k R2 100k VBUS VOUT NTC CHRG 16 PROG 19 2 R3 BAT 6 7 3 4 PB1 HPWR BVIN SUSP VINLDO LDO PGOOD LDO_FB STBY 17 + SW BUCK_FB C2 2.2μF 11 10 3.3V RUP1 2.05M 9 13 ON GND Li-Ion BATTERY 12 BUCK_ON PBSTAT EN 14 RPROG 1.87k 1 1.8V C1 10μF LTC3553-2 T LDO SYSTEM LOAD 18 8 L1 10μH C5 10pF MEMORY I/O C4 4.7μF RLO1 649k 1.2V RUP2 332k CORE C6 10μF μC RLO2 649k R4 100k R3 100k PBSTAT PGOOD BUCK_ON STBY SUSP HPWR 35532 TA02 35532f 33 LTC3553-2 TYPICAL APPLICATIONS 3-Cell Alkaline/Lithium With PowerPath (Charger Disabled) U1 4.35V TO 5.5V USB INPUT 20 C3 10μF 15 VBUS VOUT NTC CHRG LTC3553-2 16 BAT SYSTEM LOAD 18 C1 10μF 14 17 + PROG RPROG 10k 1 19 HPWR BVIN SUSP VINLDO LDO 2 7 3 4 PB1 12 C2 2.2μF 11 10 9 SW 13 PBSTAT ON BUCK_FB 8 I/O C4 4.7μF RLO1 464k STBY BUCK_ON U2 2.5V RUP1 1M PGOOD LDO_FB 6 3 CELL ALKALINE OR LITHIUM L1 10μH 1.8V C5 10pF CORE C6 10μF RUP2 590k μC GND RLO2 464k R4 100k R5 100k R3 100k PBSTAT PGOOD STBY EN SUSP HPWR 35532 TA04 35532f 34 LTC3553-2 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UD Package 20-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1720 Rev A) 0.70 ±0.05 3.50 ± 0.05 (4 SIDES) 1.65 ± 0.05 2.10 ± 0.05 PACKAGE OUTLINE 0.20 ±0.05 0.40 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 0.75 ± 0.05 R = 0.05 TYP PIN 1 TOP MARK (NOTE 6) PIN 1 NOTCH R = 0.20 TYP OR 0.25 × 45° CHAMFER 19 20 0.40 ± 0.10 1 2 1.65 ± 0.10 (4-SIDES) (UD20) QFN 0306 REV A 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.20 ± 0.05 0.40 BSC 35532f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC3553-2 TYPICAL APPLICATION USB PowerPath With Li-Ion Battery (NTC Qualified Charging), and LDO Regulator Driven by Buck Regulator 4.35V TO 5.5V USB INPUT 20 C7 10μF R1 100k R2 100k 15 VBUS VOUT NTC CHRG 16 PROG R3 BAT 19 7 2 HPWR BVIN 17 + SW STBY VINLDO 3 4 PB1 C2 2.2μF 13 L1 4.7μH PGOOD BUCK_FB 6 LDO PBSTAT 8 C3 10pF 11 3.3V RUP1 2.05M MEMORY I/O C4 10μF RLO1 649k C5 2.2μF 10 ON LDO_FB Li-Ion BATTERY 12 SUSP BUCK_ON EN 14 RPROG 1.87k 1 1.8V C1 10μF LTC3553-2 T LDO SYSTEM LOAD 18 9 1.2V RUP2 332k RLO2 649k GND CORE C6 4.7μF μC R4 100k R3 100k PBSTAT PGOOD STBY BUCK_ON SUSP HPWR 35532 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3455 Dual DC/DC Converter with USB Power Manager and Li-Ion Battery Charger Seamless Transition Between Input Power Sources: Li-Ion Battery, USB and 5V Wall Adapter, 4mm × 4mm QFN-24 Package LTC3456 2-Cell, Multioutput DC/DC Converter with USB Power Manager Seamless Transition Between 2-Cell Battery, USB and AC Wall Adapter Input Power Sources, 4mm × 4mm QFN-24 Package LTC3554 Micropower USB Power Manager with Li-Ion Charger and Dual Buck Regulators PMIC with 10μA Standby Mode Quiescent Current, Compact 3mm × 3mm × 0.55mm 20-Pin UTQFN Package LTC3557 USB Power Manager with Li-Ion Charger, Triple Step-Down DC/DC Regulators Triple Step-Down Switching Regulators (600mA, 400mA, 400mA); 4mm × 4mm QFN-28 Package LTC3559 USB Charger with Dual Buck Regulators Adjustable, Synchronous Buck Converters, 3mm × 3mm QFN-16 Package LTC4080 500mA Standalone Charger with 300mA Synchronous Buck Charges Single-Cell Li-Ion Batteries, Timer Termination + C/10, Thermal Regulation, Buck Output: 0.8V to VBAT, Buck Input VIN: 2.7V to 5.5V, 3mm × 3mm DFN-10 Package 35532f 36 Linear Technology Corporation LT 0112 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2012