LTC3560
2.25MHz, 800mA
Synchronous Step-Down
Regulator in ThinSOT
DESCRIPTION
FEATURES
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High Efficiency: Up to 95%
Low Output Ripple (1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem if
the load switch resistance is low and it is driven quickly.
The only solution is to limit the rise time of the switch
drive so that the load rise time is limited to approximately
(25 • CLOAD). Thus, a 10μF capacitor charging to 3.3V
would require a 250μs rise time, limiting the charging
current to about 130mA.
where TA is the ambient temperature.
PC Board Layout Checklist
As an example, consider the LTC3560 in dropout at an
input voltage of 2.7V, a load current of 800mA and an
ambient temperature of 70°C. From the typical performance graph of switch resistance, the RDS(ON) of the
P-channel switch at 70°C is approximately 0.31Ω. Therefore, power dissipated by the part is:
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3560. These items are also illustrated graphically
in Figures 4 and 5. Check the following in your layout:
PD = ILOAD2 • RDS(ON) = 198mW
For the SOT-23 package, the θJA is 250°C/ W. Thus, the
junction temperature of the regulator is:
TJ = 70°C + (0.198)(250) = 120°C
1. The power traces, consisting of the GND trace, the SW
trace and the VIN trace should be kept short, direct and
wide.
2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1/R2 must be connected
between the (+) plate of COUT and ground.
which is below the maximum junction temperature of
125°C.
3. Does the (+) plate of CIN connect to VIN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
Note that at higher supply voltages, the junction temperature
is lower due to reduced switch resistance (RDS(ON)).
4. Keep the (–) plates of CIN and COUT as close as possible.
Checking Transient Response
5. Keep the switching node, SW, away from the sensitive
VFB node.
The regulator loop response can be checked by looking
at the load transient response. Switching regulators
take several cycles to respond to a step in load current.
When a load step occurs, VOUT immediately shifts by an
amount equal to (ΔILOAD • ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge
or discharge COUT, which generates a feedback error
signal. The regulator loop then acts to return VOUT to its
Design Example
As a design example, assume the LTC3560 is used in
a single lithium-ion battery-powered cellular phone
application. The VIN will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.8A but most of the time it will be in
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LTC3560
APPLICATIONS INFORMATION
1
RUN SYNC/MODE
6
LTC3560
2
VFB
GND
–
5
COUT
VOUT
R2
3
+
L1
VIN
SW
R1
4
CFWD
CIN
VIN
3560 F04
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 4. LTC3560 Layout Diagram
VIA TO GND
R1
VOUT
VIN
VIA TO VIN
VIA TO VOUT
R2
PIN 1
L1
CFWD
LTC3560
SW
COUT
CIN
GND
3560 F05
Figure 5. LTC3560 Suggested Layout
standby mode, requiring only 2mA. Efficiency at both
low and high load currents is important. Output voltage
is 2.5V. With this information we can calculate L using
equation (1),
L=
V
1
VOUT 1 OUT
VIN
( f )( IL )
(3)
Substituting VOUT = 2.5V, VIN = 4.2V, ΔIL = 320mA and
f = 2.25MHz in equation (3) gives:
L=
2.5V
2.5V
1
1.4μH
2.25MHz(320mA) 4.2V
CIN will require an RMS current rating of at least 0.4A ≅
ILOAD(MAX)/2 at temperature and COUT will require an ESR
of less than 0.1Ω. In most cases, a ceramic capacitor will
satisfy this requirement.
For the feedback resistors, choose R1 = 309k. R2 can
then be calculated from equation (2) to be:
V
R2 = OUT 1 R1= 978.5k; use 976k
0.6
Figure 6 shows the complete circuit along with its efficiency curve.
A 1.5μH inductor works well for this application. For best
efficiency choose a 960mA or greater inductor with less
than 0.2Ω series resistance.
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LTC3560
APPLICATIONS INFORMATION
100
90
VOUT = 2.5V
VIN
2.7V
TO 4.2V
4
CIN*
10μF
CER
VIN
SW
3
10pF
LTC3560
1
6
1.5μH**
COUT*
10μF
CER
RUN
SYNC/MODE VFB
5
976k
GND
2
3560 F06a
VOUT
2.5V
EFFICIENCY (%)
80
Burst Mode
OPERATION
70
PULSE
SKIPPING
60
50
40
30
20
309k
VIN = 3.6V
VIN = 4.2V
10
0
0.1
* TDK C2012X5R0J106M
**TDK VLF3010AT-1R5N1R2
1
10
100
OUTPUT CURRENT (mA)
1000
3560 F06b
Figure 6a
Figure 6b
VOUT
200mV/DIV
AC COUPLED
VOUT
200mV/DIV
AC COUPLED
IL
1A/DIV
IL
1A/DIV
ILOAD
1A/DIV
ILOAD
1A/DIV
VIN = 3.6V
20μs/DIV
VOUT = 2.5V
ILOAD = 100mA TO 800mA
Burst Mode OPERATION
Figure 6c
3560 F06c
20μs/DIV
VIN = 3.6V
VOUT = 2.5V
ILOAD = 100mA TO 800mA
PULSE SKIPPING MODE
3560 F06d
Figure 6d
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LTC3560
APPLICATIONS INFORMATION
100
90
4
CIN*
10μF
CER
3MHz CLK
VIN
SW
1μH**
3
10pF
LTC3560
1
6
COUT*
10μF
CER
RUN
SYNC/MODE VFB
5
GND
2
3560 F07a
VOUT
1.2V
301k
EFFICIENCY (%)
80
VIN
2.7V
TO 4.2V
70
60
50
40
30
301k
20
VIN = 2.7V
VIN = 3.6V
VIN = 4.2V
10
*TDK C2012X5R0J106M
**MURATA LQH32CN1R0M33
0
1
10
100
LOAD CURRENT (mA)
1000
3560 F07b
Figure 7a
Figure 7b
VOUT
100mV/DIV
AC COUPLED
VOUT
100mV/DIV
AC COUPLED
IL
500mA/DIV
IL
500mA/DIV
ILOAD
500mA/DIV
ILOAD
500mA/DIV
VIN = 3.6V
20μs/DIV
VOUT = 1.2V
ILOAD = 300A TO 800mA
Figure 7c
3560 F07c
20μs/DIV
VIN = 3.6V
VOUT = 1.2V
ILOAD = 0mA TO 500mA
3560 F07d
Figure 7d
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LTC3560
PACKAGE DESCRIPTION
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
0.62
MAX
2.90 BSC
(NOTE 4)
0.95
REF
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
1.90 BSC
S6 TSOT-23 0302 REV B
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3560
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