LTC3602
2.5A, 10V, Monolithic
Synchronous Step-Down
Regulator
DESCRIPTION
FEATURES
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Wide Input Voltage Range: 4.5V to 10V
2.5A Output Current
Low RDS(ON) Internal Switches: 65mΩ and 90mΩ
Programmable Frequency: 300kHz to 3MHz
Low Quiescent Current: 75μA
0.6V ±1% Reference Allows Low Output Voltage
99% Maximum Duty Cycle
Adjustable Burst Mode® Clamp
Synchronizable to External Clock
Power Good Output Voltage Monitor
Overtemperature Protection
Available in 16-Lead Exposed TSSOP and
4mm × 4mm QFN Packages
The LTC®3602 is a high efficiency, monolithic synchronous,
step-down DC/DC converter utilizing a constant-frequency,
current mode architecture. It operates from an input voltage
range of 4.5V to 10V and provides an adjustable regulated
output voltage from 0.6V to 9.5V while delivering up to
2.5A of output current. The internal synchronous power
switch with 65mΩ on-resistance increases efficiency
and eliminates the need for an external Schottky diode.
The switching frequency can either be set by an external
resistor or synchronized to an external clock. OPTI-LOOP®
compensation allows the transient response to be optimized
over a wide range of loads and output capacitors.
The LTC3602 can be configured for either Burst Mode operation or forced continuous operation. Forced continuous
operation reduces noise and RF interference, while Burst
Mode operation provides the high efficiency at light loads.
In Burst Mode operation, external control of the burst
clamp level allows the output voltage ripple to be adjusted
according to the requirements of the application.
APPLICATIONS
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Point-of-Load Supplies
Portable Instruments
Server Backplane Power
Battery-Powered Devices
, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V, 2.5A, 1MHz Step-Down Regulator
Efficiency and Power Loss vs Load Current
100
VIN
4.5V TO 10V
95
1μF
RUN
BOOST
0.22μF
RT
105k
2.2μH
PGOOD
SW
LTC3602
100μF
TRACK/SS
4.32k
ITH
1nF
105k
VFB
85
POWER LOSS
80
100
75
70
10
65
PGND
SYNC/MODE
VOUT
3.3V
2.5A
1000
POWER LOSS (mW)
INTVCC
PVIN
EFFICIENCY
90
EFFICIENCY (%)
22μF
10000
VIN = 7V
60
0.01
475k
0.1
1
LOAD CURRENT (A)
1
10
3602 TA01b
22pF
3602 TA01
3602fb
1
LTC3602
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage (PVIN) ....................... –0.3V to 11V
SW (DC)...................................... –0.3V to (PVIN + 0.3V)
BOOST ................................. (VSW –0.3V) to (VSW + 6V)
RUN ........................................................... –0.3V to 11V
All Other Pins ............................................... –0.3V to 6V
Peak SW Sink and Source Current (Note 7) .............6.5A
Operating Temperature Range (Note 2)....–40°C to 85°C
Junction Temperature (Notes 5, 6)........................ 125°C
Lead Temperature
(Soldering, FE Package 10 seconds)................. 300°C
3
14 BOOST
ITH
4
VFB
5
12 SW
RUN
6
11 SW
TRACK/SS
7
10 PGND
PGND
8
9
17
SW
SW
15 PGND
PVIN 1
14 PGND
PVIN 2
13 SW
13 PGND
21
INTVCC 3
12 PGND
SYNC/MODE 4
11 TRACK/SS
PGOOD 5
PGND
6
7
8
9 10
FE PACKAGE
16-LEAD PLASTIC TSSOP
RUN
RT
20 19 18 17 16
SGND
15 PVIN
VFB
16 INTVCC
2
RT
1
PGOOD
ITH
SYNC/MODE
TOP VIEW
SW
TOP VIEW
SW
BOOST
PIN CONFIGURATION
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 37°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3602EFE#PBF
LTC3602EFE#TRPBF
3602FE
16-Lead Plastic TSSOP
–40°C to 85°C
LTC3602IFE#PBF
LTC3602IFE#TRPBF
3602FE
16-Lead Plastic TSSOP
–40°C to 85°C
LTC3602EUF#PBF
LTC3602EUF#TRPBF
3602
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
LTC3602IUF#PBF
LTC3602IUF#TRPBF
3602
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 8.4V unless otherwise specified.
SYMBOL
PARAMETER
PVIN
Operating Voltage Range
CONDITIONS
MIN
TYP
4.5
VFB
Regulated Feedback Voltage
ITH = 0.7V (Note 3)
ΔVFB(LINEREG)
Feedback Voltage Line Regulation
VIN = 5V to 10V, ITH = 0.7V
ΔVFB(LOADREG)
Feedback Voltage Load Regulation
ITH = 0.36V to 0.84V
l
0.594
MAX
10
0.6
0.606
0.005
l
0.02
UNITS
V
V
%/V
0.1
%
3602fb
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LTC3602
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 8.4V unless otherwise specified.
SYMBOL
PARAMETER
TYP
MAX
UNITS
ΔVPGOOD
Power Good Range
CONDITIONS
MIN
±10
±12
%
RPGOOD
Power Good Resistance
11
18
Ω
IFB
FB Input Bias Current
10
nA
gm
Transconductance Amplifier gm
1.7
ms
IS
Supply Current
Active Mode
Sleep Mode
Shutdown
(Note 4)
INTVCC
VCC LDO Output Voltage
tON, MIN
Minimum Controllable ON-Time
VRUN
RUN Pin ON Threshold
ITRACK/SS
TRACK/SS Pull-Up Current
fOSC
Oscillator Frequency
fSYNC
SYNC Capture Range
RDS(ON)
Top Switch On-Resistance
Bottom Switch On-Resistance
ILIM
Peak Current Limit
ILSW
Switch Leakage Current
VUVLO
INTVCC Undervoltage Lockout
VUVLO, HYS
INTVCC Undervoltage Lockout Hysteresis
500
75
0.2
700
100
1
μA
μA
μA
4.8
5
5.2
V
0.4
0.7
90
l
VRUN Rising
ns
1
1.25
RT = 105k
0.8
1
0.3
μA
1.2
MHz
3
MHz
90
67
3.8
INTVCC Ramping Up
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3602E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3602 is tested in a feedback loop that adjusts VFB to
achieve a specified error amplifier output voltage (ITH).
4.1
V
mΩ
mΩ
4.5
5.2
A
0.1
1
μA
4.2
4.3
V
700
mV
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient temperature TA and the power
dissipation as follows: TJ = TA + (PD)(θJA C/W).
Note 6: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 7: This limit indicates the current density limitations of the internal
metallization and it is not tested in production.
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Operation
Load Step Transient Forced Continuous
VIN = 7V
VOUT = 3.3V
LOAD = 50mA
VIN = 7V
VOUT = 3.3V
OUTPUT
VOLTAGE
50mV/DIV
OUTPUT
VOLTAGE
100mV/DIV
INDUCTOR
CURRENT
500mA/DIV
LOAD
CURRENT
1A/DIV
10μs/DIV
3602 G01
10μs/DIV
3602 G02
3602fb
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LTC3602
TYPICAL PERFORMANCE CHARACTERISTICS
Switch On-Resistance
vs Input Voltage
VREF vs Temperature
95
RESISTANCE (mΩ)
0.6004
VREF (V)
TOP
90
0.6006
0.6002
0.6000
0.5998
140
VBOOST – VSW = INTVCC
VIN = 8.4V
85
80
75
BOTTOM
70
100
5
6
8
7
INPUT VOLTAGE (V)
6
3000
1015
5
2500
2000
1000
1
500
7
6
8
INPUT VOLTAGE (V)
5
9
985
0
10
50
100
150 200
ROSC (k)
250
300
1015
ACTIVE
995
990
400
300
200
SLEEP
100
985
500
QUIESCENT CURRENT (μA)
QUIESCENT CURRENT (μA)
1000
25
50
75
100
125
TEMPERATURE (°C)
3602 G09
8
9
4
5
6
7
8
INPUT VOLTAGE (V)
9
10
3602 G10
ACTIVE
400
300
200
100
0
0
6
7
INPUT VOLTAGE (V)
600
500
1005
5
Quiescent Current
vs Temperature
600
ROSC = 105k
1010
4
3602 G08
Quiescent Current
vs Input Voltage
Frequency vs Temperature
980
–50 –25
980
350
3602 G07
3602 G06
1020
995
990
0
4
1005
1000
1500
2
0
ROSC = 105k
1010
FREQUENCY (kHz)
VRUN = 0V
125
Frequency vs Input Voltage
1020
FREQUENCY (kHz)
INPUT CURRENT (nA)
Frequency vs ROSC
3
100
3602 G05
3500
4
50
25
75
0
TEMPERATURE (°C)
3602 G04
PVIN Leakage Current
vs Input Voltage
FREQUENCY (kHz)
BOTTOM
0
–50 –25
10
9
3602 G03
7
80
20
4
125
TOP
40
60
50
25
75
0
TEMPERATURE (°C)
100
60
65
0.5996
–50 –25
VIN = 8.4V
120
RESISTANCE (mΩ)
0.6008
Switch On-Resistance
vs Temperature
0
–50 –25
SLEEP
50
25
75
0
TEMPERATURE (°C)
100
125
3602 G11
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LTC3602
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Peak Inductor Current
vs Burst Clamp Voltage
Maximum Peak Inductor Current
vs Duty Cycle
100
5
2.0
1.5
1.0
0.5
0
0.4
0.7
0.9
0.5
0.6
0.8
BURST CLAMP VOLTAGE (V)
3
2
1
0
1.0
Efficiency vs Input Voltage
95
ILOAD = 1A
90
ILOAD = 2.5A
96
50
VIN = 9V
EFFICIENCY (%)
60
85
80
2.2μH
94
92
1μH
90
88
20
75
84
70
0.1
1
LOAD CURRENT (A)
4
10
4.7μH
86
10
0
0.01
10
FIGURE 6 CIRCUIT
VIN = 7V
ILOAD = 1A
98
VIN = 5V
EFFICIENCY (%)
EFFICIENCY (%)
0.1
1
LOAD CURRENT (A)
Efficiency vs Frequency
100
FIGURE 6 CIRCUIT
30
5
7
6
8
INPUT VOLTAGE (V)
9
10
0
500
1000 1500 2000
FREQUENCY (kHz)
5V LDO Output Voltage
vs Temperature
Load Regulation
0.10
3000
TRACK/SS Current
vs Temperature
5.10
FIGURE 6 CIRCUIT
VIN = 7V
2500
3602 G17
3602 G16
3602 G15
1.40
5.08
0.00
–0.10
1.35
5.06
TRACK/SS CURRENT (μA)
LDO OUTPUT VOLTAGE (V)
ΔVOUT /VOUT (%)
80
3602 G14
100
FIGURE 6 CIRCUIT
40
85
70
0.01
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
0
90
70
VIN = 9V
90
3602 G13
Efficiency vs Load Current,
Forced Continuous
80
VIN = 5V
75
3602 G12
100
FIGURE 6 CIRCUIT
95
4
EFFICIENCY (%)
2.5
PEAK INDUCTOR CURRENT (A)
PEAK INDUCTOR CURRENT (A)
3.0
Efficiency vs Load Current,
Burst Mode Operation
5.04
5.02
5.00
4.98
4.96
4.94
1.30
1.25
1.20
1.15
4.92
–0.20
0
0.5
1
1.5
2
LOAD CURRENT (A)
2.5
3
3602 G18
4.90
–50
–25
50
25
0
75
TEMPERATURE (oC)
100
125
3602 G19
1.10
–50
–25
50
25
0
75
TEMPERATURE (oC)
100
125
3602 G20
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LTC3602
PIN FUNCTIONS
FE/UF Package
SYNC/MODE (Pin 1/Pin 4): Mode Select and External
Clock Synchronization Input.
be programmed by connecting a capacitor between this
pin and ground. Leave this pin floating to use the internal
1ms soft-start clamp. Do not tie this pin to INTVCC or to
PVIN.
PGOOD (Pin 2/Pin 5): Power Good Output. Open-drain
logic output that is pulled to ground when the output voltage is not within ±10% of regulation point.
PGND (Pins 8, 9, 10/Pins 12, 13, 14, 15): Power
Ground.
RT (Pin 3/Pin 6): Frequency Set Pin.
SW (Pins 11, 12, 13/Pins 16, 17, 18, 19): Switch Node
Connection to the Inductor.
ITH (Pin 4/Pin 7): Error Amplifier Compensation Point.
VFB (Pin 5/Pin 8): Feedback Pin.
SGND (Pin 17/Pin 9, Pin 21): Signal Ground.
BOOST (Pin 14/Pin 20): Bootstrapped Supply to the Top
Side Floating Gate Driver.
RUN (Pin 6/Pin 10): Run Control Input. This pin may be
tied to PVIN to enable the chip.
PVIN (Pin 15/Pins 1,2): Power Input Supply. Decouple
this pin with a capacitor to PGND
TRACK/SS (Pin 7/Pin 11): Tracking Input for the Controller
or Optional External Soft-Start Input. This pin allows the
start-up of VOUT to “track” the external voltage at this pin
using an external resistor divider. An external soft-start can
INTVCC (Pin 16/Pin 3): Output of Internal 5V LDO.
Exposed Pad (Pin 17/Pin 21): SGND. Exposed pad is
signal ground and must be soldered to the PCB.
BLOCK DIAGRAM
ITH
BOOST
INTVCC
PVIN
1μA
0.6V
LDO
VOLTAGE
REFERENCE
SLOPE
COMPENSATION
RECOVERY
TRACK/SS
1ms
SOFT-START
+
+
+
–
VFB
BCLAMP
+
–
BURST
COMPARATOR
+
MAIN
I-COMPARATOR
SW
+
–
OVER-CURRENT
COMPARATOR
REVERSE
COMPARATOR
PGOOD
+
–
LOGIC
–
SW
SLOPE
COMPENSATION
OSILLATOR
+
0.66V
–
–
SYNC/MODE
0.54V
+
ERROR
AMPLIFIER
+
–
RT
RUN
SW
PGND
PGND
PGND
SYNC/MODE
3602 BD
3602fb
6
LTC3602
OPERATION
Main Control Loop
Burst Mode Operation
The LTC3602 is a monolithic, constant-frequency, currentmode step-down DC/DC converter. During normal operation, the internal top power switch (N-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the ITH pin.
The error amplifier adjusts the voltage on the ITH pin by
comparing the feedback signal from a resistor divider on
the VFB pin with an internal 0.6V reference. When the load
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error amplifier raises
the ITH voltage until the average inductor current matches
the new load current. When the top power MOSFET shuts
off, the synchronous power switch (N-channel MOSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at –2.5A for forced continuous mode and 0A
for Burst Mode operation.
Connecting the SYNC/MODE pin to a voltage in the range
of 0.42V to 1V enables Burst Mode operation. In Burst
Mode operation, the internal power MOSFETs operate
intermittently at light loads. This increases efficiency by
minimizing switching losses. During Burst Mode operation, the minimum peak inductor current is externally set
by the voltage on the SYNC/MODE pin and the voltage
on the ITH pin is monitored by the burst comparator to
determine when sleep mode is enabled and disabled.
When the average inductor current is greater than the
load current, the voltage on the ITH pin drops. As the ITH
voltage falls below 330mV, the burst comparator trips and
enables sleep mode. During sleep mode, the top power
MOSFET is held off and the ITH pin is disconnected from
the output of the error amplifier. The majority of the internal
circuitry is also turned off to reduce the quiescent current
to 75μA while the load current is solely supplied by the
output capacitor. When the output voltage drops, the ITH
pin is reconnected to the output of the error amplifier and
the top power MOSFET along with all the internal circuitry
is switched back on. This process repeats at a rate that
is dependent on the load demand. Pulse-skipping operation is implemented by connecting the SYNC/MODE pin
to ground. This forces the burst clamp level to be at 0V.
As the load current decreases, the peak inductor current
will be determined by the voltage on the ITH pin until the
ITH voltage drops below 330mV. At this point, the peak
inductor current is determined by the minimum on-time
of the current comparator. If the load demand is less than
the average of the minimum on-time inductor current,
switching cycles will be skipped to keep the output voltage in regulation.
The operating frequency is externally set by an external
resistor connected between the RT pin and ground. The
practical switching frequency can range from 300kHz to
3MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ±7.5%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET’s current limit is reached.
Forced Continuous Mode
Connecting the SYNC/MODE pin to INTVCC will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation, but may be desirable in
some applications where it is necessary to keep switching
harmonics out of a signal band. The output voltage ripple
is minimized in this mode.
Frequency Synchronization
The internal oscillator of the LTC3602 can be synchronized
to an external clock connected to the SYNC/MODE pin.
The frequency of the external clock can be in the range of
300kHz to 3MHz. For this application, the oscillator timing
resistor should be chosen to correspond to a frequency
that is 25% lower than the synchronization frequency.
When synchronized, the LTC3602 will operate in pulseskipping mode.
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LTC3602
OPERATION
Dropout Operation
Overtemperature Protection
When the input supply voltage decreases toward the output
voltage, the duty cycle increases toward the maximum
on-time. Further reduction of the supply voltage forces the
top switch to remain on for more than one cycle until it
attempts to stay on continuously. In order to replenish the
voltage on the floating BOOST supply capacitor, however,
the top switch is forced off and the bottom switch is forced
on for approximately 85ns every sixteen clock cycles. This
achieves an effective duty cycle that can exceed 99%. The
output voltage will then be primarily determined by the
input voltage minus the voltage drop across the upper
internal N-channel MOSFET and the inductor.
When using the LTC3602 in an application circuit, care
must be taken not to exceed any of the ratings specified in the Absolute Maximum Ratings section. As an
added safeguard, however, the LTC3602 does incorporate
an overtemperature shutdown feature. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance. After the part has cooled to below 115°C,
it will restart.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant-frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 30%. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3602, however,
slope compensation recovery is implemented to reduce
the variation of the maximum inductor peak current (and
therefore the maximum available output current) over the
range of duty cycles.
Short-Circuit Protection
When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle.
To prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases to more than 4.5A, the
top power MOSFET will be held off and switching cycles
will be skipped until the inductor current is reduced.
Voltage Tracking and Soft-Start
Some microprocessors and DSP chips need two power
supplies with different voltage levels. These systems often
require voltage sequencing between the core power supply
and the I/O power supply. Without proper sequencing,
latch-up failure or excessive current draw may occur that
could result in damage to the processor’s I/O ports or the
I/O ports of a supporting system device such as memory,
an FPGA or a data converter. To ensure that the I/O loads
are not driven until the core voltage is properly biased,
tracking of the core supply and the I/O supply voltage is
necessary.
Voltage tracking is enabled by applying a ramp voltage to
the TRACK/SS pin. When the voltage on the TRACK pin
is below 0.6V, the feedback voltage will regulate to this
tracking voltage. When the tracking voltage exceeds 0.6V,
tracking is disabled and the feedback voltage will regulate
to the internal reference voltage.
The TRACK/SS pin is also used to implement an external
soft-start function. A 1.2μA current is sourced from this
pin so that an external capacitor may be added to create
a smooth ramp. If this ramp is slower than the internal
1ms soft-start, then the output voltage will track this ramp
during start up instead. Leave this pin floating to use the
internal 1ms soft-start ramp. Do not tie the TRACK/SS
pin to INTVCC or to PVIN.
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LTC3602
APPLICATIONS INFORMATION
The basic LTC3602 application circuit is shown on the front
page of this data sheet. External component selection is
determined by the maximum load current and begins with
the selection of the inductor value and operating frequency
followed by CIN and COUT.
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance values and/or capacitance to
maintain low output ripple voltage. The operating frequency
of the LTC3602 is determined by an external resistor that is
connected between the RT pin and ground. The value of the
resistor sets the ramp current that is used to charge and
discharge an internal timing capacitor within the oscillator
and can be calculated by using the following equation:
R OSC =
1.15 • 1011
– 10k
f(Hz)
Although frequencies as high as 3MHz are possible, the
minimum on-time of the LTC3602 imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 90ns. Therefore, the minimum duty cycle is
equal to 100 • 90ns • f(Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN and decreases
with higher inductance.
⎛V ⎞ ⎛ V ⎞
ΔIL = ⎜ OUT ⎟ • ⎜ 1– OUT ⎟
⎝ fL ⎠ ⎝
VIN ⎠
Having a lower ripple current reduces the ESR losses
in the output capacitors and the output voltage ripple.
Highest efficiency operation is achieved at low frequency
with small ripple current. This, however, requires a large
inductor.
A reasonable starting point for selecting the ripple current
is ΔIL = 0.4(IMAX), where IMAX is the maximum output
current. The largest ripple current occurs at the highest
VIN. To guarantee that the ripple current stays below a
specified maximum, the inductor value should be chosen
according to the following equation:
⎛ V
⎞ ⎛
VOUT ⎞
OUT
•
1–
L=⎜
⎟ ⎜
⎟
⎝ fΔIL(MAX) ⎠ ⎝ VIN(MAX) ⎠
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of the more expensive ferrite cores. Actual
core loss is independent of core size for a fixed inductor
value but it is very dependent on the inductance selected.
As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of
wire and therefore copper losses will increase.
Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the
size/current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate energy but generally
cost more than powdered iron core inductors with similar
3602fb
9
LTC3602
APPLICATIONS INFORMATION
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and any
radiated field/EMI requirements. New designs for surface
mount inductors are available from Coiltronics, Coilcraft,
Toko and Sumida.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent
large ripple voltage, a low ESR input capacitor sized for
the maximum RMS current should be used. RMS current
is given by:
IRMS = IOUT(MAX ) •
VOUT
•
VIN
VIN
–1
VOUT
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in
the design.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients, as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response as described in a later section.
The output ripple, ΔVOUT, is determined by:
⎛
1 ⎞
ΔVOUT ≤ ΔIL • ⎜ ESR +
8fCOUT ⎟⎠
⎝
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capacitors
have excellent low ESR characteristics but can have a high
voltage coefficient and audible piezoelectric effects. The
high Q of ceramic capacitors with trace inductance can
also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
VIN. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
⎛ R2 ⎞
VOUT = 0.6V • ⎜ 1+ ⎟
⎝ R1⎠
The resistive divider allows the VFB pin to sense a fraction
of the output voltage as shown in Figure 1.
VOUT
R2
VFB
LTC3602
R1
SGND
3602 F01
Figure 1. Setting the Output Voltage
3602fb
10
LTC3602
APPLICATIONS INFORMATION
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is less than INTVCC
by 1V or more, Burst Mode operation is enabled. During
Burst Mode operation, the voltage on the SYNC/MODE
pin determines the burst clamp level. This level sets the
minimum peak inductor current, IBURST, for each switching
cycle according to the following equation:
VBURST =
IBURST
+ 0.42V
6A / V
VBURST is the voltage on the SYNC/MODE pin. IBURST can
be programmed in the range of 0A to 3.5A, which corresponds to a VBURST range of 0.42V to 1V. As the output
load current drops, the peak inductor current decreases
to keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than IBURST, the burst clamp will force the peak inductor
current to remain equal to IBURST regardless of further
reductions in the load current. Since the average inductor
current is therefore greater than the output load current,
the voltage on the ITH pin will decrease. When the ITH
voltage drops to 330mV, sleep mode is enabled in which
both power MOSFETs are shut off along with most of the
circuitry to minimize power consumption. All circuitry is
turned back on and the power MOSFETs begin switching
again when the output voltage drops out of regulation. The
value for IBURST is determined by the desired amount of
output voltage ripple. As the value of IBURST increases, the
sleep time between pulses and the output voltage ripple
increases. The burst clamp voltage, VBURST, can be set
by a resistor divider from the INTVCC pin. Alternatively,
the SYNC/MODE pin may be tied directly to the VFB pin to
set VBURST = 0.6V (IBURST = 1A), or through an additional
divider resistor (R3) to set VBURST = 0.46V to 0.6V (see
Figure 2).
Pulse-skipping, which is a compromise between low output
voltage ripple and efficiency, can be implemented by connecting the SYNC/MODE pin to ground. This sets IBURST to
0A. In this condition, the peak inductor current is limited by
the minimum on-time of the current comparator and the
lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads,
pulse-skipping allows only a few switching cycles to be
skipped while maintaining the output voltage in regulation.
Frequency Synchronization
The LTC3602’s internal oscillator can be synchronized
to an external clock signal. During synchronization, the
top MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 3MHz. Synchronization only occurs if
the external frequency is greater than the frequency set by
the RT resistor. Because slope compensation is generated
by the oscillator’s internal ramp, the external frequency
should be set 25% higher than the frequency set by the
RT resistor to ensure that adequate slope compensation
is present. When synchronized, the LTC3602 will operate
in pulse-skipping mode.
INTVCC Regulator
The LTC3602 features an integrated P-channel low dropout
linear regulator (LDO) that supplies power to the INTVCC
supply pin from the PVIN pin. This LDO supply has been
designed to deliver up to 35mA of load current for the
powering of the internal gate drivers and other internal
circuitry. A small external load may also be applied provided
that the total current from the INTVCC supply does not
exceed 35mA. The INTVCC pin should be bypassed with
no less than a 0.22μF ceramic capacitor. A 1μF ceramic
capacitor is suitable for most applications.
R2
INTVCC
LTC3602
R2
SYNC/MODE
LTC3602
R3 (OPTIONAL)
SYNC/MODE
R1
SGND
VOUT
FB
R1
SGND
3602 F02
VBURST = 0.46V TO 1V
VBURST = 0.46V TO 0.6V
Figure 2. Programing the Burst Clamp
3602fb
11
LTC3602
APPLICATIONS INFORMATION
Topside MOSFET Driver Supply (BOOST Pin)
The LTC3602 uses a bootstrapped supply to power the
gate of the internal topside MOSFET (Figure 3). When the
topside MOSFET is off and the SW pin is low, diode DBST
charges capacitor CBST to the voltage on the INTVCC supply. In order to turn on the topside MOSFET, the voltage on
the BOOST pin is then applied to its gate. As the topside
MOSFET turns on, the SW pin rises to the PVIN voltage
and the BOOST pin rises to PVIN + INTVCC, thereby keeping the MOSFET fully enhanced. For most applications, a
0.22μF ceramic capacitor is appropriate for CBST. Schottky
diode DBST should have a reverse breakdown voltage that
is greater than PVIN(MAX).
DBST
CINTVCC
BOOST
CBST
SW
Figure 3. Topside MOSFET Supply
Run and Soft-Start/Tracking Functions
The LTC3602 has a low power shutdown mode which is
controlled by the RUN pin. Pulling the RUN pin below 0.7V
puts the LTC3602 into a low quiescent current shutdown
mode (IQ < 1μA). When the RUN pin is greater than 0.7V,
the controller is enabled. The RUN pin can be driven directly
from logic as shown in Figure 4.
Soft-start and tracking are implemented by limiting the
effective reference voltage as seen by the error amplifier.
Ramping up the effective reference into the error amp in
turn causes a smooth and controlled ramp on the output
PVIN
LTC3602
4.7MΩ
RUN
0.6
1.2µA
When the LTC3602 detects a fault condition (either
undervoltage lockout or overtemperature), the TRACK/SS
pin is quickly pulled to ground and the internal soft-start
timer is also reset. This ensures an orderly restart when
using an external soft-start capacitor.
VOUT RTA RA + RB
=
•
VX
RA RTA + RTB
3602 F03
3.3V OR 5V
t SS = CSS •
To implement tracking, a resistor divider is placed between
an external supply (VX) and the TRACK/SS pin as shown
in Figure 5a. This technique can be used to cause VOUT to
ratiometrically track the VX supply (Figure 5b), according
to the following:
INTVCC
LTC3602
voltage of the converter. To use the default, internal 1ms
soft-start ramp, leave the TRACK/SS pin floating. Do not
tie the TRACK/SS pin to INTVCC or to PVIN. To increase the
soft-start time above 1ms, place a cap on the TRACK/SS
pin. A 1.2μA internal pull-up current will charge this cap,
resulting in a soft-start ramp time given by:
LTC3602
For coincident tracking, as shown in Figure 5c, (VOUT =
VX during start-up),
RTA = RA, RTB = RB
Note that the 1.2μA current that is sourced from the
TRACK/SS pin will cause a slight offset in the voltage seen
on the TRACK/SS pin and consequently on the VOUT voltage during tracking. This VOUT offset due to the TRACK/SS
current is given by:
VOS,TRK = (1.2µA) •
RTARTA RA +RB
•
RTA +RTB
RA
For most applications, this offset is small and has minimal
effect on tracking performance. For improved tracking accuracy, reduce the parallel impedance of RTA and RTB.
RUN
3602 F04
Figure 4. RUN Pin Interfacing
3602fb
12
LTC3602
APPLICATIONS INFORMATION
VOUT
The VIN operating current loss dominates the efficiency loss
at very low load currents whereas the I2R loss dominates
the efficiency loss at medium to high load currents.
RB
VX
VFB
RTB
LTC3602
RA
TRACK/SS
RTA
3602 F05a
Figure 5a. Using the TRACK/SS Pin to Track VX
OUTPUT VOLTAGE
VX
VOUT
TIME
(5b) Ratiometric Tracking
OUTPUT VOLTAGE
VX
VOUT
3602 F05b,c
TIME
(5c) Coincident Tracking
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: VIN operating current and I2R losses.
1. The VIN operating current comprises three components:
The DC Supply Current as given in the electrical characteristics, the internal MOSFET gate charge currents
and the internal topside MOSFET transition losses. The
MOSFET gate charge current results from switching the
gate capacitance of the internal power MOSFET switches.
The gates of these switches are driven from the INTVCC
supply. Each time the gate is switched from high to
low to high again, a packet of charge dQ moves from
INTVCC to ground. The resulting dQ/dt is the current
out of INTVCC that is typically larger than the DC bias
current. In continuous mode, the gate charge current
can be approximated by IGATECHG = f(9.5nC). Since the
INTVCC voltage is generated from VIN by a linear regulator, the current that is internally drawn from the INTVCC
supply can be treated as VIN current for the purposes
of efficiency considerations.
Transition losses apply only to the internal topside
MOSFET and become more prominent at higher input
voltages. Transition losses can be estimated from:
Transition Loss = (1.7) VIN2 • IO(MAX) • (120pF) • f
2. I2R losses are calculated from the resistances of the
internal switches, RSW and external inductor RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current:
I2R Loss = IO2(RSW + RL)
Other losses, including CIN and COUT ESR dissipative
losses and inductor core losses, generally account for
less than 2% of the total power loss.
3602fb
13
LTC3602
APPLICATIONS INFORMATION
Thermal Considerations
Checking Transient Response
In most applications, the LTC3602 does not dissipate much
heat due to its high efficiency. But, in applications where the
LTC3602 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperature of the part. If the junction temperature reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD•(ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or discharge COUT, generating a feedback error signal used by the
regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem. The ITH
pin external components and output capacitor shown in the
front page application will provide adequate compensation
for most applications.
To prevent the LTC3602 from exceeding the maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
TR = (PD) • (θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, TJ, is given by:
Design Example
As a design example, consider using the LTC3602 in
an application with the following specifications: VIN =
8.4V, VOUT = 3.3V, IOUT(MAX) = 2.5A, IOUT(MIN) = 100mA,
f= 1MHz. Because efficiency is important at both high and
low load current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
TJ = TA + TR
where TA is the ambient temperature.
As an example, consider the LTC3602 in dropout at an
input voltage of 8V, a load current of 2.5A and an ambient temperature of 70°C. From the Typical Performance
graph of Switch Resistance, the RDS(ON) of the top switch
at 70°C is approximately 120mΩ. Therefore, power dissipated by the part is:
PD = (ILOAD2)(RDS(ON)) = (2.5A)2(120mΩ) = 0.75W
For the TSSOP package, the θJA is 38°C/W. Thus the junction temperature of the regulator is:
TJ = 70°C + (0.75W)(38°C/W) = 98.5°C
which is below the maximum junction temperature of
125°C.
ROSC =
1.15 • 1011
– 10k = 105k
1MHz
Next, calculate the inductor value for about 40% ripple
current at maximum VIN:
⎛ 3.3V
⎞ ⎛ 3.3V ⎞
⎟⎟ • ⎜1–
L = ⎜⎜
⎟ = 2µH
⎝ (1MHz ) (1A ) ⎠ ⎝ 8.4V ⎠
Using a 2.2μH inductor results in a maximum ripple current of:
⎛
⎞ ⎛ 3.3V ⎞
3.3V
⎟⎟ • ⎜1–
ΔIL = ⎜⎜
⎟ = 0.91A
8.4V
2.2µH
1MHz
⎝
⎠
(
)
(
)
⎝
⎠
COUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. In this application, a tantalum capacitor will be used to provide the bulk
3602fb
14
LTC3602
APPLICATIONS INFORMATION
capacitance and a ceramic capacitor in parallel to lower
the total effective ESR. For this design, a 100μF ceramic
capacitor will be used. CIN should be sized for a maximum
current rating of:
IRMS = 2.5A •
3.3V
8.4V
•
– 1 = 1.22ARMS
8.4V
3.3V
Decoupling the PVIN pin with a 22μF ceramic capacitor is
adequate for most applications.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3602. Check the following in your layout:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3602.
The output voltage can now be programmed by choosing
the values of R1 and R2. Chose R1 = 105k and calculate
R2 as:
⎛ VOUT ⎞
R2 =R1 ⎜⎜
– 1⎟⎟ = 472.5k
⎝ 0.6V ⎠
2. Connect the (+) terminal of the input capacitor(s), CIN, as
close as possible to the PVIN pin. This capacitor provides
the AC current into the internal power MOSFETs.
Choose a standard value of R2 = 475k. The voltage on
the MODE pin will be set to 0.6V by tying the MODE pin
to the FB pin. This will set the burst current equal to approximately 1A. Figure 6 shows a complete schematic for
this design example.
4. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. You can connect the copper areas to any
DC net (PVIN, INTVCC, VOUT, PGND, SGND, or any other
DC rail in your system).
3. Keep the switching node, SW, away from all sensitive
small signal nodes.
CVCC
1μF
RPG
200k
SYNC/MODE
PGOOD
INTVCC
PVIN
PGOOD
ROSC
105k
CITH
1nF
D1
RT
BOOST
CBST
0.22μF
RITH
4.32k
ITH
R1
105k
R2
475k
VIN
8.4V
CIN
22μF
CFB
22pF
LTC3602
SW
VFB
SW
RUN
SW
TRACK/SS
PGND
PGND
PGND
L1
2.2μH
VOUT
3.3V
2.5A
COUT
100μF
3602 F06
L1: VISHAY IHLP2525CZER2R2MO1
CIN: TAIYO YUDEN TMK325BJ226MM-T
COUT: TDK C3225X5ROJ107M
Figure 6. 8.4V to 3.3V, 2.5A Regulator at 1MHz, Burst Mode Operation
3602fb
15
LTC3602
TYPICAL APPLICATIONS
1.8V, 2.5A Regulator at 1MHz, Burst Mode Operation
CVCC
1μF
RPG
200k
R3
845k
INTVCC
SYNC/MODE
PGOOD
R4
137k
CITH
1nF
PVIN
PGOOD
ROSC
105k
D1
RT
BOOST
CBST
0.22μF
RITH
4.32k
LTC3602
ITH
R1
105k
CFB
22pF
VIN
5V to 10V
CIN
22μF
R2
210k
SW
VFB
SW
RUN
SW
TRACK/SS
PGND
PGND
PGND
L1
1μH
VOUT
1.8V
2.5A
COUT
100μF
s2
L1: VISHAY IHLP2525CZER1R0MO1
CIN: TAIYO YUDEN TMK325BJ226MM-T
COUT: TAIYO YUDEN AMK316BJ107ML
3602 TA02
Efficinecy vs Load Current
100
EFFICIENCY (%)
95
90
85
80
VIN = 5V
VIN = 8.4V
VIN = 10V
75
70
0.01
0.1
1
LOAD CURRENT (A)
10
3602 TA02b
3602fb
16
LTC3602
TYPICAL APPLICATIONS
3.3V, 2.5A Regulator at 2MHz, Forced Continuous, Small Size
CVCC
1μF
RPG
200k
SYNC/MODE
PGOOD
INTVCC
PVIN
PGOOD
ROSC
47.5k
D1
RT
CITH
470pF
BOOST
CBST
0.22μF
RITH
2.94k
LTC3602
ITH
R1
105k
CFB
10pF
R2
475k
VIN
10V
CIN
22μF
SW
VFB
SW
RUN
SW
TRACK/SS
PGND
PGND
PGND
L1
1μH
VOUT
3.3V
2.5A
COUT
47μF
L1: VISHAY IHLP1616ABER1R0M01
CIN: TAIYO YUDEN EMK316BJ226ML-T
COUT: MURATA GRM3ICR60J476ME19
3602 TA04
2.5V, 2.5A Regulator, Synchronized to 1.8MHz
1.8MHz
EXT. CLK
CVCC
1μF
RPG
200k
SYNC/MODE
PGOOD
INTVCC
PVIN
PGOOD
ROSC
69.8k
CITH
470pF RITH
2.94k
D1
RT
ITH
R1
105k
CFB
22pF
R2
332k
VIN
8.4V
CIN
22μF
BOOST
CBST
0.22μF
LTC3602
SW
VFB
SW
RUN
SW
TRACK/SS
PGND
PGND
PGND
L1: VISHAY IHLP2525CZER1R0M01
CIN: TAIYO YUDEN TMK325BJ226MM-T
COUT: TDK C3225X5ROJ107M
L1
1μH
VOUT
2.5V
2.5A
COUT
100μF
3602 TA05
3602fb
17
LTC3602
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
4.90 – 5.10*
(.193 – .201)
2.74
(.108)
2.74
(.108)
16 1514 13 12 1110
6.60 p0.10
9
2.74
(.108)
4.50 p0.10
2.74 6.40
(.108) (.252)
BSC
SEE NOTE 4
0.45 p0.05
1.05 p0.10
0.65 BSC
1 2 3 4 5 6 7 8
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.25
REF
1.10
(.0433)
MAX
0o – 8o
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE16 (BA) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3602fb
18
LTC3602
PACKAGE DESCRIPTION
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 p0.05
4.50 p 0.05
3.10 p 0.05
2.00 REF
2.45 p 0.05
2.45 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 p 0.05
4.00 p 0.10
BOTTOM VIEW—EXPOSED PAD
R = 0.05
TYP
R = 0.115
TYP
19 20
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2.45 p 0.10
4.00 p 0.10
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 s 45o
CHAMFER
2
2.00 REF
2.45 p 0.10
(UF20) QFN 01-07 REV A
0.200 REF
0.00 – 0.05
0.25 p 0.05
0.50 BSC
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3602fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3602
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1877
600mA (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter
96% Efficiency, VIN: 2.7V to 10V, VOUT(MIN) = 0.8V,
IQ = 10μA, ISD
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湘ICP备2023018690号
