FEATURES
LTC3633A-2/LTC3633A-3
Dual Channel 3A, 20V
Monolithic Synchronous
Step-Down Regulator
DESCRIPTION
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The LTC®3633A-2 is a high efficiency, dual-channel monolithic synchronous buck regulator using a controlled on-time,
current mode architecture, with phase lockable switching
frequency. The two channels can run 180° out of phase to
relax the requirements for input and output capacitance. The
operating supply voltage range is from 3.6V to 20V, making
it suitable for lithium-ion battery stacks as well as point of
load power supply applications from a 12V or 5V supply.
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3.6V to 20V Input Voltage Range
3A Output Current per Channel
Up to 95% Efficiency
Low Duty Cycle Operation: 5% at 2.25MHz
Selectable 0°/180° Phase Shift Between Channels
Adjustable Switching Frequency: 500kHz to 4MHz
External Frequency Synchronization
Current Mode Operation for Excellent Line and
Load Transient Response
0.6V Reference Allows Low Output Voltages
User Selectable Burst Mode® Operation or Forced
Continuous Operation
Output Voltage Tracking and Soft-Start Capability
Short-Circuit Protected
Overvoltage Input and Overtemperature Protection
Power Good Status Outputs
Available in (4mm × 5mm) QFN-28 and 28-Lead
TSSOP Packages
The operating frequency is programmable from 500kHz to
4MHz with an external resistor and may be synchronized
to an external clock signal. The high frequency capability allows the use of small surface mount inductors and
capacitors. The unique constant frequency/controlled ontime architecture is ideal for high step-down ratio applications that operate at high frequency while demanding fast
transient response. An internal phase locked loop servos
the on-time of the internal one-shot timer to match the
frequency of the internal clock or an applied external clock.
APPLICATIONS
Distributed Power Systems
Battery Powered Instruments
n Point of Load Power Supplies
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L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611.
The LTC3633A-2 can select between forced continuous
mode and high efficiency Burst Mode operation. The
LTC3633A-2 and LTC3633A-3 differ in their output voltage sense range (refer to Table 1 in the Operation section
for a description of the entire LTC3633A product family).
TYPICAL APPLICATION
VOUT2
5V AT 3A
1.5µH
22µF
73.2k
47µF
x2
PVIN2
RUN1
RUN2
PVIN1 SVIN
SW2
VON2
VFB2
10k
90
INTVCC
ITH1
LTC3633A-2
ITH2
RT
MODE/SYNC
PHMODE
TRACKSS2
PGOOD2
BOOST2
0.1µF
Efficiency vs Load Current
100
SGND PGND
TRACKSS1
PGOOD1
BOOST1
SW1
VON1
VFB1
0.1µF
1µH
Burst Mode
OPERATION
80
2.2µF
EFFICIENCY (%)
VIN
6V TO 20V
70
60
50
40
30
20
VOUT1
3.3V AT 3A
10
VIN = 12V
0
0.001
10k 45.3k
22µF
0.01
VOUT = 5V
VOUT = 3.3V
1
0.1
LOAD CURRENT (A)
10
3633a23 TA01b
3633a23 TA01a
3633a23fb
For more information www.linear.com/LTC3633A-2
1
LTC3633A-2/LTC3633A-3
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PVIN1, PVIN2, SVIN....................................... –0.3V to 20V
PGOOD1, PGOOD2, VON1, VON2.................. –0.3V to 18V
BOOST1, BOOST2....................................... –0.3V to 23V
BOOST1-SW1, BOOST2-SW2.................... –0.3V to 3.6V
INTVCC, TRACKSS1, TRACKSS2................. –0.3V to 3.6V
ITH1, ITH2, RT, MODE/SYNC......... –0.3V to INTVCC + 0.3V
VFB1, VFB2, PHMODE.................... –0.3V to INTVCC + 0.3V
RUN1.............................................. –0.3V to SVIN + 0.3V
RUN2.......................................................... –0.3V to 20V
Operating Junction Temperature Range
(Notes 3, 4)............................................. –40°C to 125°C
Storage Temperature Range.................... –65°C to 150°C
PIN CONFIGURATION
TOP VIEW
28 27 26 25 24 23
VFB1
26 SW1
SW1
27 SW1
3
VON1
28 VON1
2
ITH1
1
TRACKSS1
VFB1
ITH1
SW1
TRACKSS1
TOP VIEW
PGOOD1 1
22 PVIN1
PGOOD1
4
25 PVIN1
PHMODE 2
21 PVIN1
PHMODE
5
24 PVIN1
RUN1
6
23 SVIN
19 BOOST1
MODE/SYNC
7
RT
8
RUN2 6
18 INTVCC
17 BOOST2
RUN2
9
SGND 7
16 PVIN2
PGOOD2 8
SGND 10
15 PVIN2
19 PVIN2
PGOOD2 11
18 PVIN2
RUN1 3
20 SVIN
MODE/SYNC 4
29
PGND
RT 5
SW2
SW2
VON2
ITH2
VFB2
TRACKSS2
9 10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB
29
PGND
22 BOOST1
21 INTVCC
20 BOOST2
VFB2 12
17 SW2
TRACKSS2 13
16 SW2
ITH2 14
15 VON2
FE PACKAGE
28-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 25°C/W
EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
LTC3633AEUFD-2#PBF
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3633AEUFD-2#TRPBF 633A2
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3633AIUFD-2#PBF
LTC3633AIUFD-2#TRPBF
633A2
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3633AEFE-2#PBF
LTC3633AEFE-2#TRPBF
LTC3633AFE-2
28-Lead Plastic TSSOP
–40°C to 125°C
LTC3633AIFE-2#PBF
LTC3633AIFE-2#TRPBF
LTC3633AFE-2
28-Lead Plastic TSSOP
–40°C to 125°C
LTC3633AEUFD-3#PBF
LTC3633AEUFD-3#TRPBF 633A3
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3633AIUFD-3#PBF
LTC3633AIUFD-3#TRPBF
633A3
28-Lead (4mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3633AEFE-3#PBF
LTC3633AEFE-3#TRPBF
LTC3633AFE-3
28-Lead Plastic TSSOP
–40°C to 125°C
LTC3633AIFE-3#PBF
LTC3633AIFE-3#TRPBF
LTC3633AFE-3
28-Lead Plastic TSSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3633a23fb
2
For more information www.linear.com/LTC3633A-2
LTC3633A-2/LTC3633A-3
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). PVIN1 = PVIN2 = SVIN = 12V unless otherwise noted.
SYMBOL
PARAMETER
SVIN
Supply Range
CONDITIONS
PVIN1 Supply Range
PVIN2 Supply Range
3.6V < SVIN < 20V
MIN
MAX
UNITS
l
3.6
20
V
l
l
1.5
1.5
20
20
V
V
0.6
1.5
6
12
V
V
LTC3633A-2, VON = VOUT
LTC3633A-3, VON = VOUT
Output Voltage Range (Note 4)
TYP
IQ
Input DC Supply Current (PVIN1 + PVIN2 + SVIN)
Both Channels Active (Note 5)
MODE = 0V
Sleep Current
MODE = INTVCC, VFB1, VFB2 > 0.6
Shutdown
RUN1 = RUN2 = 0V
VFB
Feedback Reference Voltage
∆VLINE_REG
Reference Voltage Line Regulation
PVIN = 3.6V to 20V
0.002
%/V
∆VLOAD_REG
Output Voltage Load Regulation
ITH = 0.8V to 1.6V
0.05
%
1.3
500
13
l
0.594
0.6
mA
µA
µA
0.606
±30
V
IFB
Feedback Pin Input Current
gm(EA)
Error Amplifier Transconductance
ITH = 1.2V
1.8
mS
tON
Minimum On Time
VON = 0.6V, PVIN = 4V
20
ns
tOFF
Minimum Off Time
PVIN = 6V
fOSC
Oscillator Frequency
VRT = INTVCC
RT = 162k
RT = 80.6k
ILIM
Positive Valley Switch Current Limit
45
nA
ns
1.4
1.7
3.4
2
2
4
2.6
2.3
4.6
MHz
MHz
MHz
2.6
3.5
4.5
A
Negative Inductor Valley Current Limit
–2
A
RDS(ON)
Top Switch On-Resistance
Bottom Switch On-Resistance
130
65
mΩ
mΩ
ISW(LKG)
Switch Leakage Current
PVIN = 20V, VRUN = 0V
V VIN-OV
VIN Overvoltage Lockout Threshold
PVIN Rising
PVIN Falling
INTVCC Voltage
3.6V < SVIN < 20V, 0mA Load
INTVCC Load Regulation
0mA to 50mA Load, SVIN = 4V to 20V
RUN Threshold Rising
RUN Threshold Falling
0.01
±1
µA
20.3
22.5
21.5
22.5
V
V
3.1
3.3
3.5
V
1.18
0.98
1.22
1.01
1.26
1.04
V
V
0
±3
µA
8
–8
10
–10
%
%
1.3
l
l
RUN Leakage Current
PGOOD Good-to-Bad Threshold
VFB Rising
VFB Falling
PGOOD Bad-to-Good Threshold
VFB Rising
VFB Falling
RPGOOD
PGOOD Pull-Down Resistance
10mA Load
tPGOOD
Power Good Filter Time
tSS
Internal Soft-Start Time
10% to 90% Rise Time
VFB During Tracking
TRACKSS = 0.3V
ITRACKSS
–3
3
20
TRACKSS Pull-Up Current
0.28
%
–5
5
%
%
20
Ω
40
µs
400
700
µs
0.3
0.315
V
1.4
µA
3633a23fb
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3
LTC3633A-2/LTC3633A-3
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). PVIN1 = PVIN2 = SVIN = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VPHMODE
PHMODE Threshold Voltage
PHMODE VIH
PHMODE VIL
1
VMODE/SYNC
MODE/SYNC Threshold Voltage
MODE VIH
MODE VIL
1
SYNC Threshold Voltage
SYNC VIH
0.95
MODE/SYNC Input Current
MODE = 0V
MODE = INTVCC
IMODE
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3633A-2/LTC3633A-3 is tested under pulsed load
conditions such that TJ ≈ TA. The LTC3633AE-2/ LTC3633AE-3 is
guaranteed to meet specifications from 0°C to 85°C junction temperature.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LTC3633AI-2/ LTC3633AI-3 is guaranteed
over the full –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature
TYP
MAX
UNITS
0.3
V
V
0.4
V
V
V
1.5
–1.5
µA
µA
(TJ, in °C) is calculated from the ambient temperature (TA, in °C) and
power dissipation (PD, in Watts) according to the formula:
TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal
impedance.
Note 3: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 4: Output voltages outside the specified range are not optimized for
controlled on-time operation. Refer to the Applications Information section
for further discussions related to the output voltage range.
Note 5: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
3633a23fb
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For more information www.linear.com/LTC3633A-2
LTC3633A-2/LTC3633A-3
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = 25°C, PVIN1 = PVIN2 = SVIN = 12V, fSW = 1MHz,
L = 1µH unless otherwise noted.
Efficiency vs Load Current
Efficiency vs Load Current
Forced Continuous Mode
Burst Mode Operation
Operation
Efficiency vs Load Current
100
100
VOUT = 1.8V
90
100
VOUT = 1.8V
80
70
70
50
40
30
VIN = 4V
VIN = 8V
VIN = 12V
VIN = 20V
20
10
0
0.001
0.01
1
0.1
LOAD CURRENT (A)
EFFICIENCY (%)
80
70
60
60
50
40
30
VIN = 4V
VIN = 8V
VIN = 12V
VIN = 20V
20
10
0
0.001
10
0.01
1
0.1
LOAD CURRENT (A)
3633a23 G01
100
40
L = 2.2µH
VOUT = 5V
VOUT = 3.3V
VOUT = 5V
VOUT = 3.3V
30
20
10
0
0.001
10
0.01
1
0.1
LOAD CURRENT (A)
10
3633a23 G03
Reference Voltage
vs Temperature
0.605
VOUT = 1.8V
0.603
90
60
50
40
30
VIN = 4V
VIN = 8V
VIN = 12V
VIN =15V
VIN = 20V
20
10
0
0.0001
0.001
0.01
0.1
LOAD CURRENT (A)
1
85
VFB (V)
70
EFFICIENCY (%)
EFFICIENCY (%)
50
95
80
80
75
70
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 1A
ILOAD = 3A
65
60
10
4
6
10 12 14 16
INPUT VOLTAGE (V)
8
0.599
0.597
18
20
0.595
–50 –25
2.6
8
0.8
0.4
0.0
RT = INTVCC
2.4
6
4
FREQUENCY (MHz)
FREQUENCY VARIATION (%)
VOUT = 1.8V
25 50 75 100 125 150
TEMPERATURE (°C)
Oscillator Internal Set Frequency
vs Temperature
10
Burst Mode OPERATION
FORCED CONTINUOUS
1.2
0
3633a23 G06
Oscillator Frequency
vs Temperature
Load Regulation
1.6
0.601
3633a23 G05
3633a23 G04
∆VOUT/VOUT (%)
60
Efficiency vs Input Voltage
Burst Mode Operation
VOUT = 1.2V
90
FORCED
CONTINUOUS
OPERATION
3633a23 G02
Efficiency vs Load Current
Burst Mode Operation
100
Burst Mode OPERATION
90
80
EFFICIENCY (%)
EFFICIENCY (%)
90
2
0
–2
–4
–6
2.2
2.0
1.8
1.6
–8
–0.4
0
0.5
1
1.5
ILOAD (A)
2
2.5
3
3633a23 G07
–10
–50
–25
0
50
75
25
TEMPERATURE (°C)
100
125
3633a23 G08
1.4
–50
–25
0
50
75
25
TEMPERATURE (°C)
100
125
3633a23 G09
3633a23fb
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5
LTC3633A-2/LTC3633A-3
T
TYPICAL
PERFORMANCE CHARACTERISTICS J = 25°C, PVIN1 = PVIN2 = SVIN = 12V, fSW = 1MHz,
L = 1µH unless otherwise noted.
Quiescent Current vs VIN
Burst Mode Operation
Internal MOSFET RDS(ON)
vs Temperature
200
900
180
800
160
700
100
80
20
90°C
18
16
25°C
500
–40°C
IQ (µA)
TOP SWITCH
120
400
300
60
BOTTOM SWITCH
40
0
25
75
50
TEMPERATURE (°C)
–25
100
0
125
4
2
4
6
8
10
12 14
VIN (V)
16
18
SYNCHRONOUS SWITCH
MAIN SWITCH
7000
3.9
2.0
3.8
1.8
4000
3.6
3.5
3000
2000
3.4
0
10
12 14
VIN (V)
16
25 50 75 100 125 150
TEMPERATURE (°C)
18
20
3.3
–50 –25
1.4
1.2
1.0
0.8
1000
0
–50 –25
8
1.6
ITRACKSS (µA)
5000
6
TRACKSS Pull-Up Current
vs Temperature
3.7
ILIM (A)
LEAKAGE CURRENT (nA)
8000
6000
4
3633a G12
Valley Current Limit
vs Temperature
Switch Leakage vs Temperature
9000
0
20
3633a23 G11
3633a23 G10
10000
10
6
100
0
–50
14
12
8
200
20
Shutdown Current vs VIN
22
600
IQ (µA)
RDS(ON) (mΩ)
140
24
0
25
75
50
TEMPERATURE (°C)
100
125
0.6
–50 –25
50
25
75
0
TEMPERATURE (°C)
Burst Mode Operation
125
3633a23 G15
3633a23 G14
3633a23 G13
100
Load Step
VOUT
AC-COUPLED
100mV/DIV
SW
10V/DIV
VOUT
50mV/DIV
IL
2A/DIV
IL
1A/DIV
5µs/DIV
VOUT = 1.8V
ILOAD = 100mA
3633a23 G17
20µs/DIV
VOUT = 1.8V
ILOAD = 100mA to 3A
CITH = 220pF
RITH = 13kΩ
3633a23 G18
3633a23fb
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For more information www.linear.com/LTC3633A-2
LTC3633A-2/LTC3633A-3
T
TYPICAL
PERFORMANCE CHARACTERISTICS J = 25°C, PVIN1 = PVIN2 = SVIN = 12V, fSW = 1MHz,
L = 1µH unless otherwise noted.
Load Step (Internal Compensation)
VOUT
AC-COUPLED
100mV/DIV
IL
2A/DIV
20µs/DIV
VOUT = 1.8V
ILOAD = 100mA to 3A
ITH = INTVCC
RUN
2V/DIV
RUN
2V/DIV
VOUT
1V/DIV
VOUT
1V/DIV
IL
2A/DIV
IL
1A/DIV
3633a23 G19
VOUT = 1.8V
CSS = 4.7nF
ILOAD = 150mA
400µs/DIV
RUN
2V/DIV
RUN
2V/DIV
VOUT 1.8V
1V/DIV
VOUT 1.8V
1V/DIV
IL
1A/DIV
IL
2A/DIV
200µs/DIV
3633a23 G20
VOUT = 1.8V
CSS = 4.7nF
ILOAD = 150mA
400µs/DIV
3633a23 G21
Start-Up into Prebiased Output
(Forced Continuous Mode)
Start-Up into Prebiased Output
(Burst Mode Operation)
ILOAD = 0mA
Start-Up (Forced Continuous Mode)
Start-Up (Burst Mode Operation)
3633a23 G22
ILOAD = 0mA
1ms/DIV
3633a23 G23
3633a23fb
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7
LTC3633A-2/LTC3633A-3
PIN FUNCTIONS
(QFN/TSSOP)
PGOOD1 (Pin 1/Pin 4): Channel 1 Open-Drain Power
Good Output Pin. PGOOD1 is pulled to ground when the
voltage on the VFB1 pin is not within ±8% (typical) of the
internal 0.6V reference. PGOOD1 becomes high impedance once the VFB1 pin returns to within ±5% (typical) of
the internal reference.
PHMODE (Pin 2/Pin 5): Phase Select Input. Tie this pin
to ground to force both channels to switch in phase. Tie
this pin to INTVCC to force both channels to switch 180°
out of phase. Do not float this pin.
RUN1 (Pin 3/Pin 6): Channel 1 Regulator Enable Pin.
Enables channel 1 operation by tying RUN1 above 1.22V.
Tying it below 1V places channel 1 into shutdown. Do not
float this pin.
MODE/SYNC (Pin 4/Pin 7): Mode Select and External
Synchronization Input. Tie this pin to ground to force
continuous synchronous operation at all output loads.
Floating this pin or tying it to INTVCC enables high efficiency Burst Mode operation at light loads. Drive this pin
with a clock to synchronize the LTC3633A-2 switching.
An internal phase-locked loop will force the bottom power
NMOS’s turn on signal to be synchronized with the rising
edge of the CLKIN signal. When this pin is driven with a
clock, forced continuous mode is automatically selected.
RT (Pin 5/Pin 8): Oscillator Frequency Program Pin.
Connect an external resistor (between 80k to 640k) from
this pin to SGND in order to program the frequency from
500kHz to 4MHz. When RT is tied to INTVCC, the switching
frequency will default to 2MHz.
RUN2 (Pin 6/Pin 9): Channel 2 Regulator Enable Pin.
Enables channel 2 operation by tying RUN2 above 1.22V.
Tying it below 1V places channel 2 into shutdown. Do not
float this pin.
SGND (Pin 7/Pin 10): Signal Ground Pin. This pin should
have a low noise connection to reference ground. The
feedback resistor network, external compensation network,
and RT resistor should be connected to this ground.
PGOOD2 (Pin 8/Pin 11): Channel 2 Open-Drain Power
Good Output Pin. PGOOD2 is pulled to ground when the
voltage on the VFB2 pin is not within ±8% (typical) of the
internal 0.6V reference. PGOOD2 becomes high impedance once the VFB2 pin returns to within ±5% (typical) of
the internal reference.
VFB2 (Pin 9/Pin 12): Channel 2 Output Feedback Voltage
Pin. Input to the error amplifier that compares the feedback
voltage to the internal 0.6V reference voltage. Connect this
pin to a resistor divider network to program the desired
output voltage.
TRACKSS2 (Pin 10/Pin 13): Output Tracking and SoftStart Input Pin for Channel 2. Forcing a voltage below
0.6V on this pin bypasses the internal reference input to
the error amplifier. The LTC3633A-2 will servo the FB pin
to the TRACK voltage under this condition. Above 0.6V,
the tracking function stops and the internal reference
resumes control of the error amplifier. An internal 1.4µA
pull up current from INTVCC allows a soft start function
to be implemented by connecting a capacitor between
this pin and SGND.
ITH2 (Pin 11/Pin 14): Channel 2 Error Amplifier Output
and Switching Regulator Compensation Pin. Connect this
pin to appropriate external components to compensate
the regulator loop frequency response. Connect this pin
to INTVCC to use the default internal compensation.
VON2 (Pin 12/Pin 15): On-Time Voltage Input for Channel 2. This pin sets the voltage trip point for the on-time
comparator. Tying this pin to the output voltage makes
the on-time proportional to VOUT2 when VOUT2 is within
the VON2 sense range (0.6V – 6V for LTC3633A-2, 1.5V
– 12V for LTC3633A-3). When VOUT2 is outside the VON2
sense range, the switching frequency may deviate from
the programmed frequency. The pin impedance is nominally 140kΩ.
SW2 (Pins 13, 14/Pins 16, 17): Channel 2 Switch Node
Connection to External Inductor. Voltage swing of SW is
from a diode voltage drop below ground to PVIN.
PVIN2 (Pins 15, 16/Pins 18, 19): Power Supply Input for
Channel 2. Input voltage to the on chip power MOSFETs
on channel 2. This input is capable of operating from a
different supply voltage than PVIN1.
3633a23fb
8
For more information www.linear.com/LTC3633A-2
LTC3633A-2/LTC3633A-3
PIN FUNCTIONS
(QFN/TSSOP)
BOOST2 (Pin 17/Pin 20): Boosted Floating Driver Supply
for Channel 2. The (+) terminal of the bootstrap capacitor
connects to this pin while the (–) terminal connects to
the SW pin. The normal operation voltage swing of this
pin ranges from a diode voltage drop below INTVCC up
to PVIN+INTVCC.
INTVCC (Pin 18/Pin 21): Internal 3.3V Regulator Output.
The internal power drivers and control circuits are powered
from this voltage. The internal regulator is disabled when
both channel 1 and channel 2 are disabled with the RUN1/
RUN2 inputs. Decouple this pin to power ground with a
minimum of 1µF low ESR ceramic capacitor.
BOOST1 (Pin 19/Pin 22): Boosted Floating Driver Supply
for Channel 1. The (+) terminal of the bootstrap capacitor
connects to this pin while the (–) terminal connects to
the SW pin. The normal operation voltage swing of this
pin ranges from a diode voltage drop below INTVCC up
to PVIN + INTVCC.
SVIN (Pin 20/Pin 23): Signal Input Supply. This pin powers
the internal control circuitry. The internal LDO for INTVCC
is powered from this pin.
PVIN1 (Pins 21, 22/Pins 24, 25): Power Supply Input for
Channel 1. Input voltage to the on chip power MOSFETs
on channel 1.
SW1 (Pins 23,24/Pins 26, 27): Channel 1 Switch Node
Connection to External Inductor. Voltage swing of SW is
from a diode voltage drop below ground to PVIN.
VON1 (Pin 25/Pin 28): On-Time Voltage Input for Channel 1. This pin sets the voltage trip point for the on-time
comparator. Tying this pin to the regulated output voltage
makes the on-time proportional to VOUT1 when VOUT1 is
within the VON1 sense range (0.6V – 6V for LTC3633A-2,
1.5V – 12V for LTC3633A-3). When VOUT is outside the
VON sense range, the switching frequency may deviate
from the programmed frequency. The pin impedance is
nominally 140kΩ.
ITH1 (Pin 26/Pin 1): Channel 1 Error Amplifier Output and
Switching Regulator Compensation Pin. Connect this pin
to appropriate external components to compensate the
regulator loop frequency response. Connect this pin to
INTVCC to use the default internal compensation.
TRACKSS1 (Pin 27/Pin 2): Output Tracking and Soft-Start
Input Pin for Channel 1. Forcing a voltage below 0.6V on
this pin bypasses the internal reference input to the error
amplifier. The LTC3633A-2 will servo the FB pin to the
TRACK voltage. Above 0.6V, the tracking function stops
and the internal reference resumes control of the error
amplifier. An internal 1.4µA pull up current from INTVCC
allows a soft-start function to be implemented by connecting a capacitor between this pin and SGND.
VFB1 (Pin 28/Pin 3): Channel 1 Output Feedback Voltage
Pin. Input to the error amplifier that compares the feedback
voltage to the internal 0.6V reference voltage. Connect this
pin to a resistor divider network to program the desired
output voltage.
PGND (Exposed Pad Pin 29/Exposed Pad Pin 29): Power
Ground Pin. The (–) terminal of the input bypass capacitor, CIN, and the (–) terminal of the output capacitor, COUT,
should be tied to this pin with a low impedance connection. This pin must be soldered to the PCB to provide low
impedance electrical contact to power ground and good
thermal contact to the PCB.
3633a23fb
For more information www.linear.com/LTC3633A-2
9
LTC3633A-2/LTC3633A-3
BLOCK DIAGRAM
CIN
RUN
VON
PVIN
1.22V
140k
+
AV = 1
–
RUN
PVIN
0.6V (LTC3633A-2)
1.5V (LTC3633A-3)
ION
ION
CONTROLLER
OSC1
INTVCC
6V (LTC3633A-2)
12V (LTC3633A-3)
V
tON = VON
IION
RUN
R
S Q
ON
BOOST
SWITCH
LOGIC
AND
ANTISHOOT
THROUGH
TG
M1
COUT
BG
ICMP
+
COMP
SELECT
M2
IREV
–
–
CBOOST
L1
SW
PGND
+
SENSE–
SENSE+
R2
ITH
FB
RC
IDEAL DIODES
CC1
R1
0.6V
REF
–
EA
–
+
0.648V
INTERNAL
SOFT-START
0V
PGOOD
+
INTVCC
1.4µA
–
TRACK
–
UV
TRACKSS
SS
+
0.552V
+
FC BURST
MODE
SELECT
CSS
0.48V AT START-UP
0.10V AFTER START-UP
CHANNEL 1
OSC1
SVIN
CSVIN
RT
OSC
OSC
PLL-SYNC
MODE/SYNC
3.3V
REG
RRT
PHMODE
PHASE
SELECT
INTVCC
CVCC
SGND
OSC2
CHANNEL 2 (SAME AS CHANNEL 1)
3633a23 BD
3633a23fb
10
For more information www.linear.com/LTC3633A-2
LTC3633A-2/LTC3633A-3
OPERATION
The LTC3633A-2 is a dual-channel, current mode monolithic
step down regulator capable of providing 3A of output
current from each channel. Its unique controlled on-time
architecture allows extremely low step-down ratios while
maintaining a constant switching frequency. Each channel
is enabled by raising the voltage on the RUN pin above
1.22V nominally.
The LTC3633A-2 has a VON sense range of 0.6V to 6V, while
the LTC3633A-3 has a VON sense range of 1.5V to 12V. The
following table highlights the difference between the parts
in the 3633A family. Consult the LTC3633A/LTC3633A-1
data sheet for more details on specific characteristics of
those products.
Table 1. LTC3633A Family Features
PART
NUMBER
OUTPUT
VOLTAGE
SENSE RANGE
SVIN
INPUT
V2P5
OUTPUT
LTC3633 PIN
COMPATIBLE
LTC3633A
0.6V TO 6V
NO
YES
YES
LTC3633A-1
1.5V TO 12V
NO
YES
YES
LTC3633A-2
0.6V TO 6V
YES
NO
NO
LTC3633A-3
1.5V TO 12V
YES
NO
NO
Main Control Loop
In normal operation, the internal top power MOSFET is
turned on for a fixed interval determined by a fixed one-shot
timer (“ON” signal in Block Diagram). When the top power
MOSFET turns off, the bottom power MOSFET turns on until
the current comparator ICMP trips, thus restarting the one
shot timer and initiating the next cycle. Inductor current is
measured by sensing the voltage drop across the SW and
PGND nodes of the bottom power MOSFET. The voltage on
the ITH pin sets the comparator threshold corresponding
to inductor valley current. The error amplifier EA adjusts
this ITH voltage by comparing an internal 0.6V reference to
the feedback signal VFB derived from the output voltage. If
the load current increases, it causes a drop in the feedback
voltage relative to the internal reference. The ITH voltage
then rises until the average inductor current matches that
of the load current.
The operating frequency is determined by the value of the
RT resistor, which programs the current for the internal oscillator. An internal phase-locked loop servos the switching
regulator on-time to track the internal oscillator edge and
force a constant switching frequency. A clock signal can be
applied to the MODE/SYNC pin to synchronize the switching
frequency to an external source. The regulator defaults to
forced continuous operation once the clock signal is applied.
At light load currents, the inductor current can drop to zero
and become negative. In Burst Mode operation, a current
reversal comparator (IREV) detects the negative inductor
current and shuts off the bottom power MOSFET, resulting in discontinuous operation and increased efficiency.
Both power MOSFETs will remain off until the ITH voltage
rises above the zero current level to initiate another cycle.
During this time, the output capacitor supplies the load
current and the part is placed into a low current sleep
mode. Discontinuous mode operation is disabled by tying
the MODE/SYNC pin to ground, which forces continuous
synchronous operation regardless of output load current.
“Power Good” Status Output
The PGOOD open-drain output will be pulled low if the
regulator output exits a ±8% window around the regulation
point. This condition is released once regulation within a
±5% window is achieved. To prevent unwanted PGOOD
glitches during transients or dynamic VOUT changes, the
LTC3633A-2 PGOOD falling edge includes a filter time of
approximately 40µs.
PVIN Overvoltage Protection
In order to protect the internal power MOSFET devices
against transient input voltage spikes, the LTC3633A-2
constantly monitors each PVIN pin for an overvoltage
condition. When PVIN rises above 22.5V, the regulator
suspends operation by shutting off both power MOSFETs
on the corresponding channel. Once PVIN drops below
21.5V, the regulator immediately resumes normal operation. The regulator executes its soft-start function when
exiting an overvoltage condition.
Out-Of-Phase Operation
Tying the PHMODE pin high sets the SW2 falling edge to
be 180° out of phase with the SW1 falling edge. There is
a significant advantage to running both channels out of
phase. When running the channels in phase, both top-side
MOSFETs are on simultaneously, causing large current
pulses to be drawn from the input capacitor and supply
at the same time.
For more information www.linear.com/LTC3633A-2
3633a23fb
11
LTC3633A-2/LTC3633A-3
OPERATION
When running the LTC3633A-2 channels out of phase, the
large current pulses are interleaved, effectively reducing
the amount of time the pulses overlap. Thus, the total
RMS input current is decreased, which both relaxes the
capacitance requirements for the input bypass capacitors
and reduces the voltage noise on the supply line.
One potential disadvantage to this configuration occurs
when one channel is operating at 50% duty cycle. In this
situation, switching noise can potentially couple from one
channel to the other, resulting in frequency jitter on one
or both channels. This effect can be mitigated with a well
designed board layout.
APPLICATIONS INFORMATION
6000
5000
FREQUENCY (kHz)
A general LTC3633A-2 application circuit is shown on the
first page of this data sheet. External component selection
is largely driven by the load requirement and switching
frequency. Component selection typically begins with
the selection of the inductor L and resistor RT. Once the
inductor is chosen, the input capacitor, CIN, and the output capacitor, COUT, can be selected. Next, the feedback
resistors are selected to set the desired output voltage.
Finally, the remaining optional external components can be
selected for functions such as external loop compensation,
tracking/soft-start, input UVLO, and PGOOD.
4000
3000
2000
1000
0
0
100
200 300 400 500
RT RESISTOR (kΩ)
Programming Switching Frequency
600
700
3633a23 F01
Selection of the switching frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
Connecting a resistor from the RT pin to SGND programs
the switching frequency (f) between 500kHz and 4MHz
according to the following formula:
3.2E11
RRT =
f
where RRT is in Ω and f is in Hz.
When RT is tied to INTVCC, the switching frequency will
default to approximately 2MHz, as set by an internal resistor. This internal resistor is more sensitive to process
and temperature variations than an external resistor
(see Typical Performance Characteristics) and is best used
for applications where switching frequency accuracy is
not critical.
Figure 1. Switching Frequency vs RT
Inductor Selection
For a given input and output voltage, the inductor value and
operating frequency determine the inductor ripple current.
More specifically, the inductor ripple current decreases
with higher inductor value or higher operating frequency
according to the following equation:
V
V
∆IL = OUT 1– OUT
f •L
VIN
Where ΔIL = inductor ripple current, f = operating frequency
L = inductor value and VIN is the input power supply voltage
applied to the PVIN inputs. A trade-off between component
size, efficiency and operating frequency can be seen from
this equation. Accepting larger values of ∆IL allows the
use of lower value inductors but results in greater inductor
core loss, greater ESR loss in the output capacitor, and
larger output voltage ripple. Generally, highest efficiency
operation is obtained at low operating frequency with
small ripple current.
3633a23fb
12
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LTC3633A-2/LTC3633A-3
APPLICATIONS INFORMATION
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest PVIN. Exceeding 60% of
IOUT(MAX) is not recommended. To guarantee that ripple
current does not exceed a specified maximum, the inductance should be chosen according to:
V
V
OUT
1– OUT
L =
f • ∆IL(MAX) VIN(MAX)
The inductor ripple current also must not be so large that
its valley current level exceeds the negative current limit,
which can be as small as –1.2A. If the negative current
limit is exceeded while the part is in the forced continuous mode of operation, VOUT can get charged up to above
its regulation level – until the inductor current no longer
exceeds the negative current limit. In such instances,
choose a larger inductor value to reduce the inductor
ripple current. The alternative is to reduce the inductor
ripple current by decreasing the RT resistor value which
will increase the switching frequency.
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire, leading to increased DCR
and copper loss.
Ferrite designs exhibit very low core loss and are preferred at high switching frequencies, so design goals
can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means
that inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current, so it is important to ensure that
the core will not saturate.
Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. Table 1 gives a
sampling of available surface mount inductors.
Table 1. Inductor Selection Table
INDUCTANCE DCR
(µH)
(mΩ)
MAX
DIMENSIONS
CURRENT
(mm)
(A)
Würth Electronik WE-HC 744312 Series
0.25
2.5
18
7 × 7.7
0.47
16
3.4
0.72
7.5
12
1.0
9.5
11
1.5
10.5
9
Vishay IHLP-2020BZ-01 Series
0.22
5.2
15
5.2 × 5.5
0.33
8.2
12
0.47
8.8
11.5
0.68
12.4
10
1
20
7
Toko FDV0620 Series
0.20
4.5
12.4
7 × 7.7
0.47
8.3
9.0
1.0
18.3
5.7
Coilcraft D01813H Series
0.33
4
10
6 × 8.9
0.56
10
7.7
1.2
17
5.3
TDK RLF7030 Series
1.0
8.8
6.4
6.9 × 7.3
1.5
9.6
6.1
HEIGHT
(mm)
3.8
2
2.0
5.0
3.2
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the trapezoidal wave current at the drain of the top power MOSFET.
To prevent large voltage transients from occurring, a low
ESR input capacitor sized for the maximum RMS current is
recommended. The maximum RMS current is given by:
IRMS = IOUT(MAX)
VOUT ( VIN − VOUT )
VIN
This formula has a maximum at VIN = 2VOUT, where
IRMS ≅ IOUT/2. This simple worst case condition is commonly used for design because even significant deviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher
temperature than required.
3633a23fb
For more information www.linear.com/LTC3633A-2
13
LTC3633A-2/LTC3633A-3
APPLICATIONS INFORMATION
Several capacitors may also be paralleled to meet size or
height requirements in the design. For low input voltage
applications, sufficient bulk input capacitance is needed
to minimize transient effects during output load changes.
Even though the LTC3633A-2 design includes an overvoltage protection circuit, care must always be taken to
ensure input voltage transients do not pose an overvoltage
hazard to the part.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response. The output ripple, ΔVOUT, is
approximated by:
1
∆VOUT < ∆IL ESR +
8 • f • COUT
3 • ∆IOUT
f • VDROOP
Though this equation provides a good approximation, more
capacitance may be required depending on the duty cycle
and load step requirements. The actual VDROOP should be
verified by applying a load step to the output.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are available
in small case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
14
When choosing the input and output ceramic capacitors,
choose the X5R and X7R dielectric formulations. These
dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
INTVCC Regulator Bypass Capacitor
When using low-ESR ceramic capacitors, it is more useful
to choose the output capacitor value to fulfill a charge storage requirement. During a load step, the output capacitor
must instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and the
output capacitor size. Typically, 3 to 4 cycles are required
to respond to a load step, but only in the first cycle does
the output drop linearly. The output droop, VDROOP, is
usually about 3 times the linear drop of the first cycle.
Thus, a good place to start is with the output capacitor
size of approximately:
COUT ≈
applications. However, due to the self-resonant and high-Q
characteristics of some types of ceramic capacitors, care
must be taken when these capacitors are used at the input.
When a ceramic capacitor is used at the input and the
power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the PVIN
input. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at PVIN large enough to damage the part. For
a more detailed discussion, refer to Application Note 88.
An internal low dropout (LDO) regulator draws power
from the SVIN input and produces the 3.3V supply that
powers the internal bias circuitry and drives the gate of
the internal MOSFET switches. The INTVCC pin connects
to the output of this regulator and must have a minimum
of 1µF ceramic decoupling capacitance to ground. The
decoupling capacitor should have low impedance electrical
connections to the INTVCC and PGND pins to provide the
transient currents required by the LTC3633A-2. This supply is intended only to supply additional DC load currents
as desired and not intended to regulate large transient or
AC behavior, as this may impact LTC3633A-2 operation.
As long as the INTVCC rail is powered by SVIN, the regulator control circuitry will operate, regardless of the PVIN
voltages. Thus, the SVIN input can be powered from a
different supply voltage than either PVIN1 or PVIN2. This
characteristic makes the LTC3633A-2/LTC3633A-3 very
flexible and easy to use in systems with multiple power
sources.
Operating from Multiple Power Sources
Channel 1 and channel 2 may be operated from separate
input power sources. In cases where one power source is
disconnected, the other regulator can continue to operate
provided that SVIN remain powered. This can be done with
a simple diode-OR circuit, as shown in Figure 2.
For more information www.linear.com/LTC3633A-2
3633a23fb
LTC3633A-2/LTC3633A-3
APPLICATIONS INFORMATION
SUPPLY1
or phase margin reduction due to stray capacitances
at the VFB node. Care should be taken to route the VFB
trace away from any noise source, such as the SW trace.
To improve the frequency response of the main control
loop, a feedforward capacitor, CF , may be used as shown
in Figure 3.
PVIN1
LTC3633A-2
SVIN
SUPPLY2
PVIN2
3633a23 F02
Figure 2. Diode-OR Circuit
Furthermore, as long as SVIN is powered, the LTC3633A-2/
LTC3633A-3 operates as a step-down regulator with PVIN
voltages as low as 1.5V (subject to minimum off-time
constraints). However, at PVIN voltages less than 3V, internal on-time calculation errors increase, and controlled
on-time operation is not guaranteed. If this occurs, the
output voltages will remain in regulation, but the switching frequency of each channel may deviate from the
programmed frequency under these conditions and phase
lock between the two channels may be lost.
Connecting the VON pin to the output voltage makes the
on-time proportional the output voltage and allows the
internal on-time servo loop to lock the converter’s switching
frequency to the programmed value. If the output voltage
is outside the VON sense range (0.6V – 6V for LTC3633A-2,
1.5V – 12V for LTC3633A-3), the output voltage will stay
in regulation, but the switching frequency may deviate
from the programmed frequency.
VOUT
R2
FB
LTC3633A-2
Boost Capacitor
The LTC3633A-2 uses a “bootstrap” circuit to create a
voltage rail above the applied input voltage PVIN. Specifically, a boost capacitor, CBOOST, is charged to a voltage
approximately equal to INTVCC each time the bottom power
MOSFET is turned on. The charge on this capacitor is then
used to supply the required transient current during the
remainder of the switching cycle. When the top MOSFET
is turned on, the BOOST pin voltage will be equal to approximately PVIN + 3.3V. For most applications, a 0.1µF
ceramic capacitor closely connected between the BOOST
and SW pins will provide adequate performance.
CF
R1
SGND
3633a23 F02
Figure 3. Setting the Output Voltage
Minimum Off-Time/On-Time Considerations
The minimum off-time is the smallest amount of time that
the LTC3633A-2 can turn on the bottom power MOSFET,
trip the current comparator and turn the power MOSFET
back off. This time is typically 45ns. For the controlled
on-time architecture, the minimum off-time limit imposes
a maximum duty cycle of:
DC(MAX) = 1– f • ( tOFF(MIN) + 2 • tDEAD )
Output Voltage Programming
Each regulator’s output voltage is set by an external resistive divider according to the following equation:
where f is the switching frequency, tDEAD is the nonoverlap
time, or “dead time” (typically 10ns) and tOFF(MIN) is the
minimum off-time. If the maximum duty cycle is surpassed,
due to a dropping input voltage for example, the output
will drop out of regulation. The minimum input voltage to
avoid this dropout condition is:
R2
VOUT = 0.6V 1+
R1
The desired output voltage is set by appropriate selection
of resistors R1 and R2 as shown in Figure 3. Choosing
large values for R1 and R2 will result in improved zeroload efficiency but may lead to undesirable noise coupling
VIN(MIN) =
VOUT
1− f • ( tOFF(MIN) + 2 • tDEAD )
3633a23fb
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15
LTC3633A-2/LTC3633A-3
APPLICATIONS INFORMATION
Conversely, the minimum on-time is the smallest duration of time in which the top power MOSFET can be in
its “on” state. This time is typically 20ns. In continuous
mode operation, the minimum on-time limit imposes a
minimum duty cycle of:
capacitor CF can be added to improve the high frequency
response, as previously shown in Figure 3. Capacitor CF
provides phase lead by creating a high frequency zero
with R2 which improves the phase margin.
ITH
DC(MIN) = ( f • tON(MIN) )
RCOMP
13k
CCOMP
220pF
LTC3633A-2
where tON(MIN) is the minimum on-time. As the equation
shows, reducing the operating frequency will alleviate the
minimum duty cycle constraint.
In the rare cases where the minimum duty cycle is
surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its
programmed value. This constraint may not be of critical
importance in most cases, so high switching frequencies
may be used in the design without any fear of severe
consequences. As the sections on Inductor and Capacitor
selection show, high switching frequencies allow the use
of smaller board components, thus reducing the footprint
of the application circuit.
Internal/External Loop Compensation
The LTC3633A-2 provides the option to use a fixed internal
loop compensation network to reduce both the required
external component count and design time. The internal
loop compensation network can be selected by connecting the ITH pin to the INTVCC pin. To ensure stability it is
recommended that internal compensation only be used with
applications with fSW > 1MHz. Alternatively, the user may
choose specific external loop compensation components
to optimize the main control loop transient response as
desired. External loop compensation is chosen by simply
connecting the desired network to the ITH pin.
Suggested compensation component values are shown in
Figure 4. For a 2MHz application, an R-C network of 220pF
and 13kΩ provides a good starting point. The bandwidth
of the loop increases with decreasing C. If R is increased
by the same factor that C is decreased, the zero frequency
will be kept the same, thereby keeping the phase the same
in the most critical frequency range of the feedback loop.
A 10pF bypass capacitor on the ITH pin is recommended
for the purposes of filtering out high frequency coupling
from stray board capacitance. In addition, a feedforward
SGND
3633a23 F04
Figure 4. Compensation Component
Checking Transient Response
The regulator loop response can be checked by observing
the response of the system to a load step. When configured
for external compensation, the availability of the ITH pin
not only allows optimization of the control loop behavior
but also provides a DC-coupled and AC filtered closed loop
response test point. The DC step, rise time, and settling
behavior at this test point reflect the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin.
The ITH external components shown in Figure 4 circuit
will provide an adequate starting point for most applications. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because their various types and values determine the
loop gain and phase. An output current pulse of 20% to
100% of full load current having a rise time of ~1µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where
ESR is the effective series resistance of COUT. ΔILOAD also
begins to charge or discharge COUT generating a feedback
error signal used by the regulator to return VOUT to its
3633a23fb
16
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LTC3633A-2/LTC3633A-3
APPLICATIONS INFORMATION
steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
When observing the response of VOUT to a load step, the
initial output voltage step may not be within the bandwidth
of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
In some applications, a more severe transient can be
caused by switching in loads with large (>10µF) input
capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in
VOUT. No regulator can deliver enough current to prevent
this problem, if the switch connecting the load has low
resistance and is driven quickly. The solution is to limit
the turn-on speed of the load switch driver. A hot swap
controller is designed specifically for this purpose and
usually incorporates current limiting, short-circuit protection, and soft starting.
MODE/SYNC Operation
The MODE/SYNC pin is a multipurpose pin allowing both
mode selection and operating frequency synchronization.
Floating this pin or connecting it to INTVCC enables Burst
Mode operation for superior efficiency at low load currents
at the expense of slightly higher output voltage ripple. When
the MODE/SYNC pin is tied to ground, forced continuous
mode operation is selected, creating the lowest fixed output
ripple at the expense of light load efficiency.
The LTC3633A-2 will detect the presence of the external
clock signal on the MODE/SYNC pin and synchronize the
internal oscillator to the phase and frequency of the incoming clock. The presence of an external clock will place
both regulators into forced continuous mode operation.
Output Voltage Tracking and Soft-Start
The LTC3633A-2 allows the user to control the output
voltage ramp rate by means of the TRACKSS pin. From
0 to 0.6V, the TRACKSS voltage will override the internal
0.6V reference input to the error amplifier, thus regulating
the feedback voltage to that of the TRACKSS pin. When
TRACKSS is above 0.6V, tracking is disabled and the feedback voltage will regulate to the internal reference voltage.
The voltage at the TRACKSS pin may be driven from an
external source, or alternatively, the user may leverage
the internal 1.4µA pull-up current source to implement
a soft-start function by connecting an external capacitor
(CSS) from the TRACKSS pin to ground. The relationship
between output rise time and TRACKSS capacitance is
given by:
tSS = 430000Ω • CSS
A default internal soft-start ramp forces a minimum softstart time of 400µs by overriding the TRACKSS pin input
during this time period. Hence, capacitance values less
than approximately 1000pF will not significantly affect
soft-start behavior.
When driving the TRACKSS pin from another source, each
channel’s output can be set up to either coincidentally or
ratiometrically track another supply’s output, as shown
in Figure 5. In the following discussions, VOUT1 refers to
the LTC3633A-2 output 1 as a master channel and VOUT2
refers to output 2 as a slave channel. In practice, either
channel can be used as the master.
To implement the coincident tracking in Figure 5a, connect an additional resistive divider to VOUT1 and connect
its midpoint to the TRACKSS pin of the slave channel.
The ratio of this divider should be the same as that of the
slave channel’s feedback divider shown in Figure 6a. In
this tracking mode, VOUT1 must be set higher than VOUT2.
To implement the ratiometric tracking, the feedback pin of
the master channel should connect to the TRACKSS pin of
the slave channel (as in Figure 6b). By selecting different
resistors, the LTC3633A-2 can achieve different modes of
tracking including the two in Figure 5.
3633a23fb
For more information www.linear.com/LTC3633A-2
17
LTC3633A-2/LTC3633A-3
APPLICATIONS INFORMATION
VOUT1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT1
VOUT2
TIME
VOUT2
TIME
3633a23 F05a
(5a) Coincident Tracking
3633a23 F05b
(5b) Ratiometric Tracking
Figure 5. Two Different Modes of Output Voltage Tracking
VOUT1
TO
TRACKSS2
PIN
VOUT2
R3
R4
R1
R2
TO
VFB1
PIN
TO
VFB2
PIN
R3
R4
VOUT1
VOUT2
R1
TO
TRACKSS2
PIN
R2
TO
VFB1
PIN
R3
TO
VFB2
PIN
R4
3633a23 F06a
3633a23 F06b
(6a) Coincident Tracking Setup
(6b) Ratiometric Tracking Setup
Figure 6. Setup for Coincident and Ratiometric Tracking
Upon start-up, the regulator defaults to Burst Mode operation until the output exceeds 80% of its final value (VFB >
0.48V). Once the output reaches this voltage, the operating
mode of the regulator switches to the mode selected by
the MODE/SYNC pin as described above. During normal
operation, if the output drops below 10% of its final value
(as it may when tracking down, for instance), the regulator will automatically switch to Burst Mode operation to
prevent inductor saturation and improve TRACKSS pin
accuracy.
Output Power Good
The PGOOD output of the LTC3633A-2 is driven by a 20Ω
(typical) open-drain pull-down device. This device will be
turned off once the output voltage is within 5% (typical) of
the target regulation point, allowing the voltage at PGOOD
to rise via an external pull-up resistor. If the output voltage
exits an 8% (typical) regulation window around the target
regulation point, the open-drain output will pull down
with 20Ω output resistance to ground, thus dropping the
PGOOD pin voltage. This behavior is described in Figure 7.
NOMINAL OUTPUT
PGOOD
VOLTAGE
–8%
–5%
0%
5%
8%
OUTPUT VOLTAGE
3633a23 F07
Figure 7. PGOOD Pin Behavior
A filter time of 40µs (typical) acts to prevent unwanted
PGOOD output changes during VOUT transient events.
As a result, the output voltage must be within the target
regulation window of 5% for 40µs before the PGOOD pin
pulls high. Conversely, the output voltage must exit the
8% regulation window for 40µs before the PGOOD pin
pulls to ground.
3633a23fb
18
For more information www.linear.com/LTC3633A-2
LTC3633A-2/LTC3633A-3
APPLICATIONS INFORMATION
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 +…)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of the
losses in LTC3633A-2 circuits: 1) I2R losses, 2) switching
losses and quiescent power loss 3) transition losses and
other losses.
1. I2R losses are calculated from the DC resistances of the
internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flows through
inductor L but is “chopped” between the internal top and
bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
2. The internal LDO draws power from the SVIN input to
regulate the INTVCC rail. The total power loss here is
the sum of the switching losses and quiescent current
losses from the control circuitry.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves from
VIN to ground. The resulting dQ/dt is a current out of
INTVCC that is typically much larger than the DC control
bias current. In continuous mode, IGATECHG = f(QT + QB),
where QT and QB are the gate charges of the internal
top and bottom power MOSFETs and f is the switching
frequency. For estimation purposes, (QT + QB) on each
LTC3633A-2 regulator channel is approximately 2.3nC.
To calculate the total power loss from the LDO load,
simply add the gate charge current and quiescent current and multiply by the voltage applied to SVIN:
PLDO = (IGATECHG + IQ) • SVIN
3. Other “hidden” losses such as transition loss, copper trace resistances, and internal load currents can
account for additional efficiency degradations in the
overall power system. Transition loss arises from the
brief amount of time the top power MOSFET spends
in the saturated region during switch node transitions.
The LTC3633A-2 internal power devices switch quickly
enough that these losses are not significant compared
to other sources.
Other losses, including diode conduction losses during
dead-time and inductor core losses, generally account
for less than 2% total additional loss.
Thermal Considerations
The LTC3633A-2 requires the exposed package backplane
metal (PGND) to be well soldered to the PC board to
provide good thermal contact. This gives the QFN and
TSSOP packages exceptional thermal properties, which
are necessary to prevent excessive self-heating of the part
in normal operation.
In a majority of applications, the LTC3633A-2 does not
dissipate much heat due to its high efficiency and low
thermal resistance of its exposed-back QFN package.
However, in applications where the LTC3633A-2 is running
at high ambient temperature, high input supply voltage,
high switching frequency, and maximum output current
load, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature
reaches approximately 150°C, both power switches will
be turned off until temperature returns to 140°C.
To prevent the LTC3633A-2 from exceeding the maximum
junction temperature of 125°C, the user will need to do
some thermal analysis. The goal of the thermal analysis
is to determine whether the power dissipated exceeds the
maximum junction temperature of the part. The temperature rise is given by:
TRISE = PD • θJA
3633a23fb
For more information www.linear.com/LTC3633A-2
19
LTC3633A-2/LTC3633A-3
APPLICATIONS INFORMATION
1.8V
10.2V
RDS(ON)TOP •
+RDS(ON)BOT •
= 81.3mΩ
12V
12V
From the previous section’s discussion on gate drive, we
estimate the total gate drive current through the LDO to be
2MHz • 2.3nC = 4.6mA, and IQ of one channel is 0.65mA
(see Electrical Characteristics). Therefore, the total power
dissipated by a single regulator is:
PD = IOUT2 • RSW + SVIN • (IGATECHG + IQ)
PD = (2A)2 • (0.0813Ω) + (12V) • (4.6mA + 0.65mA)
= 0.388W
Running two regulators under the same conditions would
result in a power dissipation of 0.776W. The QFN 5mm
× 4mm package junction-to-ambient thermal resistance,
θJA, is around 43°C/W. Therefore, the junction temperature
of the regulator operating in a 70°C ambient temperature
is approximately:
TJ = 0.776W • 43°C/W + 70°C = 103°C
which is below the maximum junction temperature of
125°C. With higher ambient temperatures, a heat sink
or cooling fan should be considered to drop the junction-to-ambient thermal resistance. Alternatively, the
TSSOP package may be a better choice for high power
applications, since it has better thermal properties than
the QFN package.
Remembering that the above junction temperature is
obtained from an RDS(ON) at 70°C, we might recalculate
the junction temperature based on a higher RDS(ON) since
it increases with temperature. Redoing the calculation
assuming that RSW increased 12% at 103°C yields a new
junction temperature of 107°C. If the application calls for
a higher ambient temperature and/or higher load currents,
care should be taken to reduce the temperature rise of the
part by using a heat sink or air flow.
Figure 8 is a temperature derating curve based on the
DC1347 demo board (QFN package). It can be used to
estimate the maximum allowable ambient temperature
for given DC load currents in order to avoid exceeding
the maximum operating junction temperature of 125°C.
3.5
CHANNEL 1 LOAD CURRENT (A)
As an example, consider the case when one of the regulators is used in an application where VIN = SVIN = 12V,
IOUT = 2A, frequency = 2MHz, VOUT = 1.8V. From the RDS(ON)
graphs in the Typical Performance Characteristics section,
the top switch on-resistance is nominally 145mΩ and the
bottom switch on-resistance is nominally 70mΩ at 70°C
ambient. The equivalent power MOSFET resistance RSW is:
3.0
2.5
2.0
1.5
1.0
CH2 LOAD = 0A
CH2 LOAD = 1A
CH2 LOAD = 2A
CH2 LOAD = 3A
0.5
0
0
25
75
100
50
MAXIMUM ALLOWABLE AMBIENT
TEMPERATURE (°C)
125
3633a23 F08
Figure 8. Temperature Derating Curve for DC1347 Demo Circuit
Junction Temperature Measurement
The junction-to-ambient thermal resistance will vary depending on the size and amount of heat sinking copper
on the PCB board where the part is mounted, as well as
the amount of air flow on the device. In order to properly
evaluate this thermal resistance, the junction temperature
needs to be measured. A clever way to measure the junction
temperature directly is to use the internal junction diode
on one of the pins (PGOOD) to measure its diode voltage
change based on ambient temperature change.
First remove any external passive component on the PGOOD
pin, then pull out 100μA from the PGOOD pin to turn on its
internal junction diode and bias the PGOOD pin to a negative
voltage. With no output current load, measure the PGOOD
voltage at an ambient temperature of 25°C, 75°C and 125°C
to establish a slope relationship between the delta voltage on
PGOOD and delta ambient temperature. Once this slope is established, then the junction temperature rise can be measured
as a function of power loss in the package with corresponding
output load current. Although making this measurement with
this method does violate absolute maximum voltage ratings
on the PGOOD pin, the applied power is so low that there
should be no significant risk of damaging the device.
3633a23fb
20
For more information www.linear.com/LTC3633A-2
LTC3633A-2/LTC3633A-3
APPLICATIONS INFORMATION
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3633A-2. Check the following in your layout:
1) Do the input capacitors connect to the PVIN and PGND
pins as close as possible? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers.
2) The output capacitor, COUT, and inductor L should be
closely connected to minimize loss. The (–) plate of
COUT should be closely connected to both PGND and
the (–) plate of CIN.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, the correct RT resistor value for 2MHz switching frequency must be chosen. Based on the equation discussed
earlier, RT should be 160k; the closest standard value is
162k. RT can be tied to INTVCC if switching frequency
accuracy is not critical.
Next, determine the channel 1 inductor value for about
40% ripple current at maximum VIN:
1.8V
1.8V
L1=
1−
= 0.64µH
2MHz • 1.2A 13.2V
A standard value of 0.68µH should work well here. Solving
the same equation for channel 2 results in a 1µH inductor.
3) The resistive divider, (e.g. R1 to R4 in Figure 9) must be
connected between the (+) plate of COUT and a ground
line terminated near SGND. The feedback signal VFB
should be routed away from noisy components and
traces, such as the SW line, and its trace length should
be minimized. In addition, the RT resistor and loop compensation components should be terminated to SGND.
COUT will be selected based on the charge storage requirement. For a VDROOP of 90mV for a 3A load step:
4) Keep sensitive components away from the SW pin.
The RT resistor, the compensation components, the
feedback resistors, and the INTVCC bypass capacitor
should all be routed away from the SW trace and the
inductor L.
A 47µF ceramic capacitor should be sufficient for channel 1.
Solving the same equation for channel 2 (using 5% of
VOUT for VDROOP) results in 27µF of capacitance (22µF is
the closest standard value).
5) A ground plane is preferred, but if not available, the
signal and power grounds should be segregated with
both connecting to a common, low noise reference point.
The connection to the PGND pin should be made with
a minimal resistance trace from the reference point.
6) Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
These copper areas should be connected to the exposed
backside of the package (PGND).
Refer to Figures 10 and 11 for board layout examples.
Design Example
As a design example, consider using the LTC3633A-2 in
an application with the following specifications: VIN(MAX) =
13.2V, VOUT1 = 1.8V, VOUT2 = 3.3V, IOUT(MAX) = 3A, IOUT(MIN)
= 10mA, f = 2MHz, VDROOP ~ (5% • VOUT). The following
discussion will use equations from the previous sections.
COUT1 ≈
3 • ∆IOUT
3 • (3A)
=
= 50µF
f • VDROOP (2MHz)(90mV)
CIN should be sized for a maximum current rating of:
IRMS = 3A
1.8V (13.2V − 1.8V )
13.2V
= 1A
Solving this equation for channel 2 results in an RMS
input current of 1.3A. Decoupling each PVIN input with
a 47µF ceramic capacitor should be adequate for most
applications.
Lastly, the feedback resistors must be chosen. Picking
R1 and R3 to be 12.1k, R2 and R4 are calculated to be:
1.8V
R2 = (12.1k) •
– 1 = 24.2k
0.6V
3.3V
R4 = (12.1k) •
– 1 = 54.5k
0.6V
The final circuit is shown in Figure 9.
3633a23fb
For more information www.linear.com/LTC3633A-2
21
LTC3633A-2/LTC3633A-3
APPLICATIONS INFORMATION
VIN
12V
CIN
47µF
×2
PVIN2
RUN1
RUN2
L2
1µH
C2
2.2µF
MODE/SYNC
PHMODE
TRACKSS1
PGOOD1
BOOST1
0.1µF
0.1µF
SW2
VON2
VFB2
R4
R3
54.9k 12.1k
COUT2
22µF
SVIN
INTVCC
ITH1
ITH2
LTC3633A-2
RT
TRACKSS2
PGOOD2
BOOST2
R5
162k
VOUT2
3.3V AT 3A
PVIN1
SGND PGND
SW1
VON1
VFB1
L1
0.68µH
VOUT1
1.8V AT 3A
R2
R1
12.1k 24.3k
COUT1
47µF
3633a23 F09
Figure 9. Design Example Circuit
VIA TO BOOST1
VIA TO VON1/R2 (NOT SHOWN)
VOUT1
VIA TO VON1 AND R2 (NOT SHOWN)
COUT1
L1
GND
COUT1
VIAS TO GROUND
PLANE
SW1
CBOOST1
CIN
GND
VIAS TO GROUND
PLANE
CVCC
VIA TO GROUND
PLANE
SGND
(TO NONPOWER
COMPONENTS)
VIAS TO GROUND
PLANE
CBOOST2
VIN
SW2
VIA TO BOOST2
CIN
VIAS TO GROUND
PLANE
L2
GND
VIAS TO GROUND
PLANE
COUT2
VIAS TO GROUND
PLANE
VOUT2
VIA TO BOOST2
CBOOST1
SGND
(TO NONPOWER
COMPONENTS)
GND
L2
VIA TO BOOST1
SW1
CVCC
CIN
SW2
L1
CIN
VIN
CBOOST2
VOUT1
VIAS TO GROUND
PLANE
COUT2
VOUT2
3633a23 F10
3633a23 F11
VIA TO VON2/R4 (NOT SHOWN)
VIA TO VON2 AND R4 (NOT SHOWN)
Figure 10. Example of Power Component Layout for QFN Package
Figure 11. Example of Power Component
Layout for TSSOP Package
3633a23fb
22
For more information www.linear.com/LTC3633A-2
LTC3633A-2/LTC3633A-3
TYPICAL APPLICATIONS
1.8V/2.5V 4MHz Buck Regulator
VIN
12V
PVIN2
C1
22µF
×2
PVIN1
SVIN
INTVCC
RUN1
RUN2
ITH2
ITH1
6.98k
10pF
C2
2.2µF
PHMODE
220pF
6.98k
LTC3633A-2
10pF
220pF
RT
R5
80.6k
VOUT2
2.5V AT 3A
MODE/SYNC
0.1µF
R4
31.6k
COUT2
22µF
BOOST1
BOOST2
L2
0.82µH
L1
0.68µH
0.1µF
SW2
VON2
VFB2
R3
10k
SW1
VON1
VFB1
SGND PGND
R1
12.1k
R2
24.3k
VOUT1
1.8V AT 3A
COUT1
47µF
3633a23 TA02
3.3V/1.8V Sequenced Regulator with 6V Input UVLO (VOUT1 Enabled After VOUT2)
VIN
6V TO 20V
C1
47µF
×2
R7
154k
R6
100k
PVIN2
PVIN1
SVIN
RUN1
PGOOD2
INTVCC
ITH1
ITH2
RUN2
C2
2.2µF
LTC3633A-2
R8
40k
MODE/SYNC
PHMODE
RT
R5
162k
VOUT2
3.3V AT 3A
COUT2
22µF
L2
1µH
R4
54.9k
BOOST2
BOOST1
0.1µF
0.1µF
SW2
VON2
VFB2
R3
12.1k
SGND PGND
SW1
VON1
VFB1
R1
12.1k
L1
0.68µH
R2
24.3k
VOUT1
1.8V AT 3A
COUT1
47µF
3633a23 TA03
3633a23fb
For more information www.linear.com/LTC3633A-2
23
LTC3633A-2/LTC3633A-3
TYPICAL APPLICATIONS
1.2V/1.8V Buck Regulator with Coincident Tracking and 6V Input UVLO
VIN
6V TO 20V
PVIN2
R7
154k
C1
47µF
×2
RUN1
RUN2
PVIN1
SVIN
INTVCC
ITH1
ITH2
MODE/SYNC
R8
40k
C2
2.2µF
LTC3633A-2
PHMODE
RT
TRACKSS2
R5
196k
L2
0.47µH
VOUT2
1.2V AT 3A
R4
10k
COUT2
68µF
BOOST2
BOOST1
0.1µF
0.1µF
SW2
VON2
VFB2
R3
10k
SGND PGND
SW1
VON1
VFB1
R1
10k
L1
0.68µH
VOUT1
1.8V AT 3A
R2
15k
R6
4.99k
COUT1
47µF
3633a23 TA04
Dual Output Regulator From Multiple Input Supplies
12V
(POWERS VOUT2)
5V
(POWERS VOUT1)
47µF
PVIN2
787k
SVIN
RUN2
RT
COUT2
22µF
BOOST2
100k
C2
2.2µF
BOOST1
0.1µF
SW2
VON2
VFB2
47µF
RUN1
0.1µF
R4
R3
54.9k 12.1k
274k
INTVCC
ITH1
ITH2
MODE/SYNC
PHMODE
R5
162k
VOUT2
3.3V AT 3A
1µF
LTC3633A-2
100k
L2
1µH
PVIN1
SGND PGND
L1
0.68µH
SW1
VON1
VFB1
R1
12.1k
R2
24.3k
VOUT1
1.8V AT 3A
COUT1
47µF
3633a23 TA05
3633a23fb
24
For more information www.linear.com/LTC3633A-2
LTC3633A-2/LTC3633A-3
TYPICAL APPLICATIONS
6A 1MHz 2-Phase Buck Regulator
SVIN
VIN
3.6V TO 20V
C1
22µF
×2
PVIN1
BOOST1
PVIN2
RUN1
SW1
RUN2
LTC3633A-2
COUT
47µF
×2
0.1µF 1µH
SW2
VON1
ITH1
ITH2
6.04k
VOUT
1.5V AT 6A
BOOST2
INTVCC
PHMODE
C2
2.2µF
0.1µF 1µH
VON2
29.4k
VFB1
1nF
VFB2
RT
19.6k
MODE/SYNC
324k
SGND PGND
3633a23 TA07
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev J)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.40
2.74
(.252)
(.108)
BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.25
REF
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP REV J 1012
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3633a23fb
For more information www.linear.com/LTC3633A-2
25
LTC3633A-2/LTC3633A-3
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.50 REF
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.50 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD28) QFN 0506 REV B
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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26
For more information www.linear.com/LTC3633A-2
LTC3633A-2/LTC3633A-3
REVISION HISTORY
REV
DATE
DESCRIPTION
A
12/13
Clarified Absolute Maximum Ratings
PAGE NUMBER
B
5/15
2
Clarified ILIM limits.
3
Clarified Inductor Selection.
13
3633a23fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
www.linear.com/LTC3633A-2
tion that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
27
LTC3633A-2/LTC3633A-3
TYPICAL APPLICATION
2.5V Regulator with Battery Backup
Q3
20k
Q1
PVIN2
22µF
2 CELL Li-Ion
BATTERY
5V TO 20V
SVIN
1µF
20k
MAIN SUPPLY
5V TO 20V
PGOOD2
PVIN1
22µF
274k
100k
309k
BOOST1
20k
RUN2
SW1
RUN1
BOOST2
20k
100k
INTVCC
PHMODE
MODE/SYNC
PGOOD1
ITH1
ITH2
C2
2.2µF
13k
200pF
LTC3633A-2
Q4
Q2
RT
13k
200pF
SGND PGND
324k
SW2
VON1
0.1µF 2.2µH
VOUT
2.5V
AT 6A
COUT
47µF
×2
0.1µF 2.2µH
VON2
84.5k
VFB2
604Ω
VFB1
26.1k
3633a23 TA06
Q1, Q2: VISHAY SILICONIX P-CHANNEL MOSFET SI4953ADY
Q3, Q4: ROHM SEMICONDUCTOR NPN TRANSISTOR IMX1T110
RELATED PARTS
PART
NUMBER
DESCRIPTION
COMMENTS
LTC3633
15V, Dual 3A (IOUT ), 4MHz Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN: 3.6V to 15V, VOUT(MIN) = 0.6V, IQ = 500µA, ISD < 13µA,
4mm × 5mm QFN-28, TSSOP-28E
LTC3605
15V, 5A (IOUT ), 4MHz, Synchronous Step-Down DC/
DC Converter
95% Efficiency, VIN: 4V to 15V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD < 15µA,
4mm × 4mm QFN-24
LTC3603
15V, 2.5A (IOUT ), 3MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA,
4mm × 4mm QFN-20, MSOP-16E
LTC3602
10V, 2.5A (IOUT ), 3MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN: 4.5V to 10V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA,
3mm × 3mm QFN-16, MSOP-16E
LTC3601
15V, 1.5A (IOUT ), 4MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 300µA, ISD < 1µA,
4mm × 4mm QFN-20, MSOP-16E
LTC3605A
20V, 5A (IOUT ), 4MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN: 4V to 20V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD < 15µA,
4mm × 4mm QFN-24
LTC3604
15V, 2.5A (IOUT ), 4MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN: 3.6V to 15V, VOUT(MIN) = 0.6V, IQ = 300µA, ISD < 15µA,
3mm × 3mm QFN-16, MSOP-16E
LTC3626
20V, 2.5A Synchronous Monolithic Step-Down
Regulator with Current and Temperature Monitoring
95% Efficiency, VIN: 3.6V to 20V, VOUT(MIN) = 0.6V, IQ = 300μA, ISD < 15μA,
3mm × 4mm QFN-20
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28 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC3633A-2
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC3633A-2
LT 0515 REV B • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2012
工商网监
湘ICP备2023018690号
