LTC3634
15V Dual 3A Monolithic
Step-Down Regulator
for DDR Power
DESCRIPTION
FEATURES
3.6V to 15V Input Voltage Range
nn ±3A Output Current per Channel
nn Up to 95% Efficiency
nn Selectable 90°/180° Phase Shift Between Channels
nn Adjustable Switching Frequency: 500kHz to 4MHz
nn VTTR = V
DDQ /2 = VTT Reference
nn ±1.6% Accurate VTTR at 0.75V
nn Optimal V
OUT Range: 0.6V to 3V
nn ±10mA Buffered Output Supplies V
REF Reference Voltage
nn Current Mode Operation for Excellent Line and Load
Transient Response
nn External Clock Synchronization
nn Short-Circuit Protected
nn Input Overvoltage and Overtemperature Protection
nn Power Good Status Outputs
nn Available in (4mm × 5mm) QFN-28 and Thermally
Enhanced 28-Lead TSSOP Packages
The LTC®3634 is a high efficiency, dual-channel monolithic
synchronous step-down regulator which provides power
supply and bus termination rails for DDR1, DDR2, and
DDR3 SDRAM controllers. The operating input voltage
range is 3.6V to 15V, making it suitable for point-of-load
power supply applications from a 5V or 12V input, as well
as various battery powered systems.
nn
The VTT regulated output voltage is equal to VDDQIN• 0.5.
An on-chip buffer capable of driving a 10mA load provides a low noise reference output (VTTR) also equal to
VDDQIN • 0.5.
The operating frequency is programmable and synchronizable from 500kHz to 4MHz with an external resistor.
The two channels can operate 180° out-of-phase, which
relaxes the requirements for input and output capacitance.
The unique controlled on-time architecture is ideal for
powering DDR applications from a 12V supply at high
switching frequencies, allowing the use of smaller external
components.
APPLICATIONS
nn
DDR Memory Power Supplies
The LTC3634 is offered in both 28-pin 4mm × 5mm QFN
and 28-pin exposed pad TSSOP packages.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and PolyPhase are registered
trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 5481178,
5847554, 6580258, 6476589, 6774611.
TYPICAL APPLICATION
47µF
×2
VIN2
2.2µF
0.1µF
1.5µH
24.3k
560pF
ITH2
SGND
PGND
100µF
×2
SW2
VFB2
VON2
VTTR
3634 TA01a
VREF
0.9V
0.01µF
0.82µH
VTT
0.9V/±3A
100µF
×4
910pF
2.0
VIN = 12V
90
VDDQ
1.8V/3A
12.1k
0.1µF
26.4k
18k
100
RUN1
BOOST1
RUN2
SW1
INTVCC LTC3634
PHMODE
VON1
VDDQIN
MODE/SYNC
VFB1
RT
BOOST2
ITH1
1.8
1.6
80
1.4
70
VDDQ
VTT (SINKING CURRENT)
VTT (SOURCING CURRENT)
60
50
1.2
1.0
40
0.8
30
0.6
20
0.4
10
0.2
0
0
0.5
2
1.5
1
LOAD CURRENT (A)
2.5
3
POWER LOSS (W)
324k
Efficiency and Power Loss
vs Load Current
VIN1
EFFICIENCY (%)
VIN
3.6V TO 15V
0
3634 TA01b
3634fc
For more information www.linear.com/LTC3034
1
LTC3634
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN1, VIN2.................................................... –0.3V to 16V
VIN1, VIN2 Transient (Note 2)........................... ............18V
PGOOD1, PGOOD2, VON1, VON2.................. –0.3V to 16V
VTTR, INTVCC, TRACKSS, VDDQIN........... –0.3V to 3.6V
ITH1, ITH2, RT, MODE/SYNC......–0.3V to INTVCC + 0.3V
VFB1, VFB2, PHMODE...................–0.3V to INTVCC + 0.3V
BOOST1-SW1, BOOST2-SW2..................... –0.3V to 3.6V
BOOST1, BOOST2.....................................–0.3V to 19.6V
RUN1, RUN2..................................... –0.3V to VIN + 0.3V
SW Source and Sink Current (DC) (Note 3).................3A
Operating Junction Temperature Range (Notes 4, 5, 8)
LTC3634E, LTC3634I.......................... –40°C to 125°C
LTC3634H........................................... –40°C to 150°C
LTC3634MP........................................ –55°C to 150°C
Storage Temperature Range...................– 65°C to 150°C
Lead Temperature
(Soldering, 10 sec, TSSOP Package)...................... 260°C
PIN CONFIGURATION
TOP VIEW
SW1
SW1
VON1
ITH1
TRACKSS
VFB1
TOP VIEW
28 27 26 25 24 23
PGOOD1 1
22 VIN1
PHMODE 2
21 VIN1
RUN1 3
20 BOOST1
MODE/SYNC 4
19 INTVCC
29
PGND
ITH1
1
28 VON1
TRACKSS
2
27 SW1
VFB1
3
26 SW1
PGOOD1
4
25 VIN1
PHMODE
5
24 VIN1
RUN1
6
23 BOOST1
MODE/SYNC
7
22 INTVCC
RT
8
RUN2 6
17 BOOST2
RUN2
9
SGND 7
16 VIN2
SGND 10
19 VIN2
15 VIN2
PGOOD2 11
18 VIN2
RT 5
18 VTTR
PGOOD2 8
SW2
SW2
VON2
ITH2
VFB2
VDDQIN
9 10 11 12 13 14
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB
21 VTTR
20 BOOST2
VFB2 12
17 SW2
VDDQIN 13
16 SW2
ITH2 14
15 VON2
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
2
29
PGND
FE PACKAGE
28-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 25°C/W
EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB
3634fc
For more information www.linear.com/LTC3034
LTC3634
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3634EUFD#PBF
LTC3634EUFD#TRPBF
3634
28-Lead (5mm × 4mm) Plastic QFN
–40°C to 125°C
LTC3634IUFD#PBF
LTC3634IUFD#TRPBF
3634
28-Lead (5mm × 4mm) Plastic QFN
–40°C to 125°C
LTC3634HUFD#PBF
LTC3634HUFD#TRPBF
3634
28-Lead (5mm × 4mm) Plastic QFN
–40°C to 150°C
LTC3634MPUFD#PBF
LTC3634MPUFD#TRPBF
3634
28-Lead (5mm × 4mm) Plastic QFN
–55°C to 150°C
LTC3634EFE#PBF
LTC3634EFE#TRPBF
LTC3634FE
28-Lead Plastic TSSOP
–40°C to 125°C
LTC3634IFE#PBF
LTC3634IFE#TRPBF
LTC3634FE
28-Lead Plastic TSSOP
–40°C to 125°C
LTC3634HFE#PBF
LTC3634HFE#TRPBF
LTC3634FE
28-Lead Plastic TSSOP
–40°C to 150°C
LTC3634MPFE#PBF
LTC3634MPFE#TRPBF
LTC3634FE
28-Lead Plastic TSSOP
–55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified junction
temperature range, otherwise specifications are at TA = 25°C (Note 4). VIN = 12V, INTVCC = 3.3V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VIN
VIN1, Operating Supply Range
VIN2, Operating Supply Range
VIN1 > 3.6V
Output Voltage Range
VON = VOUT (Note 6)
IQ
Input DC Supply Current (VIN1 + VIN2)
Active (Note 7)
Shutdown
RUN1 = RUN2 = VIN
RUN1 = RUN2 = 0V
VFBREG1
Feedback Reference Voltage
3.6V < VIN < 15V, 0.5V < ITH < 1.8V
0°C < TA < 85°C
–55°C < TA < 150°C
MIN
l
l
TYP
MAX
UNITS
3.6
1.4
15
15
V
V
0.6
3
V
1.3
15
l
l
0.594
0.592
mA
µA
0.6
0.6
0.606
0.606
V
V
VFBREG2
Feedback Reference Voltage
3.6V < VIN < 15V, 0.5V < ITH < 1.8V
l
VTTR – 6
VTTR
VTTR + 6
mV
VTTR
VTTR Voltage Reference
1.5V < VDDQIN < 2.6V
ILOAD = ±10mA, CLOAD < 10nF
l
0.492 •
VDDQIN
0.50 •
VDDQIN
0.508 •
VDDQIN
V
IFB
Feedback Pin Input Current
±30
nA
gm(EA)
Error Amplifier Transconductance
ITH = 1.2V
1.0
mS
tON(MIN)
Minimum On-Time
VON = 0.5V, VIN = 4V
20
tOFF(MIN)
Minimum Off-Time
VIN = 6V
40
60
ns
ns
fOSC
Oscillator Frequency
VRT = INTVCC
RT = 162k
RT = 80.6k
1.4
1.7
3.4
2
2
4
2.6
2.3
4.6
MHz
MHz
MHz
ILIM1
Channel 1 Valley Switch Current Limit
Positive Limit
Negative Limit
3.3
4.4
8
5.5
A
A
ILIM2
Channel 2 Valley Switch Current Limit
Positive Limit
Negative Limit
3.3
4.4
8
5.5
A
A
RDS(ON)
Channel 1
Top Switch On-Resistance
Bottom Switch On-Resistance
Channel 2
Top Switch On-Resistance
Bottom Switch On-Resistance
130
65
mΩ
mΩ
130
65
mΩ
mΩ
3634fc
For more information www.linear.com/LTC3034
3
LTC3634
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C (Note 4). VIN = 12V, INTVCC = 3.3V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
Switch Leakage Current
VIN = 15V, VRUN = 0V
MIN
VIN Overvoltage Lockout Threshold
VIN Rising
VIN Falling
INTVCC Voltage
3.6V < VIN < 15V, 0mA Load
INTVCC Load Regulation
0mA to 50mA Load, VIN = 4V to 15V
RUN Threshold Rising
RUN Threshold Falling
TYP
MAX
0.01
±1
µA
16.8
15.8
17.5
16.5
18
17
V
V
3.1
3.3
3.5
V
1.18
0.98
1.22
1.01
1.26
1.04
V
V
0
±1
µA
10
–10
%
%
0.7
l
l
RUN Leakage Current
PGOOD Good-to-Bad Threshold
VFB Rising
VFB Falling
8
–8
PGOOD Hysteresis
VFB from Bad-to-Good
15
PGOOD Pull-Down Resistance
10mA Load
UNITS
%
mV
15
Ω
Power Good Filter Time
20
40
µs
tSS1
Channel 1 Internal Soft-Start Ramp Rate
0.7
1.2
V/ms
tSS2
Channel 2 Internal Soft-Start Ramp Rate
RPGOOD
VFB1 During Tracking
ITRACKSS
TRACKSS = 0.3V
2.2
0.3
TRACKSS Pull-Up Current
Phase Shift Between Channel 1 and
Channel 2
PHMODE = 0V
PHMODE = INTVCC
PHMODE Threshold Voltage
VIH
VIL
1
MODE/SYNC Threshold Voltage
VIH
VIL
1
SYNC Threshold Voltage
VIH
0.95
MODE/SYNC Input Current
MODE = 0V
MODE = INTVCC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Transient event duration must be < 1% of total lifetime of the part.
Note 3: Guaranteed by long term current density limitations.
Note 4: The LTC3634 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3634E is guaranteed to meet specified performance
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3634I is guaranteed to meet specifications over the –40°C to 125°C
operating junction temperature range. The LTC3634H is guaranteed
over the –40°C to 150°C operating junction temperature range and the
LTC3634MP is tested and guaranteed over the –55°C to 150°C operating
junction temperature range. High junction temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125°C. Note that the maximum ambient temperature consistent with
4
1.5
0.28
V/ms
0.315
V
1.4
µA
90
180
deg
deg
0.3
V
V
0.4
V
V
V
1.5
–1.5
µA
µA
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance and
other environmental factors.
Note 5: The junction temperature (TJ , in °C) is calculated from the ambient
temperature (TA , in °C), package thermal impedance (θJA, in °C/W), and
power dissipation (PD, in Watts) according to the formula: TJ = TA + PD • θJA.
Note 6: Output voltage settings above 3V are not optimized for controlled
on-time operation. For designs that set output voltages above 3V, please
refer to the Applications Information section for information on device
operation outside the optimized range.
Note 7: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
3634fc
For more information www.linear.com/LTC3034
LTC3634
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12V, fSW = 1MHz, L = 1.5μH unless
otherwise noted.
Efficiency vs Load Current
(Burst Mode Operation)
80
80
70
70
60
50
40
30
10
0
0.001
0.01
0.1
1
LOAD CURRENT (A)
80
50
40
30
VIN = 4V
VIN = 8V
VIN = 12V
VIN = 15V
20
10
0
0.001
10
0.01
0.1
1
LOAD CURRENT (A)
VIN = 12V
VIN = 8V
VIN = 4V
0.4
90
1.0
75
IOUT = 10mA
IOUT = 100mA
IOUT = 1A
IOUT = 3A
65
–1
0
1
OUTPUT CURRENT (A)
2
0.1
1
LOAD CURRENT (A)
10
VTT Power Loss vs Load Current
80
0.2
–2
0.01
3634 G03
1.2
70
–3
0
0.001
POWER LOSS (W)
0.6
VIN = 4V
VIN = 8V
VIN = 12V
VIN = 15V
10
95
85
0.8
0
40
30
Efficiency vs Input Voltage
EFFICIENCY (%)
POWER LOSS (W)
1.0
50
3634 G02
VTT Power Loss vs Load Current,
Sourcing and Sinking
VTT = 0.9V
L = 0.82µH
70
60
20
10
3634 G01
1.2
VOUT = 1.5V
90
60
VIN = 4V
VIN = 8V
VIN = 12V
VIN = 15V
20
100
VOUT = 1.8V
90
EFFICIENCY (%)
EFFICIENCY (%)
100
VOUT = 1.8V
90
Efficiency vs Load Current
(Forced Continuous)
EFFICIENCY (%)
100
Efficiency vs Load Current
(Forced Continuous)
60
3
4
6
8
10
12
INPUT VOLTAGE (V)
VTT = 0.75V
L = 0.82µH
0.8
0.6
0.4
0.2
14
0
16
–3
–2
–1
0
1
OUTPUT CURRENT (A)
3634 G05
3634 G04
Reference Voltage
vs Temperature
2
3
3634 G06
Oscillator Frequency
vs Temperature
0.605
VIN = 15V
VIN = 12V
VIN = 8V
VIN = 4V
Oscillator Internal Set Frequency
vs Temperature
10
2.6
0.601
0.599
0.597
2.4
6
4
FREQUENCY (MHz)
FREQUENCY VARIATION (%)
REFERENCE VOLTAGE (V)
8
0.603
2
0
–2
–4
–6
2.2
2.0
1.8
1.6
–8
0.595
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3634 G07
–10
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3634 G08
1.4
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3634 G09
3634fc
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5
LTC3634
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12V, fSW = 1MHz, L = 1.5μH unless
otherwise noted.
RDS(ON) vs Temperature
Shutdown Current vs VIN
160
20000
16
16000
14
120
IQ (µA)
100
80
BOTTOM SWITCH
60
12
10
8
6
40
4
20
2
0
–50 –25
0
0
25 50 75 100 125 150
TEMPERATURE (°C)
8000
4
8
6
10
VIN (V)
12
14
0
–50 –25
16
TRACKSS Pull-Up Current
vs Temperature
2.0
5.5
–5
1.8
–6
1.6
–7
1.4
4.0
3.5
3.0
2.5
0
25 50 75 100 125 150
TEMPERATURE (°C)
3634 G13
6
ILIM (µA)
–4
VALLEY CURRENT LIMIT (A)
6.0
4.5
25 50 75 100 125 150
TEMPERATURE (°C)
3634 G12
Valley Current Negative Limit
vs Temperature
5.0
0
3634 G11
Valley Current Positive Limit
vs Temperature
VALLEY CURRENT LIMIT (A)
12000
4000
3634 G10
2.0
–50 –25
MAIN SWITCH
SYNCHRONOUS SWITCH
18
TOP SWITCH
140
RDS(ON) (mΩ)
Switch Leakage vs Temperature
20
SWITCH LEAKAGE (nA)
180
–8
1.2
–9
1.0
–10
0.8
–11
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3634 G14
0.6
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3634 G15
3634fc
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LTC3634
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12V, fSW = 1MHz, L = 1.5μH unless
otherwise noted.
Load Regulation
VTTR Load Regulation
0.3
VDDQ
VTT
0.2
VDDQ Load Step
0.2
VOUT
100mV/DIV
AC-COUPLED
0.1
VTTR ERROR (%)
VTTR ERROR (%)
0.1
0
–0.1
0
IL
2A/DIV
–0.1
–0.2
–0.3
–3
–2
0
–1
1
LOAD CURRENT (A)
2
3
–0.2
–10 –8 –6 –4 –2 0 2 4 6
VTTR LOAD CURRENT (mA)
8
10
3634 G17
3634 G16
VTT Load Step
VOUT = 1.8V
ILOAD = 0A TO 3A
Start-Up
VOUT
100mV/DIV
AC-COUPLED
20µs/DIV
Start-Up (Channel 2)
RUN2
5V/DIV
RUN1 = RUN2
5V/DIV
VDDQ
VTT
VDDQ
VTT
1V/DIV
IL
2A/DIV
20µs/DIV
3634 G19
VDDQ
VDDQ
VTT
1V/DIV
VTT
VTTR
1V/DIV
VTTR
1V/DIV
VOUT = 0.9V
ILOAD = –2A TO 2A
3634 G18
200µs/DIV
3634 G20
RUN1 = 5V
200µs/DIV
3634 G21
3634fc
For more information www.linear.com/LTC3034
7
LTC3634
PIN FUNCTIONS
(QFN/TSSOP)
PGOOD1 (Pin 1/Pin 4): Channel 1 Open-Drain Power Good
Output Pin. PGOOD1 is pulled to ground when the voltage
on the VFB1 pin is not within ±8% (typical) of the internal
0.6V reference. This threshold has 15mV of hysteresis.
PGOOD2 (Pin 8/Pin 11): Channel 2 Open-Drain Power
Good Output Pin. PGOOD2 is pulled to ground when
the voltage on the VFB2 pin is not within 8% (typical) of
VDDQIN • 0.5. This threshold has 15mV of hysteresis.
PHMODE (Pin 2/Pin 5): Phase Select Input. Tie this pin to
ground to force both channels to switch 90° out-of-phase.
Tie this pin to INTVCC to force both channels to switch
180° out-of-phase. Do not float this pin.
VFB2 (Pin 9/Pin 12): Channel 2 Output Feedback Voltage
Pin. Input to the error amplifier that compares the feedback
voltage to VTTR. Connect this pin directly to the output in
order to set VOUT2 equal to VTTR.
RUN1 (Pin 3/Pin 6): Channel 1 Regulator Enable Pin.
Enables channel 1 operation by tying RUN1 above 1.22V.
Tying it below 1V places Channel 1 into shutdown. Do not
float this pin.
VDDQIN (Pin 10/Pin 13): External Reference Input for
Channel 2. An internal resistor divider sets the VTTR pin
voltage to be equal to half the voltage applied to this input.
Channel 2 uses the VTTR pin voltage as its error amplifier
reference.
MODE/SYNC (Pin 4/Pin 7): Channel 1 Mode Select and
External Synchronization Input. Tie this pin to ground to
force continuous synchronous operation on Channel 1.
Floating this pin or tying it to INTVCC enables high
efficiency Burst Mode® operation at light loads. Channel 2
operation is forced continuous regardless of the state of
this pin. Drive this pin with a clock to synchronize the
LTC3634 switching frequency. An internal phase-locked
loop will force the bottom power NMOS’s turn-on signal to
be synchronized with the rising edge of the CLKIN signal.
When this pin is driven with a clock, forced continuous
mode is automatically selected.
RT (Pin 5/Pin 8): Oscillator Frequency Program Pin.
Connect an external resistor (between 80k to 640k) from
this pin to SGND in order to program the frequency from
500kHz to 4MHz. When RT is tied to INTVCC, the switching frequency will default to 2MHz. See the Applications
Information section.
RUN2 (Pin 6/Pin 9): Channel 2 Regulator Enable Pin.
Enables channel 2 operation by tying RUN2 above 1.22V.
Tying it below 1V places Channel 2 into shutdown. Do not
float this pin.
SGND (Pin 7/Pin 10): Signal Ground Pin. This pin should
have a low noise connection to reference ground. The
feedback resistor network, external compensation network,
and RT resistor should be connected to this ground.
8
ITH2 (Pin 11/Pin 14): Channel 2 Error Amplifier Output
and Switching Regulator Compensation Pin. Connect this
pin to appropriate external components to compensate the
regulator loop frequency response. See the Applications
Information section for guidelines on component selection.
VON2 (Pin 12/Pin 15): On-Time Voltage Input for Channel 2. This pin sets the voltage trip point for the on-time
comparator. Tying this pin to the output voltage makes the
on-time proportional to VOUT2 when VOUT2 < 3V. When
VOUT2 > 3V, switching frequency may become higher than
the set frequency (see the Applications Information section). The pin impedance is nominally 150kΩ.
SW2 (Pins 13, 14/Pins 16, 17): Channel 2 Switch Node
Connection to External Inductor. Voltage swing of SW is
from a diode voltage below ground to a diode voltage
above VIN2.
VIN2 (Pins 15, 16/Pins 18, 19): Power Supply Input for
Channel 2. Input voltage to the on-chip power MOSFETs
on channel 2. This input is capable of operating from a
supply voltage separate from VIN1.
BOOST2 (Pin 17/Pin 20): Boosted Floating Driver Supply
for Channel 2. The (+) terminal of the bootstrap capacitor
connects to this pin while the (–) terminal connects to
the SW pin. The normal operation voltage swing of this
pin ranges from a diode voltage drop below INTVCC up
to VIN2 + INTVCC.
3634fc
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LTC3634
PIN FUNCTIONS
(QFN/TSSOP)
VTTR (Pin 18/Pin 21): Reference Output. This output is
used to supply the VREF voltage for DDR memory. An onchip buffer amplifier outputs a low noise reference voltage
equal to VDDQIN/2. This output is capable of supplying
10mA. The buffer output can drive capacitive loads up to
0.01µF. A small series resistance (1Ω) between the output
and the load further increases the amount of capacitance
that the amplifier can drive. The error amplifier for channel
2 uses this voltage as its reference voltage.
INTVCC (Pin 19/Pin 22): Internal 3.3V Regulator Output.
The internal gate drivers and control circuits are powered
from this voltage. Decouple this pin to power ground with
a minimum of 1μF low ESR ceramic capacitor. The internal
regulator is disabled when both Channel 1 and Channel 2
are disabled with the RUN1/RUN2 inputs.
BOOST1 (Pin 20/Pin 23): Boosted Floating Driver Supply
for Channel 1. The (+) terminal of the bootstrap capacitor
connects to this pin while the (–) terminal connects to
the SW pin. The normal operation voltage swing of this
pin ranges from a diode voltage drop below INTVCC up
to VIN1 + INTVCC.
VIN1 (Pins 21, 22/Pins 24, 25): Power Supply Input for
Channel 1. Input voltage to the on-chip power MOSFETs
on channel 1. The internal LDO for INTVCC is powered
from this pin.
SW1 (Pins 23, 24/Pins 26, 27): Channel 1 Switch Node
Connection to External Inductor. Voltage swing of SW is
from a diode voltage drop below ground to a diode voltage above VIN1.
VON1 (Pin 25/Pin 28): On-Time Voltage Input for Channel 1. This pin sets the voltage trip point for the on-time
comparator. Tying this pin to the regulated output voltage
makes the on-time proportional to VOUT1 when VOUT1 <
3V. When VOUT1 > 3V, switching frequency may become
higher than the set frequency (see the Applications Information section). The pin impedance is nominally 150kΩ.
ITH1 (Pin 26/Pin 1): Channel 1 Error Amplifier Output and
Switching Regulator Compensation Pin. Connect this pin
to appropriate external components to compensate the
regulator loop frequency response. See the Applications
Information section for guidelines on component selection.
TRACKSS (Pin 27/Pin 2): Output Tracking and Soft-Start
Input Pin for Channel 1. Forcing a voltage below 0.6V on
this pin bypasses the internal reference input to the error
amplifier. The LTC3634 will servo the FB pin to the TRACK
voltage. Above 0.6V, the tracking function stops and the
internal reference resumes control of the error amplifier.
An internal 1.4μA pull-up current from INTVCC allows a
soft-start function to be implemented by connecting a
capacitor between this pin and SGND.
VFB1 (Pin 28/Pin 3): Channel 1 Output Feedback Voltage
Pin. Input to the error amplifier that compares the feedback
voltage to the internal 0.6V reference voltage. Connect this
pin to a resistor divider network to program the desired
output voltage. Connecting this pin to INTVCC configures
the LTC3634 for 2-phase, single output operation; see
the Applications Information section for full discussion.
PGND (Exposed Pad Pin 29/Exposed Pad Pin 29): Power
Ground Pin. The (–) terminal of the input bypass capacitor,
CIN, and the (–) terminal of the output capacitor, COUT,
should be tied to this pin with a low impedance connection. This pin must be soldered to the PCB to provide a
low impedance electrical contact to power ground and
good thermal contact to the PCB.
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9
LTC3634
BLOCK DIAGRAM
VON
CHANNEL 1
RUN
CIN
VIN
1.22V
+
AV = 1
150k
INTVCC
VIN
OSC1
–
RUN
3V
ION
ION
CONTROLLER
V
tON = VON
ION
R
S
ICMP
+
BOOST
ON
Q
SWITCH
LOGIC
AND
ANTISHOOT
THROUGH
IREV
–
–
TG
M1
BG
M2
+
CBOOST
SW
L1
COUT
PGND
SENSE–
SENSE+
R2
VFB1
IDEAL DIODES
R1
ITH1
RC1
–
EA
0.648V
–
OV
PGOOD1
INTERNAL
SOFT-START
+
CC1
–
+
OSC1
FC BURST
+
PGOOD2
TRACKSS
0.552V
CSS
OSC
MODE/SYNC
OSC
PLL-SYNC
PHASE
SELECT
OSC2
VDDQIN
VDDQIN • 0.54
OV
VDDQIN • 0.5
–
UV
+
ITH2
–
+
CVCC
VTTR
IDEAL DIODES
VDDQIN • 0.46
+
EA
–
RC2
INTVCC
3.3V
REG
PVIN1
+
PHMODE
1.4µA
MODE
SELECT
0.48V AT START-UP
0.10V AFTER START-UP
–
RRT
INTVCC
–
TRACKSS
UV
RT
0.6V
REF
+
INTERNAL
SOFT-START
VFB2
CC2
CHANNEL 2 (SAME AS CHANNEL 1)
3634 BD
10
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LTC3634
OPERATION
The LTC3634 is a dual-channel, current mode monolithic
step-down regulator designed to provide high efficiency
power conversion for DDR memory supplies and bus termination. Its unique controlled on-time architecture allows
extremely low step-down ratios while maintaining a fast,
constant switching frequency. Each channel is enabled by
raising the voltage on the RUN pin above 1.22V nominally.
Main Control Loop
In normal operation, the internal top power MOSFET is
turned on for a fixed interval determined by a one-shot
timer (ON signal in the Block Diagram). When the top
power MOSFET turns off, the bottom power MOSFET turns
on until the current comparator ICMP trips, thus restarting
the one-shot timer and initiating the next cycle. Inductor
current is measured by sensing the voltage drop across
the bottom power MOSFET. The voltage on the ITH pin sets
the comparator threshold corresponding to inductor valley
current. The error amplifier EA adjusts this ITH voltage
by comparing the feedback signal VFB (derived from the
output voltage) to an internal 0.6V reference voltage (channel 1) or the VTTR voltage (channel 2). If the load current
increases, it causes a drop in the feedback voltage relative
to the reference voltage. The ITH voltage then rises until the
average inductor current matches that of the load current.
The switching frequency is determined by the value of the
RT resistor, which programs the current for the internal
oscillator. An internal phase-locked loop servos the oneshot timer (ON signal) such that the internal oscillator
edge phase-locks to the SW node edge, thus forcing a
constant switching frequency. This unique controlled
on-time architecture also allows the switching frequency
to be synchronized to an external clock source when it
is applied to the MODE/SYNC pin. Channel 1 defaults to
forced continuous operation once the clock signal is applied (channel 2 is always in forced continuous operation).
VTTR Output Buffer
The VTTR pin outputs a voltage equal to one half of
VDDQIN. It is capable of sourcing/sinking 10mA and
driving capacitive loads up to 0.01µF. A small series
resistance (1Ω) between the output and the load further
increases the amount of capacitance that the amplifier can
drive. The error amplifier for channel 2 uses this voltage
as its reference voltage.
High Efficiency Burst Mode Operation
At light load currents, the inductor current can drop to zero
and become negative. In Burst Mode operation (available
only on channel 1), a current reversal comparator (IREV)
detects the negative inductor current and shuts off the bottom power MOSFET, resulting in discontinuous operation
and increased efficiency. Both power MOSFETs will remain
off until the ITH voltage rises above the zero current level to
initiate another cycle. During this time, the output capacitor
supplies the load current and the part is placed into a low
current sleep mode. Burst Mode operation is disabled by tying the MODE/SYNC pin to ground, which forces continuous
synchronous operation regardless of output load current.
Power Good Status Output
The PGOOD open-drain output will be pulled low if the
regulator output exits a ±8% window around the regulation
point. This threshold has 15mV of hysteresis relative to
the VFB pin. To prevent unwanted PGOOD glitches during
transients or dynamic VOUT changes, the LTC3634 PGOOD
falling edge includes a filter time of approximately 40μs.
For the VTT output (channel 2), VTTR is the regulation
point. The PGOOD2 pin will always be low when the VTTR
output voltage is less than 300mV.
VIN Overvoltage Protection
In order to protect the internal power MOSFET devices
against long transient voltage events, the LTC3634 constantly monitors each VIN pin for an overvoltage condition. When VIN rises above 17.5V, the regulator suspends
operation by shutting off both power MOSFETs on the
corresponding channel. Once VIN drops below 16.5V, the
regulator immediately resumes normal operation. The
regulator does not execute its soft-start function when
exiting an overvoltage condition.
Out-Of-Phase Operation
Tying the PHMODE pin high sets the SW2 falling edge to
be 180° out-of-phase with the SW1 falling edge. There is
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11
LTC3634
OPERATION
a significant advantage to running both channels out-ofphase. When running the channels in phase, both topside
MOSFETs are on simultaneously, causing large current
pulses to be drawn from the input capacitor and supply
at the same time. When running the LTC3634 channels
out-of-phase, the large current pulses are interleaved,
effectively reducing the amount of time the pulses overlap.
Thus, the total RMS input current is decreased, which both
relaxes the capacitance requirements for the VIN bypass
capacitors and reduces the voltage noise on the supply
line. One potential disadvantage to this configuration occurs
when one channel is operating at 50% duty cycle. In this
situation, SW node transitions can potentially couple from
one channel to the other, resulting in frequency jitter on one
or both channels. This effect can be mitigated with a well
designed board layout. Alternatively, tying PHMODE low
changes the phase difference to be 90°, which may prevent
SW1 and SW2 from transitioning at the same point in time.
APPLICATIONS INFORMATION
A general LTC3634 application circuit is shown in Figure 1.
External component selection is largely driven by the load
requirement and switching frequency. Component selection typically begins with selecting the feedback resistors
to set the desired output voltage. Next the inductor L and
resistor RT are selected. Once the inductor is chosen, the
input capacitor (CIN) and the output capacitor (COUT) can
be selected. Finally, the loop compensation components
may be selected to stabilize the step-down regulator. The
remaining optional external components can then be selected for functions such as loop compensation, TRACKSS,
VIN, UVLO, and PGOOD.
Programming Switching Frequency
Selection of the switching frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but generally requires
larger inductance and capacitance values to maintain low
output ripple voltage. Connecting a resistor from the RT
pin to SGND programs the switching frequency (f) between
500kHz and 4MHz according to the following formula:
3.2E11
RRT =
f
where RRT is in Ω and f is in Hz.
VIN
3.6V TO 15V
C1
RRT
RCOMP1
VIN2
C2
2.2µF
VIN1
BOOST1
RUN1
RUN2
LTC3634
SW1
RT
VON1
INTVCC
PHMODE
VDDQIN
MODE/SYNC
VFB1
ITH1
BOOST2
ITH2
SW2
VFB2
VON2
VTTR
C5
(OPT)
SGND
PGND
3634 F01
L1
R2
VDDQ
COUT1
R1
0.1µF
C4
(OPT)
CCOMP1
RCOMP2
0.1µF
L2
VTT
VREF
COUT2
C3
0.01µF
CCOMP2
Figure 1. Typical Application Circuit for DDR Memory Supply
12
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LTC3634
APPLICATIONS INFORMATION
The buffered output voltage on the VTTR pin is nominally
equal to half of the VDDQIN voltage; thus configuring VOUT2
as a VTT bus termination supply for DDR memory is as
simple as shorting VOUT2 to VFB2 and connecting VDDQIN
directly to the VOUT1 (the VDDQ supply).
6000
FREQUENCY (kHz)
5000
4000
3000
2000
1000
0
0
100
200 300 400 500
RT RESISTOR (kΩ)
600
700
3634 F02
Figure 2. Switching Frequency vs RT
When RT is tied to INTVCC, the switching frequency will
default to approximately 2MHz, as set by an internal resistor. This internal resistor is more sensitive to process and
temperature variations than an external resistor (see the
Typical Performance Characteristics section) and is best
used for applications where switching frequency accuracy
is not critical.
Output Voltage Programming
Each regulator’s output voltage is set by an external resistive divider according to the following equation:
R2
VOUT = VFBREG 1+
R1
The LTC3634 controlled on-time architecture is optimized
for an output voltage range of 0.6V to 3V, which is suitable for powering DDR memory. The LTC3634 is capable
of regulating higher output voltages; however, controlled
on-time behavior is not ensured. When the output voltage
is greater than 3V, the step-down regulator is forced to
increase the switching frequency in order to achieve output
regulation. Furthermore, external clock synchronization is
no longer possible, and channel 2 cannot maintain 90°/180°
phase operation with respect to channel 1. In short, the
LTC3634 will behave like a constant on-time regulator
instead of a controlled on-time regulator. Therefore, output
voltages greater than 3V should only be used in applications where switching frequency and channel-to-channel
phase-locking are not critical performance characteristics.
Inductor Selection
where VFBREG is the reference voltage as specified in the
Electrical Characteristics Table. The reference voltage is
600mV for channel 1; for channel 2 the reference voltage
is equal to the VTTR pin voltage. The desired output voltage is set by appropriate selection of resistors R1 and R2
as shown in Figure 3.
VOUT
R2
CF
(OPTIONAL)
VFB
LTC3634
Choosing large values for R1 and R2 will result in improved zero-load efficiency but may lead to undesirable
noise coupling or phase margin reduction due to stray
capacitances at the VFB node. Care should be taken to
route the VFB trace away from any noise source, such as
the SW trace.
R1
SGND
3634 F03
For a given input and output voltage, the inductor value and
operating frequency determine the inductor ripple current.
More specifically, the inductor ripple current decreases
with higher inductor value or higher operating frequency
according to the following equation:
V V
∆IL = OUT 1− OUT
f •L
VIN
where ΔIL = inductor ripple current, f = operating frequency
and L = inductor value. A trade-off between component
size, efficiency and operating frequency can be seen from
this equation. Accepting larger values of ΔIL allows the
use of lower value inductors but results in greater inductor
Figure 3. Setting the Output Voltage
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LTC3634
APPLICATIONS INFORMATION
core loss, greater ESR loss in the output capacitor, and
larger output voltage ripple. Generally, highest efficiency
operation is obtained at low operating frequency with
small ripple current.
A reasonable starting point is to choose a ripple current
somewhere between 600mA and 1.2A peak-to-peak. Note
that the largest ripple current occurs at the highest VIN.
Exceeding 1.8A is not recommended in order to minimize
output voltage ripple. To guarantee that ripple current does
not exceed a specified maximum, the inductance should
be chosen according to:
V
VOUT
OUT
L=
1−
f • ∆IL(MAX) VIN(MAX)
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire, leading to increased DCR
and copper loss.
Table 1. Inductor Selection Table
INDUCTANCE DCR
MAX
(µH)
(mΩ) CURRENT (A)
Würth Electronik WE-HC 744310 Series
0.24
2.1
18.0
0.55
3.8
14.0
0.95
6.4
11.0
1.15
9.0
8.5
2.00
14.0
6.5
Vishay IHLP-2020BZ-01 Series
0.22
5.2
15
0.33
8.2
12
0.47
8.8
11.5
0.68
12.4
10
1
20
7
Toko FDV0620 Series
0.20
4.5
12.4
0.47
8.3
9.0
1.0
18.3
5.7
Coilcraft D01813H Series
0.33
4
10
0.56
10
7.7
1.2
17
5.3
TDK RLF7030 Series
1.0
8.8
6.4
1.5
9.6
6.1
DIMENSIONS
(mm)
HEIGHT
(mm)
7×7
3.3
5.2 × 5.5
2
7 × 7.7
2.0
6 × 8.9
5.0
6.9 × 7.3
3.2
CIN and COUT Selection
Ferrite designs exhibit very low core loss and are preferred at high switching frequencies, so design goals
can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means
that inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current, so it is important to ensure that
the core will not saturate.
The input capacitance, CIN, is needed to filter the trapezoidal wave current at the drain of the top power MOSFET.
To prevent large voltage transients from occurring, a low
ESR input capacitor sized for the maximum RMS current
is recommended. The maximum RMS current for a single
regulator is given by:
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. Table 1 gives a
sampling of available surface mount inductors.
14
IRMS = I OUT(MAX)
VOUT ( VIN − VOUT )
VIN
When both regulators are active, the input current waveform is significantly different. Furthermore, the input RMS
current varies depending on each output’s load current as
well as whether VTT is sinking or sourcing current.
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LTC3634
APPLICATIONS INFORMATION
When SW1 and SW2 operate 180° out-of-phase, the worstcase input RMS current occurs when the VTT supply is
sinking current and VDDQ is sourcing the same amount of
current. Knowing that VOUT2 = one-half VOUT1 in the DDR
application, the input RMS current in this case is given by:
D1
IRMS = I OUT(MAX) D1 1.5− for D1 < 0.5
4
3
IRMS = I OUT(MAX) 1− D1 for D1 > 0.5
4
where D1 is the duty cycle of channel 1 (VDDQ supply).
These equations show that maximum IRMS occurs at
50% duty cycle (VIN = 2 • VOUT1). This simple worst-case
condition may be used for design as deviations in duty
cycle do not offer significant relief. Note that ripple current
ratings from capacitor manufacturers are often based on
only 2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a higher
temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. For low input voltage
applications, sufficient bulk input capacitance is needed
to minimize transient effects during output load changes.
Even though the LTC3634 design includes an overvoltage
protection circuit, care must always be taken to ensure
input voltage transients do not pose an overvoltage hazard to the part.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response. The output ripple, ΔVOUT, is
approximated by:
1
∆VOUT < ∆IL ESR +
8 • f •COUT
must instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and
the output capacitor size. Typically, three to four cycles
are required to respond to a load step, but only in the first
cycle does the output drop linearly. The output droop,
VDROOP, is usually about three times the linear drop of
the first cycle, provided the loop crossover frequency is
maximized. Thus, a good place to start is with the output
capacitor size of approximately:
COUT ≈
3 • ∆IOUT
f • VDROOP
Though this equation provides a good approximation, more
capacitance may be required depending on the duty cycle
and load step requirements. The actual VDROOP should be
verified by applying a load step to the output.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are available
in small case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, due to the self-resonant and highQ characteristics of some types of ceramic capacitors,
care must be taken when these capacitors are used at
the input. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
VIN input. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part. For
a more detailed discussion, refer to Application Note 88.
When choosing the input and output ceramic capacitors,
choose the X5R and X7R dielectric formulations. These
dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
When using low-ESR ceramic capacitors, it is more useful to choose the output capacitor value to fulfill a charge
storage requirement. During a load step, the output capacitor
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LTC3634
APPLICATIONS INFORMATION
Choosing Compensation Components
Loop compensation is a complicated subject and Application Note 76 is recommended reading for a full discussion
on maximizing loop bandwidth in a current mode switching regulator. This section will provide a quick method on
choosing proper components to compensate the LTC3634
regulators.
Figure 4 shows the recommended components to be connected to the ITH pin, and Figure 5 shows an approximate
bode plot of the buck regulator loop using these components. It is assumed that the major poles in the system
(the output capacitor pole and the error amplifier output
pole) are located at a frequency lower than the crossover
frequency.
ITH
Once fC is chosen, the value of RCOMP that sets this crossover frequency can be calculated by the following equation:
2π • fC •COUT V
OUT
RCOMP =
g m(EA) • g m(MOD) VFBREG
where gm(EA) is the error amplifier transconductance
(see the Electrical Characteristics section), and gm(MOD)
is the modulator transconductance (the transfer function
from ITH voltage to current comparator threshold). For
the LTC3634, this transconductance is nominally 7Ω–1.
Once RCOMP is determined, CCOMP can be chosen to set
the zero frequency (fZ):
RCOMP
LTC3634
The first step is to choose the crossover frequency fC.
Higher crossover frequencies will result in a faster loop
transient response; however, in order to avoid higher order loop dynamics from the switching power stage, it is
recommended that fC not exceed one-tenth the switching
frequency (fSW).
CBYP
CCOMP
SGND
3634 F04
Figure 4. Compensation and Filtering Components
1
2π •CCOMP •RCOMP
For 90° of phase margin, fZ should be chosen to be less
than one-tenth of fC.
Since the ITH node is sensitive to noise coupling, a small
bypass capacitor (CBYP) may be used to filter out board
noise. However, this cap contributes a pole at fP and may
introduce some phase loss at the crossover frequency:
|H(s)|
–2
–1
ƒZ
ƒP
0dB
LOG (ƒ)
ƒC
3634 F05
Figure 5. Bode Plot of Regulator Loop
16
fZ =
fP =
1
2π •C BYP •RCOMP
For best results, fP should be set high enough such that
phase margin is not significantly affected.
If necessary, a capacitor CF (as shown in Figure 3) may
be used to add some phase lead.
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LTC3634
APPLICATIONS INFORMATION
Checking Transient Response
The regulator loop response can be checked by observing
the response of the system to a load step. The ITH pin not
only allows optimization of the control loop behavior but
also provides a DC-coupled and AC filtered closed loop
response test point. The DC step, rise time, and settling
behavior at this test point reflect the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin.
After choosing compensation values as discussed in the
previous section, the design should be tested to verify
stability. The component values may be modified slightly
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because their various types and values determine
the loop gain and phase. An output current pulse of 20%
to 100% of full load current having a rise time of ~1μs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where
ESR is the effective series resistance of COUT. ΔILOAD also
begins to charge or discharge COUT, generating a feedback
error signal used by the regulator to return VOUT to its
steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
When observing the response of VOUT to a load step, the
initial output voltage step may not be within the bandwidth of
the feedback loop, so the standard second order overshoot/
DC ratio cannot be used to determine phase margin. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>10μF) input capacitors.
The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting.
INTVCC Regulator Bypass Capacitor
An internal low dropout (LDO) regulator produces the 3.3V
supply that powers the internal bias circuitry and drives
the gate of the internal MOSFET switches. The INTVCC pin
connects to the output of this regulator and must have a
minimum of 1μF ceramic bypass capacitance to ground.
This capacitor should have low impedance electrical
connections to the INTVCC and PGND pins to provide the
transient currents required by the LTC3634. This supply
is intended only to supply additional DC load currents as
desired and not intended to regulate large transient or AC
behavior, as this may impact LTC3634 operation.
Boost Capacitor
The LTC3634 uses a bootstrap circuit to create a voltage
rail above the applied input voltage VIN. Specifically, a boost
capacitor, CBOOST, is charged to a voltage approximately
equal to INTVCC each time the bottom power MOSFET is
turned on. The charge on this capacitor is then used to
supply the required transient current during the remainder
of the switching cycle. When the top MOSFET is turned on,
the BOOST pin voltage will be equal to approximately VIN
+ 3.3V. For most applications, a 0.1μF ceramic capacitor
closely connected between the BOOST and SW pins will
provide adequate performance.
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LTC3634
APPLICATIONS INFORMATION
Minimum Off-Time/On-Time Considerations
MODE/SYNC Operation
The minimum off-time is the smallest amount of time that
the LTC3634 can turn on the bottom power MOSFET, trip
the current comparator and turn the power MOSFET back
off. This time is typically 40ns. For the controlled on-time
control architecture, the minimum off-time limit imposes
a maximum duty cycle of:
The MODE/SYNC pin is a multipurpose pin allowing both
mode selection and operating frequency synchronization.
Floating this pin or connecting it to INTVCC enables Burst
Mode operation on channel 1 for superior efficiency at
light load currents at the expense of slightly higher output voltage ripple. When the MODE/SYNC pin is tied to
ground, forced continuous mode operation is selected,
creating the lowest fixed output ripple at the expense of
light load efficiency.
DCMAX = 1– f • (tOFF(MIN) + 2 • tDEAD)
where f is the switching frequency, tDEAD is the nonoverlap
time of the switches, or dead time (typically 15ns), and
tOFF(MIN) is the minimum off-time. If the maximum duty
cycle is surpassed, due to a decreasing input voltage
for example, the output will drop out of regulation. The
minimum input voltage to avoid this dropout condition is:
VIN(MIN) =
(
VOUT
1− f • tOFF(MIN) + 2 • tDEAD
)
Conversely, the minimum on-time is the smallest duration of time in which the top power MOSFET can be in
its ON state. This time is typically 20ns. In continuous
mode operation, the minimum on-time limit imposes a
minimum duty cycle of:
DCMIN = (f • tON(MIN))
where tON(MIN) is the minimum on-time. As the equation
shows, reducing the operating frequency will alleviate the
minimum duty cycle constraint.
When the regulator output is sinking current, the effective
minimum on-time of the converter will be increased by the
non-overlap time of the power MOSFETs (or the “deadtime”) during each SW node transition. This “dead-time”
is nominally 15ns, so when sinking current, the minimum
on-time is effectively 15ns + 15ns + 20ns = 50ns.
If the minimum on-time constraint is violated, the converter
will automatically reduce its own switching frequency in
order to maintain output regulation. Once the converter
reduces its switching frequency, the phase information
is lost and the two channels will switch asynchronously.
Furthermore, the regulator may need to be compensated
more conservatively due to the lower switching frequency.
18
The LTC3634 will detect the presence of the external
clock signal on the MODE/SYNC pin and synchronize the
internal oscillator to the phase and frequency of the incoming clock. The presence of an external clock will place
both regulators into forced continuous mode operation.
Although the RT resistor is not strictly necessary when
synchronizing to an external clock, it is recommended to
use a RT resistor that matches the nominal external clock
frequency in order to keep the switching regulator biased
correctly whenever the external clock signal is suddenly
removed or reapplied.
Channel 1 Output Voltage Tracking and Soft-Start
The LTC3634 allows the user to control the output voltage
ramp rate of channel 1 by means of the TRACKSS pin.
From 0 to 0.6V, the TRACKSS voltage will override the
internal 0.6V reference input to the error amplifier, thus
regulating the feedback voltage to that of the TRACKSS
pin. When TRACKSS is above 0.6V, tracking is disabled
and the feedback voltage will regulate to the internal
reference voltage.
The voltage at the TRACKSS pin may be driven from an
external source, or alternatively, the user may leverage
the internal 1.4μA pull-up current source to implement
a soft-start function by connecting an external capacitor
(CSS) from the TRACKSS pin to ground. The relationship
between output rise time and TRACKSS capacitance is
given by:
tSS = 430000Ω • CSS
3634fc
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LTC3634
APPLICATIONS INFORMATION
A default internal soft-start ramp forces a minimum softstart time of 400μs by overriding the TRACKSS pin input
during this time period. Hence, capacitance values less
than approximately 1000pF will not significantly affect
soft-start behavior.
Start-Up Behavior
Upon start-up, both channels immediately default to
discontinuous operation. Channel 1 will remain in discontinuous Burst Mode operation until its output rises to
greater than 80% of its final value (VFB > 480mV). Once
the output exceeds this voltage, the operating mode of
the regulator switches to the mode selected by the MODE/
SYNC pin as described above. During normal operation,
if the output drops below 10% of its final value (as it may
when tracking down, for instance), the regulator will
automatically switch to Burst Mode operation to prevent
inductor saturation and improve TRACKSS pin accuracy.
Channel 2 (the VTT termination supply) remains in discontinuous operation until its output rises above 300mV, at
which point it will automatically switch to forced continuous
operation. This ensures that the regulator output has suf-
ficient voltage to discharge the inductor in continuous mode
and prevent excessive build-up of energy in the inductor.
Output Power Good
The PGOOD output of the LTC3634 is driven by a 15Ω
(typical) open-drain pull-down device. If the output voltage exits an 8% (typical) regulation window around the
target regulation point, the open-drain output will pull down
with 15Ω output resistance to ground, thus dropping the
PGOOD pin voltage. This pull-down device will not shut
off until the output re-enters this window and overcomes
a small amount of hysteresis. This behavior is described
in Figure 6.
A filter time of 40μs (typical) acts to prevent unwanted
PGOOD output changes during VOUT transient events. As
a result, the output voltage must exit the 8% regulation
window for 40μs before the PGOOD pin pulls to ground.
Conversely, the output voltage must be within the target
regulation window for 40μs before the PGOOD pin pulls
high.
NOMINAL OUTPUT
VHYS
VHYS(CH1): 2.5%
VHYS
VHYS(CH2):
PGOOD
VOLTAGE
–8%
0%
8%
15mV
• 100%
VTTR
OUTPUT VOLTAGE
3634 F06
Figure 6. PGOOD Pin Behavior
3634fc
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19
LTC3634
APPLICATIONS INFORMATION
2-Phase, Single VTT Output Configuration
VIN1 and VIN2 may be powered from separate supply voltages (see Figure 12). This is useful in cases where power
needs to be shared between two different sources. It is
important to note that when the VTT output sinks current,
it will backfeed through the converter and out of the VIN
pins. Care must be taken to ensure that the input supplies
are able to handle this condition.
The two regulators on the LTC3634 can be easily combined to provide a single 2-phase VTT termination supply
capable of sourcing and sinking up to 6A. The circuit is
shown in Figure 7.
In this circuit, VFB1 is tied to INTVCC to put the LTC3634
into 2-phase operation. When set up for 2-phase operation,
the inputs to channel 1’s transconductance error amplifier
are switched to be the same as channel 2’s inputs (VFB2
and VTTR), allowing it to be paralleled with channel 2’s
error amplifier. The ITH1 and ITH2 pins should be tied
together externally to force equal current sharing between
both channels.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
Only one compensation network is needed on the ITH
node, although separate filter caps for each ITH pin may
be helpful depending on the board layout. In this parallel
configuration, it is important to note that the effective gm(EA)
and gm(MOD) are twice as large as that of a single channel.
% Efficiency = 100% – (L1 + L2 + L3 +…)
where L1, L2, etc. are the individual losses as a percentage
of input power. Although all dissipative elements in the
circuit produce losses, three main sources usually account
for most of the losses in LTC3634 circuits: 1) conduction
losses, 2) switching losses and quiescent power loss 3)
transition losses and other losses.
One advantage to this 2-phase configuration is that both
input and output current ripple is significantly reduced
compared to a single phase 6A converter solution, because
the current waveforms from each regulator are interleaved.
Refer to Application Note 77 for a full discussion and
analysis on PolyPhase® converters.
VIN
3.6V TO 15V
R1
160k
C1
47µF
×2
VIN2
C2
2.2µF
VDDQ
SUPPLY
6k
BOOST1
RUN1
RUN2
LTC3634
SW1
RT
BOOST2
INTVCC
PHMODE
SW2
VFB1
VFB2
VDDQIN
VON2
VON1
ITH1
10pF
1000pF
0.1µF
L1
0.47µH
0.1µF
L2
0.47µH
SGND
MODE/SYNC
PGND
VTT
VDDQ /2 AT ±6A
COUT2
100µF
×4
VTTR
ITH2
10pF
VIN1
0.01µF
VREF
VDDQ /2 AT ±10mA
3634 F07
Figure 7. Application Circuit for a 2-Phase, ±6A Single VTT Output
20
3634fc
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LTC3634
APPLICATIONS INFORMATION
1. Conduction losses are calculated from the DC resistances of the internal switches, RSW, and external
inductor, RL. In continuous mode, the average output
current flows through inductor L but is “chopped”
between the internal top and bottom power MOSFETs.
Thus, the series resistance looking into the SW pin is a
function of both top and bottom MOSFET RDS(ON) and
the duty cycle (DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. So to calculate conduction losses:
Conduction Loss = IOUT2 (RSW + RL)
2. The internal LDO supplies the power to the INTVCC rail.
The total power loss here is the sum of the switching
losses and quiescent current losses from the control
circuitry.
Each time a power MOSFET gate is switched from low
to high to low again, a packet of charge dQ moves from
VIN to ground. The resulting dQ/dt is a current out of
INTVCC that is typically much larger than the DC control
bias current. In continuous mode, IGATECHG = f • (QT +
QB), where QT and QB are the gate charges of the internal
top and bottom power MOSFETs and f is the switching
frequency. For estimation purposes, (QT + QB) on each
LTC3634 regulator channel is approximately 2.3nC.
To calculate the total power loss from the LDO load,
simply add the gate charge current and quiescent current and multiply by VIN:
PLDO = (IGATECHG + IQ) • VIN
3. Other hidden losses such as transition loss, copper trace
resistances, and internal load currents can account for
additional efficiency degradations in the overall power
system. Transition loss arises from the brief amount of
time the top power MOSFET spends in the saturated
region during switch node transitions. The LTC3634
internal power devices switch quickly enough that these
losses are not significant compared to other sources.
Other losses, including diode conduction losses during
dead-time and inductor core losses, generally account
for less than 2% total additional loss.
Thermal Considerations
The LTC3634 requires the exposed package back-plane
metal (PGND) to be well soldered to the PC board to
provide good thermal contact. This gives the QFN and
TSSOP packages exceptional thermal properties, which
are necessary to prevent excessive self-heating of the part
in normal operation.
In a majority of applications, the LTC3634 does not dissipate much heat due to its high efficiency and low thermal
resistance of its exposed-back QFN package. However, in
applications where the LTC3634 is running at high ambient temperature, high VIN, high switching frequency, and
maximum output current load, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 170°C,
both power switches will be turned off until the temperature
returns to 160°C.
To prevent the LTC3634 from exceeding the maximum
junction temperature of 125°C, the user will need to do
some thermal analysis. The goal of the thermal analysis
is to determine whether the power dissipated exceeds the
maximum junction temperature of the part. The temperature rise is given by:
TRISE = PD • θJA
As an example, consider the case when the LTC3634 is
used to power DDR2 SDRAM and is used in an application
where maximum ambient temperature is 70°C, VIN = 12V,
frequency = 1MHz, VDDQ = 1.8V, VTT = 0.9V, and ILOAD =
2A for both channels.
From the RDS(ON) graphs in the Typical Performance
Characteristics section, the top switch on-resistance is
nominally 140mΩ and the bottom switch on-resistance
is nominally 75mΩ at 70°C ambient. For the VDDQ supply,
the equivalent power MOSFET resistance RSW1 is:
RDS(ON)TOP •
1.8V
10.2V
+RDS(ON)BOT •
= 84.8mΩ
12V
12V
The same calculation to the VTT supply (0.9V), yields
RSW2 = 79.9mΩ.
From the previous section’s discussion on gate drive, we
estimate the total gate charge current for each regulator to
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21
LTC3634
APPLICATIONS INFORMATION
PD = (IOUT1)
2
(
•RSW1 + I OUT2
)
2
+ VIN • (IGATECHG +IQ )
2
•RSW2
2
PD = (2A) • 0.0848Ω +(2A) • 0.0799Ω
+12V • ( 2.3mA • 2) +1.3mA = 0.730W
The QFN 4mm × 5mm package junction-to-ambient thermal
resistance, θJA, is around 43°C/W. Therefore, the junction
temperature of the regulator operating in a 70°C ambient
temperature is approximately:
TJ = 0.730W • 43°C/W + 70°C = 101°C
which is below the maximum junction temperature of
125°C. With higher ambient temperatures, a heat sink or
cooling fan should be considered to drop the junction-toambient thermal resistance. Alternatively, the exposed pad
TSSOP package may be a better choice for high power
applications, since it has better thermal properties than
the QFN package.
Remembering that the above junction temperature is obtained from a RDS(ON) at 70°C, we might recalculate the
junction temperature based on a higher RDS(ON) since it
increases with temperature. Redoing the calculation assuming that RSW increased 12% at 101°C yields a new
junction temperature of 105°C.
Figure 8 is a temperature derating curve based on the
DC1708 demo board (QFN package). It can be used as
a guideline to estimate the maximum allowable ambient
temperature for given DC load currents in order to avoid
exceeding the maximum operating junction temperature
of 125°C.
Junction Temperature Measurement
The junction-to-ambient thermal resistance will vary depending on the size and amount of heat sinking copper
on the PCB board where the part is mounted, as well as
the amount of air flow on the device. In order to properly
evaluate this thermal resistance, the junction temperature
needs to be measured. A clever way to measure the junction
22
3.5
CHANNEL 1 LOAD CURRENT (A)
be 1MHz • 2.3nC = 2.3mA, and the total IQ of both channels is 1.3mA (see the Electrical Characteristics section).
Therefore, the total power dissipated by both regulators is:
3.0
2.5
2.0
1.5
1.0
CH2 LOAD = 0A
CH2 LOAD = 1A
CH2 LOAD = 2A
CH2 LOAD = 3A
0.5
0
0
25
75
100
50
MAXIMUM ALLOWABLE AMBIENT
TEMPERATURE (°C)
125
3634 F08
Figure 8. Temperature Derating Curve for DC1708 Demo Circuit
temperature directly is to use the internal junction diode
on one of the PGOOD pins to measure its diode voltage
change based on ambient temperature change.
First remove any external passive component on the PGOOD
pin, then pull out 100μA from the PGOOD pin to turn on
its internal junction diode and bias the PGOOD pin to a
negative voltage. With no output current load, measure the
PGOOD voltage at an ambient temperature of 25°C, 75°C
and 125°C to establish a slope relationship between the
voltage on PGOOD and ambient temperature. Once this
slope is established, then the junction temperature rise can
be measured as a function of power loss in the package
with corresponding output load current. Although making
this measurement with this method does violate absolute
maximum voltage ratings on the PGOOD pin, the applied
power is so low that there should be no significant risk
of damaging the device.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3634. Check the following in your layout:
1. Do the input capacitors connect to the VIN and PGND
pins as close as possible? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers.
2. The output capacitor, COUT, and inductor L should be
closely connected to minimize loss. The (–) plate of
3634fc
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APPLICATIONS INFORMATION
COUT should be closely connected to both PGND and
the (–) plate of CIN.
3. The resistive divider, (e.g. R1 and R2 in Figure 1) must
be connected between the (+) plate of COUT and a
ground line terminated near SGND. The feedback signal
VFB should be routed away from noisy components
and traces, such as the SW line, and its trace length
should be minimized. In addition, the RT resistor and
loop compensation components should be terminated
to SGND.
4. Keep sensitive components away from the SW pin. The
RT resistor, the compensation components, the feedback
resistors, and the INTVCC bypass capacitor should all
be routed away from the SW trace and the inductor L.
5. A ground plane is preferred, but if not available, the
signal and power grounds should be segregated with
both connecting to a common, low noise reference point.
The connection to the PGND pin should be made with
a minimal resistance trace from the reference point.
6. Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
These copper areas should be connected to the exposed
backside of the package (PGND). Refer to Figures 10
and 11 for board layout examples.
Design Example
As a design example, consider using the LTC3634 (as
shown in Figure 1) to power DDR2 SDRAM with the following specifications: VIN(MAX) = 13.2V, IOUT(MAX) = ±2A,
f = 1MHz, VDROOP(VDDQ) < 60mV, VDROOP(VTT) < 30mV.
The following discussion will use equations from the
previous sections.
First, the correct RT resistor value for 1MHz switching
frequency must be chosen. Based on previous discussions, RT is calculated to be
3.2E11
RT =
= 320kΩ
f
The closest standard value is 324k.
Next, select values for R1 and R2 to set channel 1 (VDDQ)
to be 1.8V for DDR2 SDRAM. Choosing R1 to be 12.1k,
R2 is calculated to be:
1.8V
R2 = 12.1k •
−1 = 24.2k
0.6V
The closest standard value is 24.3k. Tying VDDQIN to
VOUT1 sets VOUT2 to be half of VOUT1.
Next, we can pick inductor values for both the VDDQ and
VTT outputs. Choosing inductor current ripple to be 1A
at maximum VIN:
1.8V
1.8V
L1=
1−
= 1.55µH
13.2V
1MHz •1A
0.9V
0.9V
L2 =
1−
= 0.838µH
13.2V
1MHz •1A
Standard values of 1.5μH and 0.82µH should be used.
Ceramic caps will be used for COUT and will be selected
based on the charge storage requirement. Assuming a
worst case 4A load step (–2A to 2A):
COUT1 ≈
3 • 4A
= 200µF
1MHz • 60mV
COUT2 ≈
3 • 4A
= 400µF
1MHz • 30mV
Lastly, we will choose compensation components. Choosing the crossover frequency fC = 50kHz:
2π • 50kHz • 200µF 1.8V
RCOMP1 =
= 27kΩ
−1
−1
1mΩ • 7Ω
0.6V
2π • 50kHz • 400µF 0.9V
RCOMP2 =
= 18kΩ
1mΩ −1 • 7Ω −1 0.9V
Choosing the zero frequency to be 10kHz yields CCOMP1 =
589pF and CCOMP2 = 884pF. The closest standard values
for the compensation components are 26.7k, 18k, 560pF
and 910pF, respectively.
The final circuit is shown in Figure 9.
3634fc
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23
LTC3634
APPLICATIONS INFORMATION
VIN
3.6V TO 15V
C1
47µF
×2
R3
324k
RCOMP1
26.7k
V
VIN1
RUN1 IN2
BOOST1
RUN2
LTC3634
SW1
RT
VON1
INTVCC
PHMODE
VDDQIN
MODE/SYNC
VFB1
C2
2.2µF
C4
10pF
ITH2
C5
10pF
SGND
PGND
SW2
VFB2
VON2
VTTR
3634 F09
VDDQ
1.8V
COUT1
100µF
×2
R2
24.3k
L2
0.82µH
0.1µF
CCOMP1
560pF
RCOMP2
18k
R1
12.1k
BOOST2
ITH1
L1
1.5µH
0.1µF
VTT
0.9V
COUT2
100µF
×4
VREF
0.9V
0.01µF
CCOMP2
910pF
Figure 9. Design Example Circuit
VIA TO BOOST1
VIA TO VON1/R2 (NOT SHOWN)
VOUT1
VIA TO VON1 AND R2 (NOT SHOWN)
COUT1
L1
COUT1
GND
VIAS TO GROUND
PLANE
SW1
CBOOST1
VIAS TO GROUND
PLANE
GND
CIN
L1
CIN
VIA TO BOOST1
VIN
SGND (TO NONPOWER
COMPONENTS)
CBOOST2
SW1
VIAS TO GROUND
PLANE
CBOOST1
CBOOST2
SGND (TO NONPOWER
COMPONENTS)
CIN
SW2
VIN
SW2
VIA TO BOOST2
CIN
GND
VIAS TO GROUND
PLANE
L2
VOUT1
VIAS TO GROUND
PLANE
L2
GND
VIAS TO GROUND
PLANE
COUT2
COUT2
VOUT2
VOUT2
3634 F11
VIA TO BOOST2
VIA TO VON2 AND VFB2 (NOT SHOWN)
Figure 10. Example of Power Component Layout
for QFN Package
24
VIA TO VON2 AND VFB2 (NOT SHOWN)
3634 F10
Figure 11. Example of Power Component Layout
for TSSOP Package
3634fc
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LTC3634
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3634#packaging for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0506 REV B
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3634fc
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25
LTC3634
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3634#packaging for the most recent package drawings.
FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev J)
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
6.40
2.74
(.252)
(.108)
BSC
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN MILLIMETERS
(INCHES)
3. DRAWING NOT TO SCALE
26
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP REV J 1012
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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LTC3634
REVISION HISTORY
REV
DATE
DESCRIPTION
A
09/13
Clarified Absolute Maximum Ratings, added H and MP grades to Order Information.
PAGE NUMBER
2
Clarified parametric data.
3, 4
Clarified graphs.
5, 6
Clarified RUN1, RUN2 pin function, INTVCC.
7, 8
Clarified minimum on-time description.
18
Clarified maximum junction temperature in Thermal Considerations.
21
Clarified Related Parts, added LTC3786 and LTC3633A.
28
B
12/13
Clarified dead-time from 10ns to 15ns.
18
C
01/16
Added package option for mini reels
Expanded VTTR pin description
Expanded description in VTTR Output Buffer
2
9
11
3634fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC3034
27
LTC3634
TYPICAL APPLICATION
VIN
3.6V TO
15V
RT
162k
12V
C1
22µF
RUN1
BOOST1
RUN2
LTC3634
SW1
RT
VON1
INTVCC
PHMODE
VDDQIN
MODE/SYNC
VFB1
C2
2.2µF
RCOMP1
26.4k
CCOMP1
560pF
ITH1
BOOST2
ITH2
SW2
VFB2
VON2
VTTR
RCOMP2
18k
C5
10pF
L1
1µH
0.1µF
R2
18.2k
R1
12.1k
SGND
PGND
VDDQ
1.5V
COUT1
100µF
×2
C2
2.2µF
C3
0.01µF
3634 TA02a
CCOMP2
910pF
COUT2
100µF
×4
Figure 12a. VTT Powered from VDDQ
10k
C3
47µF
VIN2
BOOST1
RUN1
RUN2
LTC3634
SW1
RT
BOOST2
INTVCC
PHMODE
SW2
VFB1
VFB2
VDDQIN
VON2
VON1
ITH1
R1
324k
VTT
0.75V
VREF
VIN1
VDDQ
SUPPLY
L2
0.47µH
0.1µF
C4
10pF
C1
22µF
C6
22µF
VIN2
VIN1
0.1µF
L1
1.5µH
0.1µF
L2
1.5µH
5V
VTT
VDDQ /2
AT ±6A
COUT2
100µF
×4
10pF
680pF
ITH2
10pF
SGND
VTTR
MODE/SYNC
PGND
0.01µF
VREF
VDDQ /2
AT ±10mA
3634 TA02b
Figure 12b. 2-Phase VTT Termination Using Two Input Supplies
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3633
15V, Dual 3A (IOUT), 4MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN(MIN) = 3.6V, VIN(MAX) = 15V, VOUT(MIN) = 0.6V,
IQ = 500µA, ISD
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