LTC3718
Low Input Voltage
DC/DC Controller for
DDR/QDR Memory Termination
DESCRIPTIO
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FEATURES
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The LTC®3718 is a high current, high efficiency synchronous switching regulator controller for DDR and QDRTM
memory termination. It operates from an input as low as
1.5V and provides a regulated output voltage equal to
(0.5)VIN. The controller uses a valley current control
architecture to enable high frequency operation with very
low on-times without requiring a sense resistor. Operating
frequency is selected by an external resistor and is compensated for variations in VIN and VOUT. The LTC3718 uses
a pair of standard 5V logic level N-channel external
MOSFETs, eliminating the need for expensive P-channel
or low threshold devices.
Very Low VIN(MIN): 1.5V
Ultrafast Transient Response
True Current Mode Control
5V Drive for N-Channel MOSFETs Eliminates
Auxillary 5V Supply
No Sense Resistor Required
Uses Standard 5V Logic-Level N-Channel MOSFETs
VOUT(MIN): 0.4V
VOUT Tracks 1/2 VIN or External VREF
Symmetrical Source and Sink Output Current Limit
Adjustable Switching Frequency
tON(MIN) COUT VOUT RSENSE (10 – 4 [F/V s])
Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or
desired. The feature can be overridden by adding a pullup current greater than 5µA to the RUN/SS pin. The
additional current prevents the discharge of C SS during a
fault and also shortens the soft-start period. Using a
resistor to VIN as shown in Figure 6a is simple, but slightly
increases shutdown current. Connecting a resistor to
INTVCC as shown in Figure 6b eliminates the additional
shutdown current, but requires a diode to isolate CSS. Any
pull-up network must be able to pull RUN/SS above the
4.2V maximum threshold of the latchoff circuit and overcome the 4µA maximum discharge current.
INTVCC Supply
The 5V supply that powers the drivers and internal circuitry within the LTC3718 can be supplied by either an
internal P-channel low dropout regulator if VIN is greater
than 5V or the internal boost regulator if VIN is less than 5V.
The INTVCC pin can supply up to 50mA RMS and must be
bypassed to ground with a minimum of 4.7µF tantalum or
other low ESR capacitor. Good bypassing is necessary to
supply the high transient currents required by the MOSFET
gate drivers. Applications using large MOSFETs with a
high input voltage and high frequency of operation may
cause the LTC3718 to exceed its maximum junction temperature rating or RMS current rating. In continuous mode
operation, this current is IGATECHG = f(Qg(TOP) + Qg(BOT)).
The junction temperature can be estimated from the
equations given in Note 2 of the Electrical Characteristics.
Inductor Selection for Boost Converter
For the boost converter, the inductance should be 4.7µH
for input voltages less then 3.3V and 10µH for inputs
above 3.3V. The inductor should have a saturation current
rating of approximately 0.5A or greater. A guide for selecting an inductor for the boost converter is to choose a ripple
current that is 40% of the current supplied by the boost
converter. To ensure that the ripple current doesn’t exceed
a specified amount, the inductance can be chosen according to the following equation:
VIN2(MAX)
VIN2(MIN) 1 –
VOUT (BOOST)
L=
∆I • f
Diode D3 Selection
A Schottky diode is recommended for use in the boost
converter section. The Motorola MBR0520 is a very good
choice.
Boost Converter Output Capacitor
Because the LTC3718’s boost converter is internally compensated, loop stability must be carefully considered when
choosing its output capacitor. Small, low cost tantalum
capacitors have some ESR, which aids stability. However,
ceramic capacitors are becoming more popular, having
attractive characteristics such as near-zero ESR, small size
and reasonable cost. Simply replacing a tantalum output
capacitor with a ceramic unit will decrease the phase margin,
in some cases to unacceptable levels. With the addition of
a phase-lead capacitor and isolating resistor, the boost
converter portion of the LTC3718 can be used successfully with ceramic output capacitors.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3718 circuits:
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LTC3718
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APPLICATIO S I FOR ATIO
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I2R
loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the
loss will range from 1% up to 10% as the output current
varies from 1A to 10A for a 1.5V output.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f
3. INTVCC current. This is the sum of the MOSFET driver
and control currents.
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability
problem. The ITH pin external components shown in
Figure 1 will provide adequate compensation for most
applications. For a detailed explanation of switching
control loop theory see Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: VIN = 2.5V, VOUT = 1.25V ±100mV,
IOUT(MAX) = ±6A, f = 300kHz. First, calculate the timing
resistor with VON = VOUT:
RON =
2.5V − 0.7V
= 240k
(2.5V)(300kHz)(10pF )
Next, use a standard value of 237k and choose the inductor
for about 40% ripple current at the maximum VIN:
L=
1.25V
1.25V
1–
= 0.87µH
(300kHz)(0.4)(6A)
2.5V
Selecting a standard value of 1µH results in a maximum
ripple current of:
∆IL =
1.25V
1.25V
1–
= 2.1A
(300kHz)(1µH)
2.5V
Next, choose the synchronous MOSFET switch. Choosing
an IRF7811A (RDS(ON) = 0.013Ω, CRSS = 60pF, θJA =
50°C/W) yields a nominal sense voltage of:
VSNS(NOM) = (6A)(1.3)(0.013Ω) = 101.4mV
Tying VRNG to 1V will set the current sense voltage range
for a nominal value of 100mV with current limit occurring
at 133mV. To check if the current limit is acceptable,
assume a junction temperature of about 10°C above a
50°C ambient with ρ60°C = 1.15:
ILIMIT ≥
133mV
1
+ (2.1A) = 9.9A
(1.15)(0.013Ω) 2
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LTC3718
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APPLICATIO S I FOR ATIO
ESR of 0.005Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
and double check the assumed TJ in the MOSFET:
2
PBOT
2.5V – 1.25V 9.9A
=
(1.15)(0.013Ω)
2.5V
2
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (2.6A) (0.005Ω) = 13mV
= 0.18W
However, a 0A to 6A load step will cause an output change
of up to:
TJ = 50°C + (0.18W)(50°C/W) = 59°C
Now check the power dissipation of the top MOSFET at
current limit with ρ90°C = 1.35:
∆VOUT(STEP) = ∆ILOAD (ESR) = (6A) (0.005Ω) = 30mV
The inductor for the boost converter is selected by first
choosing an allowable ripple current. The boost converter
will be operating in discontinous mode. If we select a ripple
current of 170mA for the boost converter, then:
( ) (1.35)(0.013Ω)
2
+ (1.7)(2.5V )(9.9A ) (60pF )(300kHz )
PTOP =
1.25V
9.9A
2.5V
2
3.3V
3.3V 1 −
5V
= 0.87 W
L=
TJ = 50°C + (0.87W)(50°C/W) = 93.5°C
CIN is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low
1
2
PGOOD
3
RR1
10k
4
RC
4.75k
5
C2
100pF
C1 820pF
RON
237k
6
7
8
9
10
11
12
RF1
12.1k
RF3
10k
RUN/SS
BOOST
VON
TG
PGOOD
SW1
24
23
SENSE +
21
ITH
SENSE –
20
PGND1
LTC3718
ION
BG
VFB1
INTVCC
VREF
VIN1
SHDN
VIN2
SGND2
PGND2
VFB2
SW2
RF2
37.4k
CIN1
22µF
×2
DB
CMDSH-3
CB
0.33µF
M1
IRF7811A
CIN2
330µF
VIN
2.5V
D1
B340A
22
VRNG
SGND1
= 4.7µH
The complete circuit is shown in Figure 7.
CSS
0.1µF
RR2
39.2k
RPG
100k
(170mA)(1.4MHz)
L1
1µH
COUT
270µF
×2
19
18
M2
IRF7811A
D2
B340A
VOUT
1.25V
± 6A
17
16
15
CIN2
4.7µF
14
L2
4.7µH
13
D3
MBR0520
CVCC1
10µF
CF4
1000pF
3718 F07
Figure 7. Design Example: 1.25V/±6A at 300kHz from 2.5V
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LTC3718
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APPLICATIO S I FOR ATIO
PC Board Layout Checklist
• Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power component. You can connect the copper
areas to any DC net (VIN, VOUT, GND or to any other DC
rail in your system).
When laying out a PC board follow one of the two
suggested approaches. The simple PC board layout
requires a dedicated ground plane layer. Also, for higher
currents, it is recommended to use a multilayer board to
help with heat sinking power components.
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper operation of the controller. These items are also illustrated in
Figure 8.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
• Place LTC3718 chip with Pins 13 to 24 facing the
power components. Keep the components connected
to Pins 1 to 12 close to LTC3718 (noise sensitive
components).
• Place M2 as close to the controller as possible, keeping the PGND, BG and SW traces short.
• Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3718.
Use several bigger vias for power components.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and PGND pins.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
• Connect the top driver boost capacitor CB closely to
the BOOST and SW pins.
CSS
1
2
3
4
C1
RC
5
6
RON
C2
7
8
9
10
11
12
RF3
RF5
RUN/SS
BOOST
VON
TG
SW1
PGOOD
VRNG
ITH
22
21
SENSE –
20
INTVCC
VFB1
VREF
VIN1
SHDN
VIN2
SGND2
PGND2
VFB2
SW2
VIN
CB
23
SENSE +
SGND1
PGND1
LTC3718
ION
BG
+
24
M1
CIN
DB
L1
VOUT
COUT
19
M2
D2
18
17
CVCC
–
16
15
3718 F08
14
13
CIN2
L2
BOLD LINES INDICATE HIGH CURRENT PATHS
D3
RF4
Figure 8. LTC3718 Layout Diagram
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LTC3718
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TYPICAL APPLICATIO
One Half VIN, ±10A Bus Terminator
CSS
0.1µF X7R
RPG
100k
1
2
3
PGOOD
C1
820pF
X7R
4
RC 4.75k
5
C2
100pF
6
RON
237k
7
8
9
10
11
12
RUN/SS
VON
TG
PGOOD
SW1
21
ITH
SENSE –
20
PGND1
LTC3718
ION
BG
VFB1
INTVCC
VREF
VIN1
SHDN
VIN2
PGND2
SGND2
SW2
VFB2
M1
Si7440DP
CIN2****
330µF
D1
B340A
22
SENSE +
SGND1
CB 0.33µF
X7R
23
VRNG
RF3
10k
RF1
12.1k
BOOST
DB
CMDSH-3
24
VIN
2.5V
CIN1
22µF X5R
×2
L1**
0.8µH
+
19
18
M2
Si7440DP
D2
B340A
COUT*
470µF
×2
VOUT
1.25V
±10A
22µF
X5R
17
16
15
4.7µF
6.3V X7R
14
L2***
4.7µH
13
CVCC1
10µF 6.3V
X5R
RF2
37.4k
D3
MBR0520
3718 TA02
CF4
1000pF X7R
*SANYO POSCAP 4TPB470M
**SUMIDA CEP125-0R8MC
***PANASONIC ELJPC4R7MF
****SANYO POSCAP 6TPB330M
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PACKAGE DESCRIPTIO
G Package
24-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
7.90 – 8.50*
(.311 – .335)
24 23 22 21 20 19 18 17 16 15 14 13
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
RECOMMENDED SOLDER PAD LAYOUT
0.65
BSC
1 2 3 4 5 6 7 8 9 10 11 12
2.0
(.079)
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
0.65
(.0256)
BSC
0.22 – 0.38
0.05
(.009 – .015)
(.002)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3. DRAWING NOT TO SCALE
G24 SSOP 0802
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3718
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TYPICAL APPLICATIO
Dual Output 2.5V, ±10A Buck Converter and 5V to 12V/130mA Boost Converter
CSS
0.1µF X7R
RPG
100k
1
2
3
PGOOD
C1
3300pF
X7R
4
RC 10k
5
C2
100pF
RON
237k
6
7
RFB
249k
8
RREF
499k
9
10
11
12
RF3
10k
RF1
12.3k
RUN/SS
BOOST
VON
TG
SW1
PGOOD
SENSE +
VRNG
ITH
SENSE
SGND1
–
PGND1
LTC3718
ION
BG
VFB1
INTVCC
VREF
VIN1
SHDN
VIN2
SGND2
PGND2
VFB2
SW2
VIN
6V TO 24V
CIN1****
33µF
×2
25V
DB
CMDSH-3
24
CB 0.33µF
X7R
23
D1
B340A
M1
Si7440DP
22
21
L1**
1.8µH
20
19
RF
1Ω
18
M2
Si7440DP
+
D2
B340A
COUT*
470µF
×2
VOUT1
2.5V
±10A
17
CF
0.1µF
16
15
CVCC2
4.7µF
VIN2
5V
CIN2
22µF X5R
14
L2***
10µH
13
RF2
107k
CVCC1
4.7µF
X5R
CF4
200pF X7R
D3
MBR0520
*SANYO POSCAP 4TPB470M
**TOKO D104C
***PANASONIC ELJPC4R7MF
****KEMET T495X336K025AS
VOUT2
12V
130mA
3718 TA03
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No RSENSE and ThinSOT are trademarks of Linear Technology Corporation.
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