LTC3722-1/LTC3722-2
Synchronous Dual Mode
Phase Modulated
Full Bridge Controllers
DESCRIPTION
FEATURES
Adaptive or Manual Delay Control for Zero Voltage
Switching Operation
n Adjustable Synchronous Rectification Timing for
Highest Efficiency
n Adjustable Maximum ZVS Delay
n Adjustable System Undervoltage Lockout Hysteresis
n Programmable Leading Edge Blanking
n Very Low Start-Up and Quiescent Currents
n Current Mode (LTC3722-1) or Voltage Mode
(LTC3722-2) Operation
n Programmable Slope Compensation
n V
CC UVLO and 25mA Shunt Regulator
n 50mA Output Drivers
n Soft-Start, Cycle-by-Cycle Current Limiting and
Hiccup Mode Short-Circuit Protection
n 5V, 15mA Low Dropout Regulator
n 24-Pin Surface Mount GN Package
n
APPLICATIONS
Telecommunications, Infrastructure Power Systems
Distributed Power Architectures
n Server Power Supplies
The LTC®3722-1/LTC3722-2 phase-shift PWM controllers
provide all of the control and protection functions necessary to implement a high efficiency, zero voltage switched
(ZVS), full bridge power converter. Adaptive ZVS circuitry
delays the turn-on signals for each MOSFET independent
of internal and external component tolerances. Manual
delay set mode enables secondary side control operation
or direct control of switch turn-on delays.
The LTC3722-1/LTC3722-2 feature adjustable synchronous rectifier timing for optimal efficiency. A UVLO program
input provides accurate system turn-on and turn-off
voltages. The LTC3722-1 features peak current mode
control with programmable slope compensation and
leading edge blanking, while the LTC3722-2 employs
voltage mode control.
The LTC3722-1/LTC3722-2 feature extremely low operating
and start-up currents. Both devices include a full range of
protection features and are available in the 24-pin surface
mount GN package.
n
n
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
VIN
36V TO
72V
CIN
R1
12VOUT , 240W Converter Efficiency
U2
U1
MA
95
MC
T1
36VIN
L2
MB
VOUT
12V
COUT
MD
RCS
90
EFFICIENCY (%)
L1
LTC3722
48VIN
72VIN
85
80
ME
T2
C1
U1, U2: LTC4440 GATE DRIVER
U3: LTC3901 GATE DRIVER
U3
75
MF
0
2
4
6
8 10 12 14 16 18 20
CURRENT (A)
372212 TA01b
372212 TA01a
Rev C
Document Feedback
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1
LTC3722-1/LTC3722-2
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VCC to GND (Low Impedance Source)......... –0.3V to 10V
(Chip Self Regulates at 10.3V)
UVLO to GND...............................................–0.3V to VCC
All Other Pins to GND
(Low Impedance Source)........................... –0.3V to 5.5V
VCC (Current Fed)....................................................25mA
VREF Output Current.................................. Self Regulated
Outputs (A, B, C, D, E, F) Current........................ ±100mA
Operating Junction Temperature Range
(Note 6)................................................... –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
PIN CONFIGURATION
LTC3722-1
LTC3722-2
TOP VIEW
TOP VIEW
SYNC
1
24 CT
SYNC
1
24 CT
DPRG
2
23 GND
RAMP
2
23 GND
CS
3
22 PGND
CS
3
22 PGND
COMP
4
21 OUTA
COMP
4
21 OUTA
RLEB
5
20 OUTB
DPRG
5
20 OUTB
FB
6
19 OUTC
FB
6
19 OUTC
SS
7
18 VCC
SS
7
18 VCC
NC
8
17 OUTD
NC
8
17 OUTD
PDLY
9
16 OUTE
PDLY
9
16 OUTE
SBUS 10
15 OUTF
SBUS 10
15 OUTF
ADLY 11
14 VREF
ADLY 11
14 VREF
UVLO 12
13 SPRG
UVLO 12
13 SPRG
GN PACKAGE
24-LEAD NARROW PLASTIC SSOP
GN PACKAGE
24-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
TJMAX = 125°C, θJA = 100°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3722EGN-1#PBF
LTC3722EGN-1#TRPBF
LTC3722EGN-1
24-Lead Plastic SSOP
–40°C to 85°C
LTC3722EGN-2#PBF
LTC3722EGN-2#TRPBF
LTC3722EGN-2
24-Lead Plastic SSOP
–40°C to 85°C
LTC3722IGN-1#PBF
LTC3722IGN-1#TRPBF
LTC3722IGN-1
24-Lead Plastic SSOP
–40°C to 85°C
LTC3722IGN-2#PBF
LTC3722IGN-2#TRPBF
LTC3722IGN-2
24-Lead Plastic SSOP
–40°C to 85°C
LTC3722HGN-1#PBF
LTC3722HGN-1#TRPBF
LTC3722HGN-1
24-Lead Plastic SSOP
–40°C to 150°C
Consult ADI Marketing for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev C
2
For more information www.analog.com
LTC3722-1/LTC3722-2
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V, CT = 270pF, RDPRG = 60.4k, RSPRG = 100k, unless
otherwise noted (Note 6).
SYMBOL
PARAMETER
CONDITIONS
VCCUV
VCC Under Voltage Lockout
Measured on VCC
VCCHY
VCC UVLO Hysteresis
Measured on VCC
ICCST
Start-Up Current
VCC = VUVLO – 0.3V
LTC3722E-1/LTC3722I-1/LTC3722E-2/LTC3722I-2
LTC3722H-1
MIN
TYP
MAX
UNITS
10.25
10.5
V
Input Supply
3.8
l
l
4.2
V
145
145
230
250
µA
µA
5
8
mA
10.3
10.8
V
ICCRN
Operating Current
No Load on Outputs
VSHUNT
Shunt Regulator Voltage
Current into VCC = 10mA
RSHUNT
Shunt Resistance
Current into VCC = 10mA to 17mA
1.1
3.5
Ω
SUVLO
System UVLO Threshold
Measured on UVLO Pin, 10mA into VCC
4.8
5.0
5.2
V
SHYST
System UVLO Hysteresis Current
Current Flows Out of UVLO Pin
8.5
10
11.5
µA
DTHR
Delay Pin Threshold
ADLY and PDLY
SBUS = 1.5V
SBUS = 2.25V
1.4
2.1
1.5
2.25
1.6
2.4
V
V
DHYS
Delay Hysteresis Current
ADLY and PDLY
SBUS = 1.5V, ADLY/PDLY = 1.7V
1.3
mA
DTMO
Delay Timeout
RDPRG = 60.4K
100
ns
DFXT
Fixed Delay Threshold
Measured on SBUS
4
V
DFTM
Fixed Delay Time
SBUS = VREF , ADLY, PDLY = 1V
70
ns
Delay Blocks
l
l
Phase Modulator
ICS
CS Discharge Current
CS = 1V, COMP = 0V, CT = 4V,
LTC3722-1 Only
50
mA
ISLP
Slope Compensation Current
Measured on CS, CT = 1V
CT = 2.25V
30
68
µA
µA
DCMAX
Maximum Phase Shift
COMP = 4.5V
l
98.5
%
DCMIN
Minimum Phase Shift
COMP = 0V
l
OSCI
Initial Accuracy
TA = 25°C, CT = 270pF
OSCT
Total Variation
VCC = 6.5V to 9.5V
OSCV
CT Ramp Amplitude
Measured on CT
OSYT
SYNC Threshold
Measured on SYNC
OSYW
Minimum SYNC Pulse Width
Measured at Outputs (Note 2)
75
ns
OSYR
SYNC Frequency Range
Measured at Outputs (Note 2)
1000
kHz
FB Input Voltage
COMP = 2.5V (Note 4)
1.172
95
0
0.5
%
225
250
275
kHz
215
250
285
kHz
Oscillator
l
2.5
1.6
1.9
V
2.2
V
Error Amplifier
VFB
FBI
FB Input Range
Measured on FB (Note 5)
–0.3
AVOL
Open-Loop Gain
COMP = 1V to 3V (Note 4)
70
IIB
Input Bias Current
COMP = 2.5V (Note 4)
1.204
2.5
90
5
4.7
1.236
V
V
dB
20
4.92
nA
VOH
Output High
Load on COMP = –100µA
VOL
Output Low
Load on COMP = 100µA
ISOURCE
Output Source Current
COMP = 2.5V
400
800
µA
ISINK
Output Sink Current
COMP = 2.5V
2
5
mA
0.18
V
0.4
V
Rev C
For more information www.analog.com
3
LTC3722-1/LTC3722-2
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V, CT = 270pF, RDPRG = 60.4k, RSPRG = 100k, unless
otherwise noted (Note 6).
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4.925
5.00
5.075
V
2
15
mV
mV
Reference
VREF
Initial Accuracy
TA = 25°C, Measured on VREF
REFLD
Load Regulation
Load on VREF = 100µA to 5mA
REFLN
Line Regulation
VCC = 6.5V to 9.5V
REFTV
Total Variation
Line, Load
REFSC
Short-Circuit Current
OUTH(x)
0.9
10
4.900
5.000
5.100
VREF Shorted to GND
18
30
45
Output High Voltage
IOUT(x) = –50mA
7.9
8.4
OUTL(x)
Output Low Voltage
IOUT(x) = 50mA
0.6
1
V
RHI(x)
Pull-Up Resistance
IOUT(x) = –50mA to –10mA
22
30
Ω
RLO(x)
Pull-Down Resistance
IOUT(x) = –50mA to –10mA
12
20
Ω
tr(x)
Rise Time
COUT(x) = 50pF (Note 8)
5
15
ns
tf(x)
Fall Time
COUT(x) = 50pF (Note 8)
5
15
ns
SDEL
SYNC Driver Turn-0ff Delay
RSPRG = 100k
l
V
mA
Outputs
V
180
ns
Current Limit and Shutdown
CLPP
Pulse by Pulse Current Limit Threshold
Measured on CS
LTC3722E-1/LTC3722I-1/LTC3722E-2/LTC3722I-2
LTC3722H-1
270
270
300
300
330
340
CLSD
Shutdown Current Limit Threshold
Measured on CS
0.55
0.65
0.73
CLDEL
Current Limit Delay to Output
100mV Overdrive on CS (Notes 3, 7)
SSI
Soft-Start Current
SS = 2.5V
7
12
17
µA
SSR
Soft-Start Reset Threshold
Measured on SS
0.7
0.4
0.1
V
FLT
Fault Reset Threshold
Measured on SS
4.5
3.9
3.5
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Sync amplitude = 5VP-P , pulse width = 75ns. Verify output (A-F)
frequency = one-half sync frequency.
Note 3: Includes leading edge blanking delay, RLEB = 20k.
Note 4: FB is driven by a servo-loop amplifier to control VCOMP for these
tests.
Note 5: Set FB to –0.3V, 2.5V and insure that COMP does not phase invert.
Note 6: The LTC3722 is tested under pulsed load condition such that
TJ ≈ TA. The LTC3722E-1/LTC3722E-2 are guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to
85°C operating junction temperature range are assured by design,
80
mV
mV
V
ns
characterization and correlation with statistical process controls. The
LTC3722I-1/LTC3722I-2 are guaranteed over the –40°C to 85°C operating
junction temperature range and the LTC3722H-1 is guaranteed over the
–40°C to 150°C operating junction temperature range.
High junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 7: Guaranteed by design, not tested in production.
Note 8: Rise time is measured from the 10% to 90% points of the rising
edge of the driver output signal. Fall time is measured from the 90% to
10% points of the falling edge of the driver output signal.
Rev C
4
For more information www.analog.com
LTC3722-1/LTC3722-2
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up ICC vs VCC
200
10.50
TA = 25°C
260
TA = 25°C
CT = 270pF
FREQUENCY (kHz)
10.25
VCC (V)
ICC (µA)
150
Oscillator Frequency
vs Temperature
VCC vs ISHUNT
100
10.00
50
250
240
9.75
0
2
0
6
4
8
VCC (V)
9.50
10
10
0
30
20
ISHUNT (mA)
372212 G01
40
230
–50 –30 –10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
50
372212 G02
372212 G03
350
Leading Edge Blanking Time
vs RLEB
5.05
TA = 25°C
300
VREF vs IREF
TA = 25°C
5.00
5.00
TA = 85°C
150
4.95
VREF (V)
200
VREF (V)
BLANK TIME (ns)
250
4.90
4.99
4.98
TA = –40°C
100
4.85
50
0
VREF vs Temperature
5.01
0 10 20 30 40 50 60
RLEB (k)
4.80
70 80 90 100
4.97
0
5
372212 G04
10
15 20
25
IREF (mA)
30
35
4.96
–50 –30 –10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
40
372212 G05
372212 G06
1.300
HYSTERESIS CURRENT (mA)
180
170
160
–180
150
140
130
–270
120
–360
110
10
1.302
190
TA = 25°C
ICC (µA)
GAIN (dB)
PHASE (DEG)
100
80
60
40
20
0
Delay Hysteresis Current
vs Temperature
Start-Up ICC vs Temperature
Error Amplifier Gain/Phase
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
372212 G07
100
–60
SBUS = 1.5V
1.298
1.296
1.294
1.292
1.290
1.288
1.286
1.284
1.282
–30
0
30
60
90
TEMPERATURE (°C)
120
150
372212 G08
1.280
–60
–30
60
30
0
90
TEMPERATURE (°C)
120
150
372212 G09
Rev C
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5
LTC3722-1/LTC3722-2
TYPICAL PERFORMANCE CHARACTERISTICS
Slope Current vs Temperature
10.5
90
CT = 2.25V
80
Delay Pin Threshold
vs Temperature
VCC Shunt Voltage vs Temperature
2.4
ICC = 10mA
2.3
10.4
2.2
50
40
CT = 1V
30
20
10.3
THRESHOLD (V)
SHUNT VOLTAGE (V)
10.2
10.1
10.0
0
–60
–30
0
30
60
90
TEMPERATURE (°C)
60
30
90
0
TEMPERATURE (°C)
1.9
1.8
1.7
SBUS = 1.5V
120
1.4
–60
150
FB Input Voltage vs Temperature
1.210
300
1.209
300
250
250
200
DELAY (ns)
150
TA = 25°C
SBUS = 2.25V
1.205
120
ZVS Delay in Fixed Mode,
SBUS = 5V
TA = 25°C
1.208
1.206
60
30
0
90
TEMPERATURE (°C)
372212 G12
Delay Timeout vs RDPRG
1.207
–30
372212 G11
372212 G10
FB VOLTAGE (V)
2.0
1.5
9.8
–60 –30
150
120
2.1
1.6
9.9
10
ADLY = PDLY = 2.25V
150
SBUS = 1.125V
100
ADLY = PDLY = 1.5V
200
SBUS = 1.5V
DELAY (ns)
CURRENT (µA)
70
60
SBUS = 2.25V
150
ADLY = PDLY = 1.125V
100
1.204
50
1.203
1.202
–60 –30
90
60
30
TEMPERATURE (°C)
0
120
150
0
50
10
60
110
160
210
RDPRG (kΩ)
260
0
310
10
60
372212 G14
110
160
210
RDPRG (kΩ)
260
310
372212 G15
372212 G13
Synchronous Driver Turn-Off Delay in
Adaptive Mode, SBUS = 1.5V
Synchronous Driver Turn-Off
Delay in Fixed Mode
350
TA = 25°C
260
TA = 25°C
300
220
DELAY (ns)
DELAY (nS)
250
200
150
100
50
60
10
60
110
RSPRG (kΩ)
160
210
372212 G16
A HI-E LOW
140
100
0
B HI-F LOW
180
20
10 30 50 70 90 110 130 150 170 190
RSPRG (kΩ)
372212 G17
Rev C
6
For more information www.analog.com
LTC3722-1/LTC3722-2
PIN FUNCTIONS
(LTC3722-1/LTC3722-2)
SYNC (Pin 1/Pin 1): Synchronization Input/Output for the
Oscillator. The input threshold for SYNC is approximately
1.9V, making it compatible with both CMOS and TTL logic.
Terminate SYNC with a 5.1k resistor to GND.
DPRG (Pin 2/Pin 5): Programming Input for Default Zero
Voltage Transition (ZVS) Delay. Connect a resistor from
DPRG to VREF to set the maximum turn on delay for outputs
A, B, C, D. The nominal voltage on DPRG is 2V.
RAMP (NA/Pin 2): Input to Phase Modulator Comparator
for LTC3722-2 only. The voltage on RAMP is internally
level shifted by 650mV.
CS (Pin 3/Pin 3): Input to Phase Modulator for the
LTC3722-1. Input to pulse-by-pulse and overload current
limit comparators, output of slope compensation circuitry.
The pulse by pulse comparator has a nominal 300mV
threshold, while the overload comparator has a nominal
650mV threshold.
COMP (Pin 4/Pin 4): Error Amplifier Output, Inverting
Input to Phase Modulator.
RLEB (Pin 5/NA): Timing Resistor for Leading Edge Blanking. Use a 10k to 100k resistor to program from 40ns to
310ns of leading edge blanking of the current sense signal
on CS for the LTC3722-1. A ±1% tolerance resistor is
recommended. The LTC3722-2 has a fixed blanking time
of approximately 80ns.
FB (Pin 6/Pin 6): Error Amplifier Inverting Input. This is
the voltage feedback input for the LTC3722. The nominal
regulation voltage at FB is 1.204V.
SS (Pin 7/Pin 7): Soft-Start/Restart Delay Circuitry Timing
Capacitor. A capacitor from SS to GND provides a controlled
ramp of the current command (LTC3722-1), or duty cycle
(LTC3722-2). During overload conditions SS is discharged
to ground initiating a soft-start cycle.
NC (Pin 8/Pin 8): No Connection. Tie this pin to GND.
PDLY (Pin 9/Pin 9): Passive Leg Delay Circuit Input. PDLY
is connected through a voltage divider to the left leg of
the bridge in adaptive ZVS mode. In fixed ZVS mode, a
voltage between 0V and 2.5V on PDLY, programs a fixed
ZVS delay time for the passive leg transition.
SBUS (Pin 10/Pin 10): Line Voltage Sense Input. SBUS is
connected to the main DC voltage feed by a resistive voltage divider when using adaptive ZVS control. The voltage
divider is designed to produce 1.5V on SBUS at nominal
VIN. If SBUS is tied to VREF , the LTC3722-1/LTC3722-2 is
configured for fixed mode ZVS control.
ADLY (Pin 11/Pin 11): Active Leg Delay Circuit Input. ADLY
is connected through a voltage divider to the right leg of
the bridge in adaptive ZVS mode. In fixed ZVS mode, a
voltage between 0V and 2.5V on ADLY, programs a fixed
ZVS delay time for the active leg transition.
UVLO (Pin 12/Pin 12): Input to Program System TurnOn and Turn-Off Voltages. The nominal threshold of the
UVLO comparator is 5V. UVLO is connected to the main
DC system feed through a resistor divider. When the
UVLO threshold is exceeded, the LTC3722-1/LTC3722-2
commences a soft-start cycle and a 10µA (nominal) current is fed out of UVLO to program the desired amount of
system hysteresis. The hysteresis level can be adjusted
by changing the resistance of the divider.
SPRG (Pin 13/Pin 13): A resistor is connected between
SPRG and GND to set the turn-off delay for the synchronous
rectifier driver outputs (OUTE and OUTF). The nominal
voltage on SPRG is 2V.
VREF (Pin 14/Pin 14): Output of the 5V Reference. VREF
is capable of supplying up to 18mA to external circuitry.
VREF should be decoupled to GND with a 1µF ceramic
capacitor.
OUTF (Pin 15/Pin 15): 50mA Driver for Synchronous
Rectifier Associated with OUTB and OUTC.
OUTE (Pin 16/Pin 16): 50mA Driver for Synchronous
Rectifier Associated with OUTA and OUTD.
OUTD (Pin 17/Pin 17): 50mA Driver for Low Side of the
Full Bridge Active Leg.
VCC (Pin 18/Pin 18): Supply Voltage Input to the
LTC3722-1/LTC3722-2 and 10.25V Shunt Regulator.
The chip is enabled after VCC has risen high enough to
allow the VCC shunt regulator to conduct current and the
UVLO comparator threshold is exceeded. Once the VCC
shunt regulator has turned on, VCC can drop to as low as
6V (typ) and maintain operation.
Rev C
For more information www.analog.com
7
LTC3722-1/LTC3722-2
PIN FUNCTIONS
(LTC3722-1/LTC3722-2)
GND (Pin 23/Pin 23): All circuits other than the output
drivers in the LTC3722 are referenced to GND. Use of a
ground plane is recommended but not absolutely necessary.
OUTC (Pin 19/Pin 19): 50mA Driver for High Side of the
Full Bridge Active Leg.
OUTB (Pin 20/Pin 20): 50mA Driver for Low Side of the
Full Bridge Passive Leg.
CT (Pin 24/Pin 24): Timing Capacitor for the Oscillator.
Use a ±5% or better low ESR ceramic capacitor for best
results.
OUTA (Pin 21/Pin 21): 50mA Driver for High Side of the
Full Bridge Passive Leg.
PGND (Pin 22/Pin 22): Power Ground for the LTC3722.
The output drivers of the LTC3722 are referenced to
PGND. Connect the ceramic VCC bypass capacitor directly to PGND.
BLOCK DIAGRAM
LTC3722-1 Current Mode SYNC Phase-Shift PWM
VCC
UVLO
VREF
CT
SYNC
SPRG
DPRG
SBUS
18
12
14
24
1
13
2
10
VCC UVLO
10.25V = ON
6V = OFF
FB
6
–
1.2V
+
+
ERROR
AMPLIFIER
COMP
4
R1
50k
OUTA
21
Q
1 = ENABLE
0 = DISABLE
T
QB
SYNC
RECTIFIER
DRIVE
LOGIC
PHASE
MODULATOR
VREF
+
650mV
–
OUTB
20
VCC
GOOD
QB
R
Q
S
R QB
12µA
7
PASSIVE
DELAY
–
R2
14.9k
650mV
SS
S
SHUTDOWN
CURRENT
LIMIT
OUTE
16
OUTF
15
OUTC
19
ACTIVE
DELAY
OUTD
17
ADLY
FAULT
LOGIC
11
PGND
22
M2
SLOPE
COMPENSATION
CT/R
CS
BLANK
5
RLEB
OSC
+
M1
20Ω
3
SYSTEM
UVLO
–
5V
+
–
PDLY
9
5V
REF AND LDO
1.2V
REF GOOD
300mV
+
–
PULSE BY PULSE
CURRENT LIMIT
23
GND
372212 BD01
Rev C
8
For more information www.analog.com
LTC3722-1/LTC3722-2
BLOCK DIAGRAM
LTC3722-2 Voltage Mode SYNC Phase-Shift PWM
VCC
UVLO
VREF
CT
SYNC
SPRG
DPRG
SBUS
18
12
14
24
1
13
5
10
VCC UVLO
10.25V = ON
6V = OFF
FB
6
ERROR
AMPLIFIER
–
+
1.2V
RAMP
+
SYSTEM
UVLO
–
5V
R1
50k
COMP
4
2
OSC
OUTA
21
Q
1 = ENABLE
0 = DISABLE
T
–
+
650mV
QB
R
Q
S
R
12µA
7
+
650mV
CS
–
BLANK
+
300mV
–
SHUTDOWN
CURRENT
LIMIT
OUTE
16
SYNC
RECTIFIER
DRIVE
LOGIC
PHASE
MODULATOR
SS
OUTB
20
QB
+
–
PASSIVE
DELAY
VCC
GOOD
VREF
3
PDLY
9
5V
REF AND LDO
1.2V
REF GOOD
QB
S
OUTF
15
OUTC
19
ACTIVE
DELAY
OUTD
17
ADLY
FAULT
LOGIC
11
PGND
M2
372212 BD02
22
23
PULSE BY PULSE
CURRENT LIMIT
GND
Rev C
For more information www.analog.com
9
LTC3722-1/LTC3722-2
TIMING DIAGRAM
PASSIVE LEG
DELAY
ACTIVE LEG
DELAY
OUTA
OUTB
OUTC
OUTD
COMP
RAMP
COMP
SYNC TURN OFF
DELAY (PROGRAMMABLE)
COMP
OUTE
SYNC TURN OFF
DELAY (PROGRAMMABLE)
OUTF
NOTE: SHADED AREAS CORRESPOND TO POWER DELIVERY PULSES.
372212 TD01
OPERATION
Phase-Shift Full Bridge PWM
Conventional full bridge switching power supply topologies
are often employed for high power, isolated DC/DC and
off-line converters. Although they require two additional
switching elements, substantially greater power and higher
efficiency can be attained for a given transformer size
compared to the more common single-ended forward and
flyback converters. These improvements are realized since
the full bridge converter delivers power during both parts
of the switching cycle, reducing transformer core loss
and lowering voltage and current stresses. The full bridge
converter also provides inherent automatic transformer
flux reset and balancing due to its bidirectional drive
configuration. As a result, the maximum duty cycle range
is extended, further improving efficiency. Soft-switching
variations on the full bridge topology have been proposed
to improve and extend its performance and application.
These zero voltage switching (ZVS) techniques exploit the
generally undesirable parasitic elements present within the
power stage. The parasitic elements are utilized to drive
near lossless switching transitions for all of the external
power MOSFETs.
LTC3722-1/LTC3722-2 phase-shift PWM controllers provide enhanced performance and simplify the design task
required for a ZVS phase-shifted full bridge converter.
The primary attributes of the LTC3722-1/LTC3722-2 as
compared to currently available solutions include:
1. Truly adaptive and accurate (DirectSenseTM technology)
ZVS with programmable timeout.
Benefit: higher efficiency, higher duty cycle capability,
eliminates external trim.
2. Fixed ZVS capability.
Benefit: enables secondary-side control and simplifies
external circuit.
Rev C
10
For more information www.analog.com
LTC3722-1/LTC3722-2
OPERATION
3 Internally generated drive signals with programmable
turn-off for current doubler synchronous rectifiers.
4. Programmable (single resistor) leading edge blanking.
elements are detailed in this data sheet. The secondary
voltage of the transformer is the primary voltage divided
by the transformer turns ratio. Similar to a buck converter,
the secondary square wave is applied to an output filter
inductor and capacitor to produce a well regulated DC
output voltage.
Benefit: prevents spurious operation, reduces external
filtering required on CS.
Switching Transitions
Benefit: eliminates external glue logic, drivers, optimal
timing for highest efficiency.
5. Programmable (single resistor) slope compensation.
Benefit: eliminates external glue circuitry.
6. Optimized current mode control architecture.
Benefit: eliminates glue circuitry, less overshoot at
start-up, faster recovery from system faults.
7. Programmable system undervoltage lockout and hysteresis.
Benefit: provides an accurate turn-on voltage for power
supply and reduces external circuitry.
As a result, the LTC3722-1/LTC3722-2 makes the ZVS topology feasible for a wider variety of applications, including
those at lower power levels.
The LTC3722-1/LTC3722-2 control four external power
switches in a full bridge arrangement. The load on the
bridge is the primary winding of a power transformer. The
diagonal switches in the bridge connect the primary winding between the input voltage and ground every oscillator
cycle. The pair of switches that conduct are alternated by
an internal flip-flop in the LTC3722-1/LTC3722-2. Thus,
the voltage applied to the primary is reversed in polarity
on every switching cycle and each output drive signal is
one-half the frequency of the oscillator. The on-time of
each driver signal is slightly less than 50%. The on-time
overlap of the diagonal switch pairs is controlled by the
LTC3722-1/LTC3722-2 phase modulation circuitry (refer
to the Block and Timing Diagrams). This overlap sets the
approximate duty cycle of the converter. The LTC3722‑1/
LTC3722-2 driver output signals (OUTA to OUTF) are
optimized for interface with an external gate driver IC or
buffer. External power MOSFETs A and C require high side
driver circuitry, while B and D are ground referenced and E
and F are ground referenced but on the secondary-side of
the isolation barrier. Methods for providing drive to these
The phase-shifted full bridge can be described by four
primary operating states. The key to understanding how
ZVS occurs is revealed by examining the states in detail.
Each full cycle of the transformer has two distinct periods
in which power is delivered to the output, and two “freewheeling” periods. The two sides of the external bridge
have fundamentally different operating characteristics that
become important when designing for ZVS over a wide
load current range. The left bridge leg is referred to as the
passive leg, while the right leg is referred to as the active
leg. The following descriptions provide insight as to why
these differences exist.
State 1 (Power Pulse 1)
As shown in Figure 1, State 1 begins with MA, MD and MF
“ON” and MB, MC and ME “OFF.” During the simultaneous conduction of MA and MD, the full input voltage is
applied across the transformer primary winding and following the dot convention, VIN/N is applied to the left side
of LO1 allowing current to increase in LO1. The primary
current during this period is approximately equal to the
output inductor current (LO1) divided by the transformer
turns ratio plus the transformer magnetizing current
(VIN • tON)/(LMAG • 2). MD turns off and ME turns on at
the end of State 1.
State 2 (Active Transition and Freewheel Interval)
MD turns off when the phase modulator comparator transitions. At this instant, the voltage on the MD/MC junction
begins to rise towards the applied input voltage (VIN).
The transformer’s magnetizing current and the reflected
output inductor current propels this action. The slew rate
is limited by MOSFET MC and MD’s outputcapacitance
(COSS), snubbing capacitance and the transformer interwinding capacitance. The voltage transition on the active
leg from the ground reference point to VIN will always
Rev C
For more information www.analog.com
11
LTC3722-1/LTC3722-2
OPERATION
State 1
POWER PULSE 1
VIN
VOUT
L01
MA
MC
N:1
MB
MD
LOAD
L02
MF
ME
+
IP ≈ IL01 /N + (VIN • TON)/LMAG
State 2
ACTIVE
TRANSITION
MA
PRIMARY AND
SECONDARY SHORTED
FREEWHEEL
INTERVAL
MC
VOUT
MA
MC
LOAD
MB
State 3
MD
MC
MB
MD
MA
MD
MF
ME
PASSIVE
TRANSITION
MA
State 4
MB
POWER PULSE 2
VOUT
MC
LOAD
MB
MD
MF
ME
+
372212 F01
Rev C
12
For more information www.analog.com
LTC3722-1/LTC3722-2
OPERATION
occur, independent of load current as long as energy in
the transformer’s magnetizing and leakage inductance is
greater than the capacitive energy. That is, 1/2 • (LM + LI)
• IM2 > 1/2 • 2 • COSS • VIN2 — the worst case occurs
when the load current is zero. This condition is usually
easy to meet. The magnetizing current is virtually constant
during this transition because the magnetizing inductance
has positive voltage applied across it throughout the low
to high transition. Since the leg is actively driven by this
current source, it is called the active or linear transition.
When the voltage on the active leg has risen to VIN,
MOSFET MC is switched on by the ZVS circuitry. The
primary current now flows through the two high side
MOSFETs (MA and MC). The transformer’s secondary
windings are electrically shorted at this time since both
ME and MF are “ON”. As long as positive current flows
in LO1 and LO2, the transformer primary (magnetizing)
inductance is also shorted through normal transformer
action. MA and MF turn off at the end of State 2.
State 3 (Passive Transition)
MA turns off when the oscillator timing period ends, i.e.,
the clock pulse toggles the internal flip-flop. At the instant
MA turns off, the voltage on the MA/MB junction begins to
decay towards the lower supply (GND). The energy available
to drive this transition is limited to the primary leakage
inductance and added commutating inductance which
have (IMAG + IOUT/2N) flowing through them initially. The
magnetizing and output inductors do not contribute any
energy because they are effectively shorted as mentioned
previously, significantly reducing the available energy. This
is the major difference between the active and passive
transitions. If the energy stored in the leakage and commutating inductance is greater than the capacitive energy,
the transition will be completed successfully. During the
transition, an increasing reverse voltage is applied to the
leakage and commutating inductances, helping the overall
primary current to decay. The inductive energy is thus
resonantly transferred to the capacitive elements, hence,
the term passive or resonant transition. Assuming there
is sufficient inductive energy to propel the bridge leg to
GND, the time required will be approximately equal to:
π
2
LC
When the voltage on the passive leg nears GND, MOSFET
MB is commanded “ON” by the ZVS circuitry. Current
continues to increase in the leakage and external series
inductance which is opposite in polarity to the reflected
output inductor current. When this current is equal in
magnitude to the reflected output current, the primary
current reverses direction, the opposite secondary winding
becomes forward biased and a new power pulse is initiated. The time required for the current reversal reduces
the effective maximum duty cycle and must be considered
when computing the power transformer turns ratio. If
ZVS is required over the entire range of loads, a small
commutating inductor is added in series with the primary
to aid with the passive leg transition, since the leakage
inductance alone is usually not sufficient and predictable
enough to guarantee ZVS over the full load range.
State 4 (Power Pulse 2)
During power pulse 2, current builds up in the primary
winding in the opposite direction as power pulse 1. The
primary current consists of reflected output inductor current and current due to the primary magnetizing inductance.
At the end of State 4, MOSFET MC turns off and an active
transition, essentially similar to State 2 but opposite in
direction (high to low), takes place.
Zero Voltage Switching (ZVS)
A lossless switching transition requires that the respective
full bridge MOSFETs be switched to the “ON” state at the
exact instant their drain-to-source voltage is zero. Delaying
the turn-on results in lower efficiency due to circulating current flowing in the body diode of the primary side MOSFET
rather than its low resistance channel. Premature turn-on
produces hard switching of the MOSFETs, increasing noise
and power dissipation.
LTC3722-1/LTC3722-2 Adaptive Delay Circuitry
The LTC3722-1/LTC3722-2 monitors both the input supply
and instantaneous bridge leg voltages, and commands
a switching transition when the expected zero voltage
condition is reached. DirectSense technology provides
optimal turn-on delay timing, regardless of input voltage,
output load, or component tolerances. The DirectSense
technique requires only a simple voltage divider sense
Rev C
For more information www.analog.com
13
LTC3722-1/LTC3722-2
OPERATION
network to implement. If there is not enough energy to
fully commutate the bridge leg to a ZVS condition, the
LTC3722-1/LTC3722-2 automatically overrides the DirectSense circuitry and forces a transition. The override
or default delay time is programmed with a resistor from
DPRG to VREF .
Adaptive Mode
The LTC3722-1/LTC3722-2 are configured for adaptive
delay sensing with three pins, ADLY, PDLY and SBUS.
ADLY and PDLY sense the active and passive delay legs
respectively via a voltage divider network, as shown in
Figure 2.
VIN
A
R2
SBUS
C
R5
PDLY
B
R1
R3
1k
ADLY
R6
D
R4
1k
RCS
372212 F02
delays exist between the time at which the LTC3722‑1/
LTC3722-2 controller output transitions, to the time at
which the power MOSFET switches on due to MOSFET
turn-on delay and external driver circuit delay. Ideally, we
want the power MOSFET to switch at the instant there
is zero volts across it. By setting a threshold voltage for
ADLY and PDLY corresponding to several volts across the
MOSFET, the LTC3722-1/LTC3722-2 can anticipate a zero
voltage VDS and signal the external driver and switch to
turn-on. The amount of anticipation can be tailored for
any application by modifying the upper divider resistor(s).
The LTC3722-1/LTC3722-2 DirectSense circuitry sources
a trimmed current out of PDLY and ADLY (proportional
to SBUS) after a low to high level transition occurs. This
provides hysteresis and noise immunity for the PDLY and
ADLY circuitry, and sets the high to low threshold on ADLY or
PDLY to nearly the same level as the low to high threshold,
thereby making the upper and lower MOSFET VDS switch
points virtually identical, independent of VIN.
Example: VIN = 48V nominal (36V to 72V)
1. Set up SBUS: 1.5V is desired on SBUS with VIN = 48V.
Set divider current to 100µA.
R1 =
Figure 2. Adaptive Mode
The threshold voltage on PDLY and ADLY for both the rising and falling transitions is set by the voltage on SBUS.
A buffered version of this voltage is used as the threshold
level for the internal DirectSense circuitry. At nominal VIN,
the voltage on SBUS is set to 1.5V by an external voltage
divider between VIN and GND, making this voltage directly
proportional to VIN. The LTC3722-1/LTC3722-2 DirectSense
circuitry uses this characteristic to zero voltage switch
all of the external power MOSFETs, independent of input
voltage.
ADLY and PDLY are connected through voltage dividers to
the active and passive bridge legs respectively. The lower
resistor in the divider is set to 1k. The upper resistor in
the divider is selected for the desired positive transition
trip threshold.
R2 =
1.5V
100µA
= 15k
48V − 1.5V
100µA
= 465k
An optional small capacitor (0.001µF) can be added
across R1 to decouple noise from this input.
2. Set up ADLY and PDLY: 7V of anticipation is desired
in this circuit to account for the delays of the external
MOSFET driver and gate drive components.
R3, R4 = 1k, sets a nominal 1.5mA in the divider chain
at the threshold.
R5, R6 =
(48V − 7V − 1.5V)
1.5m A
= 26.3k,
use (2) equal 13k segments.
To set up the ADLY and PDLY resistors, first determine at
what drain to source voltage to turn-on the MOSFETs. Finite
Rev C
14
For more information www.analog.com
LTC3722-1/LTC3722-2
OPERATION
Fixed Delay Mode
Powering the LTC3722-1/LTC3722-2
The LTC3722-1/LTC3722-2 provides the flexibility through
the SBUS pin to disable the DirectSense delay circuitry
and enable fixed ZVS delays. The level of fixed ZVS delay
is proportional to the voltage programmed through the
voltage divider on the PDLY and ADLY pins (see Figure 3
for more detail).
The LTC3722-1/LTC3722-2 utilize an integrated VCC shunt
regulator to serve the dual purposes of limiting the voltage applied to VCC as well as signaling that the chip’s bias
voltage is sufficient to begin switching operation (undervoltage lockout). With its typical 10.2V turn-on voltage
and 4.2V UVLO hysteresis, the LTC3722-1/LTC3722-2
is tolerant of loosely regulated input sources such as an
auxiliary transformer winding. The VCC shunt is capable
of sinking up to 25mA of externally applied current. The
UVLO turn-on and turn-off thresholds are derived from
an internally trimmed reference making them extremely
accurate. In addition, the LTC3722-1/LTC3722-2 exhibits
very low (145µA typ) start-up current that allows the use
of 1/8W to 1/4W trickle charge start-up resistors.
VREF
R1
SBUS
PDLY
R2
ADLY
R3
372212 F03
The trickle charge resistor should be selected as follows:
Figure 3. Setup for Fixed ZVS Delays
Programming Adaptive Delay Time-Out
The LTC3722-1/LTC3722-2 controllers include a feature to
program the maximum time delay before a bridge switch
turn on command is summoned. This function will come
into play if there is not enough energy to commutate a
bridge leg to the opposite supply rail, therefore bypassing
the adaptive delay circuitry. The time delay can be set with
an external resistor connected between DPRG and VREF
(see Figure 4). The nominal regulated voltage on DPRG is
2V. The external resistor programs a current which flows
into DPRG. The delay can be adjusted from approximately
35ns to 300ns, depending on the resistor value. If DPRG
is left open, the delay time is approximately 400ns. The
amount of delay can also be modulated based on an external
current source that feeds current into DPRG. Care must be
taken to limit the current fed into DPRG to 350µA or less.
10.7V
250µA
Adding a small safety margin and choosing standard
values yields:
APPLICATION
VIN RANGE
RSTART
DC/DC
36V TO 72V
100k
Off-Line
85V to 270VRMS
430k
390VDC
1.4M
PFC Preregulator
VCC should be bypassed with a 0.1µF to 1µF multilayer
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the VCC supply before
the bootstrap winding, or an auxiliary regulator circuit
takes over.
t
C HOLDUP = (ICC + IDRIVE ) • DELAY
3.8V
(m inim um U VLO hysteresis)
VREF
RDPRG
R START(MAX) = VIN(MIN) −
DPRG
+
+
V 2V
–
SBUS
–
TURN-ON
OUTPUT
372212 F04
Figure 4. Delay Timeout Circuitry
Rev C
For more information www.analog.com
15
LTC3722-1/LTC3722-2
OPERATION
Regulated bias supplies as low as 7V can be utilized to
provide bias to the LTC3722-1/LTC3722-2. Figure 5 shows
various bias supply configurations.
VBIAS < VUVLO
12V ±10%
1.5k
1N5226
3V
VIN
1N914
RSTART
0.1µF
0.1µF
+
VCC
VCC
CHOLD
to UVLO is present and greater than 5V prior to the VCC
UVLO circuitry activation, then the internal UVLO logic
will prevent output switching until the following three
conditions are met: (1) VCC UVLO is enabled, (2) VREF is
in regulation and (3) UVLO pin is greater than 5V.
UVLO can also be used to enable and disable the power
converter. An open drain transistor connected to UVLO,
as shown in Figure 6, provides this capability.
372212 F05
Off-Line Bias Supply Generation
Figure 5. Bias Configurations
Care must be taken to control the rise rate at VCC during
start-up to less than 0.1V/µs. This will ensure the internal
band-gap circuit is in regulation before certain IC functions are enabled.
Programming Undervoltage Lockout
The LTC3722-1/LTC3722-2 provides undervoltage lockout
(UVLO) control for the input DC voltage feed to the power
converter in addition to the VCC UVLO function described
in the preceding section. Input DC feed UVLO is provided
with the UVLO pin. A comparator on UVLO compares a
divided down input DC feed voltage to the 5V precision
reference. When the 5V level is exceeded on UVLO, the
SS pin is released and output switching commences. At
the same time a 10µA current is enabled which flows out
of UVLO into the voltage divider connected to UVLO. The
amount of DC feed hysteresis provided by this current is:
10µA • RTOP , see Figure 6. The system UVLO threshold is:
5V • [(RTOP + RBOTTOM)/RBOTTOM]. If the voltage applied
If a regulated bias supply is not available to provide VCC
voltage to the LTC3722-1/LTC3722-2 and supporting
circuitry, one must be generated. Since the power requirement is small, approximately 1W, and the regulation is not
critical, a simple open-loop method is usually the easiest
and lowest cost approach. One method that works well
is to add a winding to the main power transformer, and
post regulate the resultant square wave with an L-C filter
(see Figure 7a). The advantage of this approach is that it
maintains decent regulation as the supply voltage varies,
and it does not require full safety isolation from the input
winding of the transformer. Some manufacturers include a
primary winding for this purpose in their standard product
offerings as well. A different approach is to add a winding
to the output inductor and peak detect and filter the square
wave signal (see Figure 7b). The polarity of this winding
VIN
VCC
RSTART
15V*
+
2k
0.1µF
CHOLD
372212 F07a
*OPTIONAL
Figure 7a. Auxiliary Winding Bias Supply
RTOP
UVLO
ON OFF
RBOTTOM
VIN
LOUT
RSTART
ISO BARRIER
VOUT
+
372212 F06
Figure 6. System UVLO Setup
0.1µF
VCC
CHOLD
372212 F07b
Figure 7b. Output Inductor Bias Supply
Rev C
16
For more information www.analog.com
LTC3722-1/LTC3722-2
OPERATION
is designed so that the positive voltage square wave is
produced while the output inductor is freewheeling. An
advantage of this technique over the previous is that it
does not require a separate filter inductor and since the
voltage is derived from the well regulated output voltage, it
is also well controlled. One disadvantage is that this winding will require the same safety isolation that is required
for the main transformer. Another disadvantage is that a
much larger VCC filter capacitor is needed, since it does
not generate a voltage as the output is first starting up,
or during short-circuit conditions.
Programming the LTC3722-1/LTC3722-2 Oscillator
The high accuracy LTC3722-1/LTC3722-2 oscillator circuit
provides flexibility to program the switching frequency,
slope compensation, and synchronization with minimal
external components. The LTC3722-1/LTC3722-2 oscillator
circuitry produces a 2.5V peak-to-peak amplitude ramp
waveform on CT and a narrow pulse on SYNC that can be
used to synchronize other PWM chips. Typical maximum
duty cycles of 98.5% are obtained at 300kHz and 96% at
1MHz. A compensating slope current is derived from the
oscillator ramp waveform and sourced out of CS.
The desired amount of slope compensation is selected with
single external resistor. A capacitor to GND on CT programs
the switching frequency. The CT ramp discharge current is
internally set to a high value (>10mA). The dedicated SYNC
I/O pin easily achieves synchronization. The LTC3722-1/
CT OF SLAVE(S) IS
1.25 CT OF MASTER.
CT
CT
LTC3722
1k
LTC3722
1k
•
•
5.1k
•
UP TO
5 SLAVES
SYNC
Design Procedure:
1. Choose CT for the desired oscillator frequency. The
switching frequency selected must be consistent with
the power magnetics and output power level. In general,
increasing the switching frequency will decrease the
maximum achievable output power, due to limitations
of maximum duty cycle imposed by transformer core
reset and ZVS. Remember that the tranformer frequency is one-half that of the oscillator.
CT =
1
(13.4 k • fOSC )
Example: Desired fOSC = 330kHz
CT = 1/(13.4k • fOSC) = 226pF, choose closest standard
value of 220pF. A 5% or better tolerance multilayer NPO
or X7R ceramic capacitor is recommended for best
performance.
2. The LTC3722-1/LTC3722-2 can either synchronize other
PWMs, or be synchronized to an external frequency
source or PWM chip (see Figure 8 for details).
SYNC PULSE AMPLITUDE > 2.7V
SYNC PULSE WIDTH LIMITS:
75ns < PW < (1250 • CT)ns
75ns < PW < 275ns FOR CT = 220pF
CT
CT
5.1k
SYNC
5.1k
MASTER
SYNC
LTC3722-2 can be set up to either synchronize other PWM
chips or be synchronized by another chip or external clock
source. The 1.9V SYNC threshold allows the LTC3722-1/
LTC3722-2 to be synchronized directly from all standard
3V and 5V logic families.
LTC3722
EXTERNAL
FREQUENCY
SOURCE
CT
CT
SLAVES
1k
SYNC
LTC3722
CT
CT
5.1k
372212 F08b
372212 F08a
Figure 8a. SYNC Output (Master Mode)
Figure 8b. SYNC Input from an External Source
Rev C
For more information www.analog.com
17
LTC3722-1/LTC3722-2
OPERATION
3. Slope compensation is required for most peak current
mode controllers in order to prevent subharmonic
oscillation of the current control loop. In general, if the
system duty cycle exceeds 50% in a fixed frequency,
continuous current mode converter, an unstable condition exists within the current control loop. Any
perturbation in the current signal is amplified by the
PWM modulator resulting in an unstable condition.
Some common manifestations of this include alternate
pulse nonuniformity and pulse width jitter. Fortunately,
this can be addressed by adding a corrective slope to
the current sense signal or by subtracting the same
slope from the current command signal (error amplifier output). In theory, the current doubler output
configuration does not require slope compensation
since the output inductor duty cycles only approach
50%. However, transient conditions can momentarily
cause higher duty cycles and therefore, the possibility
for unstable operation.
The exact amount of required slope compensation is
easily programmed by the LTC3722-1/LTC3722-2 with
the addition of a single external resistor (see Figure 9).
The LTC3722-1/LTC3722-2 generates a current that
is proportional to the instantaneous voltage on CT,
(33µA/V(CT)). Thus, at the peak of CT, this current is
approximately 74µA and is output from the CS pin. A
resistor connected between CS and the external current
sense resistor sums in the required amount of slope
compensation. The value of this resistor is dependent on
several factors including minimum VIN, VOUT , switching frequency, current sense resistor value and output
inductor value. An illustrative example with the design
equation for current doubler secondary follows.
Transformer turns ratio (N) =
VIN(MIN) •
D C MAX
(2 • VOUT )
= 5
RCS = 0.05Ω
fSW = 300kH z, i .e., transformer f =
fSW
2
= 150 kH z
R SLOPE = VO •
= 3.3V •
R CS
(2 • L • fSW • 74µA • N)
0.05
2 • 2.2µH • 300k • 74µA • 5
RSLOPE = 338Ω, choose the next higher standard value
to account for tolerances in ISLOPE, RCS, N and L.
LTC3722
I=
CT
33k
V(CT)
33k
CS
RSLOPE
ADDED
SLOPE
CURRENT SENSE
WAVEFORM
BRIDGE
CURRENT
RCS
372212 F09
Figure 9. Slope Compensation Circuitry
Example:
VIN = 36V to 72V
VOUT = 3.3V
IOUT = 40A
L = 2.2µH
Rev C
18
For more information www.analog.com
LTC3722-1/LTC3722-2
OPERATION
Current Sensing and Overcurrent Protection
ever, with high input voltage, very low RDS(ON) MOSFETs
and a shorted output, or with saturating magnetics, the
overcurrent comparator provides a means of protecting
the power converter.
Current sensing provides feedback for the current mode
control loop and protection from overload conditions. The
LTC3722-1/LTC3722-2 are compatible with either resistive sensing or current transformer methods. Internally
connected to the LTC3722-1/LTC3722-2 CS pin are two
comparators that provide pulse-by-pulse and overcurrent
shutdown functions respectively (see Figure 10).
Leading Edge Blanking
The LTC3722-1/LTC3722-2 provides programmable leading
edge blanking to prevent nuisance tripping of the current
sense circuitry. Leading edge blanking relieves the filtering requirements for the CS pin, greatly improving the
response to real overcurrent conditions. It also allows
the use of a ground referenced current sense resistor
or transformer(s), further simplifying the design. With a
single 10k to 100k resistor from RLEB to GND, blanking
times of approximately 40ns to 320ns are programmed. If
not required, connecting RLEB to VREF can disable leading
edge blanking. Keep in mind that the use of leading edge
blanking will set a minimum linear control range for the
phase modulation circuitry.
The pulse-by-pulse comparator has a 300mV nominal
threshold. If the 300mV threshold is exceeded, the PWM
cycle is terminated. The overcurrent comparator is set
approximately 2x higher than the pulse-by-pulse level.
If the current signal exceeds this level, the PWM cycle is
terminated, the soft-start capacitor is quickly discharged
and a soft-start cycle is initiated. If the overcurrent condition
persists, the LTC3722-1/LTC3722-2 halts PWM operation
and waits for the soft-start capacitor to charge up to approximately 4V before a retry is allowed. The soft-start
capacitor is charged by an internal 12µA current source.
If the fault condition has not cleared when soft-start
reaches 4V, the soft-start pin is again discharged and a
new cycle is initiated. This is referred to as hiccup mode
operation. In normal operation and under most abnormal
conditions, the pulse-by-pulse comparator is fast enough
to prevent hiccup mode operation. In severe cases, how-
Q
PWM
LOGIC
Q
S Q
S
–
R
UVLO
ENABLE
R
+
S Q
–
4.1V
–
OVERLOAD
CURRENT LIMIT
+
12µA
SS
0.4V
CSS
–
650mV
H = SHUTDOWN
OUTPUTS
UVLO
ENABLE
+
RCS
300mV
A resistor connected between input common and the
sources of MB and MD is the simplest method of current
sensing for the full bridge converter. This is the preferred
method for low to moderate power levels. The sense
resistor should be chosen such that the maximum rated
PWM
LATCH
PULSE BY PULSE
CURRENT LIMIT
φMOD
BLANK
+
CS
Resistive Sensing
Q
372212 F10
Figure 10. Current Sense/Fault Circuitry Detail
Rev C
For more information www.analog.com
19
LTC3722-1/LTC3722-2
OPERATION
N
w here : N = Transform er turns ratio = P
NS
The advantage of the high side location is a greater immunity to leading edge noise spikes, since gate charge
current and reflected rectifier recovery current are largely
eliminated. Figure 11 illustrates a typical current sense
transformer based sensing scheme. RS in this case is
calculated the same as in the resistive case, only its value
is increased by the sense transformer turns ratio. At high
duty cycles, it may become difficult or impossible to reset the current transformer. This is because the required
transformer reset voltage increases as the available time
for reset decreases to equalize the (volt • seconds) applied.
The interwinding capacitance and secondary inductance of
the current sense transformer form a resonant circuit that
limits the dV/dT on the secondary of the CS transformer.
This, in turn, limits the maximum achievable duty cycle for
the CS transformer. Attempts to operate beyond this limit
will cause the transformer core to “walk” and eventually
saturate, opening up the current feedback loop.
LTC3722-2:
Common methods to address this limitation include:
output current for the converter can be delivered at the
lowest expected VIN. Use the following formula to calculate
the optimal value for RCS. IP equation valid for current
doubler secondary.
LTC3722-1:
R CS =
300m V – (82.5µA • R SLOPE )
IP (PEAK)
IP (PEAK) =
IO(MAX)
2 • N • EFF
+
VIN(MAX) • D MIN
L MAG • f CLK • 2
+
VO (1– D MIN )
L OUT • f CLK • N
R CS =
1. Reducing the maximum duty cycle by lowering the
power transformer turns ratio.
300m V
IP (PEAK)
2. Reducing the switching frequency of the converter.
Current Transformer Sensing
3. Employ external active reset circuitry.
A current sense transformer can be used in lieu of resistive
sensing with the LTC3722-1/LTC3722-2. Current sense
transformers are available in many styles from several
manufacturers. A typical sense transformer for this application will use a 1:50 turns ratio (N), so that the sense
resistor value is N times larger, and the secondary current
N times smaller than in the resistive sense case. Therefore,
the sense resistor power loss is about N times less with
the transformer method, neglecting the transformers core
and copper losses. The disadvantages of this approach
include, higher cost and complexity, lower accuracy,
core reset/maximum duty cycle limitations and lower
speed. Nevertheless, for very high power applications,
this method is preferred. The sense transformer primary
is placed in the same location as the ground referenced
sense resistor, or between the upper MOSFET drains in
the (MA, MC) and VIN.
4. Using two CS transformers summed together.
5. Choose a CS transformer optimized for high frequency
applications.
MD
SOURCE
MB
SOURCE
RSLOPE
RAMP
N:1
RS
CURRENT
TRANSFORMER
CS
OPTIONAL
FILTERING
372212 F11
Figure 11. Current Transformer Sense Circuitry
Rev C
20
For more information www.analog.com
LTC3722-1/LTC3722-2
OPERATION
Phase Modulator (LTC3722-1)
The LTC3722-1 phase modulation control circuitry is
comprised of the phase modulation comparator and logic,
the error amplifier, and the soft-start amplifier (see Figure
12). Together, these elements develop the required phase
overlap (duty cycle) required to keep the output voltage
in regulation. In isolated applications, the sensed output
voltage error signal is fed back to COMP across the input to
output isolation boundary by an optical coupler and shunt
reference/error amplifier (LT®1431) combination. The FB
pin is connected to GND, forcing COMP high. The collector of the optoisolator is connected to COMP directly. The
voltage COMP is internally attenuated by the LTC3722-1.
The attenuated COMP voltage provides one input to the
phase modulation comparator. This is the current command. The other input to the phase modulation comparator is the RAMP voltage, level shifted by approximately
650mV. This is the current loop feedback. During every
switching cycle, alternate diagonal switches (MA-MD or
MB-MC) conduct and cause current in an output inductor to increase. This current is seen on the primary of the
power transformer divided by the turns ratio. Since the
current sense resistor is connected between GND and the
two bottom bridge transistors, a voltage proportional to
the output inductor current will be seen across RSENSE.
The high side of RSENSE is also connected to CS, usually
through a small resistor (RSLOPE). When the voltage on
CS exceeds either (COMP/4.3) –650mV, or 300mV, the
overlap conduction period will terminate. During normal
operation, the attenuated COMP voltage will determine
the CS trip point. During start-up, or slewing conditions
following a large load step, the 300mV CS threshold will
terminate the cycle, as COMP will be driven high, such
that the attenuated version exceeds the 300mV threshold.
In extreme conditions, the 650mV threshold on CS will be
exceeded, invoking a soft-start/restart cycle.
Selecting the Power Stage Components
Perhaps the most critical part of the overall design of the
converter is selecting the power MOSFETs, transformer,
inductors and filter capacitors. Tremendous gains in efficiency, transient performance and overall operation can
be obtained as long as a few simple guidelines are followed
with the phase-shifted full bridge topology.
TOGGLE
F/F
FB
–
1.2V
ERROR
AMPLIFIER
PHASE
MODULATION
COMPARATOR
+
50k
COMP
VREF
SS
CLK
12µA SOFT-START
AMPLIFIER
+
–
IDEAL
+
–
Q
A
Q
B
–
PHASE
MODULATION
LOGIC
+
S Q
CLK
650mV
C
D
R
FROM
CURRENT
LIMIT
COMPARATOR
14.9k
RLEB
CS
BLANKING
Q S
R
CLK
372212 F12
Figure 12. Phase Modulation Circuitry (LTC3722-1)
Rev C
For more information www.analog.com
21
LTC3722-1/LTC3722-2
OPERATION
Power Transformer
where:
Switching frequency, core material characteristics, series
resistance and input/output voltages all play an important
role in transformer selection. Close attention also needs
to be paid to leakage and magnetizing inductances as
they play an important role in how well the converter will
achieve ZVS. Planar magnetics are very well suited to
these applications because of their excellent control of
these parameters.
D = minimum duty cycle
Turns Ratio
The required turns ratio for a current doubler secondary
is given below. Depending on the magnetics selected, this
value may need to be reduced slightly.
Turns ratio formula:
N=
VIN(MIN) • D MAX
where:
2 • VOUT
VIN(MIN) = Minimum VIN for operation
DMAX = Maximum duty cycle of controller (DCMAX)
Output Capacitors
Output capacitor selection has a dramatic impact on ripple
voltage, dynamic response to transients and stability.
Capacitor ESR along with output inductor ripple current
will determine the peak-to-peak voltage ripple on the output. The current doubler configuration is advantageous
because it has inherent ripple current reduction. The dual
output inductors deliver current to the output capacitor 180
degrees out-of-phase, in effect, partially canceling each
other’s ripple current. This reduction is maximized at high
duty cycle and decreases as the duty cycle reduces. This
means that a current doubler converter requires less output
capacitance for the same performance as a conventional
converter. By determining the minimum duty cycle for the
converter, worse-case VOUT ripple can be derived by the
following formula:
VORIPPLE = IRIPPLE • ESR =
VO • ESR
L O • 2 • f SW
(1– D)(1– 2D)
fSW = oscillator frequency
LO = output inductance
ESR = output capacitor series resistance
The amount of bulk capacitance required is usually system
dependent, but has some relationship to output inductance
value, switching frequency, load power and dynamic load
characteristics. Polymer electrolytic capacitors are the
preferred choice for their combination of low ESR, small
size and high reliability. For less demanding applications,
or those not constrained by size, aluminum electrolytic
capacitors are commonly applied. Most DC/DC converters in the 100kHz to 300kHz range use 20µF to 25µF of
bulk capacitance per watt of output power. Converters
switching at higher frequencies can usually use less bulk
capacitance. In systems where dynamic response is critical,
additional high frequency capacitors, such as ceramics,
can substantially reduce voltage transients.
Power MOSFETs
The full bridge power MOSFETs should be selected for
their RDS(ON) and BVDSS ratings. Select the lowest BVDSS
rated MOSFET available for a given input voltage range
leaving at least a 20% voltage margin. Conduction losses
are directly proportional to RDS(ON). Since the full bridge
has two MOSFETs in the power path most of the time,
conduction losses are approximately equal to:
2 • R DS(ON) • I 2 , w here I =
IO
2N
Switching losses in the MOSFETs are dominated by the
power required to charge their gates, and turn-on and
turn-off losses. At higher power levels, gate charge power
is seldom a significant contributor to efficiency loss. ZVS
operation virtually eliminates turn-on losses. Turn-off
losses are reduced by the use of an external drain to source
snubber capacitor and/or a very low resistance turn-off
driver. If synchronous rectifier MOSFETs are used on the
secondary, the same general guidelines apply. Keep in
mind, however, that the BVDSS rating needed for these can
be greater than VIN(MAX)/N, depending on how well the
Rev C
22
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LTC3722-1/LTC3722-2
OPERATION
secondary is snubbed. Without snubbing, the secondary
voltage can ring to levels far beyond what is expected due
to the resonant tank circuit formed between the secondary
leakage inductance and the COSS (output capacitance) of
the synchronous rectifier MOSFETs.
Switching Frequency Selection
Unless constrained by other system requirements, the
power converter’s switching frequency is usually set as
high as possible while staying within the desired efficiency
target. The benefits of higher switching frequencies are
many including smaller size, weight and reduced bulk
capacitance. In the full bridge phase-shift converter, these
principles are generally the same with the added complication of maintaining zero voltage transitions, and therefore,
higher efficiency. ZVS is achieved in a finite time during
the switching cycle. During the ZVS time, power is not
delivered to the output; the act of ZVS reduces the maximum available duty cycle. This reduction is proportional
to maximum output power since the parasitic capacitive
element (MOSFETs) that increase ZVS time get larger as
power levels increase. This implies an inverse relationship
between output power level and switching frequency.
Table 1 displays recommended maximum switching
frequency vs power level for a 30V/75V in to 3.3V/5V out
converter. Higher switching frequencies can be used if the
input voltage range is limited, the output voltage is lower
and/or lower efficiency can be tolerated.
Table 1. Switching Frequency vs Power Level
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