LTC3726
Secondary-Side Synchronous
Forward Controller
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DESCRIPTIO
FEATURES
Secondary-Side Control for Fast Transient Response
Self-Starting Architecture Eliminates Need for
Separate Bias Regulator
Proprietary Gate Drive Encoding Scheme Reduces
System Complexity
Current Mode Control Ensures Current Sharing
PLL Fixed Frequency: 100kHz to 500kHz
±1% Output Voltage Accuracy
OPTI-LOOP Compensation
Available in a Narrow 16-Lead SSOP Package
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APPLICATIO S
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Isolated 48V Telecommunication Systems
Internet Servers and Routers
Distributed Power Step-Down Converters
Automotive and Heavy Equipment
The LTC®3726 is a secondary-side controller for synchronous forward converters. When used in conjunction with
the LTC3705/LTC3725 gate driver and primary-side controllers, the part creates a complete isolated power supply
that combines the simplicity of OPTI-LOOP® compensation with the speed of secondary-side control.
The LTC3726 has been designed to simplify the design of
highly efficient, secondary-side forward converters. Working in concert with the LTC3705 or LTC 3725, the LTC3726
forms a robust, self-starting converter that eliminates the
need for the separate bias regulator that is commonly used
in secondary-side control applications. In addition, a proprietary scheme is used to multiplex gate drive signals and
DC bias power across the isolation barrier through a
single, tiny pulse transformer.
The LTC3726 is available in a 16-lead SSOP package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6144194. Other patents pending.
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TYPICAL APPLICATIO
36V-72V to 3.3V/20A Isolated Forward Converter
VIN+
T1
•
Si7852DP
•
1.2Ω
VOUT+
L1
1.2µH
MURS120
CMPSH1-4
1µF
100V
x3
5k
Si7852DP
Si7336ADP
Si7336ADP
×2
330µF
6.3V
×3
FZT690B
MURS120
2mΩ
2W
30mΩ
1W
VIN–
BOOST TG
VCC
FB/IN
+
T2
•
IS –
FG
SW SG
VOUT–
PT +
•
VCC
FS/SYNC
IS +
FB/PHASE
LTC3726
ITH
LTC3705
SS/FLT
680pF
PT –
FS/IN–
GND PGND VSLMT
33nF
1µF
TS BG IS
UVLO
15k
1%
2.2µF
102k
1%
L1: COILCRAFT SER2010-122
T1: PULSE PA0807
T2: PULSE PA0297
BAS21 0.22µF
NDRV
2.2µF
25V
7.5V
100k
FQT7N10
365k
1%
10µF
25V
162k
RUN/SS GND
33nF
PGND
SLP
MODE
20k
22.6k
1%
3726 TA01
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LTC3726
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
VCC ........................................................... – 0.3V to 10V
SW ............................................................... –5V to 50V
ITH, RUN/SS ............................................... – 0.3V to 7V
All Other Pins ............................................ – 0.3V to 10V
Operating Ambient Temperature Range (Note 2)
LTC3726EGN ...................................... – 40°C to 85°C
LTC3726IGN ....................................... – 40°C to 85°C
Operating Junction Temperature (Note 3) ........... 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TOP VIEW
SG
1
16 VCC
FG
2
15 PT+
MODE
3
14 PT–
FB/PHASE
4
13 PGND
ITH
5
12 SW
RUN/SS
6
11 IS+
SLP
7
10 IS–
GND
8
9
FS/SYNC
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/W
ORDER PART NUMBER
LTC3726EGN
LTC3726IGN
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 7V, GND = PGND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.594
0.600
0.606
V
Main Control Loop
VFB
Regulated Feedback Voltage
(Note 4) ITH = 1.2V
∆VFB(LINREG)
Feedback Voltage Line Regulation
VCC = 5V to 10V, ITH = 1.2V
∆VFB(LOADREG)
Feedback Voltage Load Regulation
Measured in Servo Loop,
ITH = 0.5V to 2V
VISMAX
Maximum Current Sense Threshold
RSENSE Mode, VIS = 0V
CT Mode, VIS = 0V
VISOC
Over-Current Shutdown Threshold
RSENSE Mode, VIS = 0V
CT Mode, VIS = 0V
gm
Transconductance Amplifier gm
IRUN/SS(C)
Soft-Start Charge Current
IRUN/SS(D)
Soft-Start Discharge Current
VRUN/SS
RUN/SS Pin ON Threshold
tON,MIN
Minimum ON Time
FG, SG RUP
FG, SG Driver Pull-Up On Resistance
FG, SG RDOWN
FG, SG Driver Pull-Down On Resistance
PT+, PT– RUP
PT+, PT– Driver Pull-Up Resistance
PR+, PT– RDOWN PT+, PT– Driver Pull-Down Resistance
PT+, PT– High
∆VFB(OV)
VFB Rising
Output Overvoltage Threshold
●
0.001
●
VRUN/SS = 2V
%/V
–0.01
–0.1
%
68
1.15
78
1.28
88
1.4
mV
V
87
1.45
100
1.65
113
1.85
mV
V
2.40
2.75
3.10
mS
–4
–5
–6
µA
µA
3
VRUN/SS Rising
●
0.4
0.45
0.5
200
FG, SG Low
V
ns
Ω
1.5
2.3
FG, SG High
1.5
2.3
Ω
PT+, PT– Low
1.5
2.3
Ω
1.5
2.3
Ω
17
19
%
15
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LTC3726
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 7V, GND = PGND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC Supply
VCCOP
Operating Voltage Range
ICC
Supply Current
Operating
Shutdown
5
fOSC = 200kHz (Note 5)
VRUN/SS = GND
VUVLO
UV Lockout
VCC Rising
VHYS
UV Hysteresis
10
4.2
700
●
4.52
4.60
V
mA
µA
4.70
V
0.4
V
20
µA
Oscillator and Phase-Locked Loop
IFS
FS/SYNC Pin Sourcing Current
fLOW
Oscillator Low Frequency Set Point
VFS/SYNC = GND
170
200
230
kHz
300
345
kHz
20
%
fHIGH
Oscillator High Frequency Set Point
VFS/SYNC = VCC
255
∆f (RFS)
Oscillator Resistor Set Accuracy
75kΩ < RFS/SYNC < 175kΩ
–20
fPLL(MAX)
Maximum PLL Sync Frequency
500
kHz
fPLL(MIN)
Minimum PLL Sync Frequency
75
kHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3726E is guaranteed to meet the performance
specifications from 0°C to 85°C junction temperature. Specifications over
the –40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3726I is guaranteed and tested over the full – 40°C to 85°C operating
temperature range.
Note 3: Operating junction temperature TJ (in °C) is calculated from the
ambient temperature TA and the average power dissipation PD (in Watts)
by the formula:
TJ = TA + θJA • PD
Refer to the Applications Information section for details.
Note 4: The LTC3726 is tested in a feedback loop that servos VFB to a
voltage near the internal 0.6V reference voltage to obtain the specified ITH
voltage (VITH = 1.2V).
Note 5: Operating supply current is measured in test mode. Dynamic
supply current is higher due to the internal gate charge being delivered at
the switching frequency. See Typical Performance Characteristics.
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LTC3726
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TYPICAL PERFOR A CE CHARACTERISTICS
VCC Supply Current vs
Input Voltage
Maximum Current Sense
Threshold vs ITH Voltage
Maximum Current Sense
Threshold vs Duty Cycle
100
fOSC = 200kHz
ALL GATES: CLOAD = 0
100
RSLP = 0
80
5
4
80
100kΩ
60
RSLP = 50k
40
20
7
8
INPUT VOLTAGE (V)
10
9
40
260
200
100
CT-MODE: IIS+
0
–100
–200
–400
1
5
2
3
4
IS+, IS– COMMON-MODE VOLTAGE (V)
101.5
RS-MODE: (IIS+ + IIS–)
VIS+ = VIS– = 0V
101.0
255
250
245
100.5
100.0
240
99.5
6
230
–50
–25
0
25
50
75
TEMPERATURE (°C)
3726 G05
100
99.0
–50
125
PERCENT CHANGE IN FREQUENCY (%)
470
450
440
430
100
125
3726 G08
0
25
50
75
TEMPERATURE (°C)
100
Oscillator Frequency vs RFS
5
600
4
500
3
2
R = 175KΩ
fOSC = 500kHz
1
0
–1
–2
–50
125
3726 G07
Oscillator Frequency
vs Temperature
460
–25
3726 G06
RUN/SS ON Threshold
vs Temperature
25
50
75
TEMPERATURE (°C)
3.0
2.5
235
RS-MODE: (IIS+ + IIS–)
0
1.5
2.0
ITH VOLTAGE (V)
Maximum Current Sense
Threshold vs Temperature
VIS/VIS,MAX (%)
IS PIN SOURCE CURRENT (µA)
IS PIN SOURCE CURRENT (µA)
300
–25
1.0
3726 G04
IS Pins Source Current
vs Temperature
265
420
–50
0.5
3726 G03
400
0
0
DUTY CYCLE (%)
IS Pins Source Current
–1
80
60
3726 G01
–300
40
0
20
0
FREQUENCY (kHz)
6
5
60
20
0
3
VRUN/SS (mV)
VIS/VIS,MAX (%)
6
VIS/VIS,MAX (%)
SUPPLY CURRENT (mA)
7
TA = 25°C, unless otherwise noted.
400
300
200
100
R = 75KΩ
fOSC = 100kHz
–25
0
25
50
75
TEMPERATURE (°C)
0
100
125
3726 G14
50
75
100
125
150
RFS (kΩ)
175
200
3726 G09
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LTC3726
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TYPICAL PERFOR A CE CHARACTERISTICS
FB Voltage vs Temperature
601.0
4.65
UVLO THRESHOLD VOLTAGE (V)
601.0
600.5
VFB (mV)
600.5
600.0
599.5
600.0
599.5
4.60
4.55
VCC RISING
4.50
4.45
4.40
4.35
4.30
599.0
0
25
50
75
TEMPERATURE (°C)
100
125
5
0
10
30
15
20
25
VIN SUPPLY VOLTAGE (V)
3726 G15
4.25
–50
–25
0
25
50
75
TEMPERATURE (°C)
3726 G11
100
125
3726 G16
Gate Driver On-Resistance
vs Temperature
Gate Driver On-Resistance vs VCC
1.8
2.50
1.7
2.25
1.6
2.00
RDS,ON (Ω)
–25
RDS,ON (Ω)
599.0
–50
1.5
PULL-DOWN
1.4
VCC = 7V
1.75
1.50
PULL-UP
1.3
1.25
1.2
5
6
7
8
VCC VOLTAGE (V)
9
10
1.00
–50
–25
0
25
50
75
TEMPERATURE (°C)
3726 G12
100
125
3726 G13
Efficiency (Figure 5)
Load Step (Figure 5)
95
VIN = 36V
VOUT
100mV/DIV
EFFICIENCY (%)
VFB (mV)
Undervoltage Lockout
vs Temperature
FB Voltage Line Regulation
90
VIN = 72V
IOUT
10A/DIV
85
20µs/DIV
VIN = 48V
VOUT = 3.3V
LOAD STEP = 0A TO 20A
80
0
5
10
15
LOAD CURRENT (A)
20
3726 G18
25
3726 G17
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LTC3726
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PI FU CTIO S
SG (Pin 1): Gate Drive for the “Synchronous” MOSFET.
FG (Pin 2): Gate Drive for the “Forward” MOSFET.
MODE (Pin 3): Tie to either GND or VCC to set the
maximum duty cycle at either 50% or 75% respectively.
Tie to ground through either a 200k or 100k resistor (50%
or 75% maximum duty cycle) to disable pulse encoding.
In this mode, normal PWM signals will be generated at the
PT+ pin, while a clock signal is generated at the PT– pin.
FB/PHASE (Pin 4): Inverting input of the main loop Error
Amplifier and Control Input to the Phase Selector. In
PolyPhase® Slave applications (where voltage feedback is
not needed) this pin is used to determine the phasing of the
controller CLK relative to the synchronizing signal at the
FS/SYNC pin.
ITH (Pin 5): The Output of the Main Loop Error Amplifier.
Place compensation components between the ITH pin
and GND.
RUN/SS (Pin 6): Combination Run Control and Soft-Start
Inputs. A capacitor to ground sets the ramp time of the
output voltage. Holding this pin below 0.4V causes the IC
to shut down all internal circuitry.
SLP (Pin 7): Slope Compensation Input. Place a single
resistor to ground to set the desired amount of slope
compensation.
GND (Pin 8): Signal Ground.
PolyPhase is a registered trademark of Linear Technology Corporation.
FS/SYNC (Pin 9): Combination Frequency Set and SYNC
pin. Tie to GND or VCC to run at 200kHz and 300kHz
respec-tively. Place a single resistor to ground at this pin
to set the frequency between 75kHz and 500kHz. To
synchronize, drive this pin with a clock signal to achieve
PLL synchronization from 75kHz to 500kHz. Sources
20µA of current.
IS– (Pin 10): Negative Input to the Current Sense Circuit.
When using current sense transformers, this pin may be
tied to VCC for single-ended sensing with a 1.28V maximum current trip level.
IS+ (Pin 11): Positive Input to the Current Sense Circuit.
Connect to the positive end of a current sense resistor or
to the output of a current sense transformer.
SW (Pin 12): Connect to the drain of the “synchronous”
MOSFET. This input is used for adaptive shoot-through
prevention and leading edge blanking.
PGND (Pin 13): Gate Driver Ground Pin.
PT –, PT + (Pins 14, 15): Pulse Transformer Driver Outputs. For most applications, these connect to a pulse
transformer (with a series DC blocking capacitor). The
PWM information is multiplexed together with DC power
and sent through a single pulse transformer to the primary
side. This information may be decoded by the LTC3705
gate driver and primary-side controller.
VCC (Pin 16): Main VCC Input for all Driver and Control
Circuitry.
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LTC3726
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BLOCK DIAGRA
IS+
2×
11
+
IS–
VCC
+
32×
C
–
–
10
2V
FG
ITRP
2
RESET
DOMINANT
WAIT
OVP
PGND
R
13
VCC
SG
Q
S
+
+
0.25V
C
–
+
gm = 2.8mS
C
EA
2.5V
–
SLP
3.2V
7
–
MODE
3
VCC
PT +
PGND
VCC
•
•
PT –
14
PULSE
XFMR
DRIVE
TYPE
9
OSC
AND
PLL
12
15
DRIVER
ENCODING
AND
LOGIC
OVERCURRENT
SLOPE
COMP 1
–
OC
RUN/SS
FS/SYNC
0.2V
SW
ZERO
CROSSING
DETECT
BLANK
+
FB/PHASE
+
OVP
–
5
4
DMAX
SKIP
1
WAIT
C
ITH
0.60V
PWM
BLANK
DMAX
DRIVE/DMAX
CONTROL
VCC
19
UVLO
4VSB
RUN/SS
6
VCCUV
REG
4VSB
VREF
1.24V
3726 BD
FB
VCCUV
SOFTSTART
WAIT
OC
GND
8
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LTC3726
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OPERATIO
Main Control Loop
The LTC3726 is designed to work in a constant frequency,
current mode, one or two transistor forward converter.
During normal operation, the primary-side MOSFET(s)
is (are) “clocked” on with the forward MOSFET on the secondary side. This applies the reflected input voltage across
the inductor on the secondary side. When the current in
the inductor has ramped up to the peak value as commanded by the voltage on the ITH pin, the current sense
comparator is tripped, turning off the primary-side and
forward MOSFETs. To avoid turning on the synchronous
MOSFET prematurely and causing shoot-through, the
voltage on the SW pin is monitored. This voltage will
usually fall below 0V soon after the primary-side MOSFETs
have turned completely off. When this condition is detected, the synchronous MOSFET is quickly turned on,
causing the inductor current to ramp back downwards.
The error amplifier senses the output voltage, and adjusts
the ITH voltage to obtain the peak current needed to
maintain the desired main-loop output voltage. The
LTC3726 always operates in a continuous current, synchronous switching mode. This ensures a rapid transient
response as well as a stable bias supply voltage at light
loads. A maximum duty cycle (either 50% or 75%) is
internally set via clock dividers to prevent saturation of the
main transformer. In the event of an overvoltage on the
output, the synchronous MOSFET is quickly turned on to
help protect critical loads from damage.
For most forward converter applications, the PT+ and PT–
outputs will contain a pulse-encoded PWM signal. These
outputs are driven in a complementary fashion with an
essentially constant 50% duty cycle. This results in a
stable volt-second balance as well as an efficient transfer
of bias power across the pulse transformer. As shown in
Figure 1, the beginning of the positive half-cycle coincides
with the turn-on of the primary-side MOSFET(s). Likewise,
the beginning of the negative half-cycle coincides with
the maximum duty cycle (forced turn-off of primary
switch(es) ). At the appropriate time during the positive
half-cycle, the end of the “on” time (PWM going LOW) is
signaled by briefly applying a zero volt differential across
the pulse transformer. Figure 1 illustrates the operation of
this multiplexing scheme.
The LTC3705 primary-side controller and gate driver will
decode this PWM information as well as extract the power
needed for primary-side gate drive.
DUTY CYCLE = 0%
DUTY CYCLE = 15%
150ns
150ns
7V
7V
VPT1+ – VPT1–
–7V
–7V
1 CLK PER
3726 F01
1 CLK PER
Figure 1: Gate Drive Encoding Scheme (VMODE = GND)
Gate Drive Encoding
Self-Starting Architecture
Since the LTC3726 controller resides on the secondary
side of an isolation barrier, communication to the primaryside power MOSFETs is generally done through a transformer. Moreover, it is often necessary to generate a low
voltage bias supply for the primary-side gate drive circuitry. In order to reduce the number of isolated windings
present in the system, the LTC3726 uses a proprietary
scheme to encode the PWM gate drive information and
multiplex it together with bias power for the primary-side
drive and control, using a single pulse transformer. Note
that, unlike optoisolators and other modulation techniques, this multiplexing scheme does not introduce a
significant time delay into the system.
When the LTC3726 is used in conjunction with the LTC3705/
LTC3725 primary-side controller and gate driver, a complete self-starting isolated supply is formed. When input
voltage is first applied in such an application, the LTC3705/
LTC3725 will begin switching in an “open-loop” fashion,
causing the main output to slowly ramp upwards. This is
the primary-side soft-start mode. On the secondary side,
the LTC3726 derives its operating bias voltage from a
peak-charged capacitor. This peak-charged voltage will
rise more rapidly than the main output of the converter, so
that the LTC3726 will become operational well before the
output voltage has reached its final value.
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LTC3726
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OPERATIO
When the LTC3726 has adequate operating voltage, it will
begin the procedure of assuming control from the primary
side. To do this, it first measures the voltage on the power
supply’s main output and then automatically advances its
own soft-start voltage to correspond to the main output
voltage. This ensures that the output voltage increases
monotonically as the soft-start control is transferred from
primary to secondary. The LTC3726 then begins sending
PWM signals to the LTC3705/LTC3725 on the primary
side through a pulse transformer. When the LTC3705/
LTC3725 has detected a stable signal from the secondary
controller, it transfers control of the primary switches over
to the LTC3726, beginning the secondary-side soft-start
mode. The LTC3726 continues in this mode until the
output voltage has ramped up to its final value. If for any
reason, the LTC3726 either stops sending (or initially fails
to send) PWM information to the LTC3705/LTC3725, the
LTC3705/LTC3725 will detect a FAULT and initiate a softstart retry (see the LTC3705/LTC3725 data sheet).
the inductor (either high side or ground lead sensing), or
in the source of the “forward” switch. If a current sense
transformer is used, the IS– input should be tied to VCC and
the IS+ pin to the output of the current sense transformer.
This causes the gain of the internal current sense amplifier
to be reduced by a factor of 16, so that the maximum
current sense voltage (current limit) is increased from
78mV to 1.28V. An internal, adaptive leading edge blanking circuit ensures clean operation for “switch” current
sensing applications.
Slope Compensation
Frequency Setting and Synchronization
Slope compensation is added at the input of the PWM
comparator to improve stability and noise margin of the
peak current control loop. The amount of slope compensation can be selected from one of five preprogrammed
values using the SLP pin as shown in Table 1. Note that the
amount of slope compensation doubles when the duty
cycle exceeds 50%.
The LTC3726 uses a single pin to set the operating
frequency, or to synchronize the internal oscillator to a
reference clock with an on-chip phase-locked loop (PLL).
The FS pin may be tied to GND, VCC or have a single resistor
to GND to set the switching frequency. If a clock signal
(>2V) is detected at the FS pin, the LTC3726 will automatically synchronize to the rising edge of the reference clock.
Table 2 summarizes the operation of the FS pin.
Table 1
SLP PIN
Current limit is achieved in the LTC3726 by limiting the
maximum voltage excursion of the error signal (ITH voltage). Note that if slope compensation is used, the precise
value at which current limit occurs will be a function of
duty cycle (see Typical Performance Characteristics). If a
short circuit is applied, an independent overcurrent comparator may be tripped. In this case, the LTC3726 will enter
a “hiccup” mode using the soft-start circuitry.
For synchronization between multiple LTC3726s, the PT +
pin of one LTC3726 can be used as a master clock
reference and tied to the FS pin of the other LTC3726s.
SLOPE (D < 0.5)
SLOPE (D > 0.5)
GND
0.05 • ISMAX • fOSC
0.1 • ISMAX • fOSC
VCC
None
None
400kΩ to GND
0.1 • ISMAX • fOSC
0.2 • ISMAX • fOSC
Table 2
200kΩ to GND
0.15 • ISMAX • fOSC
0.3 • ISMAX • fOSC
FS PIN
SWITCHING FREQUENCY
100kΩ to GND
0.25 • ISMAX • fOSC
0.5 • ISMAX • fOSC
GND
200kHz
50kΩ to GND
0.5 • ISMAX • fOSC
1.0 • ISMAX • fOSC
VCC
300kHz
RFS to GND
fOSC (Hz) = 4RFS – 200k
Reference Clock
fOSC = fREF (75kHz to 500kHz)
In Table 1 above, ISMAX is the maximum current limit, and fOSC is the
switching frequency.
Current Sensing and Current Limit
For current sensing, the LTC3726 supports either a current sense resistor or a current sense transformer. The
current sense resistor may either be placed in series with
This will cause all LTC3726s to operate at the same
frequency and phase. The LTC3726 can also be used as a
“Slave” in a PolyPhase application. In this case, the phase
angle of each LTC3726 can be set by using the FB/PHASE
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LTC3726
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OPERATIO
pin (see Slave Mode Operation). The Phase angle cannot
be adjusted when the FB/PHASE pin is being used for
voltage loop regulation.
Soft-Start
The soft-start circuitry has four functions: 1) to provide a
shutdown, 2) to provide a smooth ramp on the output
voltage during start-up, 3) to limit the output current in a
short-circuit situation by entering a hiccup mode, and
4) to communicate fault and shutdown information
between multiple LTC3726s in a PolyPhase application.
When the RUN/SS pin is pulled to GND, the chip is placed
into shutdown mode. If this pin is released, the RUN/SS
pin is initially charged with a 50µA current source. After the
RUN/SS pin gets above 0.5V, the chip is enabled. At the
instant that the LTC3726 is first enabled, the RUN/SS
voltage is rapidly preset to a voltage that will correspond
to the main output voltage of the DC/DC converter. (See
the Self-Starting Architecture section.) After this preset
interval has completed, the normal soft-start interval
begins and the charging current is reduced to 5µA. The
external soft-start voltage is used to internally ramp up the
0.6V reference (positive) input to the error amplifier.
When fully charged, the RUN/SS voltage remains at 3V.
In the event that the sensed switch or inductor current
exceeds the overcurrent trip threshold, an internal fault
latch is tripped. When such a fault is detected, the LTC3726
immediately goes to zero duty cycle and initiates a softstart retry. Prior to discharging the soft-start capacitor,
however, the LTC3726 first puts a voltage pulse on the
RUN/SS pin, which trips the fault latch in any other
LTC3726 that shares the RUN/SS. This ensures an orderly
shutdown of all phases in a PolyPhase application. After
the soft-start capacitor is fully discharged, the LTC3726
attempts a restart. If the fault is persistent, the system
enters a “hiccup” mode.
Note that in self-starting secondary-side control applications (with the LTC3705 or LTC3725), the presence of the
LT3726 bias voltage is dependent upon the regular switching of the primary-side MOSFETs. Therefore, depending
on the details of the application circuit, the LTC3726 may
lose its bias voltage after a fault has been detected and
before completing a soft-start retry. In this case, the
“hiccup-mode” operation is actually governed by the
LTC3705/LTC3725 soft-start circuitry (see the LTC3705/
LTC3725 data sheets).
Drive Mode and Maximum Duty Cycle
Although the LTC3726 is primarily intended to be used
with the LTC3705/LTC3725 in forward converter applications, the MODE pin provides the flexibility to use the
LTC3726 in a wide variety of additional applications. This
pin can be used to defeat the gate drive encoding scheme,
as well as change the maximum duty cycle from its default
value of 50%. The use of the MODE pin is summarized in
Table 3.
When the gate drive encoding scheme is defeated, a
standard PWM-style signal will be present at the PT+ pin
and a reference clock (in phase with the PWM signal) will
be present at the PT– pin. These outputs can be used in
“standalone” applications (without the LTC3705/LTC3725)
to drive the gates of MOSFETs in a conventional manner.
Table 3
PT+/PT– Mode
(MAX DUTY CYCLE)
INTENDED
APPLICATION
GND
Encoded PWM
(DMAX = 50%)
2-Switch Forward
with LTC3705
VCC
Encoded PWM
(DMAX = 75%)
1-Switch Forward
with LTC3725
200kΩ to GND
Standard PWM
(DMAX = 50%)
2-Switch Forward
Standalone
100kΩ to GND
Standard PWM
(DMAX = 75%)
1-Switch Forward
Standalone
MODE PIN
Overvoltage Protection
This circuit monitors the voltage on the FB input. If the
voltage on the FB pin exceeds 117% of 0.6V (0.7V), an
overvoltage (OVP) is detected. For overvoltage protection,
the secondary-side synchronous MOSFET is turned on
while all other MOSFETs are turned off. This protection
mode is not latched, so that the overvoltage detection is
cleared if the FB voltage falls below 115% of 0.6V (0.69V).
3726fb
10
LTC3726
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OPERATIO
Slave Mode Operation
When two or more LTC3726 devices are used in PolyPhase
systems, one device becomes the “Master” controller,
while the others are used as “Slaves.” Slave mode is
activated when the FB/PHASE pin is greater than approximately 2V. In this mode, the ITH pin becomes a highimpedance input, allowing it to be driven by the Master
controller. In this way, equal inductor currents are established in each of the individual phases. Also, in slave
mode, the soft-start charge/discharge currents are disabled, allowing the Master device to control the charging
and discharging of the soft-start capacitor.
have a single resistor to VCC to activate Slave mode and set
the phase angle (delay) of the internal oscillator relative to
the incoming sync signal on the FS/SYNC pin. Any one of
six preset values can be selected as summarized in Table 4.
Table 4
FB/PHASE PIN
PHASE DELAY
OPERATING MODE
VFB/PHASE < 2V
0°
Master
VFB/PHASE = VCC
180°
Slave
200kΩ to VCC
60°
Slave
100kΩ to VCC
90°
Slave
50kΩ to VCC
120°
Slave
In slave mode, the phase angle of each LTC3726 can be set
by using the FB/PHASE pin. This pin can be tied to VCC, or
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APPLICATIO S I FOR ATIO
Start-Up Considerations
In self-starting applications, the LTC3705/LTC3725 will
initially begin the soft-start of the converter in an openloop fashion. After bias is obtained on the secondary side,
the LTC3726 assumes control and completes the softstart interval. In order to ensure that control is properly
transferred from the LTC3705/LTC3725 (primary-side) to
the LTC3726 (secondary-side), it is necessary to limit the
rate of rise on the primary-side soft-start ramp so that the
LTC3726 has adequate time to wake up and assume
control before the output voltage gets too high. This
condition is satisfied for many applications if the following
relationship is maintained:
CSS,SEC ≤ CSS PRI
However, care should be taken to ensure that soft-start
transfer from primary-side to secondary-side is completed well before the output voltage reaches its target
value. A good design goal is to have the transfer completed
when the output voltage is less than one-half of its target
value. Note that the fastest output voltage rise time during
primary-side soft-start mode occurs with maximum input
voltage and minimum load current.
The open-loop start-up frequency on the LTC3705/LTC3725
is set by placing a resistor from the FB/IN + pin to GND.
Although the exact start-up frequency on the primary side
is not critical, it is generally good practice to set this
approximately equal to the operating frequency on the
secondary side. The FS/IN– start-up resistor for the
LTC3705/LTC3725 may be selected using the following:
fPRI (Hz) =
3.2 • 1010
RFS /IN– + 10k
In the event that the secondary-side circuitry fails to
properly start up and assume control of switching, there
are several fail-safe mechanisms to help avoid overvoltage
conditions. First, the LTC3705/LTC3725 contains a voltsecond clamp that will keep the primary-side duty cycle at
a level that cannot produce an overvoltage condition.
Second, the LTC3705/LTC3725 contains a time-out feature that will detect a FAULT if the LTC3726 fails to start up
and deliver PWM signals to the primary side. Finally, the
LTC3726 has an independent overvoltage detection circuit
that will crowbar the output of the DC/DC converter using
the synchronous MOSFET switch.
In the event that a short circuit is applied to the output of
the DC/DC converter prior to start-up, the LTC3726 will
generally not receive enough bias voltage to operate. In
this case, the LTC3705/LTC3725 will detect a FAULT for
3726fb
11
LTC3726
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APPLICATIO S I FOR ATIO
one of two reasons: 1) the start-up time-out feature will be
activated since the LTC3726 never sends signals to the
primary side or 2) the primary-side overcurrent circuit will
be tripped because of current buildup in the output inductor. In either case, the LTC3705/LTC3725 will initiate a
shutdown followed by a soft-start retry. See the LTC3705/
LTC3725 data sheets for further details.
ICC = IQ ,3726 + MS fOSCQ G,SEC
Bias Supply Generation
Figure 2 shows a commonly used method of developing a
VCC bias supply for the LTC3726. During start-up, the
circuit of Figure 2 uses a peak detector followed by a
simple linear regulator to rapidly develop a VCC voltage for
the LTC3726. Note that this bias voltage must rise faster
than the open-loop soft-start that is initiated by the
LTC3705/LTC3725. This ensures that the LTC3726 begins switching and assumes control of the soft-start
before the output voltage has risen substantially.
The value of R1 should be chosen to keep the peak
charging current below the maximum (non-repetitive peak)
rating of diode D1, but should otherwise be as small as
R1
1.2Ω
•
1
• BIAS
WINDING
NB
The linear regulator of Figure 2 should be designed to
handle the total expected ICC current. For self-starting
applications with the LTC3705/LTC3725, this regulator
will supply the operating bias current for both primary and
secondary side control circuitry. This current may be
approximated using the following:
CMPSH1-4
D1
R2
5K
C1
10µF
25V
Q1
FZT690B
D2
7.5V
MAIN
TRANSFORMER
PEAK CHARGER
LTC3726
C2
1µF
16V
REGULATOR
VCC
3726 F02
Figure 2. Typical Bias Supply Configuration
possible to provide a rapid charging of capacitor C1. This
capacitor serves as a reservoir to provide bias voltage as
the LTC3726 begins switching and assumes control of the
soft-start from the LTC3705/LTC3725. Care should be
taken to ensure that capacitor C1 is adequately large to
provide enough hold-up time for the LTC3726 to assume
control and establish a firm bias voltage at the main
transformer.
(
+ 2 MP fOSCQ G,PRI + IQ,3 7 05
)
+ICORE + 20C SNUB VCC fOSC
where IQ,3705 and IQ,3726 are the operating supply currents
of the LTC3705/LTC3725 and LTC3706, MP and MS are the
number of power MOSFETs used on the primary and
secondary sides, QG,PRI and QG,SEC are the total gate
charge of the primary and secondary MOSFETs, ICORE is
the core loss current associated with the pulse transformer, and CSNUB is the snubber capacitor across the
pulse transformer. Note that the current used by the
primary side circuitry is doubled by the 2:1 turns ratio of
the pulse transformer. For the Typical Application circuit
of Figure 5, the total ICC delivered by the linear regulator
is 5mA + 3(50nC)(200kHz) + 2(2(38nC)(200kHz) + 2mA)
+ 3mA + 13mA = 85mA. To accommodate this current, Q1
should have a high Beta (>300), and R2 should be chosen
to supply adequate base current at low VIN (e.g., at 36V on
the converter input), while maintaining a reasonable power
dissipation in D2 at high VIN (72V).
The turns ratio (NB) of the bias winding should be chosen
to ensure that there is adequate voltage to operate the
LTC3726 over the entire range for the DC/DC converter’s
input bus voltage (VBUS). This may be calculated using
NB =
VCC(MIN) + 1 . 2V +
R2 ⋅ ICC
β Q1
VBUS(MIN)
VCC(MIN) can be as low as 5V (if this provides adequate
gate drive voltage to maintain acceptable efficiency), or as
high as 7V. For the Figure 2 circuit if VCC(MIN) = 6V, ICC =
85mA, and VBUS = 36V-72V, this would mean a turns ratio
NB = 0.24, or a 9:2 transformer. Generally, if the output
voltage of the DC/DC converter is 3.3V or higher, then the
main output of the power transformer (tied to SW node on
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12
LTC3726
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APPLICATIO S I FOR ATIO
the LTC3726) can be used as the input to the peak charge
circuit of Figure 2. For lower output voltages, however, it
is normally necessary to use a dedicated bias winding to
generate adequate bias voltage for the LTC3726.
Current Sensing
The LTC3726 provides considerable flexibility in current sensing techniques. It supports two main methods: 1) resistive current sensing and 2) current transformer current sensing. Resistive current sensing is
generally simpler, smaller and less expensive, while
current transformer sensing is more efficient and generally appropriate for higher (> 20A) output currents.
For resistive current sensing, the sense resistor may
be placed in any one of three different locations: high
side inductor, low side inductor or low side switch, as
shown in Figure 3. Sensing the inductor current (high
•
IS+
•
LTC3726
side or low side) is generally less noisy but dissipates
more power than sensing the switch current (Figures
3a and 3b). High side inductor current sensing provides a more convenient layout than low side (no split
ground plane), but can only be used for output voltages up to 5.5V, due to the common mode limitations
of the current sense inputs (IS+ and IS–). For most
applications, low side switch current sensing will be a
good solution (Figure 3c).
For high current applications where efficiency (power
dissipation) is very important, a current sense transformer may be used. As shown in Figure 3d, the IS– pin
should be tied off to VCC when a current sense transformer
is used. This causes the IS+ pin to become a single ended
(nondifferential) current sense input with a maximum
current sense voltage of 1.28V. Figure 3d shows a typical
application circuit using a current transformer.
•
IS+
•
LTC3726
78mV MAX
78mV MAX
IS–
IS–
3726 F03a
Figure 3a. High Side Inductor:
Easier Layout, Low Noise, Accurate
3726 F03b
Figure 3b. Low Side Inductor:
Accurate, Low Noise, High VOUT Capable
•
•
•
1.28V MAX
TRIP
•
IS+
LTC3726
•
78mV MAX
LTC3726
•
IS–
5Ω TO
50Ω
VCC
IS–
3726 F03d
3726 F03c
Figure 3c. Switch Current Sensing: Easy Layout, Accurate,
Higher Efficiency, High VOUT Capable
IS+
Figure 3d. Current Transformer:
Highest Efficiency, High VOUT Capable
Figure 3. Current Sensing Techniques
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13
LTC3726
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APPLICATIO S I FOR ATIO
PolyPhase Applications
Figure 4 shows the basic connections for using the
LTC3705/LTC3725 and LTC3726 in PolyPhase applications. One of the phases is always identified as the “master,” while all other phases are “slaves.” For the LTC3705/
LTC3725 (primary side), the master monitors the VIN
voltage for undervoltage, performs the open-loop start-up
and supplies the initial VCC voltage for the master and all
slaves. The LTC3705/LTC3725 slaves simply stand by and
wait for PWM signals from their respective pulse transformers. Since the SS/FLT pins of each master and slave
LTC3705/LTC3725s are interconnected, a FAULT
(overcurrent, etc.) on any one of the phases will perform
a shutdown/restart on all phases together. The LTC3705/
LTC3725 is put into slave mode by omitting the resistor on
FS/IN–. For the LTC3726, the master performs soft-start
and voltage-loop regulation by driving all slaves to the
same current as the master using the ITH pins. Faults and
shutdowns are communicated via the interconnection of
the RUN/SS pins. The LTC3726 is put into slave mode by
tying the FB pin to VCC.
VIN+
VOUT+
VBIAS
VCC
FS/SYNC
NDRV
UVLO
FB/IN+
•
•
PT +
VCC
FB/PHASE
ITH
PT –
RUN/SS
LTC3726
(MASTER)
FS/IN–
SS/FLT
LTC3705/25
(MASTER)
VIN–
VCC
RUN/SS FS/SYNC
NDRV
SS/FLT FB/IN+
VCC
UVLO
FS/IN–
LTC3705/25
(SLAVE)
•
•
PT +
ITH
PT –
FB/PHASE
LTC3726
(SLAVE)
3726 F05
Figure 4. Connections for PolyPhase Operation
3726fb
14
LTC3726
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PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ± .005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.0532 – .0688
(1.35 – 1.75)
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3726fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3726
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TYPICAL APPLICATIO
VIN+
L1 1µH
T1
•
Si7852DP
1µF
100V
1µF
100V
x3
•
1.2Ω
CMPSH1-4
Si7336ADP
×2
9:2
Si7336ADP
Si7852DP
VIN–
5K
FZT690B
365k
1%
2mΩ
2W
BOOST TG TS BG IS
100Ω
FB/IN+
100Ω
2.2µF
25V
15k
1%
VCC
SS/FLT
FS/IN–
470pF
0.1µF
•
VOUT–
FG
SW SG
VCC
FS/SYNC
IS+
FB/PHASE
PT +
•
LTC3726
1µF
5k
ITH
PT –
RUN/SS
2:1
162k
102k
1%
IS–
GND PGND VSLMT
33nF
100Ω
1nF
T2
LTC3705
2.2µF
16V
CZT3019
L1: VISHAY IHLP-2525CZ-01
L2: COILCRAFT SER2010-122
T1: PULSE PA0807
T2: PULSE PA0297
UVLO
1nF
10µF
25V
680pF
BAS21 0.22µF
NDRV
7.5V
100Ω
100k
FQT7N10
2.2nF
250V
330µF
6.3V
×3
1µF
MURS120
30mΩ
1W
VOUT+
L2 1.2µH
10Ω
0.25W
1nF
100V
1nF
100V 10Ω
0.25W
MURS120
GND
PGND
33nF
SLP
MODE
680pF
20k
100k
22.6k
1%
3726 F05
Figure 5. 36V-72V to 3.3V/20A Isolated Forward Converter
(See Typical Performance Characteristics)
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1534
Ultralow Noise 2A Switching Regulator
Reduces Conducted and Radiated EMI, Low Switching Harmonics,
20kHz to 250kHz Switching Frequency
LT1619
Low Voltage Current Mode Controller
1.9V ≤ VIN ≤ 18V, 300kHz Operation, Boost, Flyback, SEPIC
LT1681/LT3781
Dual Transistor Synchronous Forward Controller
Operation Up to 72V Maximum
LT1725
General Purpose Isolated Flyback Controller
No Optoisolator Required, Accurate Regulation Without User Trims,
50kHz to 250kHz Switching Frequency, SSOP-16 Package
LTC1871
Wide Input Range, No RSENSE™ Controller
Operation as Low as 2.5V Input, Boost, Flyback, SEPIC
LT1910
Protected High Side MOSFET Driver
8V to 48V Supply Range, Protected –15V to 60V Supply Transient
LT1952
Single Switch Forward Controller
25W to 500W; Synchronous Controller
LTC3440
Micropower Buck-Boost DC/DC Converter
Synchronous, Single Inductor, No Schottky Diode Required
LTC3704
Positive-to-Negative DC/DC Controller
2.5V ≤ VIN ≤ 36V, No RSENSE Current Mode Operation,
Excellent Transient Response
LTC3705
Two-Switch Forward Converter Gate Driver and Controller
Use with LTC3726, Isolated Power Supplies, High Speed Gate Drivers
LT3706
PolyPhase Secondary Side Controller
Scalable Output Power; Self-Starting Architecture
LTC3722
Full Bridge Controller
Synchronous; ZVS Operation; 24-Pin SSOP
LTC3725
Two-Switch Forward Controller
On-Chip Gate-Driver; Fast Startup
No RSENSE is a trademark of Linear Technology Corporation.
3726fb
16
Linear Technology Corporation
LT 0207 REV B • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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