LTC3728L/LTC3728LX
Dual, 550kHz, 2-Phase
Synchronous Regulators
Description
Features
Dual, 180° Phased Controllers Reduce Required
Input Capacitance and Power Supply Induced Noise
n OPTI-LOOP® Compensation Minimizes C
OUT
n ±1% Output Voltage Accuracy (LTC3728LC)
n Power Good Output Voltage Indicator
n Phase-Lockable Fixed Frequency 250kHz to 550kHz
n Dual N-Channel MOSFET Synchronous Drive
n Wide V
IN Range: 4.5V to 28V Operation
n Very Low Dropout Operation: 99% Duty Cycle
n Adjustable Soft-Start Current Ramping
n Foldback Output Current Limiting
n Latched Short-Circuit Shutdown with Defeat Option
n Output Overvoltage Protection
n Low Shutdown I : 20µA
Q
n 5V and 3.3V Standby Regulators
n 3 Selectable Operating Modes: Constant-Frequency,
Burst Mode® Operation and PWM
n 5mm × 5mm QFN and 28-Lead Narrow SSOP
Packages
n
Applications
n
n
n
n
n
Notebook and Palmtop Computers
Telecom Systems
Portable Instruments
Battery-Operated Digital Devices
DC Power Distribution Systems
The LTC®3728L/LTC3728LX are dual high performance
step-down switching regulator controllers that drive all
N‑channel synchronous power MOSFET stages. A constantfrequency, current mode architecture allows phase-lockable
frequency of up to 550kHz. Power loss and noise due to
the ESR of the input capacitors are minimized by operating
the two controller output stages out of phase.
OPTI-LOOP compensation allows the transient response to
be optimized over a wide range of output capacitance and
ESR values. The precision 0.8V reference and power good
output indicator are compatible with future microprocessor generations, and a wide 4.5V to 28V (30V maximum)
input supply range encompasses all battery chemistries.
A RUN/SS pin for each controller provides both softstart and optional timed, short-circuit shutdown. Current
foldback limits MOSFET dissipation during short-circuit
conditions when overcurrent latchoff is disabled. Output
overvoltage protection circuitry latches on the bottom
MOSFET until VOUT returns to normal. The FCB mode
pin can select among Burst Mode, constant-frequency
mode and continuous inductor current mode or regulate
a secondary winding. The LTC3728L/LTC3728LX include
a power good output pin that indicates when both outputs
are within 7.5% of their designed set point.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, OPTI-LOOP and PolyPhase
are registered trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Typical Application
4.7µF
+
D3
M1
L1
3.2µH
CB1, 0.1µF
fIN
500kHz
RSENSE1
0.01Ω
VOUT1
5V
5A
+
COUT1
47µF
6V
SP
SW1
M2
TG2
BOOST1
BG1
D1
D4
VIN PGOOD INTVCC
TG1
BOOST2
LTC3728L/
LTC3728LX
PLLIN
SW2
R1
20k
1%
CC1
220pF
RC1
15k
L2
3.2µH
CB2, 0.1µF
BG2
D2
PGND
SENSE1+
SENSE2+
SENSE1–
VOSENSE1
SENSE2–
VOSENSE2
1000pF
R2
105k
1%
VIN
5.2V TO 28V
CIN
22µF
50V
CERAMIC
1µF
CERAMIC
RSENSE2
0.01Ω
1000pF
ITH1
ITH2
RUN/SS1 SGND RUN/SS2
CSS1
0.1µF
CSS2
0.1µF
CC2
220pF
RC2
15k
R3
20k
1%
R4
63.4k
1%
M1, M2: FDS6982S
Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter
COUT
56µF
6V
SP
+
VOUT2
3.3V
5A
3728 F01
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1
LTC3728L/LTC3728LX
Absolute Maximum Ratings
(Note 1)
Input Supply Voltage (VIN)......................... 30V to – 0.3V
Topside Driver Voltages
(BOOST1, BOOST2)............................... 36V to –0.3V
Switch Voltage (SW1, SW2)......................... 30V to –5V
INTVCC, EXTVCC, RUN/SS1, RUN/SS2,
(BOOST1-SW1), (BOOST2-SW2), PGOOD..... 7V to –0.3V
SENSE1+, SENSE2+, SENSE1–,
SENSE2– Voltages ......................... (1.1)INTVCC to –0.3V
PLLIN, PLLFLTR, FCB Voltages............. INTVCC to –0.3V
ITH1, ITH2, VOSENSE1, VOSENSE2 Voltages .... 2.7V to –0.3V
Peak Output Current fOSC
50
kΩ
–15
15
µA
µA
3.3V Linear Regulator
V3.3OUT
3.3V Regulator Output Voltage
No Load
3.35
3.45
V
V3.3IL
3.3V Regulator Load Regulation
I3.3 = 0 to 10mA
0.5
2
%
V3.3VL
3.3V Regulator Line Regulation
6V < VIN < 30V
0.05
0.2
%
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
0.1
0.3
V
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
±1
µA
VPG
PGOOD Trip Level, Either Controller
VOSENSE with Respect to Set Output Voltage
VOSENSE Ramping Negative
VOSENSE Ramping Positive
– 9.5
9.5
%
%
●
3.2
PGOOD Output
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC3728LUH/LTC3728LXUH: TJ = TA + (PD • 34°C/W)
LTC3728LGN: TJ = TA + (PD • 95°C/W)
Note 3: The IC is tested in a feedback loop that servos VITH1, 2 to a
specified voltage and measures the resultant VOSENSE1, 2.
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications Information
section.
–6
6
–7.5
7.5
Note 5: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 6: The minimum on-time is tested under an ideal condition without
external power FETs. It can be larger when the IC is operating in an
actual circuit. See Minimum On-Time Considerations in the Applications
Information section.
Note 7: The LTC3728LC/LTC3728LXC are guaranteed to meet performance
specifications from 0°C to 85°C. The LTC3728LE is guaranteed to meet
performance specifications over the –40°C to 85°C operating temperature
range as assured by design, characterization and correlation with statistical
process controls. The LTC3728LI is guaranteed to meet performance
specifications over the –40°C to 85°C operating temperature range.
Note 8: Guaranteed by design.
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LTC3728L/LTC3728LX
Typical Performance Characteristics
Efficiency vs Output Current
and Mode (Figure 13)
100
Efficiency vs Output Current
(Figure 13)
100
Burst Mode
OPERATION
90
80
90
50
40
CONSTANT
FREQUENCY
(BURST DISABLE)
30
20
0
0.001
VIN = 20V
70
VOUT = 5V
f = 250kHz
0.1
0.01
1
OUTPUT CURRENT (A)
EXTVCC VOLTAGE DROP (mV)
SUPPLY CURRENT (µA)
400
200
SHUTDOWN
0
5
20
10
15
INPUT VOLTAGE (V)
25
100
50
0
30
10
0
20
CURRENT (mA)
30
4.95
4.90
4.85
4.80
EXTVCC SWITCHOVER THRESHOLD
4.75
4.70
–50 –25
40
50
25
75
0
TEMPERATURE (°C)
100
125
3728L G06
Maximum Current Sense
Threshold vs Percent of Nominal
Output Voltage (Foldback)
Maximum Current Sense
Threshold vs Duty Factor
75
80
70
5.0
60
4.8
4.7
50
VSENSE (mV)
4.9
VSENSE (mV)
INTVCC VOLTAGE (V)
INTVCC VOLTAGE
5.00
3728L G05
ILOAD = 1mA
35
5.05
150
Internal 5V LDO Line Regulation
25
4.6
50
40
30
20
4.5
4.4
25
15
INPUT VOLTAGE (V)
INTVCC and EXTVCC Switch
Voltage vs Temperature
EXTVCC Voltage Drop
3728L G04
5.1
5
3728L G03
INTVCC AND EXTVCC SWITCH VOLTAGE (V)
200
1000
BOTH
CONTROLLERS ON
VOUT = 5V
IOUT = 3A
f = 250kHz
3728L G02
Supply Current vs Input Voltage
and Mode (Figure 13)
600
70
50
10
3728L G01
800
80
60
50
0.001
10
0.1
0.01
1
OUTPUT CURRENT (A)
80
60
VIN = 15V
VOUT = 5V
f = 250kHz
10
VIN = 10V
VIN = 15V
EFFICIENCY (%)
FORCED
CONTINUOUS
MODE (PWM)
60
EFFICIENCY (%)
EFFICIENCY (%)
100
VIN = 7V
90
70
0
Efficiency vs Input Voltage
(Figure 13)
10
0
5
20
15
10
INPUT VOLTAGE (V)
25
30
3728L G07
0
0
20
40
60
DUTY FACTOR (%)
80
100
3728L G08
0
50
100
0
25
75
PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
3728L G09
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LTC3728L/LTC3728LX
Typical Performance Characteristics
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
Maximum Current Sense Threshold
vs VRUN/SS (Soft-Start)
80
90
80
VSENSE(CM) = 1.6V
80
70
76
40
60
VSENSE (mV)
VSENSE (mV)
60
VSENSE (mV)
Current Sense Threshold
vs ITH Voltage
72
68
50
40
30
20
10
20
0
64
–10
–20
0
0
1
2
3
5
4
60
6
1
3
4
2
COMMON MODE VOLTAGE (V)
0
VRUN/SS (V)
FCB = 0V
VIN = 15V
FIGURE 13
VOSENSE = 0.7V
ISENSE (µA)
1.5
1.0
4
0
5
0
2
1
3
4
3728L G13
4
DROPOUT VOLTAGE (V)
76
74
72
50
0
75
25
TEMPERATURE (°C)
100
125
3728L G17
2
0
4
3728L G15
RUN/SS Current vs Temperature
1.8
VOUT = 5V
1.6
3
2
RSENSE = 0.015Ω
1
0
0
0.5
6
VSENSE COMMON MODE VOLTAGE (V)
RSENSE = 0.010Ω
–25
–100
6
Dropout Voltage vs Output Current
(Figure 14)
78
VSENSE (mV)
5
3728L G14
80
70
–50
0
VRUN/SS (V)
Maximum Current Sense
Threshold vs Temperature
2.5
–50
RUN/SS CURRENT (µA)
3
2
LOAD CURRENT (A)
2
50
0.5
1
1.5
VITH (V)
SENSE Pins Total Source Current
–0.3
0
1
100
2.0
VITH (V)
NORMALIZED VOUT (%)
2.5
–0.1
–0.4
0.5
3728L G12
VITH vs VRUN/SS
Load Regulation
–0.2
0
3728L G11
3728L G10
0.0
–30
5
1.0 1.5 2.0 2.5 3.0
OUTPUT CURRENT (A)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
3.5
4.0
3728L G18
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3728L G25
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LTC3728L/LTC3728LX
Typical Performance Characteristics
Soft-Start Up (Figure 13)
Load Step (Figure 13)
VOUT
5V/DIV
Load Step (Figure 13)
VOUT
200mV/DIV
VOUT
200mV/DIV
IL
2A/DIV
IL
2A/DIV
VRUN/SS
5V/DIV
IL
2A/DIV
VIN = 15V
VOUT = 5V
5ms/DIV
3728L G19
VIN = 15V
20µs/DIV
VOUT = 5V
VPLLFLTR = 0V
LOAD STEP = 0A TO 3A
Burst Mode OPERATION
Input Source/Capacitor
Instantaneous Current (Figure 13)
IIN
2A/DIV
3728L G20
3728L G21
Constant-Frequency (Burst Inhibit)
Operation (Figure 13)
Burst Mode Operation (Figure 13)
VOUT
20mV/DIV
VOUT
20mV/DIV
VIN
200mV/DIV
VIN = 15V
20µs/DIV
VOUT = 5V
VPLLFLTR = 0V
LOAD STEP = 0A TO 3A
CONTINUOUS MODE
VSW1
10V/DIV
IL
0.5A/DIV
VSW2
10V/DIV
VIN = 15V
1µs/DIV
VOUT1 = 5V, VOUT2 = 3.3V
VPLLFLTR = 0V
IOUT5 = IOUT3.3 = 2A
3728L G22
IL
0.5A/DIV
VIN = 15V
VOUT = 5V
VPLLFLTR = 0V
VFCB = OPEN
IOUT = 20mA
10µs/DIV
3728L G23
VIN = 15V
VOUT = 5V
VPLLFLTR = 0V
VFCB = 5V
IOUT = 20mA
2µs/DIV
3728L G24
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LTC3728L/LTC3728LX
Typical Performance Characteristics
Current Sense Pin Input Current
vs Temperature
31
29
27
50
0
75
25
TEMPERATURE (°C)
100
125
600
8
6
4
2
0
–50
–25
50
0
75
25
TEMPERATURE (°C)
3728L G26
VPLLFLTR = 1.2V
400
300
VPLLFLTR = 0V
200
100
125
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
3728L G28
Shutdown Latch Thresholds
vs Temperature
3.50
4.5
3.45
3.40
3.35
3.30
3.25
50
25
75
0
TEMPERATURE (°C)
500
3728L G27
Undervoltage Lockout
vs Temperature
3.20
–50 –25
VPLLFLTR = 2.4V
100
SHUTDOWN LATCH THRESHOLDS (V)
–25
700
FREQUENCY (kHz)
EXTVCC SWITCH RESISTANCE (Ω)
33
25
–50
Oscillator Frequency
vs Temperature
10
VOUT = 5V
UNDERVOLTAGE LOCKOUT (V)
CURRENT SENSE INPUT CURRENT (µA)
35
EXTVCC Switch Resistance
vs Temperature
100
125
3728L G29
LATCH ARMING
4.0
3.5
LATCHOFF
THRESHOLD
3.0
2.5
2.0
1.5
1.0
0.5
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
3728L G30
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LTC3728L/LTC3728LX
Pin Functions
VOSENSE1, VOSENSE2: Error Amplifier Feedback Input.
Receives the remotely sensed feedback voltage for each
controller from an external resistive divider across the
output.
TG2, TG1: High Current Gate Drives for Top N-Channel
MOSFETs. These are the outputs of floating drivers with
a voltage swing equal to INTVCC – 0.5V superimposed on
the switch node voltage SW.
PLLFLTR: Filter Connection for Phase-Locked Loop. Alternatively, this pin can be driven with an AC or DC voltage
source to vary the frequency of the internal oscillator.
SW2, SW1: Switch Node Connections to Inductors. Voltage
swing at these pins is from a Schottky diode (external)
voltage drop below ground to VIN.
PLLIN: External Synchronization Input to Phase Detector.
This pin is internally terminated to SGND with 50kΩ. The
phase-locked loop will force the rising top gate signal of
controller 1 to be synchronized with the rising edge of
the PLLIN signal.
BOOST2, BOOST1: Bootstrapped Supplies to the Topside Floating Drivers. Capacitors are connected between
the boost and switch pins and Schottky diodes are tied
between the boost and INTVCC pins. Voltage swing at the
boost pins is from INTVCC to (VIN + INTVCC).
FCB: Forced Continuous Control Input. This input acts
on both controllers and is normally used to regulate a
secondary winding. Pulling this pin below 0.8V will force
continuous synchronous operation.
BG2, BG1: High Current Gate Drives for Bottom (Synchronous) N-Channel MOSFETs. Voltage swing at these pins
is from ground to INTVCC.
ITH1, ITH2: Error Amplifier Output and Switching Regulator
Compensation Point. Each associated channels’ current
comparator trip point increases with this control voltage.
SGND: Small Signal Ground. Common to both controllers, this pin must be routed separately from high
current grounds to the common (–) terminals of the COUT
capacitors.
3.3VOUT: Linear Regulator Output. Capable of supplying
10mA DC with peak currents as high as 50mA.
NC: No Connect.
SENSE2 –, SENSE1–: The (–) Input to the Differential Current Comparators.
SENSE2+, SENSE1+: The (+) Input to the Differential Current
Comparators. The ITH pin voltage and controlled offsets
between the SENSE– and SENSE+ pins in conjunction with
RSENSE set the current trip threshold.
RUN/SS2, RUN/SS1: Combination of soft-start, run control
inputs and short-circuit detection timers. A capacitor to
ground at each of these pins sets the ramp time to full
output current. Forcing either of these pins back below
1.0V causes the IC to shut down the circuitry required for
that particular controller. Latchoff overcurrent protection is
also invoked via this pin as described in the Applications
Information section.
PGND: Driver Power Ground. Connects to the sources
of bottom (synchronous) N-channel MOSFETs, anodes
of the Schottky rectifiers and the (–) terminal(s) of CIN.
INTVCC: Output of the Internal 5V Linear Low Dropout
Regulator and the EXTVCC Switch. The driver and control
circuits are powered from this voltage source. Must be
decoupled to power ground with a minimum of 4.7µF
tantalum or other low ESR capacitor.
EXTVCC: External Power Input to an Internal Switch
Connected to INTVCC. This switch closes and supplies
VCC power, bypassing the internal low dropout regulator,
whenever EXTVCC is higher than 4.7V. See EXTVCC connection in Applications section. Do not exceed 7V on this pin.
VIN: Main Supply Pin. A bypass capacitor should be tied
between this pin and the signal ground pin.
PGOOD: Open-Drain Logic Output. PGOOD is pulled to
ground when the voltage on either VOSENSE pin is not
within ±7.5% of its set point.
Exposed Pad (UH Package Only): Signal Ground. Must
be soldered to the PCB, providing a local ground for the
control components of the IC, and be tied to the PGND
pin under the IC.
3728lxff
10
+
5V
VIN
R5
–
+
4.7V
3V
–
+
0.8V
4.3V
OSCILLATOR
PHASE DET
SGND (UH PACKAGE PAD)
INTVCC
EXTVCC
VIN
3.3VOUT
FCB
0.18µA
PGOOD
INTVCC
R6
50k
PLLIN
PLLFLTR
CLP
RLP
FIN
–
+
+
–
5V
LDO
REG
VREF
FCB
BINH
0.74V
INTERNAL
SUPPLY
+
–
VOSENSE2
0.86V
–
+
0.74V
VOSENSE1
0.86V
+
–
+
–
CLK2
CLK1
6V
1.2µA
SLOPE
COMP
0.86V
4(VFB)
I1
Q
R
–
+
–
SHDN
RST
4(VFB)
3mV
B
FCB
–
RUN
SOFT
START
OV
–
+
–
EA
+
0.86V
PGND
BG
SW
TG
BOOST
RUN/SS
ITH
VOSENSE
–
30k SENSE
+
30k SENSE
INTVCC
INTVCC
BOT
TOP
0.80V
VFB
SWITCH
LOGIC
I2
2.4V
45k
+
–
SHDN
TOP ON
BOT
Figure 2
45k
++
–
+
DROP
OUT
DET
0.55V
Q
S
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
CSS
CC2
CC
R2
CB
DB
R1
INTVCC
RC
VIN
+
3728 FD/F02
RSENSE
D1
+
COUT
CIN
VOUT
LTC3728L/LTC3728LX
Functional Diagram
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LTC3728L/LTC3728LX
Operation
(Refer to Functional Diagram)
Main Control Loop
Low Current Operation
The IC uses a constant-frequency, current mode step-down
architecture with the two controller channels operating
180 degrees out of phase. During normal operation, each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
comparator, I1, resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by
the voltage on the ITH pin, which is the output of each
error amplifier EA. The VOSENSE pin receives the voltage
feedback signal, which is compared to the internal reference voltage by the EA. When the load current increases,
it causes a slight decrease in VOSENSE relative to the 0.8V
reference, which in turn causes the ITH voltage to increase
until the average inductor current matches the new load
current. After the top MOSFET has turned off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by current comparator I2,
or the beginning of the next cycle.
The FCB pin is a multifunction pin providing two functions: 1) to provide regulation for a secondary winding by
temporarily forcing continuous PWM operation on both
controllers; and 2) to select between two modes of low
current operation. When the FCB pin voltage is below
0.8V, the controller forces continuous PWM current mode
operation. In this mode, the top and bottom MOSFETs
are alternately turned on to maintain the output voltage
independent of direction of inductor current. When the
FCB pin is below VINTVCC – 2V but greater than 0.8V,
the controller enters Burst Mode operation. Burst Mode
operation sets a minimum output current level before
inhibiting the top switch and turns off the synchronous
MOSFET(s) when the inductor current goes negative. This
combination of requirements will, at low currents, force
the ITH pin below a voltage threshold that will temporarily
inhibit turn-on of both output MOSFETs until the output
voltage drops. There is 60mV of hysteresis in the burst
comparator B tied to the ITH pin. This hysteresis produces
output signals to the MOSFETs that turn them on for
several cycles, followed by a variable “sleep” interval
depending upon the load current. The resultant output
voltage ripple is held to a very small value by having the
hysteretic comparator after the error amplifier gain block.
The top MOSFET drivers are biased from floating bootstrap
capacitor CB, which normally is recharged during each off
cycle through an external diode when the top MOSFET
turns off. As VIN decreases to a voltage close to VOUT,
the loop may enter dropout and attempt to turn on the
top MOSFET continuously. The dropout detector detects
this and forces the top MOSFET off for about 400ns every
tenth cycle to allow CB to recharge.
The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.2µA current source to charge soft-start capacitor CSS. When CSS
reaches 1.5V, the main control loop is enabled with the ITH
voltage clamped at approximately 30% of its maximum
value. As CSS continues to charge, the ITH pin voltage is
gradually released allowing normal, full-current operation.
When both RUN/SS1 and RUN/SS2 are low, all controller functions are shut down, including the 5V and 3.3V
regulators.
Frequency Synchronization
The phase-locked loop allows the internal oscillator to
be synchronized to an external source via the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is
also the DC frequency control input of the oscillator that
operates over a 260kHz to 550kHz range corresponding
to a DC voltage input from 0V to 2.4V. When locked, the
PLL aligns the turn on of the top MOSFET to the rising
edge of the synchronizing signal. When PLLIN is left
open, the PLLFLTR pin goes low, forcing the oscillator to
minimum frequency.
3728lxff
12
LTC3728L/LTC3728LX
operation
(Refer to Functional Diagram)
Constant-Frequency Operation
Power Good (PGOOD) Pin
When the FCB pin is tied to INTVCC, Burst Mode operation is disabled and the forced minimum output current
requirement is removed. This provides constant-frequency,
discontinuous current (preventing reverse inductor current) operation over the widest possible output current
range. This constant-frequency operation is not as efficient
as Burst Mode operation, but does provide a lower noise,
constant-frequency operating mode down to approximately
1% of the designed maximum output current.
The PGOOD pin is connected to an open drain of an internal
MOSFET. The MOSFET turns on and pulls the pin low when
either output is not within ± 7.5% of the nominal output
level as determined by the resistive feedback divider. When
both outputs meet the ±7.5% requirement, the MOSFET is
turned off within 10µs and the pin is allowed to be pulled
up by an external resistor to a source of up to 7V.
Continuous Current (PWM) Operation
The RUN/SS capacitors are used initially to limit the inrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used in a short-circuit time-out circuit.
If the output voltage falls to less than 70% of its nominal
output voltage, the RUN/SS capacitor begins discharging
on the assumption that the output is in an overcurrent and/
or short-circuit condition. If the condition lasts for a long
enough period as determined by the size of the RUN/SS
capacitor, the controller will be shut down until the RUN/
SS pin(s) voltage(s) are recycled. This built-in latchoff can
be overridden by providing a >5µA pull-up at a compliance
of 5V to the RUN/SS pin(s). This current shortens the soft
start period but also prevents net discharge of the RUN/
SS capacitor(s) during an overcurrent and/or short-circuit
condition. Foldback current limiting is also activated when
the output voltage falls below 70% of its nominal level
whether or not the short-circuit latchoff circuit is enabled.
Even if a short is present and the short-circuit latchoff is
not enabled, a safe, low output current is provided due to
internal current foldback and actual power wasted is low
due to the efficient nature of the current mode switching
regulator.
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be forced
back into the main power supply potentially boosting the
input supply to dangerous voltage levels—BEWARE!
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin. When
the EXTVCC pin is left open, an internal 5V low dropout
linear regulator supplies INTVCC power. If EXTVCC is taken
above 4.7V, the 5V regulator is turned off and an internal
switch is turned on connecting EXTVCC to INTVCC. This allows the INTVCC power to be derived from a high efficiency
external source such as the output of the regulator itself
or a secondary winding, as described in the Applications
Information section.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious conditions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff
3728lxff
13
LTC3728L/LTC3728LX
Operation
(Refer to Functional Diagram)
Theory and Benefits of 2-Phase Operation
The LTC1628 and the LTC3728L family of dual high efficiency DC/DC controllers brings the considerable benefits
of 2-phase operation to portable applications for the first
time. Notebook computers, PDAs, handheld terminals
and automotive electronics will all benefit from the lower
input filtering requirement, reduced electromagnetic interference (EMI) and increased efficiency associated with
2-phase operation.
This effectively interleaves the current pulses drawn by
the switches, greatly reducing the overlap time where
they add together. The result is a significant reduction
in total RMS input current, which in turn allows less
expensive input capacitors to be used, reduces shielding
requirements for EMI and improves real world operating
efficiency.
Why the need for 2-phase operation? Up until the
2-phase family, constant-frequency dual switching regulators operated both channels in phase (i.e., single-phase
operation). This means that both switches turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current flowing from the
input capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.
Figure 3 compares the input waveforms for a representative single-phase dual switching regulator to the LTC1628
2-phase dual switching regulator. An actual measurement of
the RMS input current under these conditions shows that
2-phase operation dropped the input current from 2.53ARMS
to 1.55ARMS. While this is an impressive reduction in itself,
remember that the power losses are proportional to IRMS2,
meaning that the actual power wasted is reduced by a factor of 2.66. The reduced input ripple voltage also means
less power is lost in the input power path, which could
include batteries, switches, trace/connector resistances
and protection circuitry. Improvements in both conducted
and radiated EMI also directly accrue as a result of the
reduced RMS input current and voltage.
With 2-phase operation, the two channels of the dualswitching regulator are operated 180 degrees out of phase.
Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator’s relative
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
IIN(MEAS) = 2.53ARMS
(a)
DC236 F03a
IIN(MEAS) = 2.53ARMS
DC236 F03b
(b)
Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators
Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows
Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency
3728lxff
14
LTC3728L/LTC3728LX
(Refer to Functional Diagram)
duty cycles which, in turn, are dependent upon the input
voltage VIN (Duty Cycle = VOUT/VIN). Figure 4 shows how
the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
It can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb
for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle.
A final question: If 2-phase operation offers such an advantage over single-phase operation for dual switching
regulators, why hasn’t it been done before? The answer
is that, while simple in concept, it is hard to implement.
Constant-frequency, current mode switching regulators
require an oscillator derived slope compensation signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in
single-phase dual switching regulators, but required the
development of a new and proprietary technique to allow
2-phase operation. In addition, isolation between the two
channels becomes more critical with 2-phase operation
because switch transitions in one channel could potentially
disrupt the operation of the other channel.
These 2-phase parts are proof that these hurdles have
been surmounted. They offer unique advantages for the
ever expanding number of high efficiency power supplies
required in portable electronics.
3.0
SINGLE PHASE
DUAL CONTROLLER
2.5
INPUT RMS CURRENT (A)
operation
2.0
1.5
2-PHASE
DUAL CONTROLLER
1.0
0.5
0
VO1 = 5V/3A
VO2 = 3.3V/3A
0
10
20
30
INPUT VOLTAGE (V)
40
3728 F04
Figure 4. RMS Input Current Comparison
3728lxff
15
LTC3728L/LTC3728LX
Applications Information
Figure 1 on the first page is a basic LTC3728L/LTC3728LX
application circuit. External component selection is driven
by the load requirement, and begins with the selection of
RSENSE and the inductor value. Next, the power MOSFETs
and D1 are selected. Finally, CIN and COUT are selected.
The circuit shown in Figure 1 can be configured for
operation up to an input voltage of 28V (limited by the
external MOSFETs).
PLLFLTR PIN VOLTAGE (V)
2.5
Allowing a margin for variations in the IC and external
component values yields:
RSENSE =
50mV
IMAX
Because of possible PCB layout-induced noise in the
current sensing loop, the AC current sensing ripple of
∆VSENSE = ∆I • RSENSE also needs to be checked in the
design to get good signal-to-noise ratio. In general, for
a reasonably good PCB layout, a 15mV ∆VSENSE voltage
is recommended as a conservative design starting point.
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to the
internal compensation required to meet stability criterion
for buck regulators operating at greater than 50% duty
factor. A curve is provided to estimate this reduction in
peak output current level depending upon the operating
duty factor.
1.5
1.0
0.5
0
200
RSENSE Selection for Output Current
RSENSE is chosen based on the required output current. The
current comparator has a maximum threshold of 75mV/
RSENSE and an input common mode range of SGND to
1.1(INTVCC). The current comparator threshold sets the
peak of the inductor current, yielding a maximum average
output current IMAX equal to the peak value less half the
peak-to-peak ripple current, ∆IL.
2.0
300
400
500
OPERATING FREQUENCY (kHz)
600
3728 F05
Figure 5. PLLFLTR Pin Voltage vs Frequency
and Frequency Synchronization in the Applications Information section for additional information.
A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 5. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 550kHz.
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆IL decreases with higher
inductance or frequency and increases with higher VIN:
∆IL =
V
1
VOUT 1– OUT
(f)(L)
VIN
Operating Frequency
The IC uses a constant-frequency, phase-lockable architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ∆I = 30% of maximum output current or
higher for good load transient response and sufficient
ripple current signal in the current loop.
3728lxff
16
LTC3728L/LTC3728LX
applications information
The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
The peak-to-peak drive levels are set by the INTVCC
voltage. This voltage is typically 5V during start-up
(see EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected (VIN
< 5V); then, sublogic level threshold MOSFETs (VGS(TH)
< 3V) should be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
Inductor Core Selection
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), Miller capacitance CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
V
Main Switch Duty Cycle = OUT
VIN
V –V
Synchronous Switch Duty Cycle = IN OUT
VIN
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and, therefore, copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space efficient,
especially when using several layers of wire. Because
they generally lack a bobbin, mounting is more difficult.
However, designs for surface mount are available that do
not increase the height significantly.
Power MOSFET and D1 Selection
The MOSFET power dissipations at maximum output
current are given by:
V
2
PMAIN = OUT (IMAX ) (1+ d )RDS(ON) +
VIN
I
( VIN )2 MAX
(RDR ) (CMILLER ) •
2
1
1
+
( f)
VINTVCC – VTHMIN VTHMIN
PSYNC =
( ) (1+ d )R
VIN – VOUT
IMAX
VIN
2
DS(ON)
Two external power MOSFETs must be selected for each
controller in the LTC3728L/LTC3728LX: One N‑channel
MOSFET for the top (main) switch, and one N‑channel
MOSFET for the bottom (synchronous) switch.
3728lxff
17
LTC3728L/LTC3728LX
Applications Information
where d is the temperature dependency of RDS(ON) and
RDR (approximately 4Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N‑channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + d) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diode, D1, shown in Figure 1 conducts during
the dead time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead
time and requiring a reverse-recovery period that could
cost as much as 3% in efficiency at high VIN. A 1A to 3A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.
CIN and COUT Selection
The selection of CIN is simplified by the multiphase architecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst-case RMS current occurs
when only one controller is operating. The controller
with the highest (VOUT)(IOUT) product needs to be used
in the subsequent formula to determine the maximum
RMS current requirement. Increasing the output current,
drawn from the other out-of-phase controller, will actually
decrease the input RMS ripple current from this maximum
value (see Figure 4). The out-of-phase technique typically
reduces the input capacitor’s RMS ripple current by a
factor of 30% to 70% when compared to a single phase
power supply solution.
The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selection process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20µF to 40µF is usually sufficient
for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used
as input capacitors, but each has drawbacks: ceramic
voltage coefficients are very high and may have audible
piezoelectric effects; tantalums need to be surge-rated;
OS-CONs suffer from higher inductance, larger case size
and limited surface-mount applicability; electrolytics’
higher ESR and dryout possibility require several to be
used. Multiphase systems allow the lowest amount of
capacitance overall. As little as one 22µF or two to three
10µF ceramic capacitors are an ideal choice in a 20W to
35W power supply due to their extremely low ESR. Even
though the capacitance at 20V is substantially below their
rating at zero-bias, very low ESR loss makes ceramics
an ideal candidate for highest efficiency battery operated
systems. Also consider parallel ceramic and high quality
electrolytic capacitors as an effective means of achieving
ESR and bulk capacitance goals.
In continuous mode, the source current of the top N‑channel
MOSFET is a square wave of duty cycle VOUT/VIN. To prevent
large voltage transients, a low ESR input capacitor sized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
1/2
CIN RequiredIRMS ≈ IMAX
VOUT ( VIN − VOUT )
VIN
This formula has a maximum at VIN = 2VOUT , where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturer’s ripple
3728lxff
18
LTC3728L/LTC3728LX
applications information
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult
the manufacturer if there is any question.
The benefit of the LTC3728L/LTC3728LX multiphase clocking can be calculated by using the equation above for the
higher power controller and then calculating the loss that
would have resulted if both controller channels switched
on at the same time. The total RMS power lost is lower
when both controllers are operating due to the interleaving of current pulses through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
in the previous equation for the worst-case controller is
adequate for the dual controller design. Remember that
input protection fuse resistance, battery resistance and
PC board trace resistance losses are also reduced due to
the reduced peak currents in a multiphase system. The
overall benefit of a multiphase design will only be fully
realized when the source impedance of the power supply/
battery is included in the efficiency testing. The drains of
the two top MOSFETs should be placed within 1cm of each
other and share a common CIN(s). Separating the drains
and CIN may produce undesirable voltage and current
resonances at VIN.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering.
The output ripple (∆VOUT) is determined by:
1
∆VOUT ≈ ∆IL ESR +
8fCOUT
Where f = operating frequency, COUT = output capacitance,
and ∆IL= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3IOUT(MAX) the output
ripple will typically be less than 50mV at the maximum
VIN assuming:
COUT Recommended ESR < 2 RSENSE
and COUT > 1/(8fRSENSE)
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guarantees
that the output capacitance does not significantly discharge
during the operating frequency period due to ripple current.
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage at or below 50mV. The ITH pin
OPTI-LOOP compensation components can be optimized
to provide stable, high performance transient response
regardless of the output capacitors selected.
Manufacturers such as Nichicon, United Chemi-Con and
Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)
(size) product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
In surface mount applications, multiple capacitors may
need to be used in parallel to meet ESR, RMS current handling and load step requirements. Aluminum
electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. Special
polymer surface mount capacitors offer very low ESR
but have lower storage capacity per unit volume than
other capacitor types. These capacitors offer a very
cost-effective output capacitor solution and are an ideal
choice when combined with a controller having high
loop bandwidth. Tantalum capacitors offer the highest
capacitance density and are often used as output capacitors for switching regulators having controlled soft-start.
Several excellent surge-tested choices are the AVX TPS,
AVX TPSV or the KEMET T510 series of surface mount
tantalums, available in case heights ranging from 2mm
to 4mm. Aluminum electrolytic capacitors can be used
in cost-driven applications providing that consideration
is given to ripple current ratings, temperature and long
term reliability. A typical application will require several
to many aluminum electrolytic capacitors in parallel. A
combination of the aforementioned capacitors will often
result in maximizing performance and minimizing overall
cost. Other capacitor types include Nichicon PL series,
3728lxff
19
LTC3728L/LTC3728LX
Applications Information
Panasonic SP, NEC Neocap, Cornell Dubilier ESRE and
Sprague 595D series. Consult manufacturers for other
specific recommendations.
INTVCC Regulator
An internal P‑channel low dropout regulator produces
5V at the INTVCC pin from the VIN supply pin. INTVCC
powers the drivers and internal circuitry within the IC.
The INTVCC pin regulator can supply a peak current of
50mA and must be bypassed to ground with a minimum
of 4.7µF tantalum, 10µF special polymer, or low ESR type
electrolytic capacitor. A 1µF ceramic capacitor placed directly adjacent to the INTVCC and PGND IC pins is highly
recommended. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between channels.
Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the IC to be exceeded.
The system supply current is normally dominated by the
gate charge current. Additional external loading of the
INTVCC and 3.3V linear regulators also needs to be taken
into account for the power dissipation calculations. The
total INTVCC current can be supplied by either the 5V internal linear regulator or by the EXTVCC input pin. When
the voltage applied to the EXTVCC pin is less than 4.7V, all
of the INTVCC current is supplied by the internal 5V linear
regulator. Power dissipation for the IC in this case is highest: (VIN)(IINTVCC), and overall efficiency is lowered. The
gate charge current is dependent on operating frequency
as discussed in the Efficiency Considerations section.
The junction temperature can be estimated by using the
equations given in Note 2 of the Electrical Characteristics.
For example, the IC VIN current is thermally limited to less
than 67mA from a 24V supply when not using the EXTVCC
pin as follows:
TJ = 70°C + (67mA)(24V)(34°C/W) = 125°C
Use of the EXTVCC input pin reduces the junction temperature to:
TJ = 70°C + (67mA)(5V)(34°C/W) = 81°C
The absolute maximum rating for the INTVCC pin is 40mA.
Dissipation should be calculated to also include any added
current drawn from the internal 3.3V linear regulator. To
prevent maximum junction temperature from being exceeded, the input supply current must be checked operating
in continuous mode at maximum VIN.
EXTVCC Connection
The IC contains an internal P‑channel MOSFET switch
connected between the EXTVCC and INTVCC pins. When
the voltage applied to EXTVCC rises above 4.7V, the internal
regulator is turned off and the switch closes, connecting
the EXTVCC pin to the INTVCC pin, thereby supplying internal
power. The switch remains closed as long as the voltage
applied to EXTVCC remains above 4.5V. This allows the
MOSFET driver and control power to be derived from the
output during normal operation (4.7V < VOUT < 7V) and
from the internal regulator when the output is out of regulation (start-up, short-circuit). If more current is required
through the EXTVCC switch than is specified, an external
Schottky diode can be added between the EXTVCC and
INTVCC pins. Do not apply greater than 7V to the EXTVCC
pin and ensure that EXTVCC (COUT )(VOUT) (10 –4) (RSENSE)
The minimum recommended soft-start capacitor of CSS =
0.1µF will be sufficient for most applications.
Fault Conditions: Current Limit and Current Foldback
The current comparators have a maximum sense voltage of 75mV resulting in a maximum MOSFET current
of 75mV/RSENSE. The maximum value of current limit
generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the highest power
dissipation in the top MOSFET.
Each controller includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch previously described is overridden. If the
output falls below 70% of its nominal output level, then
the maximum sense voltage is progressively lowered from
75mV to 25mV. Under short-circuit conditions with very
low duty cycles, the controller will begin cycle skipping
in order to limit the short-circuit current. In this situation,
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time tON(MIN)
of each controller (typically 100ns), the input voltage and
inductor value:
∆IL(SC) = tON(MIN) (VIN/L)
The resulting short-circuit current is:
ISC =
25mV 1
– ∆I
RSENSE 2 L(SC)
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the controller
is operating.
A comparator monitors the output for overvoltage conditions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage. When
this condition is sensed, the top MOSFET is turned off
and the bottom MOSFET is turned on until the overvoltage condition is cleared. The output of this comparator
is only latched by the overvoltage condition itself and
will, therefore, allow a switching regulator system having a poor PC layout to function while the design is being
debugged. The bottom MOSFET remains on continuously
for as long as the OV condition persists. If VOUT returns
to a safe level, normal operation automatically resumes. A
shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Phase-Locked Loop and Frequency Synchronization
The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This allows the top MOSFET turn-on to be locked to the rising
edge of an external source. The frequency range of the
voltage controlled oscillator is ± 50% around the center
frequency fO. A voltage applied to the PLLFLTR pin of 1.2V
corresponds to a frequency of approximately 400kHz. The
nominal operating frequency range of the IC is 260kHz to
550kHz.
The phase detector used is an edge-sensitive digital type
which provides zero degrees phase shift between the external and internal oscillators. This type of phase detector
will not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, ∆fH,
is equal to the capture range, ∆fC:
∆fH = ∆fC = ±0.5 fO (260kHz-550kHz)
3728lxff
23
LTC3728L/LTC3728LX
Applications Information
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin.
If the external frequency (fPLLIN) is greater than the oscillator frequency, f0SC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency is
less than f0SC, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus, the voltage on the PLLFLTR pin
is adjusted until the phase and frequency of the external
and internal oscillators are identical. At this stable operating point, the phase comparator output is open and the
filter capacitor CLP holds the voltage. The IC’s PLLIN pin
must be driven from a low impedance source such as a
logic gate located close to the pin. When using multiple
ICs for a phase-locked system, the PLLFLTR pin of the
master oscillator should be biased at a voltage that will
guarantee the slave oscillator(s) ability to lock onto the
master’s frequency. A DC voltage of 0.7V to 1.7V applied
to the master oscillator’s PLLFLTR pin is recommended
in order to meet this requirement. The resultant operating
frequency can range from 300kHz to 500kHz.
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The typical tested minimum on-time is 100ns under an ideal
condition without switching noise. However, the minimum
on-time can be affected by PCB switching noise in the
voltage and current loops. With a reasonably good PCB
layout, a minimum 30% inductor current ripple, approximately 15mV sensing ripple voltage and 200ns minimum
on-time are conservative estimates for starting a design.
FCB Pin Operation
The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components, CLP and RLP , determine how fast the loop
acquires lock. Typically, RLP = 10kΩ and CLP is 0.01µF
to 0.1µF.
The FCB pin can be used to regulate a secondary winding
or as a logic-level input. Continuous operation is forced
on both controllers when the FCB pin drops below 0.8V.
During continuous mode, current flows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
When primary load currents are low and/or the VIN /VOUT
ratio is low, the synchronous switch may not be on for a
sufficient amount of time to transfer power from the output
capacitor to the secondary load. Forced continuous operation will support secondary windings providing there is
sufficient synchronous switch duty factor. Thus, the FCB
input pin removes the requirement that power must be
drawn from the inductor primary in order to extract power
from the auxiliary windings. With the loop in continuous
mode, the auxiliary outputs may nominally be loaded
without regard to the primary output load.
Minimum On-Time Considerations
The secondary output voltage, VSEC, is normally set as
shown in Figure 6a by the turns ratio N of the transformer:
Minimum on-time, tON(MIN), is the smallest time duration that each controller is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
VOUT
VIN (f)
VSEC @ (N + 1) VOUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then VSEC will droop. An external resistive divider from
VSEC to the FCB pin sets a minimum voltage VSEC(MIN):
R6
VSEC(MIN) ≈ 0.8V 1+
R5
where R5 and R6 are shown in Figure 2.
3728lxff
24
LTC3728L/LTC3728LX
applications information
If VSEC drops below this level, the FCB voltage forces
temporary continuous switching operation until VSEC is
again above its minimum.
In order to prevent erratic operation if no external connections are made to the FCB pin, the FCB pin has a 0.18µA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
The following table summarizes the possible states available on the FCB pin:
Table 1
FCB Pin
Condition
0V to 0.75V
Forced Continuous Both Controllers
(Current Reversal Allowed— Burst Inhibited)
0.85V < VFCB < 4.3V
Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Feedback Resistors
Regulating a Secondary Winding
>4.8V
Burst Mode Operation Disabled
Constant-Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added
to either or both controllers by loading the ITH pin with
a resistive divider having a Thevenin equivalent voltage
source equal to the midpoint operating voltage range of
the error amplifier, or 1.2V (see Figure 8).
INTVCC
RT2
ITH
RT1
RC
LTC3728L/
LTC3728LX
CC
3728 F08
Figure 8. Active Voltage Positioning
Applied to the LTC3728L/LTC3728LX
The resistive load reduces the DC loop gain while maintaining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
reduced to half, or alternatively the amount of output
capacitance can be reduced for a particular application.
A complete explanation is included in Design Solutions
10 (see www.linear.com).
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3728L/LTC3728LX circuits: 1) IC VIN current
(including loading on the 3.3V internal regulator), 2) INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1. The VIN current has two components: the first is the
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control currents; the second is the current drawn from the 3.3V
linear regulator output. VIN current typically results in
a small (1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
50A IPK RATING
12V
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging
into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery and
double-battery.
Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 9 is the most straightforward
approach to protect a DC/DC converter from the ravages of
an automotive power line. The series diode prevents current
from flowing during reverse-battery, while the transient
suppressor clamps the input voltage during load-dump.
Note that the transient suppressor should not conduct
during double-battery operation, but must still clamp the
input voltage below breakdown of the converter. Although
the LTC3728L/LTC3728LX have a maximum input voltage
of 30V, most applications will also be limited to 30V by
the MOSFET BVDSS.
VIN
LTC3728L/
LTC3728LX
3728 F09
Figure 9. Automotive Application Protection
3728lxff
27
LTC3728L/LTC3728LX
Applications Information
Design Example
As a design example for one channel, assume VIN = 12V
(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A and
f = 300kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLFLTR
pin to a resistive divider from the INTVCC pin, generating
0.7V for 300kHz operation. The minimum inductance for
30% ripple current is:
∆IL =
VOUT VOUT
1–
(f)(L)
VIN
A 4.7µH inductor will produce 23% ripple current and a
3.3µH will result in 33%. The peak inductor current will be
the maximum DC value plus one half the ripple current, or
5.84A, for the 3.3µH value. Increasing the ripple current will
also help ensure that the minimum on-time of 200ns is not
violated. The minimum on-time occurs at maximum VIN:
tON(MIN) =
VOUT
VIN(MAX)f
=
1.8V
= 273ns
22V(300kHz)
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
RSENSE ≤
60mV
≈ 0.01Ω
5.84A
Since the output voltage is below 2.4V, the output resistive
divider will need to be sized to not only set the output voltage
but also to absorb the SENSE pin’s specified input current.
0.8V
R1(MAX) = 24k
2.4V – VOUT
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF. At
maximum input voltage with T(estimated) = 50°C:
1.8V 2
PMAIN =
(5) [1+ (0.005)(50°C – 25°C)] •
22V
5A
(0.035Ω ) + (22V )2 ( 4Ω )(215pF ) •
2
1
1
5 – 2.3 + 2.3 ( 300kHz ) = 332mW
A short-circuit to ground will result in a folded back
current of:
ISC =
25mV 1 120ns(22V)
–
= 2.1A
0.01Ω 2 3.3µH
with a typical value of RDS(ON) and d = (0.005/°C)(20) = 0.1.
The resulting power dissipated in the bottom MOSFET is:
22V – 1.8V
PSYNC =
(2.1A )2 (1.125)(0.022Ω )
22V
=
100mW
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VORIPPLE = RESR (∆IL) = 0.02Ω(1.67A) = 33mVP–P
0.8V
= 24k
= 32k
2.4V – 1.8V
3728lxff
28
LTC3728L/LTC3728LX
applications information
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 10. Figure 11 illustrates the current waveforms present in the various branches of the
2‑phase synchronous regulators operating in the continuous mode. Check the following in your layout:
1. Are the top N‑channel MOSFETs M1 and M3 located within 1cm of each other with a common drain connection
at CIN? Do not attempt to split the input decoupling for
the two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) terminals. The path formed by the top N‑channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop just described.
3. Do the LTC3728L/LTC3728LX VOSENSE pins’ resistive
dividers connect to the (+) terminals of COUT? The resistive divider must be connected between the (+) terminal
of COUT and signal ground. The R2 and R4 connections
should not be along the high current input feeds from
the input capacitor(s).
4. Are the SENSE – and SENSE + leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing
with Kelvin connections at the SENSE resistor.
5. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve
noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback pins. All of these nodes have very large and fast
moving signals and therefore should be kept on the
output side of the LTC3728L/LTC3728LX and occupy
minimum PC trace area.
7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
3728lxff
29
LTC3728L/LTC3728LX
Applications Information
RPU
PGOOD
SENSE1+
TG1
SENSE1–
SW1
VOSENSE1
BOOST1
PLLFLTR
VIN
INTVCC
3.3VOUT
ITH2
PGND
CVIN
CINTVCC
VIN
1µF
CERAMIC
CIN
M3
BOOST2
D1
COUT1
GND
COUT2
1µF
CERAMIC
BG2
M4
D2
CB2
VOSENSE2
SW2
SENSE2–
TG2
SENSE2+
RIN
M2
VOUT1
+
FCB
EXTVCC
LTC3728L/LTC3728LX
ITH1
INTVCC
SGND
3.3V
BG1
M1
RSENSE
+
PLLIN
+
fIN
R4
L1
CB1
R1
R3
PGOOD
+
R2
RUN/SS1
VPULL-UP
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