LTC3735
2-Phase, High Efficiency
DC/DC Controller for
Intel Mobile CPUs
DESCRIPTION
FEATURES
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Output Stages Operate Antiphase
±1% Output Voltage Accuracy
6-Bit IMVP-IV VID Code: VOUT = 0.7V to 1.708V
Intel Compatible Power Saving Mode (PSIB)
Stage Shedding Improves Low Current Efficiency
Power Good Output with Adaptive Masking
Lossless Voltage Positioning
Dual Input Supply Capability for Load Sharing
Resistor Programmable VOUT at Boot-Up and Deeper
Sleep State
Resistor Programmable Deep Sleep Offset
Programmable Fixed Frequency: 210kHz to 550kHz
Adjustable Soft-Start Current Ramping
Foldback Output Current Limit
Short-Circuit Shutdown Timer with Defeat Option
Overvoltage Protection
Available in 36-Lead SSOP (0.209 Wide) and 38-Lead
(5mm × 7mm) Packages
The LTC®3735 is a 2-phase synchronous step-down
switching regulator controller that drives all N-channel
power MOSFETs in a constant frequency architecture. The
output voltage is programmable by six VID bits during
normal operation and by external resistors during initial
boot-up and deeper sleep state. The LTC3735 drives its two
output stages out-of-phase at frequencies up to 550kHz
to minimize the RMS ripple currents in both input and
output capacitors. This antiphase technique also doubles
the apparent switching frequency, improving the transient
response while operating each phase at an optimum frequency for efficiency. Thermal design is further simplified
by cycle-by-cycle current sharing between the two phases.
An Intel compatible PSIB input is provided to select between
two modes of operation. Fully enhanced synchronous
mode achieves a very small output ripple and very fast
transient response while power saving mode realizes
very high efficiency. OPTI-LOOP® compensation allows
the transient response to be optimized for a wide range
of output capacitance and ESR values.
APPLICATIONS
Mobile and Desktop Computers
Internet Servers
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L, LT, LTC, LTM, OPTI-LOOP, PolyPhase, Linear Technology and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
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TYPICAL APPLICATION
MCH_PG
DPRSLPVR
STP_CPUB
PSIB
FREQSET
VID5-VID0
PGOOD
ITH
RC
4.74k
CC
470pF
100pF
232k
BG1
1µH
M2
0.002Ω
VIN
5V TO 24V
D1
PGND
SENSE1+
SENSE1–
RUN/SS
+
M3
TG2
1µH
SW2
0.1µF
SGND
VOA+
M1
TG1
SW1
M4
BG2
0.002Ω
COUT
330µF
2V
×5
VOUT
0.7V TO 1.708V
40A
CIN
10µF
35V
×4
D2
LTC3735
PVCC
4.5V TO 7V
SENSE2+
SENSE2–
4.7µF
RBOOT
BAT54A
0.47µF
0.47µF
SW2
SW1
BOOST1 RDPRSLP
BOOST2 RDPSLP
VOA+
OAOUT
VOA–
12.7k
13.3k
56.2k
1.27M
13.3k
549k
VOA+
3735 F01
Figure 1. High Current 2-Phase Step-Down Converter
3735fa
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LTC3735
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (PVCC)........................ 7V to – 0.3V
Topside Driver Voltages (BOOST1,2).......... 38V to –0.3V
Switch Voltage (SW1, 2)................................ 32V to –5V
Boosted Driver Voltages
(BOOST1-SW1, BOOST2-SW2)................ 7V to –0.3V
DPRSLPVR, STP_CPUB, MCH_PG, PGOOD,
RDPRSLP, RDPSLP, RBOOT Voltages .......... 5V to –0.3V
RUN/SS, PSIB, FREQSET Voltages ..............7V to – 0.3V
VID0-VID5 Voltages .....................................5V to – 0.3V
VFB, Voltage................................................. 2V to –0.3V
VOA+, VOA– ................................................ 3.6V to –0.3V
Peak Gate Drive Current 120dB and the unity-gain bandwidth is 2MHz.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Short-Circuit Detection
The RUN/SS capacitor is used initially to limit the inrush current from the input power source. Once the
controllers have been given time, as determined by the
capacitor on the RUN/SS pin, to charge up the output
capacitors and provide full-load current, the RUN/SS
capacitor is then used as a short-circuit timeout circuit.
If the output voltage falls to less than 70% of its nominal
output voltage the RUN/SS capacitor begins discharging assuming that the output is in a severe overcurrent
and/or short-circuit condition. If the condition lasts for
a long enough period as determined by the size of the
RUN/SS capacitor, the controller will be shut down until the
RUN/SS pin voltage is recycled. This built-in latchoff can
be overidden by providing a current >5µA to the RUN/SS
pin. This current shortens the soft-start period but also
prevents net discharge of the RUN/SS capacitor during a
severe overcurrent and/or short-circuit condition. Foldback
current limiting is activated when the output voltage falls
below 70% of its nominal level whether or not the shortcircuit latchoff circuit is enabled.
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LTC3735
APPLICATIONS INFORMATION
biased with a resistor divider to prevent noise getting
into the system.
A graph for the voltage applied to the FREQSET pin vs frequency is given in Figure 2. As the operating frequency is
increased the gate drive and switching losses will be higher,
reducing efficiency (see Efficiency Considerations). The
maximum switching frequency is approximately 550kHz.
600
550
OPERATING FREQUENCY (kHz)
The basic LTC3735 application circuit is shown in
Figure 1 on the first page of this data sheet. External component selection begins with the selection of the inductors
based on ripple current requirements and continues with
the current sensing resistors using the calculated peak
inductor current and/or maximum current limit. Next, the
power MOSFETs, D1 and D2 are selected. The operating
frequency and the inductor are chosen based mainly on
the amount of ripple current. Finally, CIN is selected for its
ability to handle the input ripple current (that PolyPhase®
operation minimizes) and COUT is chosen with low enough
ESR to meet the output ripple voltage and load step
specifications (also minimized with PolyPhase). Current
mode architecture provides inherent current sharing between output stages. The circuit shown in Figure 1 can
be configured for operation up to an input voltage of 28V
(limited by the external MOSFETs). Current mode control
allows the ability to connect the two output stages to two
different input power supply rails. A heavy output load
can take some power from each input supply according
to the selection of the RSENSE resistors.
500
450
400
350
300
250
200
150
100
0
0.5
1.0
1.5
2.0
2.5
FREQSET PIN VOLTAGE (V)
3.0
3735 F02
Figure 2. Operating Frequency vs VFREQSET
RSENSE Selection For Output Current
Inductor Value Calculation and Output Ripple Current
RSENSE1,2 are chosen based on the required peak output
current. The LTC3735 current comparator has a maximum
threshold of 72mV/RSENSE and an input common mode
range of SGND to PVCC. The current comparator threshold
sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak value less half
the peak-to-peak ripple current, ∆IL.
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
MOSFET gate charge and transition losses increase
directly with frequency. In addition to this basic tradeoff,
the effect of inductor value on ripple current and low current operation must also be considered. The PolyPhase
approach reduces both input and output ripple currents
while optimizing individual output stages to run at a lower
fundamental frequency, enhancing efficiency.
Assuming a common input power source for each output stage and allowing a margin for variations in the
LTC3735 and external component values yields:
RSENSE = 2(40mV/IMAX)
Operating Frequency
The LTC3735 uses a constant frequency architecture with
the frequency determined by an internal capacitor. This
capacitor is charged by a fixed current plus an additional
current which is proportional to the DC voltage applied
to the FREQSET pin. The FREQSET voltage is internally
set to 1.2V. It is recommended that this pin is actively
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆IL, decreases with higher
inductance or frequency and increases with higher VIN:
∆IL =
VOUT VOUT
1−
fL
VIN
where f is the individual output stage operating frequency.
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LTC3735
APPLICATIONS INFORMATION
In a 2-phase converter, the net ripple current seen by
the output capacitor is much smaller than the individual
inductor ripple currents due to ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Linear Technology Application Note 77.
Figure 3 shows the net ripple current seen by the output
capacitors for 1- and 2-phase configurations. The output
ripple current is plotted for a fixed output voltage as the
duty factor is varied between 10% and 90% on the x‑axis.
The graph can be used in place of tedious calculations,
simplifying the design process.
Accepting larger values of ∆IL allows the use of low inductances, but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
∆IL = 0.4(IOUT)/2, where IOUT is the total load current.
Remember, the maximum ∆IL occurs at the maximum
input voltage. The individual inductor ripple currents
are determined by the frequency, inductance, input and
output voltages.
1.0
1-PHASE
2-PHASE
0.9
0.8
0.6
VO/fL
∆IO(P-P)
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
A variety of inductors designed for high current, low voltage applications are available from manufacturers such
as Sumida, Coilcraft, Coiltronics, Toko and Panasonic.
Power MOSFET, D1 and D2 Selection
Two external power MOSFETs must be selected for each
output stage with the LTC3735: one N-channel MOSFET
for the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the PVCC voltage. This voltage typically ranges from 4.5V to 7V. Consequently, logic-level threshold MOSFETs must be used
in most applications. Pay close attention to the BVDSS
specification for the MOSFETs as well; most of the logiclevel MOSFETs are limited to 30V or less.
0.7
0.5
0.4
0.3
0.2
0.1
0
is very dependent on inductor type selected. As inductance
increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore copper losses will increase.
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8
0.9
3735 F03
Figure 3. Normalized Output Ripple Current
vs Duty Factor [IRMS ≈ 0.3 (∆IO(P-P)]
Inductor Core Selection
Once the values for L1 and L2 are known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ cores. Actual core loss
is independent of core size for a fixed inductor value, but it
Selection criteria for the power MOSFETs include the “ON”
resistance RDS(ON), gate charge QG, reverse transfer capacitance CRSS, breakdown voltage BVDSS and maximum
continuous drain current ID(MAX).
When the LTC3735 is operating at continuous mode in a
step-down configuration, the duty cycles for the top and
bottom MOSFETs of each power stage are approximately:
Top MOSFET Duty Cycle =
VOUT
VIN
Bottom MOSFET Duty Cycle =
VIN – VOUT
VIN
(1)
(2)
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LTC3735
APPLICATIONS INFORMATION
The conduction losses of the top and bottom MOSFETs
are therefore:
PCONTOP =
VOUT
VIN
2
I
• OUT • (1+ δ • ∆T ) •RDS(ON)(3)
2
V –V
PCONBOT = IN OUT
VIN
2
I
• OUT • (1+ δ • ∆T )
2
(4)
• RDS(ON)
where IOUT is the total output current at full load, ∆T is the
difference between MOSFET operating temperature and
room temperature, and δ is the temperature dependency
of RDS(ON). δ is roughly 0.004/°C ~ 0.006/°C for low voltage MOSFETs.
The power losses of driving the top and bottom MOSFETs
are simply:
PDRTOP = QG • PVCC • f
(5)
PDRBOT = QG • PVCC • f
(6)
Use QG data at VGS = PVCC in MOSFET data sheets. f is
the switching frequency as described previously. Please
notice that the above gate driving losses are usually not
dissipated by the MOSFETs. Instead they are mainly dissipated on the internal drivers of the LTC3735, if there are
no resistors connected between the drive pins (TG, BG)
and the gates of the MOSFETs.
The calculation of MOSFET switching loss is complicated
by several factors including the wide distribution of power
MOSFET threshold voltage, the nonlinearity of current rising/falling characteristic and the Miller Effect. Given the
data in a typical power MOSFET data sheet, the switching losses of the top and bottom MOSFETs can only be
estimated as follows:
V 2 •I
PSWTOP = IN OUT • f • CRSS •RDR •
4
per Phase
1
1
+
VDR – VTH(MIN) VTH(MIN)
PSWBOT ≈ 0
(7)
(8)
where RDR is the effective driver resistance (of approximately 2Ω), VDR is the driving voltage (= PVCC) and VTH(MIN)
is the minimum gate threshold voltage of the MOSFET.
Please notice that the switching loss of the bottom MOSFET
is effectively negligible because the current conduction of
the antiparalleling diode. This effect is often referred as
zero-voltage-transition (ZVT). Similarly when the LTC3735
converter works under fully synchronous mode at light
load, the reverse inductor current can also go through
the body diode of the top MOSFET and make the turn-on
loss to be negligible. However, equations 7 and 8 have to
be used in calculating the worst-case power loss, which
happens at highest load level.
The selection criteria of power MOSFETs start with the
stress check:
VIN < BVDSS
IMAX < ID(MAX)
and
PCONTOP + PSWTOP < top MOSFET maximum power
dissipation specification
PCONBOT + PSWBOT < bottom MOSFET maximum power
dissipation specification
The maximum power dissipation allowed for each MOSFET
depends heavily on MOSFET manufacturing and packaging, PCB layout and power supply cooling method.
Maximum power dissipation data are usually specified
in MOSFET data sheets under different PCB mounting
conditions.
The next step of selecting power MOSFETs is to minimize
the overall power loss:
POVL = PTOP + PBOT
= (PCONTOP + PDRTOP + PSWTOP) + (PCONBOT +
PDRBOT + PSWBOT)
For typical mobile CPU applications where the ratio between
input and output voltages is higher than 2:1, the bottom
MOSFET conducts load current most of the time while
the main losses of the top MOSFET are for switching and
driving. Therefore a low RDS(ON) part (or multiple parts in
parallel) would minimize the conduction loss of the bottom
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LTC3735
APPLICATIONS INFORMATION
CIN and COUT Selection
In continuous mode, the source current of each top
N‑channel MOSFET is a square wave of duty cycle VOUT/
VIN. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a closed form
equation can be found in Linear Technology Application
Note 77. Figure 4 shows the input capacitor ripple current
for a 2-phase configuration with the output voltage fixed
and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be
used in place of tedious calculations. The minimum input
ripple current can be achieved when the input voltage is
twice the output voltage.
In the graph of Figure 4, the 2-phase local maximum input
RMS capacitor currents are reached when:
VOUT 2k − 1
=
VIN
4
0.6
1-PHASE
2-PHASE
0.5
DC LOAD CURRENT
The Schottky diodes, D1 and D2 in Figure 1 conduct during the dead-time between the conduction of the top and
bottom MOSFETs. This helps reduce the current flowing
through the body diode of the bottom MOSFET. A body
diode usually has a forward conduction voltage higher than
that of a Schottky and is thus detrimental to efficiency. The
charge storage and reverse recovery of a body diode also
cause high frequency rings at the switching nodes (the
conjunction nodes between the top and bottom MOSFETs),
which are again not desired for efficiency or EMI. Some
power MOSFET manufacturers integrate a Schottky diode
with a power MOSFET, eliminating the need to parallel an
external Schottky. These integrated Schottky-MOSFETs,
however, have smaller MOSFET die sizes than conventional
parts and are thus not suitable for high current applications.
or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled to meet size or height requirements in the design.
Always consult the capacitor manufacturer if there is any
question.
RMS INPUT RIPPLE CURRNET
MOSFET while a higher RDS(ON) but lower QG and CRSS
part would be desirable for the top MOSFET.
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8
0.9
3735 F04
Figure 4. Normalized RMS Input Ripple Current
vs Duty Factor for 1 and 2 Output Stages
It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a
2‑phase implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the reduction of the input ripple current in a 2-phase system. The
required amount of input capacitance is further reduced
by the factor, 2, due to the reduction in input RMS current.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR requirement has been met, the RMS current rating generally far
exceeds the IRIPPLE(P-P) requirements. The steady state
output ripple (∆VOUT) is determined by:
where k = 1, 2
1
∆VOUT ≈ ∆IRIPPLE ESR +
16 • f • COUT
These worst-case conditions are commonly used for
design, considering input/output variations and long
term reliability. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor,
∆IRIPPLE can be calculated from the duty factor and the
∆IL of each stage. A closed form equation can be found in
where f = operating frequency of each stage, COUT =
output capacitance and ∆IRIPPLE = interleaved inductor
ripple currents.
3735fa
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LTC3735
APPLICATIONS INFORMATION
Linear Technology Application Note 77. Assuming inductors are selected to have same ripple percentage for both
1-phase and 2-phase configurations, Figure 5 shows the
reduction of output ripple current by 2-phase operation.
Not only the ripple amplitude is more than halved, but
the ripple frequency is also doubled. Compared with the
output voltage ripple for 1-phase:
1
∆VOUT ≈ ∆IRIPPLE ESR +
8 • f • COUT
∆VOUT of 2-phase is less than 50% of that of 1-phase, given
the same output capacitor ESRs. Or, to have same ∆VOUT
2-phase only need half the number of output capacitors
that are needed in 1-phase.
The output ripple varies with input voltage since ∆IL is a
function of input voltage. The output ripple will be less than
±25mV at max VIN with ∆IL = 0.4IOUT(MAX)/2 assuming:
COUT required ESR < 4(RSENSE) and
COUT > 1/(16f)(RSENSE)
The LTC3735 employs OPTI-LOOP technique to compensate the switching regulator loop with external components
(through ITH pin). OPTI-LOOP compensation speeds
up regulator’s transient response, minimizes output
capacitance and effectively removes constraints on output
capacitor ESR. It opens a much wider selection of output
capacitor types and a variety of capacitor manufactures are
available for high current, low voltage switching regulators.
∆IRIPPLE OF 2-PHASE
• 100%
∆IRIPPLE OF 1-PHASE
50
40
30
20
10
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8 0.9
3735 F05
Manufacturers such as Nichicon, United Chemicon
and Sanyo should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
dielectric capacitor available from Sanyo has the lowest
(ESR)(size) product of any aluminum electrolytic at a
somewhat higher price. An additional ceramic capacitor
in parallel with OS-CON type capacitors is recommended
to reduce the inductance effects.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer (SP)
surface mount capacitors from Panasonic offer very low
ESR also but have much lower capacitive density per unit
volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies.
Several excellent choices are the AVX TPS, AVX TPSV or the
KEMET T510 series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. Other capacitor
types include Sanyo OS-CON, POSCAPs, Kemet AO-CAPs,
Nichicon PL series and Sprague 595D series. Consult
the manufacturer for other specific recommendations. A
combination of capacitors will often result in maximizing
performance and minimizing overall cost and size.
PVCC Decoupling
The PVCC pin supplies power to the top and bottom gate
drivers and therefore must be bypassed to power ground
with a minimum of 4.7µF ceramic or tantalum capacitor.
Since the gate driving currents are of high amplitude and
high slew rate, this bypassing capacitor should be placed
very close to the PVCC and PGND pins to minimize the
parasitic inductance. Do NOT apply greater than 7V to
the PVCC pin.
The PVCC pin also supplies current to the internal control
circuitry of the LTC3735. This supply current is much
lower than that of the current for the external MOSFET
gate drive. Ceramic capacitors are very good for high
frequency filtering and a 0.1µF ~ 1µF ceramic capacitor
should be placed adjacent to the PVCC and SGND pins.
Figure 5. Output Ripple Current Reduction
of 2-Phase Over Single Phase
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LTC3735
APPLICATIONS INFORMATION
Topside MOSFET Driver Supply (CB,DB) (Refer to
Functional Diagram)
External bootstrap capacitors CB1 and CB2 connected to the
BOOST1 and BOOST2 pins supply the gate drive voltages
for the topside MOSFETs. Capacitor CB in the Functional
Diagram is charged though diode DB from PVCC when the
SW pin is low. When the topside MOSFET turns on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin rises to VIN + PVCC. The value of
the boost capacitor CB needs to be 30 to 100 times that of
the total input capacitance of the topside MOSFET(s). The
reverse breakdown of DB must be greater than PVCC(MAX).
VID Output Voltage Programming
After 27µs ~ 71µs tBOOT delay, the output voltage of the
regulator is digitally programmed as defined in Table 2
using the VID0 to VID5 logic input pins. The VID logic
inputs program a precision, 0.25% internal feedback resistive divider. The LTC3735 has an output voltage range
of 0.700V to 1.708V in 16mV steps.
Refering to the Functional Diagram, there is a resistor,
RVID, from VFB to ground. The value of RVID is controlled
by the six VID input pins. Another internal resistor, 5.33k
(RATTEN), completes the resistive divider. The output voltage
is thus set by the ratio of (RVID + 5.33k) to RVID.
An internal 1.5µA current source charges up the soft-start
capacitor, CSS. When the voltage on RUN/SS reaches 1.5V,
the controller is permitted to start operating. As the voltage on RUN/SS increases from 1.5V to 3.0V, the internal
current limit is increased from 25mV/RSENSE to 72mV/
RSENSE. The output current thus ramps up slowly, eliminating the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:
1.5V
tDELAY =
CSS = (1s/µF ) CSS
1.5µA
The time for the output current to ramp up is then:
3V − 1.5V
tIRAMP =
C = (1s/µF ) CSS
1.5µA SS
By pulling the RUN/SS pin below 1V the LTC3735 is put
into low current shutdown (IQ < 100µA). The RUN/SS pin
can be driven directly from logic as shown in Figure 6.
Diode D1 in Figure 6 reduces the start delay but allows
CSS to ramp up slowly providing the soft-start function.
The RUN/SS pin has an internal 6V zener clamp (see
Functional Diagram).
PVCC
3.3V OR 5V
D1
RUN/SS
RSS*
CSS
Each VID digital pin is a high impedance input. Therefore they must be actively pulled high or pulled low. The
logic low threshold of the VID pins is 0.3V; the logic high
threshold is 0.7V.
RUN/SS
CSS
3735 F06
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
Figure 6. RUN/SS Pin Interfacing
Soft-Start/Run Function
Start-Up Sequence (Refer to the Functional Diagram)
The RUN/SS pin provides three functions: 1) run/shutdown,
2) soft-start and 3) an optional short-circuit latchoff timer.
Soft-start reduces the input power sources’ surge currents
by gradually increasing the controller’s current limit. The
latchoff timer prevents very short, extreme load transients
from tripping the overcurrent latch. A small pull-up current (>5µA) supplied to the RUN/SS pin will prevent the
overcurrent latch from operating. The following paragraph
describes how the functions operate.
After soft-start, the output voltage of the regulator settles
at a voltage level equal to VBOOT.
VBOOT = 0.6V •
R2 • (R3 +R5)
R5 • (R1+R2)
By using different R5 resistors, VBOOT can be programmed.
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LTC3735
APPLICATIONS INFORMATION
Table 2. VID Output Voltage Programming
VID5
VID4
VID3
VID2
VID1
VID0
LTC3735
VID5
VID4
VID3
VID2
VID1
VID0
LTC3735
0
0
0
0
0
0
1.708V
1
0
0
0
0
0
1.196V
0
0
0
0
0
1
1.692V
1
0
0
0
0
1
1.180V
0
0
0
0
1
0
1.676V
1
0
0
0
1
0
1.164V
0
0
0
0
1
1
1.660V
1
0
0
0
1
1
1.148V
0
0
0
1
0
0
1.644V
1
0
0
1
0
0
1.132V
0
0
0
1
0
1
1.628V
1
0
0
1
0
1
1.116V
0
0
0
1
1
0
1.612V
1
0
0
1
1
0
1.100V
0
0
0
1
1
1
1.596V
1
0
0
1
1
1
1.084V
0
0
1
0
0
0
1.580V
1
0
1
0
0
0
1.068V
0
0
1
0
0
1
1.564V
1
0
1
0
0
1
1.052V
0
0
1
0
1
0
1.548V
1
0
1
0
1
0
1.036V
0
0
1
0
1
1
1.532V
1
0
1
0
1
1
1.020V
0
0
1
1
0
0
1.516V
1
0
1
1
0
0
1.004V
0
0
1
1
0
1
1.500V
1
0
1
1
0
1
0.988V
0
0
1
1
1
0
1.484V
1
0
1
1
1
0
0.972V
0
0
1
1
1
1
1.468V
1
0
1
1
1
1
0.956V
0
1
0
0
0
0
1.452V
1
1
0
0
0
0
0.940V
0
1
0
0
0
1
1.436V
1
1
0
0
0
1
0.924V
0
1
0
0
1
0
1.420V
1
1
0
0
1
0
0.908V
0
1
0
0
1
1
1.404V
1
1
0
0
1
1
0.892V
0
1
0
1
0
0
1.388V
1
1
0
1
0
0
0.876V
0
1
0
1
0
1
1.372V
1
1
0
1
0
1
0.860V
0
1
0
1
1
0
1.356V
1
1
0
1
1
0
0.844V
0
1
0
1
1
1
1.340V
1
1
0
1
1
1
0.828V
0
1
1
0
0
0
1.324V
1
1
1
0
0
0
0.812V
0
1
1
0
0
1
1.308V
1
1
1
0
0
1
0.796V
0
1
1
0
1
0
1.292V
1
1
1
0
1
0
0.780V
0
1
1
0
1
1
1.276V
1
1
1
0
1
1
0.764V
0
1
1
1
0
0
1.260V
1
1
1
1
0
0
0.748V
0
1
1
1
0
1
1.244V
1
1
1
1
0
1
0.732V
0
1
1
1
1
0
1.228V
1
1
1
1
1
0
0.716V
0
1
1
1
1
1
1.212V
1
1
1
1
1
1
0.700V
3735fa
18
LTC3735
APPLICATIONS INFORMATION
After the output voltage enters the ±10% regulation window
centered at VBOOT, the internal power good comparator
issues a logic high signal. Refer to the timing diagram in
Figure 7. This signal then enters a logic AND gate, with
MCH_PG being the other input, and the output of the gate
is PG shown in Figure 7. This composite PG signal is then
delayed by tBOOT amount of time and then becomes MD.
As soon as MD is asserted, the output voltage changes
from VBOOT to VVID, a voltage level totally controlled by
the six VID bits. In the LTC3735, the time tBOOT is set to
be 15 switching cycles:
1
tBOOT = 15
fS
Output Voltage Set in Deep Sleep and Deeper Sleep
States (Refer to the Functional Diagram)
If fS is set at 210kHz, tBOOT = 71µs
The output voltage could also be set by external resistors
R6 and R4 when DPRSLPVR input is high. This state is
defined to be the deeper sleep state. The output voltage
is set to VDPRSLPVR, regardless of the VID setting:
If fS is set at 550kHz, tBOOT = 27µs
RUN/SS
VVID
STP% = –
R3
• 100%
R3 +R4
By using different R4 resistors, STP_CPUB offset can be
programmed.
1.5V
VBOOT
VDPRSLPVR = 0.6V •
R2 • (R3 +R6||R4)
(R6||R4) • (R1+R2)
By using different value R6 resistors, VDPRSLPVR can be
programmed.
VOUT
90% VBOOT
(The digital input threshold voltage is set to 1.8V for
STP_CPUB, DPRSLPVR and MCH_PG inputs.)
INTERNAL PG
(OUTPUT OF
INTERNAL
POWER GOOD
COMPARATOR)
Power Good Masking
The PGOOD output monitors VOUT. When VOUT is not
within ±10% of the set point, PGOOD is pulled low with
an internal MOSFET. When VOUT is within the regulation
window, PGOOD is high impedance. PGOOD should be
pulled up by an external resistor.
MCH_PG
COMPOSITE PG
(=(INTERNAL PG)
AND (MCH_PG))
tBOOT
MD
VID BITS
The output voltage can be offset by the STP_CPUB signal.
When STP_CPUB becomes low, the output voltage will be
a certain percentage lower than that set by the VID bits in
Table 2. This state is defined to be the deep sleep state.
Referring to the Functional Diagram, we can caluculate
the STP_CPUB offset to be:
VALID
INVALID
TIME
3735 F07
During VID changes, deep sleep and deeper sleep transitions, the output voltage can initially be out of the ±10%
window of the newly set regulation point. To avoid nuisance indications from PGOOD, a timer masks PGOOD for
110µs. If VOUT is still out of regulation after this blanking
time, PGOOD goes low. Any overvoltage or undervoltage
condition is also masked for 110µs before it is reported
by PGOOD.
Figure 7. Start-Up Timing Diagram
3735fa
19
LTC3735
APPLICATIONS INFORMATION
The masking circuitry also adaptively tracks VID and state
changes. If a new change in VID or state happens before
the 110µs masking timer expires, the timer resets and
starts a fresh count of 110µs. This prevents the system
from rebooting under frequent output voltage transitions.
Refer to Figure 8 for the PGOOD timing diagram.
begins discharging on the assumption that the output is in
an overcurrent condition. If the condition lasts for a long
enough period as determined by the size of the CSS, the
controller will be shut down until the RUN/SS pin voltage
is recycled. If the overload occurs during start-up, the
time can be approximated by:
During start-up, PGOOD is actively pulled low until the RUN/
SS pin voltage reaches its arming voltage, which is 4.2V
typically, only then is the PGOOD pull-low signal released.
When RUN/SS goes low, PGOOD goes low simultaneously.
tLO1 ≈ (CSS • 0.7V)/(1.5µA) = 4.6 • 105 (CSS)
If the overload occurs after start-up, the voltage on CSS
will continue charging and will provide additional time
before latching off:
tLO2 ≈ (CSS • 2V)/(1.5µA) = 1.3 • 106 (CSS)
VID BITS
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, RSS, to the RUN/SS pin as
shown in Figure 6. This resistance shortens the softstart period and prevents the discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
condition. When deriving the 5µA current from PVCC as in
the figure, current latchoff is always defeated.
VOUT
INTERNAL PG
(OUTPUT OF
INTERNAL
POWER GOOD
COMPARATOR)
PGOOD
MASKING
110µs
110µs
PGOOD
TIME
3735 F08
Figure 8. PGOOD Timing Diagram
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to latch off the
controller when an overcurrent condition is detected. The
RUN/SS capacitor, CSS, is used initially to limit the inrush
current. After the controller has been started and been
given adequate time to charge up the output capacitors
and provide full load current, the RUN/SS capacitor is used
for a short-circuit timer. If the output voltage falls to less
than 70% of its nominal value after CSS reaches 4.2V, CSS
Why should you defeat current latchoff? During the prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is complete
whether to rely solely on foldback current limiting or to
enable the latchoff feature by removing the pull-up resistor.
The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capacitance is given by:
CSS > (COUT )(VOUT)(10-4)(RSENSE)
A recommended soft-start capacitor of CSS = 0.1µF will
be sufficient for most applications.
3735fa
20
LTC3735
APPLICATIONS INFORMATION
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3735 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON (MIN ) <
VOUT
VIN ( f )
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3735 will begin to skip
cycles resulting in variable frequency operation. The output
voltage will continue to be regulated, but the ripple current
and ripple voltage will increase.
AVP ≅ –35.5 •
V
if gm •R3 > 10 • OUT
0.6V
(9)
where RSENSE is the current sense resistor, m is the number
of phases, (m = 2 for LTC3735) R3 and RAVP are defined
in Figure 9. gm is the transconductance gain for the error
amplifier, it is about 4.5mmho for LTC3735. Rewriting
Equation 9 we can estimate the AVP resistor to be:
R AVP ≅
35.5 •R3 •RSENSE
m•| AVP|
(10)
VOUT+
R3
The minimum on-time for the LTC3735 is generally less
than 150ns. However, as the peak sense voltage decreases,
the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger ripple current and ripple voltage.
RAVP
VOA+
R2
+
VOA–
OAOUT
–
R1
If an application can operate close to the minimum
on-time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement. As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of IOUT(MAX) at VIN(MAX).
FB
–
VID
0.6V
ITH
+
3735 F09
Figure 9. Simplified Schematic Diagram
for AVP Design in LTC3735
Active Voltage Positioning
Active voltage positioning can be used to minimize peak-topeak output voltage excursion under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Active voltage positioning can easily be
added to the LTC3735. Figure 9 shows the equivalent circuit
for implementing AVP. The load line slope is estimated to be:
RSENSE R3
•
,
m
R AVP
We also adopt the current sense resistors as part of
voltage positioning slopes. So the total load line slope is
estimated to be:
AVP ≅ –35.5 •
RSENSE R3 RSENSE
•
–
,
m
R AVP
m
V
if gm •R3 >> OUT
0.6V
(11)
3735fa
21
LTC3735
APPLICATIONS INFORMATION
Rewriting this equation, we can estimate the RAVP value
to be:
R AVP≅
35.5 •R3
m •| AVP|
–1
RSENSE
(12)
Typically the calculation results based on these equations
have ±10% tolerance. So the resistor values need to be
fine tuned.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3735 circuits: 1) I2R losses, 2) Topside
MOSFET transition losses, 3) PVCC supply current and
4) CIN loss.
1) I2R losses are predicted from the DC resistances of
the fuse (if used), MOSFET, inductor, and current sense
resistor. In continuous mode the average output current
flows through L and RSENSE, but is “chopped” between the
topside MOSFET and the synchronous MOSFET. If the two
MOSFETs have approximately the same RDS(ON), then the
resistance of one MOSFET can simply be summed with
the resistances of L, RSENSE and ESR to obtain I2R losses.
For example, if each RDS(ON) = 10mΩ, RL = 10mΩ, and
RSENSE = 5mΩ, then the total resistance is 25mΩ. This
results in losses ranging from 2% to 8% as the output
current increases from 3A to 15A per output stage for a 5V
output, or a 3% to 12% loss per output stage for a 3.3V
output. Efficiency varies as the inverse square of VOUT for
the same external components and output power level.
The combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
2) Transition losses apply only to the topside MOSFET(s),
and are significant only when operating at high input voltages (typically 12V or greater). Transition losses can be
estimated from:
Transition Loss =
per Phase
2
VIN
•IOUT
4
• f • CRSS • R DR •
1
1
+
VDR – VTH(MIN) VTH(MIN)
3) PVCC drives both top and bottom MOSFETs. The MOSFET
driver current results from switching the gate capacitance
of the power MOSFETs. Each time a MOSFET gate is
switched from low to high to low again, a packet of charge
dQ moves from PVCC to ground. The resulting dQ/dt is a
current out of PVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG =
(QT + QB)f, where QT and QB are the gate charges of the
topside and bottom side MOSFETs and f is the switching
frequency.
4) The input capacitor has the difficult job of filtering
the large RMS input current to the regulator. It must
have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
The LTC3735 2-phase architecture typically halves the
input and output capacitor requirements over 1-phase
solutions.
Other losses, including COUT ESR loss, Schottky diode
conduction loss during dead time, inductor core loss and
internal control circuitry supply current generally account
for less than 2% additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
3735fa
22
LTC3735
APPLICATIONS INFORMATION
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD(ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The ITH external components shown
in the Figure 1 circuit will provide an adequate starting
point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon first because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of
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