LTC3808
No RSENSETM, Low EMI,
Synchronous DC/DC Controller
with Output Tracking
DESCRIPTIO
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FEATURES
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The LTC®3808 is a synchronous step-down switching
regulator controller that drives external complementary
power MOSFETs using few external components. The
constant frequency current mode architecture with MOSFET
VDS sensing eliminates the need for a current sense
resistor and improves efficiency.
Programmable Output Voltage Tracking
Sense Resistor Optional
Spread Spectrum Modulation for Low Noise
Constant Frequency Current Mode Operation for
Excellent Line and Load Transient Response
Wide VIN Range: 2.75V to 9.8V
Wide VOUT Range: 0.6V to VIN
0.6V ±1.5% Reference
Low Dropout Operation: 100% Duty Cycle
True PLL for Frequency Locking or Adjustment
(Frequency Range: 250kHz to 750kHz)
Selectable Burst Mode®/Pulse Skipping/Forced
Continuous Operation
Auxiliary Winding Regulation
Internal Soft-Start Circuitry
Power Good Output Voltage Monitor
Output Overvoltage Protection
Micropower Shutdown: IQ = 9µA
Tiny Thermally Enhanced Leadless (4mm × 3mm)
DFN or 16-lead SSOP Package
Burst Mode operation provides high efficiency operation
at light loads. 100% duty cycle provides low dropout
operation, extending operating time in battery-powered
systems.
The switching frequency can be programmed up to 750kHz,
allowing the use of small surface mount inductors and
capacitors. For noise sensitive applications, the LTC3808
can be externally synchronized from 250kHz to 750kHz.
Burst Mode is inhibited during synchronization or when
the SYNC/MODE pin is pulled low to reduce noise and RF
interference. To further reduce EMI, the LTC3808 incorporates a novel spread spectrum frequency modulation
technique.
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APPLICATIO S
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, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode
is a registered trademark of Linear Technology Corporation. No RSENSE is a trademark of
Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents including 5481178, 5929620, 6580258, 6304066,
5847554, 6611131, 6498466. Other Patents pending.
One or Two Cell Lithium-Ion Powered Devices
Notebook and Palmtop Computers, PDAs
Portable Instruments
Distributed DC Power Systems
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The LTC3808 is available in the tiny footprint thermally
enhanced DFN package or 16-lead SSOP package.
TYPICAL APPLICATIO
Efficiency and Power Loss vs Load Current
100
10k
EFFICIENCY
High Efficiency, 550kHz Step-Down Converter
1M
LTC3808
PLLLPF
15k
187k
220pF
VIN
SENSE+
SYNC/MODE
59k
10µF
TG
PGOOD
VFB
SW
ITH
BG
2.2µH
IPRG
RUN
+
VOUT
2.5V
2A
VIN = 3.3V
90
VIN = 5V
80
100
TYPICAL POWER
LOSS (VIN = 4.2V)
70
1
FIGURE 11 CIRCUIT
VOUT = 2.5V
50
1
3808 TA01
10
60
47µF
GND
1k
VIN = 4.2V
POWER LOSS (mW)
VIN
2.75V TO 9.8V
EFFICIENCY (%)
■
10
100
1k
LOAD CURRENT (mA)
0.1
10k
3808 TA01b
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LTC3808
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage (VIN)........................ – 0.3V to 10V
PLLLPF, RUN, SYNC/MODE, TRACK/SS,
SENSE+, IPRG Voltages ............ – 0.3V to (VIN + 0.3V)
VFB, ITH Voltages...................................... –0.3V to 2.4V
SW, SENSE– Voltages......... – 2V to VIN + 1V (10V Max)
PGOOD ..................................................... – 0.3V to 10V
TG, BG Peak Output Current ( fSYNC/MODE
fOSC < fSYNC/MODE
–3
3
µA
µA
Spread Spectrum Frequency Range
Minimum Switching Frequency
Maximum Switching Frequency
460
635
kHz
kHz
SYNC/MODE Pull-Down Current
SYNC/MODE = 2.2V
2.6
µA
PGOOD Voltage Low
IPGOOD Sinking 1mA
50
mV
PGOOD Trip Level
VFB with Respect to Set Output Voltage
VFB < 0.6V, Ramping Positive
VFB < 0.6V, Ramping Negative
VFB > 0.6V, Ramping Negative
VFB > 0.6V, Ramping Positive
PGOOD Output
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3808E is guaranteed to meet specified performance from
0°C to 70°C. Specifications over the –40°C to 85°C operating range are
assured by design characterization, and correlation with statistical process
controls.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • θJA °C/W)
–13
–16
7
10
–10.0
–13.3
10.0
13.3
–7
–10
13
16
%
%
%
%
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5: The LTC3808 is tested in a feedback loop that servos ITH to a
specified voltage and measures the resultant VFB voltage.
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as shown in Figure 1.
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LTC3808
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
95 VIN = 5V, VOUT = 2.5V
EFFICIENCY (%)
EFFICIENCY (%)
VOUT = 1.2V
80
VOUT = 1.8V
75
85
BURST MODE
(SYNC/MODE =
VIN)
80
75
70
65
70
FORCED
CONTINUOUS
(SYNC/MODE = 0V)
60
65
SYNC/MODE = VIN
VIN = 5V
60
1
10
100
1k
LOAD CURRENT (mA)
PULSE SKIPPING
(SYNC/MODE = 0.6V)
55
60
40
20
0
–20
50
10k
1
Burst Mode OPERATION
(ITH RISING)
Burst Mode OPERATION
(ITH FALLING)
FORCED CONTINUOUS
MODE
PULSE SKIPPING
MODE
80
90
VOUT = 3.3V
85
100
100
VOUT = 2.5V
95
90
Maximum Current Sense Voltage
vs ITH Pin Voltage
Efficiency vs Load Current
CURRENT LIMIT (%)
100
TA = 25°C unless otherwise noted.
10
100
1k
LOAD CURRENT (mA)
3808 G01
10k
0.5
3808 G02
Load Step (Burst Mode
Operation)
Load Step (Forced Continuous
Mode)
Load Step (Pulse Skipping Mode)
VOUT
200mV/DIV
AC COUPLED
VOUT
200mV/DIV
AC COUPLED
IL
2A/DIV
IL
2A/DIV
IL
2A/DIV
3808 G04
100µs/DIV
VIN = 3.3V
VOUT = 1.8V
ILOAD = 300mA TO 3A
SYNC/MODE = 0V
FIGURE 11 CIRCUIT
Start-Up with Internal Soft-Start
(TRACK/SS = VIN)
200µs/DIV
VIN = 4.2V
RLOAD = 1Ω
FIGURE 11 CIRCUIT
3808 G07
2
3808 G03
VOUT
200mV/DIV
AC COUPLED
100µs/DIV
VIN = 3.3V
VOUT = 1.8V
ILOAD = 300mA TO 3A
SYNC/MODE = VIN
FIGURE 11 CIRCUIT
1
1.5
ITH VOLTAGE (V)
3808 G05
100µs/DIV
VIN = 3.3V
VOUT = 1.8V
ILOAD = 300mA TO 3A
SYNC/MODE = VFB
FIGURE 11 CIRCUIT
3808 G06
Start-Up with External Soft-Start
(CSS = 10nF)
VOUT
1.8V
VOUT
1.8V
500mV/DIV
500mV/DIV
1ms/DIV
VIN = 4.2V
RLOAD = 1Ω
FIGURE 11 CIRCUIT
3808 G08
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TYPICAL PERFOR A CE CHARACTERISTICS
Start-Up with Coincident Tracking
(VOUT = 0.8V at 0s)
Start-Up with Coincident Tracking
(VOUT = 0V at 0s)
Vx
2.5V
Vx
2.5V
VOUT
1.8V
VOUT
1.8V
VOUT
1.8V
500mV/DIV
500mV/DIV
500mV/DIV
3808 G10
10ms/DIV
VIN = 4.2V
RTA = 590Ω
RTB = 1.18k
FIGURE 11 CIRCUIT
Regulated Feedback Voltage vs
Temperature
Shutdown (RUN) Threshold vs
Temperature
2.55
1.20
2.50
0.602
0.600
0.598
VIN RISING
1.15
2.45
RUN VOLTAGE (V)
INPUT VOLTAGE (V)
0.604
2.40
2.35
2.30
VIN FALLING
1.10
1.05
2.25
0.596
3808 G11
10ms/DIV
VIN = 4.2V
RTA = 590Ω
RTB = 1.69k
FIGURE 11 CIRCUIT
Undervoltage Lockout Threshold
vs Temperature
0.606
2.20
0.594
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
80
100
2.15
–60 –40 –20 0
20 40 60
TEMPERATURE (°C)
Maximum Current Sense
Threshold vs Temperature
1.04
IPRG = FLOAT
130
125
120
115
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
100
1.00
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
80
100
3808 G14
TRACK/SS Start-Up Current vs
Temperature
TRACK/SS START-UP CURRENT (µA)
135
80
3808 G13
3808 G12
MAXIMUM CURRENT SENSE THRESHOLD (mV)
FEEDBACK VOLTAGE (V)
Start-Up with Ratiometric
Tracking (VOUT = 0V at 0s)
Vx
2.5V
3808 G09
10ms/DIV
VIN = 4.2V
RTA = 590Ω
RTB = 1.18k
FIGURE 11 CIRCUIT
TA = 25°C unless otherwise noted.
80
100
3808 G16
TRACK/SS = 0V
1.02
1.00
0.98
0.96
0.94
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
80
100
3808 G17
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TYPICAL PERFOR A CE CHARACTERISTICS
SYNC/MODE Pull-Down Current
vs Temperature
Oscillator Frequency vs
Temperature
NORMALIZED FREQUENCY (%)
2.75
2.70
2.65
2.60
2.55
2.50
2.45
Oscillator Frequency vs Input
Voltage
10
5
8
4
NORMALIZED FREQUENCY SHIFT (%)
2.80
SYNC/MODE PULL-DOWN CURRENT (µA)
TA = 25°C unless otherwise noted.
6
4
2
0
–2
–4
–6
–8
2.40
–60 –40 –20 0
20 40 60
TEMPERATURE (°C)
80
–10
–60 –40 –20 0
20 40 60
TEMPERATURE (°C)
100
Shutdown Quiescent Current vs
Input Voltage
10
8
6
110
100
90
4
80
2
70
9
10
3808 G21
4
7
8
5
6
INPUT VOLTAGE (V)
9
10
3808 G20
TRACK/SS STARTUP CURRENT (µA)
SLEEP CURRENT (µA)
12
3
1.04
120
SHUTDOWN CURRENT (µA)
2
TRACK/SS Start-Up Current vs
TRACK/SS Voltage
14
7
8
5
6
INPUT VOLTAGE (V)
–4
100
16
4
–3
–5
80
130
3
–1
–2
Sleep Current vs Input Voltage
18
2
1
0
3808 G19
3808 G18
0
3
2
2
3
4
8
7
6
5
INPUT VOLTAGE (V)
1.00
0.96
0.92
0.88
0.84
9
10
3808 G22
0
0.1
0.2 0.3 0.4 0.5
TRACK/SS VOLTAGE (V)
0.6
0.7
3808 G24
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LTC3808
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PI FU CTIO S
(DFN/SSOP)
PLLLPF (Pin 1/Pin 2): Frequency Set/PLL Lowpass Filter.
When synchronizing to an external clock, this pin serves
as the low pass filter point for the phase-locked loop.
Normally, a series RC is connected between this pin and
ground.
When not synchronizing to an external clock, this pin serves
as the frequency select input. Tying this pin to GND selects
300kHz operation; tying this pin to VIN selects 750kHz
operation. Floating this pin selects 550kHz operation.
Connect a 2.2nF capacitor between this pin and GND and
a 1000pF capacitor between this pin and the SYNC/MODE
when using spread spectrum modulation operation.
SYNC/MODE (Pin 2/Pin 3): This pin performs four functions: 1) auxiliary winding feedback input, 2) external
clock synchronization input for phase-locked loop, 3)
Burst Mode, pulse skipping or forced continuous mode
select, and 4) enable spread spectrum modulation operation in pulse skipping mode. Applying a clock with frequency between 250kHz to 750kHz causes the internal
oscillator to phase-lock to the external clock and disables
Burst Mode operation but allows pulse skipping at low
load currents.
To select Burst Mode operation at light loads, tie this pin
to VIN. Grounding this pin selects forced continuous
operation, which allows the inductor current to reverse.
Tying this pin to VFB selects pulse skipping mode. In these
cases, the frequency of the internal oscillator is set by the
voltage on the PLLLPF pin. Tying to a voltage between
1.35V to VIN – 0.5V enables spread spectrum modulation
operation. In this case, an internal 2.6µA pull-down current source helps to set the voltage at this pin by tying a
resistor with appropriate value between this pin and VIN.
Do not leave this pin floating.
TRACK/SS (Pin 3/Pin 4): Tracking Input for the Controller
or Optional External Soft-Start Input. This pin allows the
start-up of VOUT to “track” the external voltage at this pin
using an external resistor divider. Tying this pin to VIN
allows VOUT start-up with the internal 1ms soft-start
clamp. An external soft-start can be programmed by
connecting a capacitor between this pin and ground. Do
not leave this pin floating.
PGOOD (Pin 4/Pin 5): Power Good Output Voltage Monitor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on the feedback pin VFB is not within
±13.3% of its nominal set point.
VFB (Pin 5/Pin 6): Feedback Pin. This pin receives the
remotely sensed feedback voltage for the controller from
an external resistor divider across the output.
ITH (Pin 6/Pin 7): Current Threshold and Error Amplifier
Compensation Point. Nominal operating range on this pin
is from 0.7V to 2V. The voltage on this pin determines the
threshold of the main current comparator.
RUN (Pin 7/Pin 8): Run Control Input. Forcing this pin
below 1.1V shuts down the chip. Driving this pin to VIN or
releasing this pin enables the chip to start-up either by
tracking the external voltage at the TRACK/SS pin or with
the internal/external soft-start, all based on the connection
at the TRACK/SS pin.
IPRG (Pin 8/Pin 10): Three-State Pin to Select Maximum
Peak Sense Voltage Threshold. This pin selects the maximum allowed voltage drop between the SENSE+ and
SENSE– or SW pins (i.e., the maximum allowed drop
across the sense resistor or the external P-channel
MOSFET). Tie to VIN, GND or float to select 204mV, 85mV
or 125mV respectively.
BG (Pin 9/Pin 11): Bottom (NMOS) Gate Drive Output.
This pin drives the gate of the external N-channel MOSFET.
This pin has an output swing from GND to SENSE+.
TG (Pin 10/Pin 12): Top (PMOS) Gate Drive Output. This
pin drives the gate of the external P-channel MOSFET. This
pin has an output swing from GND to SENSE+.
SENSE+ (Pin 11/Pin 13): Positive Input to Differential
Current Comparator. Also powers the gate drivers. Normally connected to the source of the external P-channel
MOSFET when the sense resistor is not used. Otherwise,
it is connected to the sense resistor.
VIN (Pin 12/Pin 14): Chip Signal Power Supply. This pin
powers the entire chip except for the gate drivers. Externally filtering this pin with a lowpass RC network (e.g.,
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
especially in high load current applications.
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LTC3808
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PI FU CTIO S
(DFN/SSOP)
SENSE– (Pin 13/Pin 15): Negative Input to Differential
Current Comparator. Normally is connected to the SW pin
when the sense resistor is not used. When using a current
sense resistor, connect the resistor between SENSE+ and
SENSE– and connect the source of the P-channel MOSFET
to the SENSE– pin.
Normally this pin is connected to the drain of the external
P-channel MOSFET, the drain of the external N-channel
MOSFET and the inductor.
GND (Pin 15/Pins 1, 9): Ground connection for internal
circuits, the gate drivers and the negative input to the
reverse current comparator. The exposed pad (Pin 15 in
DFN package) must be soldered to the PCB ground.
SW (Pin 14/Pin 16): Switch Node Connection to Inductor.
This pin is also an input to the reverse current comparator.
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VIN
CIN
VIN
SENSE–
SENSE+
VOLTAGE
REFERENCE
VREF
0.6V
IPRG
SLOPE
CLK
+
UNDERVOLTAGE
LOCKOUT
PVIN
S
Q
R
ICMP
SENSE+
–
VIN
BG
RUN
FCB
VIN
0.15V
SLEEP
–
+
OV
IREV
TRK/SS
0.3V
CLOCK DETECT
0.4V
–
BURSTDIS
BURSTDIS
FCB
PHASE
DETECTOR
MN
GND
+
t = 1ms
INTERNAL
SOFT-START
SYNC/MODE BURST DEFEAT
VOUT
COUT
SW
UVSD
MUX
L
ANTI-SHOOTTHROUGH
PVIN
0.7µA
1µA
MP
GND
SWITCHING
LOGIC AND
BLANKING
CIRCUIT
VIN
TRACK/SS
TG
0.68V
RB
+
+
0.54V
–
VFB
UV
–
ITH
2.6µA
RC
+
EAMP +
–
PLLLPF
VCO
VREF
0.6V
TRK/SS
VFB
CC
RA
CLK
VIN
3808 FD
PGOOD
GND
OV
UV
UVSD
IREV
+
SW
–
GND
RICMP
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LTC3808
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OPERATIO
(Refer to Functional Diagram)
Main Control Loop
The LTC3808 uses a constant frequency, current mode
architecture. During normal operation, the top external
P-channel power MOSFET is turned on when the clock
sets the RS latch, and is turned off when the current
comparator (ICMP) resets the latch. The peak inductor
current at which ICMP resets the RS latch is determined by
the voltage on the ITH pin, which is driven by the output of
the error amplifier (EAMP). The VFB pin receives the output
voltage feedback signal from an external resistor divider.
This feedback signal is compared to the internal 0.6V
reference voltage by the EAMP. When the load current
increases, it causes a slight decrease in VFB relative to the
0.6V reference, which in turn causes the ITH voltage to
increase until the average inductor current matches the
new load current. While the top P-channel MOSFET is off,
the bottom N-channel MOSFET is turned on until either the
inductor current starts to reverse, as indicated by the
current reversal comparator IRCMP, or the beginning of
the next cycle.
Shutdown, Soft-Start and Tracking Start-Up
(RUN and TRACK/SS Pins)
The LTC3808 is shut down by pulling the RUN pin low. In
shutdown, all controller functions are disabled and the
chip draws only 9µA. The TG output is held high (off) and
the BG output low (off) in shutdown. Releasing the RUN
pin allows an internal 0.7µA current source to pull up the
RUN pin to VIN. The controller is enabled when the RUN pin
reaches 1.1V.
The start-up of VOUT is based on the three different
connections on the TRACK/SS pin. The start-up of V OUT
is controlled by the LTC3808’s internal soft-start when
TRACK/SS is connected to VIN. During soft-start, the error
amplifier EAMP compares the feedback signal VFB to the
internal soft-start ramp (instead of the 0.6V reference),
which rises linearly from 0V to 0.6V in about 1ms. This
allows the output voltage to rise smoothly from 0V to its
final value while maintaining control of the inductor
current.
The 1ms soft-start time can be changed by connecting the
optional external soft-start capacitor CSS between the
TRACK/SS and GND pins. When the controller is enabled
by releasing the RUN pin, the TRACK/SS pin is charged up
by an internal 1µA current source and rises linearly from
0V to above 0.6V. The error amplifier EAMP compares the
feedback signal VFB to this ramp instead, and regulates VFB
linearly from 0V to 0.6V.
When the voltage on the TRACK/SS pin is less than the
0.6V internal reference, the LTC3808 regulates the VFB
voltage to the TRACK/SS pin instead of the 0.6V reference.
Therefore VOUT of the LTC3808 can track an external
voltage VX during start-up. Typically, a resistor divider on
VX is connected to the TRACK/SS pin to allow the start-up
of VOUT to “track” that of VX. For coincident tracking during
start-up, the regulated final value of VX should be larger
than that of VOUT, and the resistor divider on VX has the
same ratio as the divider on VOUT that is connected to VFB.
See detailed discussions in the Run and Soft-Start/
Tracking Functions in the Applications Information
Section.
Light Load Operation (Burst Mode Operation,
Continuous Conduction or Pulse Skipping Mode)
(SYNC/MODE Pin)
The LTC3808 can be programmed for either high efficiency Burst Mode operation, forced continuous conduction mode or pulse skipping mode at low load currents. To
select Burst Mode operation, tie the SYNC/MODE pin to
VIN. To select forced continuous operation, tie the SYNC/
MODE pin to a DC voltage below 0.4V (e.g., GND). Tying
the SYNC/MODE to a DC voltage above 0.4V and below
1.2V (e.g., VFB) enables pulse skipping mode. The 0.4V
threshold between forced continuous operation and pulse
skipping mode can be used in secondary winding regulation as described in the Auxiliary Winding Control Using
SYNC/MODE Pin discussion in the Applications Information section.
When the LTC3808 is in Burst Mode operation, the peak
current in the inductor is set to approximate one-fourth of
the maximum sense voltage even though the voltage on
the ITH pin indicates a lower value. If the average inductor
current is higher than the load current, the EAMP will
decrease the voltage on the ITH pin. When the ITH voltage
drops below 0.85V, the internal SLEEP signal goes high
and the external MOSFET is turned off.
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LTC3808
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OPERATIO
(Refer to Functional Diagram)
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3808 draws.
The load current is supplied by the output capacitor. As the
output voltage decreases, the EAMP increases the ITH
voltage. When the ITH voltage reaches 0.925V, the SLEEP
signal goes low and the controller resumes normal operation by turning on the external P-channel MOSFET on the
next cycle of the internal oscillator.
When the controller is enabled for Burst Mode or pulse
skipping operation, the inductor current is not allowed to
reverse. Hence, the controller operates discontinuously.
The reverse current comparator RICMP senses the drainto-source voltage of the bottom external N-channel
MOSFET. This MOSFET is turned off just before the
inductor current reaches zero, preventing it from going
negative.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by the
voltage on the ITH pin. The P-channel MOSFET is turned on
every cycle (constant frequency) regardless of the ITH pin
voltage. In this mode, the efficiency at light loads is lower
than in Burst Mode operation. However, continuous mode
has the advantages of lower output ripple and no noise at
audio frequencies.
When the SYNC/MODE pin is clocked by an external clock
source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop), or is set to a DC
voltage between 0.4V and several hundred mV below VIN,
the LTC3808 operates in PWM pulse skipping mode at
light loads. In this mode, the current comparator ICMP
may remain tripped for several cycles and force the
external P-channel MOSFET to stay off for the same
number of cycles. The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. However, it provides low current
efficiency higher than forced continuous mode, but not
nearly as high as Burst Mode operation. During start-up or
an undervoltage condition (VFB ≤ 0.54V), the LTC3808
operates in pulse skipping mode (no current reversal
allowed), regardless of the state of the SYNC/MODE pin.
Short-Circuit and Current Limit Protection
The LTC3808 monitors the voltage drop ∆VSC (between
the GND and SW pins) across the external N-channel
MOSFET with the short-circuit current limit comparator.
The allowed voltage is determined by:
∆VSC(MAX) = A • 90mV
where A is a constant determined by the state of the IPRG
pin. Floating the IPRG pin selects A = 1; tying IPRG to VIN
selects A = 5/3; tying IPRG to GND selects A = 2/3.
The inductor current limit for short-circuit protection is
determined by ∆VSC(MAX) and the on-resistance of the
external N-channel MOSFET:
ISC =
∆VSC(MAX)
RDS(ON)
Once the inductor current exceeds ISC, the short current
comparator will shut off the external P-channel MOSFET
until the inductor current drops below ISC.
Output Overvoltage Protection
As further protection, the overvoltage comparator (OVP)
guards against transient overshoots, as well as other more
serious conditions that may overvoltage the output. When
the feedback voltage on the VFB pin has risen 13.33%
above the reference voltage of 0.6V, the external P-channel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
Frequency Selection and Phase-Locked Loop
(PLLLPF and SYNC/MODE Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to maintain low output ripple voltage.
The switching frequency of the LTC3808’s controllers can
be selected using the PLLLPF pin. If the SYNC/MODE is
not being driven by an external clock source, the PLLLPF
can be floated, tied to VIN or tied to GND to select 550kHz,
750kHz or 300kHz, respectively.
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(Refer to Functional Diagram)
A phase-locked loop (PLL) is available on the LTC3808 to
synchronize the internal oscillator to an external clock
source that connects to the SYNC/MODE pin. In this case,
a series RC should be connected between the PLLLPF pin
and GND to serve as the PLL’s loop filter. The LTC3808
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of the external P-channel MOSFET to the
rising edge of the synchronizing signal.
The typical capture range of the LTC3808’s phase-locked
loop is from approximately 200kHz to 1MHz.
Spread Spectrum Modulation (SYNC/MODE and
PLLLPF Pins)
Connecting the SYNC/MODE pin to a DC voltage above
1.35V and several hundred mV below VIN enables spread
spectrum modulation (SSM) operation. An internal 2.6µA
pull-down current source at SYNC/MODE helps to set the
voltage at the SYNC/MODE pin for this operation by tying
a resistor with appropriate value between SYNC/MODE
and VIN. This mode of operation spreads the internal
oscillator frequency fOSC (= 550kHz) over a wider range
(460kHz to 635kHz), reducing the peaks of the harmonic
output on a spectral analysis of the output noise. In this
case, a 2.2nF filter cap should be connected between the
PLLLPF pin and GND and another 1000pF cap should be
connected between PLLLPF and the SYNC/MODE pin. The
controller operates in PWM pulse skipping mode at light
loads when spread spectrum modulation is selected. See
more discussions in the Spread Spectrum Modulation
with SYNC/MODE and PLLLPF Pins in the Applications
Information section.
Dropout Operation
When the input supply voltage (VIN) approaches the
output voltage, the rate of change of the inductor current
while the external P-channel MOSFET is on
(ON cycle) decreases. This reduction means that the
P-channel MOSFET will remain on for more than one
oscillator cycle if the inductor current has not ramped up
to the threshold set by the EAMP on the ITH pin. Further
reduction in the input supply voltage will eventually cause
the P-channel MOSFET to be turned on 100%; i.e., DC.
The output voltage will then be determined by the input
voltage minus the voltage drop across the P-channel
MOSFET and the inductor.
Undervoltage Lockout
To prevent operation of the P-channel MOSFET below
safe input voltage levels, an undervoltage lockout is
incorporated in the LTC3808. When the input supply
voltage (VIN) drops below 2.25V, the external P- and
N-channel MOSFETs and all internal circuits are turned
off except for the undervoltage block, which draws only
a few microamperes.
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG Pin)
When the LTC3808 controller is operating below 20% duty
cycle, the peak current sense voltage (between the SENSE+
and SENSE–/SW pins) allowed across the external Pchannel MOSFET is determined by:
∆VSENSE(MAX) = A •
VITH – 0.7 V
10
where A is a constant determined by the state of the IPRG
pin. Floating the IPRG pin selects A = 1; tying IPRG to VIN
selects A = 5/3; tying IPRG to GND selects A = 2/3. The
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(Refer to Functional Diagram)
maximum value of VITH is typically about 1.98V, so the
maximum sense voltage allowed across the external
P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG pin.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor (SF) given by the curve
in Figure 1.
The peak inductor current is determined by the peak sense
voltage and the on-resistance of the external P-channel
MOSFET:
IPK =
∆VSENSE(MAX)
RDS(ON)
If a sense resistor is used, ∆VSENSE(MAX) is the peak
current sense voltage (between the SENSE+ and SENSE–
pins) across the sense resistor. The peak inductor is
determined by the peak sense voltage and the resistance
of the sense resistor:
IPK =
∆VSENSE(MAX)
RSENSE
Power Good (PGOOD) Pin
A window comparator monitors the feedback voltage and
the open-drain PGOOD output pin is pulled low when the
feedback voltage is not within ±10% of the 0.6V reference
voltage. PGOOD is low when the LTC3808 is shut down or
in undervoltage lockout.
110
100
90
SF = I/IMAX (%)
80
70
60
50
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3808 F01
Figure 1. Maximum Peak Current vs Duty Cycle
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The typical LTC3808 application circuit is shown on
Figure 11. External component selection for the controller
is driven by the load requirement and begins with the
selection of the inductor and the power MOSFETs.
Power MOSFET Selection
The LTC3808’s controller requires two external power
MOSFETs: a P-channel MOSFET for the topside (main)
switch and a N-channel MOSFET for the bottom (synchronous) switch. The main selection criteria for the power
MOSFETs are the breakdown voltage VBR(DSS), threshold
voltage VGS(TH), on-resistance RDS(ON), reverse transfer
capacitance CRSS, turn-off delay tD(OFF) and the total gate
charge QG.
The gate drive voltage is the input supply voltage. Since the
LTC3808 is designed for operation down to low input
voltages, a sublogic level MOSFET (RDS(ON) guaranteed at
VGS = 2.5V) is required for applications that work close to
this voltage. When these MOSFETs are used, make sure
that the input supply to the LTC3808 is less than the
absolute maximum MOSFET VGS rating, which is typically
8V.
The P-channel MOSFET’s on-resistance is chosen based
on the required load current. The maximum average load
current IOUT(MAX) is equal to the peak inductor current
minus half the peak-to-peak ripple current IRIPPLE. The
LTC3808’s current comparator monitors the drain-tosource voltage VDS of the top P-channel MOSFET, which
is sensed between the SENSE+ and SW pins. The peak
inductor current is limited by the current threshold, set by
the voltage on the ITH pin, of the current comparator. The
voltage on the ITH pin is internally clamped, which limits
the maximum current sense threshold ∆VSENSE(MAX) to
approximately 125mV when IPRG is floating (85mV when
IPRG is tied low; 204mV when IPRG is tied high).
The output current that the LTC3808 can provide is given
by:
IOUT(MAX) =
∆VSENSE(MAX) IRIPPLE
–
RDS(ON)
2
where IRIPPLE is the inductor peak-to-peak ripple current
(see Inductor Value Calculation).
A reasonable starting point is setting ripple current IRIPPLE
to be 40% of IOUT(MAX). Rearranging the above equation
yields:
RDS(ON)MAX =
5 ∆VSENSE(MAX)
•
for Duty Cycle < 20%
6
IOUT(MAX)
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of RDS(ON) to provide the required
amount of load current:
RDS(ON)MAX =
∆VSENSE(MAX)
5
• SF •
6
IOUT(MAX)
where SF is a scale factor whose value is obtained from the
curve in Figure 1.
These must be further derated to take into account the
significant variation in on-resistance with temperature.
The following equation is a good guide for determining the
required RDS(ON)MAX at 25°C (manufacturer’s specification), allowing some margin for variations in the LTC3808
and external component values:
RDS(ON)MAX =
∆VSENSE(MAX)
5
• 0.9 • SF •
6
IOUT(MAX) • ρT
The ρT is a normalizing term accounting for the temperature variation in on-resistance, which is typically about
0.4%/°C, as shown in Figure 2. Junction-to-case temperature TJC is about 10°C in most applications. For a maximum ambient temperature of 70°C, using ρ80°C ~ 1.3 in
the above equation is a reasonable choice.
The N-channel MOSFET’s on resistance is chosen based
on the short-circuit current limit (ISC). The LTC3808’s
short-circuit current limit comparator monitors the drainto-source voltage VDS of the bottom N-channel MOSFET,
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ρT NORMALIZED ON RESISTANCE
2.0
VOUT
VIN
V –V
Bottom N-Channel Duty Cycle = IN OUT
VIN
Top P-Channel Duty Cycle =
1.5
1.0
The MOSFET power dissipations at maximum output
current are:
0.5
PTOP =
0
– 50
50
100
0
JUNCTION TEMPERATURE (°C)
150
3808 F02
Figure 2. RDS(ON) vs Temperature
which is sensed between the GND and SW pins. The shortcircuit current sense threshold ∆VSC is set approximately
90mV when IPRG is floating (60mV when IPRG is tied low;
150mV when IPRG is tied high). The on-resistance of Nchannel MOSFET is determined by:
RDS(ON)MAX =
∆VSC
ISC(PEAK)
The short-circuit current limit (ISC(PEAK)) should be larger
than the IOUT(MAX) with some margin to avoid interfering
with the peak current sensing loop. On the other hand, in
order to prevent the MOSFETs from excessive heating and
the inductor from saturation, ISC(PEAK) should be smaller
than the minimum value of their current ratings. A reasonable range is:
IOUT(MAX) < ISC(PEAK) < IRATING(MIN)
Therefore, the on-resistance of N-channel MOSFET should
be chosen within the following range:
∆VSC
IRATING(MIN)
< RDS(ON) <
∆VSC
IOUT(MAX)
where ∆VSC is 90mV, 60mV or 150mV with IPRG being
floated, tied to GND or VIN respectively.
The power dissipated in the MOSFET strongly depends on
its respective duty cycles and load current. When the
LTC3808 is operating in continuous mode, the duty cycles
for the MOSFETs are:
PBOT =
VOUT
• IOUT (MAX)2 • ρT • RDS(ON) + 2 • VIN2
VIN
• IOUT (MAX) • C RSS • f
VIN – VOUT
• IOUT (MAX)2 • ρT • RDS(ON)
VIN
Both MOSFETs have I2R losses and the PTOP equation
includes an additional term for transition losses, which are
largest at high input voltages. The bottom MOSFET losses
are greatest at high input voltage or during a short-circuit
when the bottom duty cycle is 100%.
The LTC3808 utilizes a non-overlapping, anti-shootthrough gate drive control scheme to ensure that the Pand N-channel MOSFETs are not turned on at the same
time. To function properly, the control scheme requires
that the MOSFETs used are intended for DC/DC switching
applications. Many power MOSFETs, particularly P-channel MOSFETs, are intended to be used as static switches
and therefore are slow to turn on or off.
Reasonable starting criteria for selecting the P-channel
MOSFET are that it must typically have a gate charge (QG)
less than 25nC to 30nC (at 4.5VGS) and a turn-off delay
(tD(OFF)) of less than approximately 140ns. However, due
to differences in test and specification methods of various
MOSFET manufacturers, and in the variations in QG and
tD(OFF) with gate drive (VIN) voltage, the P-channel MOSFET
ultimately should be evaluated in the actual LTC3808
application circuit to ensure proper operation.
Shoot-through between the P-channel and N-channel
MOSFETs can most easily be spotted by monitoring the
input supply current. As the input supply voltage increases, if the input supply current increases dramatically,
then the likely cause is shoot-through. Note that some
MOSFETs that do not work well at high input voltages (e.g.,
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VIN > 5V) may work fine at lower voltages (e.g., 3.3V).
Selecting the N-channel MOSFET is typically easier, since
for a given RDS(ON), the gate charge and turn-on and turnoff delays are much smaller than for a P-channel MOSFET.
Using a Sense Resistor
A sense resistor RSENSE can be connected between SENSE+
and SENSE– to sense the output load current. In this case,
the source of the P-channel MOSFET is connected to
SENSE– pin and the drain is connected to SW pin of
LTC3808. Therefore the current comparator monitors the
voltage developed across RSENSE instead of VDS of the
P-channel MOSFET. The output current that the LTC3808
can provide in this case is given by:
∆VSENSE(MAX) IRIPPLE
IOUT(MAX) =
–
RSENSE
2
Setting ripple current as 40% of IOUT(MAX) and using
Figure 1 to choose SF, the value of RSENSE is:
RSENSE =
∆VSENSE(MAX)
5
• SF •
6
IOUT(MAX)
See the P-channel RDS(ON) selection in Power MOSFET
Selection.
Variation in the resistance of a sense resistor is much
smaller than the variation in on-resistance of the external
MOSFET. Therefore the load current is well controlled with
a sense resistor. However the sense resistor causes extra
I2R losses in addition to the I2R losses of the MOSFET.
Therefore, using a sense resistor lowers the efficiency of
LTC3808, especially for large load current.
Operating Frequency and Synchronization
The choice of operating frequency, fOSC, is a trade-off
between efficiency and component size. Low frequency
operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss.
However, lower frequency operation requires more inductance for a given amount of ripple current.
The internal oscillator for the LTC3808’s controller runs at
a nominal 550kHz frequency when the PLLLPF pin is left
floating and the SYNC/MODE pin is not configured for
spread spectrum operation. Pulling the PLLLPF to VIN
selects 750kHz operation; pulling the PLLLPF to GND
selects 300kHz operation.
Alternatively, the LTC3808 will phase-lock to a clock signal
applied to the SYNC/MODE pin with a frequency between
250kHz and 750kHz (see Phase-Locked Loop and Frequency Synchronization).
To further reduce EMI, the nominal 550kHz frequency will
be spread over a range with frequencies between 460kHz
and 635kHz when spread spectrum modulation is
enabled (see Spread Spectrum Modulation with
SYNC/MODE and PLLLPF Pins).
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency, fOSC, directly determine
the inductor’s peak-to-peak ripple current:
IRIPPLE =
VOUT VIN – VOUT
•
VIN
fOSC • L
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
L≥
VIN – VOUT VOUT
•
fOSC • IRIPPLE VIN
Burst Mode Operation Considerations
The choice of RDS(ON) and inductor value also determines
the load current at which the LTC3808 enters Burst Mode
operation. When bursting, the controller clamps the peak
inductor current to approximately:
IBURST(PEAK) =
1 ∆VSENSE(MAX)
•
4
RDS(ON)
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The corresponding average current depends on the amount
of ripple current. Lower inductor values (higher IRIPPLE)
will reduce the load current at which Burst Mode operation
begins.
inductors wound on bobbins are generally easier to surface mount. However, designs for surface mount that do
not increase the height significantly are available from
Coiltronics, Coilcraft, Dale and Sumida.
The ripple current is normally set so that the inductor
current is continuous during the burst periods. Therefore,
Schottky Diode Selection (Optional)
IRIPPLE ≤ IBURST(PEAK)
This implies a minimum inductance of:
LMIN ≤
VIN – VOUT
V
• OUT
fOSC • IBURST(PEAK) VIN
A smaller value than LMIN could be used in the circuit,
although the inductor current will not be continuous
during burst periods, which will result in slightly lower
efficiency. In general, though, it is a good idea to keep
IRIPPLE comparable to IBURST(PEAK).
Inductor Core Selection
Once the value of L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford
the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or Kool
Mµ® cores. Actual core loss is independent of core size for
a fixed inductor value, but is very dependent on the inductance selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is
exceeded. Core saturation results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but is more expensive than
ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient,
especially when several layers of wire can be used, while
The schottky diode D in Figure 12 conducts current during
the dead time between the conduction of the power
MOSFETs. This prevents the body diode of the bottom
N-channel MOSFET from turning on and storing charge
during the dead time, which could cost as much as 1% in
efficiency. A 1A Schottky diode is generally a good size for
most LTC3808 applications, since it conducts a relatively
small average current. Larger diode results in additional
transition losses due to its larger junction capacitance.
This diode may be omitted if the efficiency loss can be
tolerated.
CIN and COUT Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (VOUT/VIN). To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
1/ 2
VOUT • ( VIN – VOUT )
CIN Re quiredIRMS ≈ IMAX •
VIN
This formula has a maximum value at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on 2000 hours of life.
This makes it advisable to further derate the capacitor or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet the
size or height requirements in the design. Due to the high
operating frequency of the LTC3808, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
Kool Mµ is a registered trademark of Magnetics, Inc.
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satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
3.3V OR 5V
LTC3808
RUN
LTC3808
RUN
⎛
⎞
1
∆VOUT ≈ IRIPPLE • ⎜ ESR +
⎟
⎝
8 • f • C OUT ⎠
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage
since IRIPPLE increase with input voltage.
Setting Output Voltage
The LTC3808 output voltage is set by an external feedback
resistor divider carefully placed across the output, as
shown in Figure 3. The regulated output voltage is determined by:
⎛ R ⎞
VOUT = 0.6 V • ⎜ 1 + B ⎟
⎝ RA ⎠
Figure 4. RUN Pin Interfacing
Once the controller is enabled, the start-up of VOUT is
controlled by the state of the TRACK/SS pin. If the TRACK/
SS pin is connected to VIN, the start-up of VOUT is controlled by internal soft-start, which slowly ramps the
positive reference to the error amplifier from 0V to 0.6V,
allowing VOUT to rise smoothly from 0V to its final value.
The default internal soft-start time is around 1ms. The
soft-start time can be changed by placing a capacitor
between the TRACK/SS pin and GND. In this case, the softstart time will be approximately:
tSS = CSS •
For most applications, a 59k resistor is suggested for RA.
In applications where minimizing the quiescent current is
critical, RA should be made bigger to limit the feedback
divider current. If RB then results in very high impedance,
it may be beneficial to bypass RB with a 50pF to 100pF
capacitor CFF.
VOUT
LTC3808
3808 F04
RB
CFF
VFB
RA
3808 F03
Figure 3. Setting Output Voltage
Run and Soft-Start/Tracking Functions
The LTC3808 has a low power shutdown mode which is
controlled by the RUN pin. Pulling the RUN pin below 1.1V
puts the LTC3808 into a low quiescent current shutdown
mode (IQ = 9µA). Releasing the RUN pin, an internal 0.7µA
(at VIN = 4.2V) current source will pull the RUN pin up to
VIN, which enables the controller. The RUN pin can be
driven directly from logic as showed in Figure 4.
600mV
1µA
where 1µA is an internal current source which is always
on.
When the voltage on the TRACK/SS pin is less than the
internal 0.6V reference, the LTC3808 regulates the VFB
voltage to the TRACK/SS pin voltage instead of 0.6V.
Therefore the start-up of VOUT can ratiometrically track an
external voltage VX, according to a ratio set by a resistor
divider at TRACK/SS pin (Figure 5a). The ratiometric
relation between VOUT and VX is (Figure 5c):
VOUT RTA RA + RB
=
•
VX
RA RTA + RTB
VOUT
VX
LTC3808
RTB
RB
VFB
TRACK/SS
RA
RTA
3808 F5a
Figure 5a. Using the TRACK/SS Pin to Track VX
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VOUT
VX
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VX
VOUT
3808 F05b,c
TIME
TIME
(5b) Coincident Tracking
(5c) Ratiometric Tracking
Figure 5b and 5c. Two Different Modes of Output Voltage Tracking
RTA = RA, RTB = RB
VX should always be greater than VOUT when using the
tracking function of TRACK/SS pin.
The internal current source (1µA), which is for external
soft-start, will cause a tracking error at VOUT. For example,
if a 59k resistor is chosen for RTA, the RTA current will be
about 10µA (600mV/59k). In this case, the 1µA internal
current source will cause about 10% (1µA/10µA • 100%)
tracking error, which is about 60mV (600mV • 10%)
referred to VFB. This is acceptable for most applications. If
a better tracking accuracy is required, the value of RTA
should be reduced.
Table 1 summarizes the different states in which the
TRACK/SS can be used.
Table 1. The States of the TRACK/SS Pin
TRACK/SS Pin
FREQUENCY
Capacitor CSS
External Soft-Start
VIN
Internal Soft-Start
Resistor Divider
VOUT Tracking an External Voltage VX
is an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relationship between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
MODE, is shown in Figure 6 and specified in the electrical
characteristics table. Note that the LTC3808 can only be
synchronized to an external clock whose frequency is
within range of the LTC3808’s internal VCO, which is
1200
1000
FREQUENCY (kHz)
For coincident tracking (VOUT = VX during start-up),
800
600
400
200
Phase-Locked Loop and Frequency Synchronization
0
0.2
The LTC3808 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the external P-channel
MOSFET to be locked to the rising edge of an external clock
signal applied to the SYNC/MODE pin. The phase detector
0.7
1.2
1.7
PLLLPF PIN VOLTAGE (V)
2.2
3808 F06
Figure 6. Relationship Between Oscillator Frequency
and Voltage at the PLLLPF Pin When Synchronizing to
an External Clock
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Table 2. The States of the PLLLPF Pin
2.4V
RLP
PLLLPF PIN
SYNC/MODE PIN
FREQUENCY
0V
DC Voltage (
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