LTC3822
No RSENSE™, Low Input
Voltage, Synchronous Step-Down
DC/DC Controller
FEATURES
DESCRIPTION
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The LTC®3822 is a synchronous step-down switching
regulator controller that drives external N-channel power
MOSFETs using few external components. The constant
frequency current mode architecture with MOSFET VDS
sensing eliminates the need for sense resistors and improves efficiency.
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No Current Sense Resistor Required
All N-Channel MOSFET Synchronous Drive
High Current Outputs Possible
Constant Frequency Current Mode Operation for
Excellent Line and Load Transient Response
VIN: 2.75V to 4.5V
±1% 0.6V Reference
Low Dropout Operation: 99% Duty Cycle
Selectable Frequency (300kHz/550kHz/750kHz)
Internal Soft-Start Circuitry
Selectable Maximum Peak Current Sense Threshold
Digital RUN Control Pin
Output Overvoltage Protection
Micropower Shutdown: IQ = 7.5μA
Tiny Thermally Enhanced Leadless (3mm × 3mm)
DFN or 10-Lead MSOP Package
A maximum duty cycle of 99% provides low dropout
operation. The switching frequency can be programmed
up to 750kHz, allowing the use of small surface mount
inductors and capacitors.
The LTC3822 is available in thermally enhanced DFN and
10-lead MSOP packages.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 5481178, 5929620,
6580258, 6304066, 5847554, 6611131, 6498466.
APPLICATIONS
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3.3VIN Systems
Li-Ion Battery Systems
TYPICAL APPLICATION
1.8V/8A High Efficiency, 550kHz Step-Down Converter
IPRG
Efficiency and Power Loss vs
Load Current
100
VIN
2.75V TO 4.5V
VIN
90
47μF
FDS6898A
SW
0.47μH
80
FREQ
ITH
LTC3822
0.22μF
BOOST
5.1k
100μF
680pF
70
BG
1
60
50
40
30
GND
POWER LOSS
0.1
20
VFB
59k
VOUT
1.8V
8A
EFFICIENCY
POWER LOSS (W)
TG
EFFICIENCY (%)
RUN
10
VIN = 3.3V
10
118k
3822 TA01
0
100
1000
LOAD CURRENT (mA)
0.01
10000
3822 TA01b
3822fa
1
LTC3822
ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Supply Voltage (VIN) ....................... –0.3V to 4.5V
BOOST Voltage .......................................... –0.3V to 10V
FREQ, RUN, IPRG Voltages ............–0.3V to (VIN + 0.3V)
VFB, ITH Voltages ...................................... –0.3V to 2.4V
SW Voltage ........................................... –2V to VIN + 1V
TG, BG Peak Output Current (1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT , causing a rapid drop in VOUT . No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25) • (CLOAD).
Thus a 10μF capacitor would be require a 250μs rise time,
limiting the charging current to about 200mA.
Design Example
For a design example, VIN will be a 3.3V power supply.
Output voltage is 1.2V with a load current requirement of
10A. The IPRG and FREQ pins will be left floating, so the
maximum current sense threshold ΔVSENSE(MAX) will be
approximately 120mV and the switching frequency will
be 550kHz.
Duty Cycle =
VOUT
= 36.4%
VIN
From Figure 1, SF = 96%.
RDS(ON)MAX =
ΔVSENSE(MAX)
5
• 0.9 • SF •
= 0.011Ω
IOUT(MAX) • ρT
6
The Si4486DY has an RDS(ON) of 9mΩ. To prevent inductor saturation during a short circuit, the inductor current
rating should be higher than 20A.
For 4A IRIPPLE, the required minimum inductor value is:
L MIN =
⎛ 1.2V ⎞
1.2V
• ⎜1–
⎟ = 0.35μH
550kHz • 4A ⎝ 3.3V ⎠
A 22A 0.39μH inductor works well for this application.
CIN will require an RMS current rating of at least 5A
at temperature. A COUT with 25mΩ ESR will cause approximately 100mV output ripple. Figure 7 shows a 12A,
3.3VIN/1.8VOUT application.
PC Board Layout Checklist
When laying out the printed circuit board, use the following checklist to ensure proper operation of the LTC3822.
Figure 5 shows a suggested PCB floorplan.
• The power loop (input capacitor, MOSFET, inductor, output
capacitor) and high di/dt loop (VIN, through both MOSFETs
to power GND and back through CIN to VIN) should be as
small as possible and located on one layer. Excess inductance here can cause increased stress on the MOSFETs
and increased high frequency ringing on the output.
• Put the feedback resistors close to the VFB pins. The ITH
compensation components should also be very close
to the LTC3822. All small-signal circuitry should be isolated from the main switching loop with ground Kelvin
connected to the output capacitor ground.
• The current sense traces (VIN and SW) should be Kelvin
connected right at the top-side MOSFET source and
drain. The positive current sense pin is shared with
the VIN pin. This must not be locally decoupled with a
capacitor.
• Keep the switch node (SW) and the gate driver nodes
(TG, BG) away from the small-signal components, especially the feedback resistors, and ITH compensation
components.
• Place CB as close as possible to the SW and BOOST
pins. This capacitor carries high di/dt MOSFET gate
drive currents. The charging current to the boost diode
should be provided from a separate VIN trace than that
to the VIN pin.
• Beware of ground loops in multiple layer PC boards. Try
to maintain one central signal ground node on the board.
If the ground plane must be used for high DC currents,
keep that path away from small signal components.
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LTC3822
APPLICATIONS INFORMATION
VIN
CIN
M1
GND
L1
SW
M2
VOUT
COUT
GND
U1
AND OTHER
SMALL-SIGNAL
COMPONENTS
GND SENSE
TRACE
3822 F05
Figure 5. LTC3822 Suggested PCB Floorplan
5V SECONDARY
SUPPLY
IPRG
VIN
2.75V TO 4.5V
VIN
RUN
FDS6898A
TG
IHLP-2525CZ-01
0.47μH
FREQ
ITH
LTC3822
22μF
2x
SW
0.22μF
BOOST
5.1k
47μF
2x
D
OPTIONAL
680pF
GND
VOUT
1.8V
8A
BG
VFB
59k
118k
3822 F06
Figure 6. Nominal 3.3VIN 1.8V/8A High Efficiency 550kHz Step-Down Converter with 5V Gate Drive
IPRG
VIN
3.3V
VIN
RUN
Si4866
TG
IHLP-2525CZ-01
0.22μH
FREQ
ITH
LTC3822
SW
47μF
2x
0.22μF
BOOST
27k
100μF
2x
Si4866
680pF
GND
VOUT
1.8V
12A
BG
VFB
59k
118k
3822 F07
Figure 7. 3.3VIN 1.8V/12A High Efficiency, High Current 550kHz Step-Down Converter
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LTC3822
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
R = 0.125
TYP
6
0.40 ± 0.10
10
1.65 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
(DD) DFN REV C 0310
5
0.200 REF
1
0.75 ±0.05
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
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LTC3822
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev H)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88 ± 0.102
(.074 ± .004)
5.23
(.206)
MIN
0.889 ± 0.127
(.035 ± .005)
1
0.05 REF
10
0.305 ± 0.038
(.0120 ± .0015)
TYP
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
10 9 8 7 6
DETAIL “A”
0° – 6° TYP
1 2 3 4 5
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.18
(.007)
0.497 ± 0.076
(.0196 ± .003)
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
0.254
(.010)
0.29
REF
1.68
(.066)
1.68 ± 0.102 3.20 – 3.45
(.066 ± .004) (.126 – .136)
0.50
(.0197)
BSC
1.88
(.074)
SEATING
PLANE
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
0.86
(.034)
REF
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MSE) 0911 REV H
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LTC3822
REVISION HISTORY
REV
DATE
DESCRIPTION
A
12/11
Changed P-channel to N-channel in the Peak Current Sense Voltage Selection and Slope Compensation (IPRG Pin)
section.
PAGE NUMBER
9
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC3822
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