LTC3826-1
30µA IQ, Dual, 2-Phase
Synchronous Step-Down Controller
DESCRIPTION
FEATURES
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Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 10V
Low Operating IQ: 30μA (One Channel On)
Out-of-Phase Controllers Reduce Required Input
Capacitance and Power Supply Induced Noise
OPTI-LOOP® Compensation Minimizes COUT
±1% Output Voltage Accuracy
Wide VIN Range: 4V to 36V Operation
Phase-Lockable Fixed Frequency 140kHz to 650kHz
Selectable Continuous, Pulse Skipping or Low Ripple
Burst Mode® Operation at Light Loads
Dual N-Channel MOSFET Synchronous Drive
Very Low Dropout Operation: 99% Duty Cycle
Adjustable Output Voltage Soft-Start or Tracking
Output Current Foldback Limiting
Power Good Output Voltage Monitor
Output Overvoltage Protection
Low Shutdown IQ: 4μA
Internal LDO Powers Gate Drive from VIN or VOUT
Small 28-Lead SSOP Package
APPLICATIONS
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Automotive Systems
Battery-Operated Digital Devices
Distributed DC Power Systems
The LTC®3826-1 is a high performance dual step-down
switching regulator controller that drives all N-channel
synchronous power MOSFET stages. A constant frequency
current mode architecture allows a phase-lockable frequency of up to 650kHz. Power loss and noise due to the
ESR of the input capacitor ESR are minimized by operating
the two controller output stages out of phase.
The 30μA no-load quiescent current extends operating
life in battery powered systems. OPTI-LOOP compensation allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
LTC3826-1 features a precision 0.8V reference and a power
good output indicator. A wide 4V to 36V input supply range
encompasses all battery chemistries.
Independent TRACK/SS pins for each controller ramp the
output voltage during start-up. Current foldback limits
MOSFET heat dissipation during short-circuit conditions.
The PLLIN/MODE pin selects among Burst Mode operation, pulse skipping mode, or continuous inductor current mode at light loads. For a leadless package version
(5mm × 5mm QFN) with additional features, see the
LTC3826 data sheet.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5481178, 5929620, 6177787, 6144194, 5408150, 6580258, 6304066, 5705919.
TYPICAL APPLICATION
High Efficiency Dual 8.5V/3.3V Step-Down Converter
Efficiency and Power Loss
vs Load Current
VIN
4V TO 36V
22μF
50V
4.7μF
INTVCC
TG1
3.3μH
BOOST1
0.1μF
BOOST2
BG2
LTC3826-1
PGND
SENSE2+
SENSE1–
62.5k
150μF
220pF
20k
15k
VFB2
ITH1
ITH2
TRACK/SS1 SGND TRACK/SS2
0.1μF
0.1μF
60
100
50
40
10
20
SENSE2–
VFB1
70
30
0.015Ω
0.015Ω
VOUT1
3.3V
5A
1000
80
7.2μH
SW2
BG1
10000
90
0.1μF
192.5k
220pF
20k
VOUT2
8.5V
3.5A
150μF
15k
POWER LOSS (mW)
SW1
SENSE1+
100
TG2
EFFICIENCY (%)
VIN
1
10
FIGURE 13 CIRCUIT
0
0.1
0.00001 0.0001 0.001 0.01
0.1
1
10
OUTPUT CURRENT (A)
38261 TA01b
38261 TA01
38261fb
1
LTC3826-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Input Supply Voltage (VIN) ......................... 36V to –0.3V
Topside Driver Voltages
BOOST1, BOOST2.................................. 42V to –0.3V
Switch Voltage (SW1, SW2) ......................... 36V to –5V
(BOOST1-SW1), (BOOST2-SW2) ............. 8.5V to –0.3V
RUN1, RUN2 ............................................... 7V to –0.3V
SENSE1+, SENSE2+, SENSE1–,
SENSE2– Voltages ..................................... 11V to –0.3V
PLLIN/MODE, PLLLPF, TRACK/SS1, TRACK/SS2
Voltages ........................................... INTVCC to –0.3V
EXTVCC ...................................................... 10V to –0.3V
ITH1, ITH2, VFB1, VFB2 Voltages ................. 2.7V to –0.3V
PGOOD1 Voltage ....................................... 8.5V to –0.3V
Peak Output Current fOSC
PGOOD Output
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPG
PGOOD Trip Level
VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
VFB Ramping Positive
MIN
l
l
l
8
l
98
0.75
0.5
85
5.0
7.2
4.5
350
220
475
650
TYP
MAX
UNITS
0.1
–0.1
0.5
0.5
–0.5
%
%
mmho
30
30
4
50
3.7
10
–220
99.4
1
0.7
100
50
50
10
75
4
12
1.35
0.9
115
μA
μA
μA
μA
V
%
μA
%
μA
V
mV
50
50
90
90
ns
ns
40
40
70
90
80
ns
ns
ns
70
ns
230
ns
5.25
0.2
7.5
0.2
4.7
0.2
5.5
1.0
7.8
1.0
V
%
V
%
V
V
390
250
530
115
800
430
280
585
140
kHz
kHz
kHz
kHz
kHz
–5
5
–12
8
μA
μA
0.1
0.3
±1
V
μA
–10
10
–8
12
%
%
38261fb
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LTC3826-1
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LTC3826-1 is tested in a feedback loop that servos VITH1, 2 to
a specified voltage and measures the resultant VFB1, 2.
Note 2: The LTC3826E-1 is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3826I-1 is guaranteed to
meet performance specifications over the full −40°C to 85°C operating
temperature range.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥40% of IMAX (see minimum on-time
considerations in the Applications Information section).
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • 95 °C/W)
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current
80
50
10
40
30
1
20
VIN = 12V
VOUT = 3.3V
1
0.1
10
POWER LOSS (mW)
100
94
70
60
50
40
92
90
88
30
86
20
VIN = 12V
VIN = 5V
VOUT = 3.3V
10
0
0.00001 0.0001 0.001 0.01
0.1
OUTPUT CURRENT (A)
38261 G01
FIGURE 13 CIRCUIT
96
80
1000
60
0
0.1
0.00001 0.0001 0.001 0.01
OUTPUT CURRENT (A)
98
90
70
10
Efficiency vs Input Voltage
100
EFFICIENCY (%)
90
EFFICIENCY (%)
Efficiency vs Load Current
10000
Burst Mode OPERATION
FORCED CONTINUOUS MODE
PULSE SKIPPING
MODE
EFFICIENCY (%)
100
1
FIGURE 13 CIRCUIT
Load Step
(Burst Mode Operation)
84
82
10
0
Load Step
(Forced Continuous Mode)
IL
2A/DIV
IL
2A/DIV
IL
2A/DIV
20μs/DIV
FIGURE 13 CIRCUIT
VOUT = 3.3V
35
40
Load Step
(Pulse Skipping Mode)
VOUT
100mV/DIV
AC
COUPLED
38261 G04
15 20 25 30
INPUT VOLTAGE (V)
38261 G03
VOUT
100mV/DIV
AC
COUPLED
20μs/DIV
10
38261 G02
VOUT
100mV/DIV
AC
COUPLED
FIGURE 13 CIRCUIT
VOUT = 3.3V
5
38261 G05
20μs/DIV
FIGURE 13 CIRCUIT
VOUT = 3.3V
38261 G06
38261fb
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LTC3826-1
TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Current at Light Load
Soft Start-Up
Tracking Start-Up
FORCED
CONTINUOUS
MODE
2A/DIV
Burst Mode
OPERATION
PULSE
SKIPPING
MODE
2μs/DIV
FIGURE 13 CIRCUIT
VOUT = 3.3V
ILOAD = 100μA
20ms/DIV
FIGURE 13 CIRCUIT
VOUT1
2V/DIV
VOUT1
2V/DIV
20ms/DIV
FIGURE 13 CIRCUIT
38261 G08
EXTVCC Switchover and INTVCC
Voltages vs Temperature
38261 G09
INTVCC Line Regulation
6.0
350
5.5
5.8
250
200
150
300μA LOAD
100
NO LOAD
50
5.4
5.6
INTVCC VOLTAGE (V)
EXTVCC AND INTVCC VOLTAGE (V)
300
INTVCC
5.4
5.2
5.0
EXTVCC RISING
4.8
4.6
EXTVCC FALLING
4.4
5.3
5.2
5.1
4.2
0
5
10
25
20
15
INPUT VOLTAGE (V)
FIGURE 13 CIRCUIT
4.0
–45
35
30
30
0
20
0
–30
–60
–90
–120
–150
–180
–210
–240
–20
10% DUTY CYCLE
0
0.2
1.0
0.4 0.6 0.8
ITH PIN VOLTAGE (V)
1.2
0
1.4
38261 G13
5
10
15 20 25 30
INPUT VOLTAGE (V)
–270
–300
35
40
38261 G12
Maximum Current Sense
Threshold vs Duty Cycle
60
40
–40
5.0
95
38261 G11
INPUT BIAS CURRENT (μA)
60
75
Sense Pins Total Input
Bias Current
PULSE SKIPPING
FORCED CONTINUOUS
Burst Mode OPERATION
(RISING)
Burst Mode OPERATION
(FALLING)
80
35
15
–5
55
TEMPERATURE (°C)
38261 G10
Maximum Current Sense Voltage
vs ITH Voltage
100
–25
MAXIMUM CURRENT SENSE VOLTAGE (mV)
SUPPLY CURRENT (μA)
VOUT2
2V/DIV
38261 G07
Total Input Supply Current
vs Input Voltage
CURRENT SENSE THRESHOLD (mV)
VOUT2
2V/DIV
120
100
80
60
40
20
0
0
1 2 3 4 5 6 7 8 9
VSENSE COMMON MODE VOLTAGE (V)
10
38261 G14
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
38261 G15
38261fb
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LTC3826-1
TYPICAL PERFORMANCE CHARACTERISTICS
44
TRACK/SS = 1V
42
100
80
60
40
20
40
38
36
34
32
30
0
3
2
1
28
24
–45 –30 –15
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
FEEDBACK VOLTAGE (V)
0
0 15 30 45 60
TEMPERATURE (°C)
75
90
TRACK/SS Pull-Up Current
vs Temperature
REGULATED FEEDBACK VOLTAGE (mV)
1.15
0.90
RUN PIN VOLTAGE (V)
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.85
0.55
0.80
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
0.50
–45 –30 –15
90
0 15 30 45 60
TEMPERATURE (°C)
Sense Pins Total Input Current
vs Temperature
75
VOUT = 3.3V
–90
–120
–150
VOUT = 0V
794
600
4
3
2
90
VPLLLPF = INTVCC
500
VPLLLPF = FLOAT
400
VPLLLPF = GND
300
100
–270
0
38261 G22
75
200
1
90
0 15 30 45 60
TEMPERATURE (°C)
700
–210
–240
75
796
800
FREQUENCY (kHz)
INPUT CURRENT (μA)
VOUT = 10V
0 15 30 45 60
TEMPERATURE (°C)
798
Oscillator Frequency
vs Temperature
5
0
–300
–45 –30 –15
800
38261 G21
6
–180
802
Shutdown Current
vs Input Voltage
60
1.4
804
792
–45 –30 –15
90
30
–60
1.2
806
38261 G20
38261 G19
–30
0.6 0.8 1.0
ITH VOLTAGE (V)
808
0.95
1.00
0.4
Regulated Feedback Voltage
vs Temperature
1.00
1.20
1.05
0.2
38261 G18
Shutdown (RUN) Threshold
vs Temperature
1.10
0
38261 G17
38261 G16
INPUT CURRENT (μA)
VSENSE = 3.3V
26
0
TRACK/SS CURRENT (μA)
4
PLLIN/MODE = 0V
INPUT CURRENT (μA)
120
Sense Pins Total Input
Bias Current vs ITH
Quiescent Current vs Temperature
QUIESCENT CURRENT (μA)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
Foldback Current Limit
5
10
15
20
25
INPUT VOLTAGE (V)
30
35
38261 G23
0
–45
–25
35
15
–5
55
TEMPERATURE (°C)
75
95
38261 G24
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LTC3826-1
TYPICAL PERFORMANCE CHARACTERISTICS
Undervoltage Lockout Threshold
vs Temperature
Oscillator Frequency
vs Input Voltage
4.2
Shutdown Current
vs Temperature
392
6
390
5
INTVCC VOLTAGE (V)
4.0
3.9
RISING
3.8
3.7
3.6
FALLING
3.5
3.4
SHUTDOWN CURRENT (μA)
OSCILLATOR FREQUENCY (kHz)
4.1
388
386
384
382
4
3
2
1
3.3
3.2
–45 –30 –15
380
0 15 30 45 60
TEMPERATURE (°C)
75
90
5
10
25
20
15
INPUT VOLTAGE (V)
38261 G25
30
35
38261 G26
0
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
38261 G27
PIN FUNCTIONS
ITH1, ITH2 (Pins 1, 13): Error Amplifier Outputs and
Switching Regulator Compensation Points. Each associated channel’s current comparator trip point increases
with this control voltage.
VFB1, VFB2 (Pins 2, 12): Receives the remotely sensed
feedback voltage for each controller from an external
resistive divider across the output.
SENSE1+, SENSE2+ (Pins 3, 11): The (+) Input to the
Differential Current Comparators. The ITH pin voltage and
controlled offsets between the SENSE– and SENSE+ pins in
conjunction with RSENSE set the current trip threshold.
SENSE1–, SENSE2– (Pins 4, 10): The (–) Input to the
Differential Current Comparators.
PLLLPF (Pin 5): The phase-locked loop’s lowpass filter is
tied to this pin when synchronizing to an external clock.
Alternatively, tie this pin to GND, INTVCC or leave floating to
select 250kHz, 530kHz or 390kHz switching frequency.
PLLIN/MODE (Pin 6): External Synchronization Input to
Phase Detector and Forced Continuous Control Input. When
an external clock is applied to this pin, the phase-locked
loop will force the rising TG1 signal to be synchronized
with the rising edge of the external clock. In this case, an
R-C filter must be connected to the PLLLPF pin. When
not synchronizing to an external clock, this input, which
acts on both controllers, determines how the LTC3826-1
operates at light loads. Pulling this pin below 0.7V selects
Burst Mode operation. Tying this pin to INTVCC forces
continuous inductor current operation. Tying this pin to
a voltage greater than 0.9V and less than INTVCC –1.2V
selects pulse skipping operation.
SGND (Pin 7): Small-signal Ground common to both
controllers, must be routed separately from high current grounds to the common (–) terminals of the CIN
capacitors.
38261fb
7
LTC3826-1
PIN FUNCTIONS
RUN1, RUN2 (Pins 8, 9): Digital Run Control Inputs for
Each Controller. Forcing either of these pins below 0.7V
shuts down that controller. Forcing both of these pins
below 0.7V shuts down the entire LTC3826-1, reducing
quiescent current to approximately 4μA.
BOOST1, BOOST2 (Pins 24, 17): Bootstrapped Supplies
to the Topside Floating Drivers. Capacitors are connected
between the BOOST and SW pins and Schottky diodes are
tied between the BOOST and INTVCC pins. Voltage swing
at the BOOST pins is from INTVCC to (VIN + INTVCC).
INTVCC (Pin 19): Output of the Internal Linear Low Dropout
Regulator. The driver and control circuits are powered
from this voltage source. Must be decoupled to power
ground with a minimum of 4.7μF tantalum or other low
ESR capacitor.
SW1, SW2 (Pins 25, 16): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to VIN.
EXTVCC (Pin 20): External Power Input to an Internal LDO
Connected to INTVCC. This LDO supplies INTVCC power,
bypassing the internal LDO powered from VIN whenever
EXTVCC is higher than 4.7V. See EXTVCC Connection in
the Applications Information section. Do not exceed 10V
on this pin.
PGND (Pin 21): Driver Power Ground. Connects to the sources
of bottom (synchronous) N-channel MOSFETs, anodes of
the Schottky rectifiers and the (–) terminal(s) of CIN.
VIN (Pin 22): Main Supply Pin. A bypass capacitor should
be tied between this pin and the signal ground pin.
BG1, BG2 (Pins 23, 18): High Current Gate Drives for Bottom (Synchronous) N-Channel MOSFETs. Voltage swing
at these pins is from ground to INTVCC.
TG1, TG2 (Pins 26, 15): High Current Gate Drives for
Top N-Channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to INTVCC – 0.5V
superimposed on the switch node voltage SW.
PGOOD1 (Pin 27): Open-Drain Logic Output. PGOOD1 is
pulled to ground when the voltage on the VFB1 pin is not
within ±10% of its set point.
TRACK/SS1, TRACK/SS2 (Pins 28, 14): External Tracking and Soft-Start Input. The LTC3826-1 regulates the
VFB1,2 voltage to the smaller of 0.8V or the voltage on the
TRACK/SS1,2 pin. A internal 1μA pull-up current source
is connected to this pin. A capacitor to ground at this
pin sets the ramp time to final regulated output voltage.
Alternatively, a resistor divider on another voltage supply
connected to this pin allows the LTC3826-1 output to track
the other supply during startup.
38261fb
8
LTC3826-1
FUNCTIONAL DIAGRAM
PLLIN/MODE
FIN
6
BOOST
100k
5
DROP
OUT
DET
CLK1
OSCILLATOR
CLK2
–
CLP
0.88V
S
Q
R
Q
BOT
VFB1
PGOOD1
FC
+
SW
TOP ON
SWITCH
LOGIC
0.4V
+
SLEEP
–
INTVCC-0.5V
ICMP
0.8V
+
BURSTEN
+
–
–
++
–
–
IR
SENSE+
+
3, 11
SENSE–
4, 10
SLOPE
COMP
–
EA
+
OV
VIN
22
EXTVCC
–
20
6V
RA
0.88V
CC
ITH
SHDN
RST
2(VFB)
1,13
CC2
FOLDBACK
RC
1μA
19
SGND
7
RB
2, 12
TRACK/SS
0.80V
0.5μA
5.25V/
7.5V
LDO
INTVCC
+
VFB
VFB
+
–
+
RSENSE
L
6mV
0.45V
2(VFB)
4.7V
VOUT
21
FC
–
PLLIN/MODE
COUT
SHDN
–
+
BG
23, 18
PGND
BURSTEN
B
25, 16
INTVCC
BOT
0.72V
CIN
D
26, 15
–
27
CB
TG
TOP
+
VIN
DB
24, 17
PLLLPF
RLP
VIN
INTVCC
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
PHASE DET
TRACK/SS
INTERNAL
SUPPLY
RUN
8, 9
28,14
SHDN
CSS
38261 FD
OPERATION
(Refer to Functional Diagram)
Main Control Loop
The LTC3826-1 uses a constant frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out of phase. During normal operation, each external top MOSFET is turned on when the
clock for that channel sets the RS latch, and is turned off
when the main current comparator, ICMP , resets the RS
latch. The peak inductor current at which ICMP trips and
resets the latch is controlled by the voltage on the ITH pin,
which is the output of the error amplifier EA. The error
amplifier compares the output voltage feedback signal at
the VFB pin, (which is generated with an external resistor
divider connected across the output voltage, VOUT , to
ground) to the internal 0.800V reference voltage. When the
load current increases, it causes a slight decrease in VFB
relative to the reference, which causes the EA to increase
the ITH voltage until the average inductor current matches
the new load current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
38261fb
9
LTC3826-1
OPERATION
(Refer to Functional Diagram)
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open or tied to a voltage less
than 4.7V, an internal 5.25V low dropout linear regulator
supplies INTVCC power from VIN. If EXTVCC is taken above
4.7V, the 5.25V regulator is turned off and a 7.5V low
dropout linear regulator is enabled that supplies INTVCC
power from EXTVCC. If EXTVCC is less than 7.5V (but
greater than 4.7V), the 7.5V regulator is in dropout and
INTVCC is approximately equal to EXTVCC. When EXTVCC
is greater than 7.5V (up to an absolute maximum rating
of 10V), INTVCC is regulated to 7.5V. Using the EXTVCC
pin allows the INTVCC power to be derived from a high
efficiency external source such as one of the LTC3826-1
switching regulator outputs.
Each top MOSFET driver is biased from the floating bootstrap capacitor CB, which normally recharges during each
off cycle through an external diode when the top MOSFET
turns off. If the input voltage VIN decreases to a voltage
close to VOUT, the loop may enter dropout and attempt
to turn on the top MOSFET continuously. The dropout
detector detects this and forces the top MOSFET off for
about one twelfth of the clock period every tenth cycle to
allow CB to recharge.
Shutdown and Start-Up (RUN1, RUN2 and TRACK/
SS1, TRACK/SS2 Pins)
The two channels of the LTC3826-1 can be independently
shut down using the RUN1 and RUN2 pins. Pulling either
of these pins below 0.7V shuts down the main control
loop for that controller. Pulling both pins low disables
both controllers and most internal circuits, including the
INTVCC regulator, and the LTC3826-1 draws only 4μA of
quiescent current.
Releasing either RUN pin allows an internal 0.5μA current
to pull up the pin and enable that controller. Alternatively,
the RUN pin may be externally pulled up or driven directly
by logic. Be careful not to exceed the Absolute Maximum
rating of 7V on this pin.
The start-up of each controller’s output voltage VOUT is controlled by the voltage on the TRACK/SS1 and TRACK/SS2
pin. When the voltage on the TRACK/SS pin is less than
the 0.8V internal reference, the LTC3826-1 regulates the
VFB voltage to the TRACK/SS pin voltage instead of the
0.8V reference. This allows the TRACK/SS pin to be used
to program a soft start by connecting an external capacitor
from the TRACK/SS pin to SGND. An internal 1μA pull-up
current charges this capacitor creating a voltage ramp on
the TRACK/SS pin. As the TRACK/SS voltage rises linearly
from 0V to 0.8V (and beyond), the output voltage VOUT
rises smoothly from zero to its final value.
Alternatively the TRACK/SS pin can be used to cause the
startup of VOUT to “track” that of another supply. Typically,
this requires connecting to the TRACK/SS pin an external
resistor divider from the other supply to ground (see
Applications Information section).
When the corresponding RUN pin is pulled low to disable
a controller, or when VIN drops below its undervoltage
lockout threshold of 3.5V, the TRACK/SS pin is pulled low
by an internal MOSFET. When in undervoltage lockout,
both controllers are disabled and the external MOSFETs
are held off.
Light Load Current Operation (Burst Mode Operation,
Pulse Skipping, or Continuous Conduction)
(PLLIN/MODE Pin)
The LTC3826-1 can be enabled to enter high efficiency
Burst Mode operation, constant frequency pulse skipping
mode, or forced continuous conduction mode at low load
currents. To select Burst Mode operation, tie the PLLIN/
MODE pin to a DC voltage below 0.7V (e.g., SGND). To
select forced continuous operation, tie the PLLIN/MODE
pin to INTVCC. To select pulse-skipping mode, tie the
PLLIN/MODE pin to a DC voltage greater than 0.9V and
less than INTVCC – 1.2V.
When a controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-tenth of the maximum sense voltage even though the
voltage on the ITH pin indicates a lower value. If the average inductor current is lower than the load current, the
error amplifier EA will decrease the voltage on the ITH pin.
When the ITH voltage drops below 0.4V, the internal sleep
signal goes high (enabling “sleep” mode) and both external
38261fb
10
LTC3826-1
OPERATION
(Refer to Functional Diagram)
MOSFETs are turned off. The ITH pin is then disconnected
from the output of the EA and “parked” at 0.425V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3826-1 draws.
If one channel is shut down and the other channel is in
sleep mode, the LTC3826-1 draws only 30μA of quiescent
current. If both channels are in sleep mode, the LTC3826-1
draws only 50μA of quiescent current. In sleep mode,
the load current is supplied by the output capacitor. As
the output voltage decreases, the EA’s output begins to
rise. When the output voltage drops enough, the ITH pin
is reconnected to the output of the EA, the sleep signal
goes low, and the controller resumes normal operation
by turning on the top external MOSFET on the next cycle
of the internal oscillator.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus, the
controller operates in discontinuous operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than
in Burst Mode operation. However, continuous has the
advantages of lower output ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse-skipping mode or clocked by an external clock source to
use the phase-locked loop (see Frequency Selection and
Phase-Locked Loop section), the LTC3826-1 operates in
PWM pulse skipping mode at light loads. In this mode,
constant frequency operation is maintained down to approximately 1% of designed maximum output current.
At very light loads, the current comparator ICMP may
remain tripped for several cycles and force the external top
MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
Frequency Selection and Phase-Locked Loop (PLLLPF
and PLLIN/MODE Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3826-1’s controllers
can be selected using the PLLLPF pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the PLLLPF pin can be floated, tied to INTVCC,
or tied to SGND to select 390kHz, 530kHz, or 250kHz,
respectively.
A phase-locked loop (PLL) is available on the LTC3826-1
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. In this
case, a series R-C should be connected between the
PLLLPF pin and SGND to serve as the PLL’s loop filter.
The LTC3826-1 phase detector adjusts the voltage on the
PLLLPF pin to align the turn-on of controller 1’s external
top MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s external top MOSFET is
180 degrees out of phase to the rising edge of the external
clock source.
The typical capture range of the LTC3826-1’s phase-locked
loop is from approximately 115kHz to 800kHz, with a
guarantee over all manufacturing variations to be between
140kHz and 650kHz. In other words, the LTC3826-1’s PLL
is guaranteed to lock to an external clock source whose
frequency is between 140kHz and 650kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
38261fb
11
LTC3826-1
OPERATION
(Refer to Functional Diagram)
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
IIN(MEAS) = 2.53ARMS
38271 F01a
IIN(MEAS) = 1.55ARMS
38271 F01a
(a)
(b)
Figure 1. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators
Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator Allows
Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency
Output Overvoltage Protection
An overvoltage comparator guards against transient overshoots as well as other more serious conditions that may
overvoltage the output. When the VFB pin rises more than
10% above its regulation point of 0.800V, the top MOSFET
is turned off and the bottom MOSFET is turned on until
the overvoltage condition is cleared.
Power Good (PGOOD1) Pin
The PGOOD1 pin is connected to an open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD1 pin low when the VFB1 pin voltage is not within
±10% of the 0.8V reference voltage. The PGOOD1 pin is also
pulled low when the RUN1 pin is low (shut down). When
the VFB1 pin voltage is within the ±10% requirement, the
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source of up to 8.5V.
THEORY AND BENEFITS OF 2-PHASE OPERATION
Why the need for 2-phase operation? Up until the 2-phase
family, constant-frequency dual switching regulators
operated both channels in phase (i.e., single-phase
operation). This means that both switches turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current flowing from the
input capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.
With 2-phase operation, the two channels of the dualswitching regulator are operated 180 degrees out of phase.
This effectively interleaves the current pulses drawn by the
switches, greatly reducing the overlap time where they add
together. The result is a significant reduction in total RMS
input current, which in turn allows less expensive input
capacitors to be used, reduces shielding requirements for
EMI and improves real world operating efficiency.
Figure 1 compares the input waveforms for a representative
single-phase dual switching regulator to the LTC3826-1
2-phase dual switching regulator. An actual measurement of the RMS input current under these conditions
shows that 2-phase operation dropped the input current
from 2.53ARMS to 1.55ARMS. While this is an impressive
reduction in itself, remember that the power losses are
proportional to IRMS2, meaning that the actual power wasted
is reduced by a factor of 2.66. The reduced input ripple
voltage also means less power is lost in the input power
path, which could include batteries, switches, trace/connector resistances and protection circuitry. Improvements
in both conducted and radiated EMI also directly accrue as
a result of the reduced RMS input current and voltage.
38261fb
12
LTC3826-1
(Refer to Functional Diagram)
Of course, the improvement afforded by 2-phase operation
is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
voltage VIN (Duty Cycle = VOUT/VIN). Figure 2 shows how
the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
It can readily be seen that the advantages of 2-phase
operation are not just limited to a narrow operating range,
for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
3.0
SINGLE PHASE
DUAL CONTROLLER
2.5
INPUT RMS CURRENT (A)
OPERATION
2.0
1.5
2-PHASE
DUAL CONTROLLER
1.0
0.5
0
V01 = 5V/3A
V02 = 3.3V/3A
0
10
20
30
INPUT VOLTAGE (V)
40
38261 F02
Figure 2. RMS Input Current Comparison
The schematic on the first page is a basic LTC3826-1
application circuit. External component selection is driven
by the load requirement, and begins with the selection of
RSENSE and the inductor value. Next, the power MOSFETs
are selected. Finally, CIN and COUT are selected.
APPLICATIONS INFORMATION
RSENSE Selection For Output Current
Operating Frequency and Synchronization
RSENSE is chosen based on the required output current.
The current comparator has a maximum threshold of
100mV/RSENSE and an input common mode range of
SGND to 10V. The current comparator threshold sets the
peak of the inductor current, yielding a maximum average
output current IMAX equal to the peak value less half the
peak-to-peak ripple current, ΔIL.
The choice of operating frequency, is a trade-off between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses,
both gate charge loss and transition loss. However, lower
frequency operation requires more inductance for a given
amount of ripple current.
Allowing a margin for variations in the IC and external
component values yields:
RSENSE =
80mV
IMAX
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to the
internal compensation required to meet stability criterion for
buck regulators operating at greater than 50% duty factor. A
curve is provided in the Typical Performance Characteristics
section to estimate this reduction in peak output current
level depending upon the operating duty factor.
The internal oscillator for each of the LTC3826-1’s controllers runs at a nominal 390kHz frequency when the
PLLLPF pin is left floating and the PLLIN/MODE pin is
a DC low or high. Pulling the PLLLPF to INTVCC selects
530kHz operation; pulling the PLLLPF to SGND selects
250kHz operation.
Alternatively, the LTC3826-1 will phase-lock to a clock
signal applied to the PLLIN/MODE pin with a frequency
between 140kHz and 650kHz (see Phase-Locked Loop
and Frequency Synchronization).
Inductor Value Calculation
The operating frequency and inductor selection are
interrelated in that higher operating frequencies allow the
38261fb
13
LTC3826-1
APPLICATIONS INFORMATION
use of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔIL decreases with higher
inductance or frequency and increases with higher VIN:
IL =
V
1
VOUT 1– OUT
(f)(L)
VIN
Accepting larger values of ΔIL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ΔIL = 0.3(IMAX). The maximum
ΔIL occurs at the maximum input voltage.
The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
10% of the current limit determined by RSENSE. Lower
inductor values (higher ΔIL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite or molypermalloy cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode (Optional)
Selection
Two external power MOSFETs must be selected for each
controller in the LTC3826-1: one N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC voltage.
This voltage is typically 5V during start-up (see EXTVCC Pin
Connection). Consequently, logic-level threshold MOSFETs
must be used in most applications. The only exception
is if low input voltage is expected (VIN < 5V); then, sublogic level threshold MOSFETs (VGS(TH) < 3V) should be
used. Pay close attention to the BVDSS specification for
the MOSFETs as well; most of the logic level MOSFETs are
limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance RDS(ON), Miller capacitance CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the Gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
VOUT
VIN
Synchronous Switch Duty Cycle =
VIN – VOUT
VIN
38261fb
14
LTC3826-1
APPLICATIONS INFORMATION
The MOSFET power dissipations at maximum output
current are given by:
PMAIN =
VOUT
2
IMAX ) (1+ )RDS(ON) +
(
VIN
( VIN )2 IMAX
(R )(C
)•
2
DR MILLER
1
1
+
( f)
VINTVCC – VTHMIN VTHMIN
PSYNC =
VIN – VOUT
2
IMAX ) (1+ δ )RDS(ON)
(
VIN
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes D3 and D4 shown in Figure 14
conduct during the dead-time between the conduction of
the two power MOSFETs. This prevents the body diode of
the bottom MOSFET from turning on, storing charge during
the dead-time and requiring a reverse recovery period that
could cost as much as 3% in efficiency at high VIN. A 1A
to 3A Schottky is generally a good compromise for both
regions of operation due to the relatively small average
current. Larger diodes result in additional transition losses
due to their larger junction capacitance.
CIN and COUT Selection
The selection of CIN is simplified by the 2-phase architecture
and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It
can be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The controller
with the highest (VOUT)(IOUT) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output
current drawn from the other controller will actually
decrease the input RMS ripple current from its maximum
value. The out-of-phase technique typically reduces the
input capacitor’s RMS ripple current by a factor of 30%
to 70% when compared to a single phase power supply
solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈
1/ 2
IMAX
⎡⎣( VOUT ) ( VIN – VOUT ) ⎤⎦
VIN
This formula has a maximum at VIN = 2VOUT , where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3826-1, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
The benefit of the LTC3826-1 2-phase operation can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
38261fb
15
LTC3826-1
APPLICATIONS INFORMATION
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the dual
controller design. Also, the input protection fuse resistance,
battery resistance, and PC board trace resistance losses
are also reduced due to the reduced peak currents in a
2-phase system. The overall benefit of a multiphase design
will only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The sources of the top MOSFETs should be placed within
1cm of each other and share a common CIN(s). Separating
the sources and CIN may produce undesirable voltage and
current resonances at VIN.
A small (0.1μF to 1μF) bypass capacitor between the chip VIN
pin and ground, placed close to the LTC3826-1, is also suggested. A 10Ω resistor placed between CIN (C1) and the VIN
pin provides further isolation between the two channels.
SENSE+ and SENSE– Pins
The common mode input range of the current comparator
is from 0V to 10V. Continuous linear operation is provided
throughout this range allowing output voltages from 0.8V
to 10V. The input stage of the current comparator requires
that current either be sourced or sunk from the SENSE pins
depending on the output voltage, as shown in the curve in
Figure 4. If the output voltage is below 1.5V, current will
flow out of both SENSE pins to the main output. In these
cases, the output can be easily pre-loaded by the VOUT
resistor divider to compensate for the current comparator’s
negative input bias current. Since VFB is servoed to the
0.8V reference voltage, RA in Figure 3 should be chosen
to be less than 0.8V/ISENSE, with ISENSE determined from
Figure 4 at the specified output voltage.
VOUT
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔVOUT) is approximated by:
OUT
Setting Output Voltage
The LTC3826-1 output voltages are each set by an external
feedback resistor divider carefully placed across the output,
as shown in Figure 3. The regulated output voltage is
determined by:
R
VOUT = 0.8V • 1+ B
R
A
CFF
RA
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
RB
VFB
38261 F03
Figure 3. Setting Output Voltage
60
30
0
INPUT BIAS CURRENT (μA)
1
VOUT IRIPPLE ESR +
8fC
1/2 LTC3826-1
–30
–60
–90
–120
–150
–180
–210
–240
–270
–300
0
1 2 3 4 5 6 7 8 9
VSENSE COMMON MODE VOLTAGE (V)
10
38261 F04
To improve the frequency response, a feed-forward
capacitor, CFF , may be used. Great care should be taken
to route the VFB line away from noise sources, such as
the inductor or the SW line.
Figure 4. SENSE Pins Input Bias Current
vs Common Mode Voltage
38261fb
16
LTC3826-1
APPLICATIONS INFORMATION
Tracking and Soft-Start (TRACK/SS Pins)
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 5.
An internal 1μA current source charges up the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
The LTC3826-1 will regulate the VFB pin (and hence VOUT)
according to the voltage on the TRACK/SS pin, allowing
VOUT to rise smoothly from 0V to its final regulated value.
The total soft-start time will be approximately:
TRACK/SS
CSS
SGND
38261 F05
Figure 5. Using the TRACK/SS Pin to Program Soft-Start
VX (MASTER)
OUTPUT VOLTAGE
The start-up of each VOUT is controlled by the voltage on
the respective TRACK/SS pin. When the voltage on the
TRACK/SS pin is less than the internal 0.8V reference, the
LTC3826-1 regulates the VFB pin voltage to the voltage on
the TRACK/SS pin instead of 0.8V. The TRACK/SS pin can
be used to program an external soft-start function or to
allow VOUT to “track” another supply during start-up.
1/2 LTC3826-1
0.8V
t SS = CSS •
1µA
TIME
VX (MASTER)
VOUT (SLAVE)
R
+ R TRACKB
VX
RA
=
• TRACKA
VOUT R TRACKA
R A + RB
For coincident tracking (VOUT = VX during start-up),
RA = RTRACKA
38261 F06A
(6a) Coincident Tracking
OUTPUT VOLTAGE
Alternatively, the TRACK/SS pin can be used to track two
(or more) supplies during start-up, as shown qualitatively
in Figures 6a and 6b. To do this, a resistor divider should
be connected from the master supply (VX) to the TRACK/
SS pin of the slave supply (VOUT), as shown in Figure 7.
During start-up VOUT will track VX according to the ratio
set by the resistor divider:
VOUT (SLAVE)
TIME
38261 F06B
(6b) Ratiometric Tracking
Figure 6. Two Different Modes of Output Voltage Tracking
RB = RTRACKB
Vx VOUT
INTVCC Regulators
The LTC3826-1 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power
at the INTVCC pin from either the VIN supply pin or the
EXTVCC pin, respectively, depending on the connection
of the EXTVCC pin. INTVCC powers the gate drivers and
much of the LTC3826-1’s internal circuitry. The VIN LDO
regulates the voltage at the INTVCC pin to 5.25V and the
RB
1/2 LTC3826-1
VFB
RA
RTRACKB
TRACK/SS
RTRACKA
38261 F07
Figure 7. Using the TRACK/SS Pin for Tracking
38261fb
17
LTC3826-1
APPLICATIONS INFORMATION
EXTVCC LDO regulates it to 7.5V. Each of these can supply
a peak current of 50mA and must be bypassed to ground
with a minimum of 4.7μF ceramic capacitor. The ceramic
capacitor placed directly adjacent to the INTVCC and
PGND IC pins is highly recommended. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3826-1 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the 5.25V
VIN LDO or the 7.5V EXTVCC LDO. When the voltage on the
EXTVCC pin is less than 4.7V, the VIN LDO is enabled. Power
dissipation for the IC in this case is highest and is equal
to VIN • INTVCC. The gate charge current is dependent on
operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated
by using the equation given in Note 2 of the Electrical Characteristics. For example, the LTC3826-1 INTVCC current is
limited to less than 24mA from a 24V supply when in the
G package and not using the EXTVCC supply:
TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from one of the LTC3826-1’s
switching regulator outputs (4.7V ≤ VOUT ≤ 10V) during
normal operation and from the VIN LDO when the output
is out of regulation (e.g., start-up, short-circuit). If more
current is required through the EXTVCC LDO than is specified, an external Schottky diode can be added between the
EXTVCC and INTVCC pins. Do not apply more than 10V to
the EXTVCC pin and make sure than EXTVCC ≤ VIN.
Significant efficiency and thermal gains can be realized
by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
For 5V to 10V regulator outputs, this means connecting
the EXTVCC pin directly to VOUT . Tying the EXTVCC pin
to a 5V supply reduces the junction temperature in the
previous example from 125°C to:
TJ = 70°C + (24mA)(5V)(95°C/W) = 81°C
However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTVCC power from
the output.
The following list summarizes the four possible connections for EXTVCC:
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (PLLIN/MODE
= INTVCC) at maximum VIN.
1. EXTVCC Left Open (or Grounded). This will cause
INTVCC to be powered from the internal 5.25V regulator
resulting in an efficiency penalty of up to 10% at high
input voltages.
When the voltage applied to EXTVCC rises above 4.7V, the
VIN LDO is turned off and the EXTVCC LDO is enabled. The
EXTVCC LDO remains on as long as the voltage applied to
EXTVCC remains above 4.5V. The EXTVCC LDO attempts
to regulate the INTVCC voltage to 7.5V, so while EXTVCC
is less than 7.5V, the LDO is in dropout and the INTVCC
voltage is approximately equal to EXTVCC. When EXTVCC
is greater than 7.5V up to an absolute maximum of 10V,
INTVCC is regulated to 7.5V.
2. EXTVCC Connected directly to VOUT . This is the normal
connection for a 5V to 10V regulator and provides the
highest efficiency.
3. EXTVCC Connected to an External supply. If an external
supply is available in the 5V to 10V range, it may be
used to power EXTVCC providing it is compatible with
the MOSFET gate drive requirements.
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18
LTC3826-1
APPLICATIONS INFORMATION
4. EXTVCC Connected to an Output-Derived Boost Network.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with the capacitive charge
pump shown in Figure 8.
VIN
CIN
1μF
+
BAT85
VIN
0.22μF
BAT85
LTC3826-1
N-CH
EXTVCC
BAT85
VN2222LL
TG1
RSENSE
VOUT
SW
L1
+
COUT
BG1
N-CH
improved. If there is no change in input current, then there
is no change in efficiency.
Fault Conditions: Current Limit and Current Foldback
The LTC3826-1 includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 70% of its nominal output level, then
the maximum sense voltage is progressively lowered from
100mV to 30mV. Under short-circuit conditions with very
low duty cycles, the LTC3826-1 will begin cycle skipping
in order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time tON(MIN) of
the LTC3826-1 (≈230ns), the input voltage and inductor
value:
ΔIL(SC) = tON(MIN) (VIN/L)
The resulting short-circuit current is:
PGND
38261 F08
Figure 8. Capacitive Charge Pump for EXTVCC
ISC =
30mV 1
– ΔI
RSENSE 2 L(SC)
Fault Conditions: Overvoltage Protection (Crowbar)
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors, CB, connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor CB in the Functional Diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is to be turned on,
the driver places the CB voltage across the gate-source
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage, SW,
rises to VIN and the BOOST pin follows. With the topside
MOSFET on, the boost voltage is above the input supply:
VBOOST = VIN + VINTVCC. The value of the boost capacitor
CB needs to be 100 times that of the total input capacitance
of the topside MOSFET(s). The reverse breakdown of the
external Schottky diode must be greater than VIN(MAX).
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the controller
is operating.
A comparator monitors the output for overvoltage
conditions. The comparator (OV) detects overvoltage faults
greater than 10% above the nominal output voltage. When
this condition is sensed, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared. The bottom MOSFET remains on
continuously for as long as the OV condition persists; if
VOUT returns to a safe level, normal operation automatically
resumes. A shorted top MOSFET will result in a high current
condition which will open the system fuse. The switching
regulator will regulate properly with a leaky top MOSFET
by altering the duty cycle to accommodate the leakage.
38261fb
19
LTC3826-1
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3826-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOSFET
of controller 1 to be locked to the rising edge of an external
clock signal applied to the PLLIN/MODE pin. The turn-on
of controller 2’s top MOSFET is thus 180 degrees out of
phase with the external clock. The phase detector is an
edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the external filter
network connected to the PLLLPF pin. The relationship
between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to PLLIN/
MODE, is shown in Figure 9 and specified in the Electrical
Characteristics table. Note that the LTC3826-1 can only
be synchronized to an external clock whose frequency is
within range of the LTC3826-1’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simplified block diagram
is shown in Figure 10.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the PLLLPF pin. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor CLP holds the voltage.
The loop filter components, CLP and RLP , smooth out
the current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01μF.
Typically, the external clock (on PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
250kHz
Floating
DC Voltage
390kHz
INTVCC
DC Voltage
530kHz
RC Loop Filter
Clock Signal
Phase-Locked to External Clock
900
800
2.4V
RLP
FREQUENCY (kHz)
700
600
CLP
500
PLLIN/
MODE
400
EXTERNAL
OSCILLATOR
300
200
PLLLPF
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
100
0
0
0.5
1
1.5
PLLLPF VOLTAGE (V)
2
2.5
38261 F10
38261 F09
Figure 9. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
Figure 10. Phase-Locked Loop Block Diagram
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20
LTC3826-1
APPLICATIONS INFORMATION
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration that the LTC3826-1 is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
tON(MIN) <
VOUT
VIN (f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3826-1 is approximately
230ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
250ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3826-1 circuits: 1) IC VIN current, 2) INTVCC
regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1. The VIN current has two components: the first is the
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control
currents; the second is the current drawn from the 3.3V
linear regulator output. VIN current typically results in
a small (1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT , causing a rapid drop in VOUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
38261fb
22
LTC3826-1
APPLICATIONS INFORMATION
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example for one channel, assume VIN =
12V(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A,
and f = 250kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLLPF
pin to GND, generating 250kHz operation. The minimum
inductance for 30% ripple current is:
IL =
VOUT VOUT
1–
(f)(L)
VIN
A 4.7μH inductor will produce 23% ripple current and a
3.3μH will result in 33%. The peak inductor current will
be the maximum DC value plus one half the ripple current, or 5.84A, for the 3.3μH value. Increasing the ripple
current will also help ensure that the minimum on-time
of 230ns is not violated. The minimum on-time occurs at
maximum VIN:
VOUT
1.8V
tON(MIN) =
=
= 327ns
VIN(MAX) f 22V(250kHz)
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
RSENSE ≤
The power dissipation on the top side MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF. At
maximum input voltage with T(estimated) = 50°C:
1.8V 2
(5) [1+ (0.005)(50°C – 25°C)] •
22V
(0.035) + (22V )2 5A
( 4)(215pF ) •
2
PMAIN =
1
1
5 – 2.3 + 2.3 ( 300kHz ) = 332mW
A short-circuit to ground will result in a folded back
current of:
ISC =
25mV 1 120ns(22V)
–
= 2.1A
0.01 2 3.3μH
with a typical value of RDS(ON) and δ = (0.005/°C)(20) =
0.1. The resulting power dissipated in the bottom MOSFET
is:
22V – 1.8V
(2.1A )2 (1.125)(0.022Ω)
22V
= 100mW
PSYNC =
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VORIPPLE = RESR (ΔIL) = 0.02Ω(1.67A) = 33mVP-P
80mV
≈ 0.012Ω
5.84A
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
38261fb
23
LTC3826-1
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 11. Figure 12 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain
connection at CIN? Do not attempt to split the input
decoupling for the two channels as it can cause a large
resonant loop.
ITH1
TRACK/SS1
VFB1
PGOOD1
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3826-1 VFB pins’ resistive dividers connect to
the (+) terminals of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
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