LTC3831EGN-1#PBF

LTC3831-1 High Power Synchronous Switching Regulator Controller for DDR Memory Termination U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®3831-1 is a high power, high efficiency switching regulator controller designed for DDR memory termination. The LTC3831-1 generates an output voltage equal to 1/2 of an external supply or reference voltage. The LTC3831-1 uses a synchronous switching architecture with N-channel MOSFETs. Additionally, the chip senses output current through the drain-source resistance of the upper N-channel FET, providing an adjustable current limit without a current sense resistor. VOUT as Low as 0.4V High Power Switching Regulator Controller for DDR Memory Termination VOUT Tracks 1/2 of VIN or External VREF No Current Sense Resistor Required Low VCC Supply: 3V to 8V Maximum Duty Cycle > 91% Over Temperature Drives All N-Channel External MOSFETs High Efficiency: Up to 95% Programmable Fixed Frequency Operation: 100kHz to 500kHz External Clock Synchronization Operation Programmable Soft-Start Low Shutdown Current: 91%. It includes a fixed frequency PWM oscillator for low output ripple operation. The 300kHz free-running clock frequency can be externally adjusted or synchronized with an external signal from 100kHz to above 500kHz. In shutdown mode, the LTC3831-1 supply current drops to