LTC3834
30µA IQ Synchronous
Step-Down Controller
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 10V
Low Operating Quiescent Current: 30µA
OPTI-LOOP® Compensation Minimizes COUT
±1% Output Voltage Accuracy
Wide VIN Range: 4V to 36V
Phase-Lockable Fixed Frequency 140kHz to 650kHz
Dual N-Channel MOSFET Synchronous Drive
Very Low Dropout Operation: 99% Duty Cycle
Adjustable Output Voltage Soft-Start or Tracking
Output Current Foldback Limiting
Power Good Output Voltage Monitor
Clock Output for PolyPhase® Applications
Output Overvoltage Protection
Low Shutdown IQ: 4µA
Internal LDO Powers Gate Drive from VIN or VOUT
Selectable Continuous, Pulse Skipping or
Burst Mode® Operation at Light Loads
Small 20-Lead TSSOP or 4mm × 5mm QFN Package
The LTC®3834 is a high performance step-down switching
regulator controller that drives an all N-channel synchronous power MOSFET stage. A constant-frequency current
mode architecture allows a phase-lockable frequency of
up to 650kHz.
The 30µA no-load quiescent current extends operating
life in battery powered systems. OPTI-LOOP compensation allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
LTC3834 features a precision 0.8V reference and a power
good output indicator. The 4V to 36V input supply range
encompasses a wide range of battery chemistries.
The TRACK/SS pin ramps the output voltage during
start‑up. Current foldback limits MOSFET heat dissipation
during short-circuit conditions. A reduced feature set
version of the part (LTC3834-1) is available in a smaller,
lower pin count package.
Comparison of LTC3834 and LTC3834-1
APPLICATIONS
n
n
n
n
CLKOUT/
PHASMD
EXTVCC
PGOOD
LTC3834
Yes
Yes
Yes
FE20/4mm × 5mm QFN
LTC3834-1
No
No
No
GN16/3mm × 5mm DFN
PART #
Automotive Systems
Telecom Systems
Battery-Operated Digital Devices
Distributed DC Power Systems
PACKAGES
L, LT, LTC, LTM, Burst Mode, PolyPhase and OPTI-LOOP are registered trademarks and
No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 5408150, 5481178,
5705919, 5929620, 6304066, 6498466, 6580258, 6611131.
TYPICAL APPLICATION
High Efficiency Synchronous Step-Down Converter
CLKOUT
PLLLPF
RUN
68.1k
VIN
4V TO 36V
90
0.22µF
TRACK/SS
ITH
LTC3834
BOOST
0.012Ω
150pF
SGND
INTVCC
PLLIN/MODE
EXTVCC
VFB
4.7µF
VOUT
3.3V
5A
150µF
70
100
60
50
10
40
30
1
20
BG
10
SENSE–
SENSE+
1000
80
3.3µH
SW
10000
100
POWER LOSS (mW)
54.2k
215k
TG
PGOOD
560pF
10µF
EFFICIENCY (%)
0.01µF
VIN
0
0.000001
PGND
0.0001
0.01
OUTPUT CURRENT (A)
1
0.1
3834 TA01b
3834 TA01
3834fc
For more information www.linear.com/LTC3834
1
LTC3834
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Input Supply Voltage (VIN).......................... 36V to –0.3V
Topside Driver Voltage (BOOST)................. 42V to –0.3V
Switch Voltage (SW)...................................... 36V to –5V
INTVCC, (BOOST-SW), CLKOUT, PGOOD .. 8.5V to –0.3V
RUN, TRACK/SS ......................................... 7V to –0.3V
SENSE+, SENSE– Voltages ..........................11V to –0.3V
PLLIN/MODE, PHASMD, PLLLPF .......... INTVCC to –0.3V
EXTVCC ...................................................... 10V to –0.3V
ITH, VFB Voltages ....................................... 2.7V to –0.3V
Peak Output Current fOSC
650
530
580
kHz
115
140
kHz
800
kHz
–5
5
µA
µA
3834fc
For more information www.linear.com/LTC3834
3
LTC3834
ELECTRICAL
CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPG
PGOOD Trip Level
VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
VFB Ramping Positive
TYP
MAX
UNITS
0.1
0.3
V
±1
µA
–8
12
%
%
PGOOD Output
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3834E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3834I is guaranteed to meet
performance specifications over the –40°C to 85°C operating temperature
range.
–12
8
–10
10
Note 4: The LTC3834 is tested in a feedback loop that servos VITH to a
specified voltage and measures the resultant VFB.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC3834FE: TJ = TA + (PD • 35°C/W)
LTC3834UFD: TJ = TA + (PD • 37°C/W)
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current
80
EFFICIENCY (%)
100
60
50
10
40
30
1
20
10
0
0.000001
FIGURE 11 CIRCUIT
0.0001
0.01
OUTPUT CURRENT (A)
1
0.1
3834 G01
4
VIN = 12V
VIN = 5V
90 VOUT = 3.3V
1000
POWER LOSS (mW)
70
Burst Mode OPERATION
FORCED CONTINUOUS MODE
PULSE SKIPPING MODE
VIN = 12V
VOUT = 3.3V
98
100
94
80
70
60
92
90
88
86
84
50
40
0.000001
VOUT = 3.3V
FIGURE 11 CIRCUIT
96
EFFICIENCY (%)
90
Efficiency vs Input Voltage
Efficiency vs Load Current
10000
EFFICIENCY (%)
100
TA = 25°C, unless otherwise noted.
82
FIGURE 11 CIRCUIT
0.0001
0.01
OUTPUT CURRENT (A)
1
3834 G02
80
0
5
10
15 20 25 30
INPUT VOLTAGE (V)
35
40
3834 G03
3834fc
For more information www.linear.com/LTC3834
LTC3834
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
(Forced Continuous Mode)
Load Step (Burst Mode Operation)
VOUT
100mV/DIV
AC
COUPLED
Load Step (Pulse Skipping Mode)
VOUT
100mV/DIV
AC
COUPLED
VOUT
100mV/DIV
AC
COUPLED
IL
2A/DIV
IL
2A/DIV
IL
2A/DIV
20µs/DIV
VOUT = 3.3V
FIGURE 11 CIRCUIT
TA = 25°C, unless otherwise noted.
20µs/DIV
VOUT = 3.3V
FIGURE 11 CIRCUIT
3834 G04
Inductor Current at Light Load
20µs/DIV
VOUT = 3.3V
FIGURE 11 CIRCUIT
3834 G05
Soft Start-Up
3834 G06
Tracking Start-Up
FORCED
CONTINUOUS
MODE
MASTER
2V/DIV
2A/DIV
Burst Mode
OPERATION
VOUT
1V/DIV
VOUT
2V/DIV
PULSE
SKIPPING
MODE
VOUT = 3.3V
2µs/DIV
ILOAD = 100µA
FIGURE 11 CIRCUIT
Total Input Supply Current vs
Input Voltage
EXTVCC Switchover and INTVCC
Voltages vs Temperature
FIGURE 11 CIRCUIT
EXTVCC AND INTVCC VOLTAGE (V)
SUPPLY CURRENT (µA)
200
300µA LOAD
100
0
3834 G09
INTVCC Line Regulation
5.8
250
NO LOAD
50
5.5
6.0
300
150
20ms/DIV
FIGURE 11 CIRCUIT
5.4
5.6
5.4
INTVCC VOLTAGE (V)
350
3834 G08
20ms/DIV
FIGURE 11 CIRCUIT
3834 G07
INTVCC
5.2
5.0
EXTVCC RISING
4.8
4.6
EXTVCC FALLING
4.4
5.3
5.2
5.1
4.2
5
10
20
25
15
INPUT VOLTAGE (V)
30
35
3834 G10
4.0
–45
–25
35
55
–5
15
TEMPERATURE (°C)
75
95
3834 G11
5.0
0
5
10
15 20 25 30
INPUT VOLTAGE (V)
35
40
3834 G12
3834fc
For more information www.linear.com/LTC3834
5
LTC3834
TYPICAL PERFORMANCE CHARACTERISTICS
SENSE Pins Total Input
Bias Current
6O
30
0
40
20
0
–30
–60
–90
–120
–150
–180
–210
–20
–240
–40
–270
–300
10% DUTY CYCLE
0
0.2
1.0
0.4 0.6 0.8
ITH PIN VOLTAGE (V)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
80
Maximum Current Sense
Threshold vs Duty
60
FORCED CONTINUOUS
Burst Mode OPERATION
(RISING)
Burst Mode OPERATION
(FALLING)
PULSE SKIPPING
INPUT BIAS CURRENT (µA)
CURRENT SENSE THRESHOLD (mV)
100
Maximum Current Sense Voltage
vs ITH Voltage Cycle
1.2
1.4
1 2 3 4 5 6 7 8 9
VSENSE COMMON MODE VOLTAGE (V)
0
3834 G13
80
60
40
20
0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3834 G15
4
40
SENSE Pins Total Input
Bias Current vs ITH
38
80
60
40
20
36
INPUT CURRENT (µA)
100
QUIESCENT CURRENT (µA)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
100
Quiescent Current vs Temperature
120
34
32
30
28
26
3
2
1
24
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
FEEDBACK VOLTAGE (V)
22
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
3834 G16
0
0
0.2
0.4
0.6 0.8 1.0
ITH VOLTAGE (V)
1.2
1.4
3834 G18
1.00
0.95
1.25
0.90
1.20
RUN PIN VOLTAGE (V)
TRACK/SS CURRENT (µA)
90
Shutdown (RUN) Threshold
vs Temperature
1.30
1.15
1.10
1.05
1.00
0.85
0.80
0.75
0.70
0.65
0.60
0.95
0.90
–45 –30 –15
75
3834 G17
TRACK/SS Pull-Up Current
vs Temperature
0.55
0 15 30 45 60
TEMPERATURE (°C)
75
90
0.50
–45 –30 –15
3834 G19
6
10
120
3834 G14
Foldback Current Limit
0
TA = 25°C, unless otherwise noted.
0 15 30 45 60
TEMPERATURE (°C)
75
90
3834 G20
3834fc
For more information www.linear.com/LTC3834
LTC3834
TYPICAL PERFORMANCE CHARACTERISTICS
SENSE Pins Total Input Bias
Current vs Temperature
60
806
0
INPUT CURRENT (µA)
804
802
800
798
796
10
VOUT = 3.3V
–30
–60
–90
–120
–150
–180
VOUT = 0V
–210
0 15 30 45 60
TEMPERATURE (°C)
75
90
–270
–300
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
3834 G21
6
4
75
90
0
5
10
30
35
3834 G23
Undervoltage Lockout Threshold
vs Temperature
4.2
800
4.1
700
4.0
600
INTVCC VOLTAGE (V)
VPLLLPF = INTVCC
500
VPLLLPF = FLOAT
400
300
VPLLLPF = GND
200
RISING
3.9
3.8
FALLING
3.7
3.6
3.5
3.4
100
3.3
0
–45
–25
35
55
–5
15
TEMPERATURE (°C)
75
3.2
–45 –30 –15
95
0 15 30 45 60
TEMPERATURE (°C)
75
90
3834 G25
3834 G24
INTVCC vs Load Current
Shutdown Current vs Temperature
5.3
7
VIN = 12V
6
SHUTDOWN CURRENT (µA)
5.2
5.1
5.0
4.9
EXTVCC = 5V
4.8
4.7
4.6
15
20
25
INPUT VOLTAGE (V)
3834 G22
Oscillator Frequency
vs Temperature
FREQUENCY (kHz)
8
2
–240
794
792
–45 –30 –15
12
VOUT = 10V
30
INTVCC VOLTAGE (V)
REGULATED FEEDBACK VOLTAGE (mV)
808
Shutdown Current
vs Input Voltage
INPUT CURRENT (µA)
Regulated Feedback Voltage
vs Temperature
TA = 25°C, unless otherwise noted.
5
4
3
2
1
0
10
40
20
30
LOAD CURRENT (mA)
50
60
0
–45 –30 –15
3834 G26
0 15 30 45 60
TEMPERATURE (°C)
75
90
3834 G27
3834fc
For more information www.linear.com/LTC3834
7
LTC3834
PIN FUNCTIONS
(FE/UFD)
CLKOUT (Pin 1/Pin 19): Open-Drain Output Clock Signal
available to daisy-chain other controller ICs for additional
MOSFET driver stages/phases.
PLLLPF (Pin 2/Pin 20): The phase-locked loop’s lowpass
filter is tied to this pin when synchronizing to an external
clock. Alternatively, tie this pin to GND, INTVCC or leave
floating to select 250kHz, 530kHz or 400kHz switching
frequency.
ITH (Pin 3/Pin 1): Error Amplifier Outputs and Switching
Regulator Compensation Points. The current comparator
trip point increases with this control voltage.
TRACK/SS (Pin 4/Pin 2): External Tracking and Soft-Start
Input. The LTC3834 regulates the VFB voltage to the smaller
of 0.8V or the voltage on the TRACK/SS pin. A internal 1µA
pull-up current source is connected to this pin. A capacitor
to ground at this pin sets the ramp time to final regulated
output voltage. Alternatively, a resistor divider on another
voltage supply connected to this pin allows the LTC3834
output to track the other supply during start-up.
VFB (Pin 5/Pin 3): Receives the remotely sensed feedback
voltage from an external resistive divider across the output.
SGND (Pin 6/Pin 4): Small-Signal Ground. Must be routed
separately from high current grounds to the common (–)
terminals of the input capacitor.
PGND (Pin 7/Pin 5): Driver Power Ground. Connects to
the source of bottom (synchronous) N-channel MOSFET,
anode of the Schottky rectifier and the (–) terminal of CIN.
BG (Pin 8/Pin 6): High Current Gate Drive for Bottom
(Synchronous) N-Channel MOSFET. Voltage swing at this
pin is from ground to INTVCC.
INTVCC (Pin 9/Pin 7): Output of the Internal Linear Low
Dropout Regulator. The driver and control circuit are
powered from this voltage source. Must be decoupled
to power ground with a minimum of 4.7µF tantalum or
ceramic capacitor.
EXTVCC (Pin 10/Pin 8): External Power Input to an Internal
LDO Connected to INTVCC. This LDO supplies VCC power,
bypassing the internal LDO powered from VIN whenever
EXTVCC is higher than 4.7V. See EXTVCC Connection in
8
the Applications Information section. Do not exceed 10V
on this pin.
VIN (Pin 11/Pin 9): Main Supply Pin. A bypass capacitor
should be tied between this pin and the signal ground pin.
SW (Pin 12/Pin 10): Switch Node Connections to Inductor.
Voltage swing at this pin is from a Schottky diode (external)
voltage drop below ground to VIN.
TG (Pin 13/Pin 11): High Current Gate Drive for Top
N-Channel MOSFET. These are the outputs of floating
drivers with a voltage swing equal to INTVCC – 0.5V superimposed on the switch node voltage SW.
BOOST (Pin 14/Pin 12): Bootstrapped Supply to the
Topside Floating Driver. A capacitor is connected between
the BOOST and SW pins and a Schottky diode is tied
between the BOOST and INTVCC pins. Voltage swing at the
BOOST pin is from INTVCC to (VIN + INTVCC).
RUN (Pin 15/Pin 13): Digital Run Control Input for
Controller. Forcing this pin below 0.7V shuts down all
controller functions, reducing the quiescent current that
the LTC3834 draws to approximately 4µA.
SENSE– (Pin 16/Pin 14): The (–) Input to the Differential
Current Comparator.
SENSE+ (Pin 17/Pin 15): The (+) Input to the Differential
Current Comparator. The ITH pin voltage and controlled
offsets between the SENSE– and SENSE+ pins in conjunction with RSENSE set the current trip threshold.
PGOOD (Pin 18/Pin 16): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on the VFB pin is not
within ±10% of its set point.
PLLIN/MODE (Pin 19/Pin 17): External Synchronization
Input to Phase Detector and Forced Continuous Control
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock. In
this case, an R-C filter must be connected to the PLLLPF
pin. When not synchronizing to an external clock, this
input determines how the LTC3834 operates at light loads.
Pulling this pin below 0.7V selects Burst Mode operation.
Tying this pin to INTVCC forces continuous inductor current
3834fc
For more information www.linear.com/LTC3834
LTC3834
PIN FUNCTIONS
(FE/UFD)
operation. Tying this pin to a voltage greater than 0.9V
and less than INTVCC selects pulse-skipping operation.
Exposed Pad (Pin 21/Pin 21): SGND. Must be soldered
to the PCB.
PHASMD (Pin 20/Pin 18): Control Input to Phase Selector
which determines the phase relationships between TG and
the CLKOUT signal.
FUNCTIONAL DIAGRAM
PLLIN/
MODE
FIN
PHASE DET
INTVCC
PHASMD
BOOST
RLP PLLLPF
CLP
DROP
OUT
DET
CLK
OSCILLATOR
INTVCC
10k CLKOUT
–
0.88V
+
PGOOD
–
+
S
Q
R
Q
BOT
SWITCH
LOGIC
BURSTEN
+
B
–
+
–
PLLIN/MODE
0.8V
+
VOUT
SHDN
ICMP
+
–
BURSTEN
0.45V
2(VFB)
VIN
L
–
++
–
–
IR
+
SENSE+
6mV
SENSE–
OV
–
RSENSE
FC
VIN
EXTVCC
COUT
SLEEP
–
EA
+
+
BG
PGND
SLOPE
COMP
4.7V
CIN
INTVCC
BOT
0.4V
CB
SW
VFB1
0.72V
DB
D
FC
TOP ON
–
INTVCC – 0.5V
TG
TOP
VIN
5.25V/
7.5V
LDO
VFB
TRACK/SS
0.80V
RB
RA
+
–
0.88V
0.5µA
ITH
CC
CC2
6V
INTVCC
VFB
RC
1µA
+
TRACK/SS
SGND
INTERNAL
SUPPLY
RUN
SHDN
CSS
3834 FD
3834fc
For more information www.linear.com/LTC3834
9
LTC3834
OPERATION (Refer to Functional Diagram)
Main Control Loop
The LTC3834 uses a constant-frequency, current mode
step-down architecture. During normal operation, the external top MOSFET is turned on when the clock sets the RS
latch, and is turned off when the main current comparator,
ICMP, resets the RS latch. The peak inductor current at
which ICMP trips and resets the latch is controlled by the
voltage on the ITH pin, which is the output of the error amplifier EA. The error amplifier compares the output voltage
feedback signal at the VFB pin, (which is generated with
an external resistor divider connected across the output
voltage, VOUT , to ground) to the internal 0.800V reference
voltage. When the load current increases, it causes a slight
decrease in VFB relative to the reference, which cause the
EA to increase the ITH voltage until the average inductor
current matches the new load current.
The top MOSFET driver is biased from the floating bootstrap
capacitor, CB, which normally recharges during each off
cycle through an external diode when the top MOSFET
turns off. If the input voltage VIN decreases to a voltage
close to VOUT , the loop may enter dropout and attempt
to turn on the top MOSFET continuously. The dropout
detector detects this and forces the top MOSFET off for
about one twelfth of the clock period every tenth cycle to
allow CB to recharge.
Shutdown and Start-Up (RUN and TRACK/SS Pins)
The LTC3834 can be shut down using the RUN pin. Pulling
this pin below 0.7V shuts down the main control loop
of the controller. A low disables the controller and most
internal circuits, including the INTVCC regulator, at which
time the LTC3834 draws only 4µA of quiescent current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
Releasing the RUN pin allows an internal 0.5µA current
to pull up the pin and enable that controller. Alternatively,
the RUN pin may be externally pulled up or driven directly
by logic. Be careful not to exceed the Absolute Maximum
rating of 7V on this pin.
INTVCC/EXTVCC Power
The start-up of the output voltage VOUT is controlled by
the voltage on the TRACK/SS pin. When the voltage on
the TRACK/SS pin is less than the 0.8V internal reference,
the LTC3834 regulates the VFB voltage to the TRACK/SS
pin voltage instead of the 0.8V reference. This allows
the TRACK/SS pin to be used to program a soft-start by
connecting an external capacitor from the TRACK/SS pin
to SGND. An internal 1µA pull-up current charges this
capacitor creating a voltage ramp on the TRACK/SS pin.
As the TRACK/SS voltage rises linearly from 0V to 0.8V
(and beyond), the output voltage VOUT rises smoothly
from zero to its final value.
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open or tied to a voltage less
than 4.7V, an internal 5.25V low dropout linear regulator
supplies INTVCC power from VIN. If EXTVCC is taken above
4.7V, the 5.25V regulator is turned off and a 7.5V low
dropout linear regulator is enabled that supplies INTVCC
power from EXTVCC. If EXTVCC is less than 7.5V (but
greater than 4.7V), the 7.5V regulator is in dropout and
INTVCC is approximately equal to EXTVCC. When EXTVCC
is greater than 7.5V (up to an absolute maximum rating
of 10V), INTVCC is regulated to 7.5V. Using the EXTVCC
pin allows the INTVCC power to be derived from a high
efficiency external source such as one of the LTC3834
switching regulator outputs.
10
Alternatively the TRACK/SS pin can be used to cause the
start-up of VOUT to “track” that of another supply. Typically, this requires connecting to the TRACK/SS pin an
external resistor divider from the other supply to ground
(see Applications Information section).
3834fc
For more information www.linear.com/LTC3834
LTC3834
OPERATION (Refer to Functional Diagram)
When the RUN pin is pulled low to disable the LTC3834, or
when VIN drops below its undervoltage lockout threshold
of 3.7V, the TRACK/SS pin is pulled low by an internal
MOSFET. When in undervoltage lockout, the controller is
disabled and the external MOSFETs are held off.
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Continuous Conduction)
(PLLIN/MODE Pin)
The LTC3834 can be enabled to enter high efficiency
Burst Mode operation, constant-frequency pulse-skipping
mode, or forced continuous conduction mode at low load
currents. To select Burst Mode operation, tie the PLLIN/
MODE pin to a DC voltage below 0.8V (e.g., SGND). To
select forced continuous operation, tie the PLLIN/MODE
pin to INTVCC. To select pulse skipping mode, tie the
PLLIN/MODE pin to a DC voltage greater than 0.8V and
less than INTVCC – 0.5V.
When the LTC3834 is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-tenth of the maximum sense voltage even though
the voltage on the ITH pin indicates a lower value. If the
average inductor current is lower than the load current, the
error amplifier EA will decrease the voltage on the ITH pin.
When the ITH voltage drops below 0.4V, the internal sleep
signal goes high (enabling “sleep” mode) and both external
MOSFETs are turned off. The ITH pin is then disconnected
from the output of the EA and “parked” at 0.425V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3834 draws
to only 30µA. In sleep mode, the load current is supplied
by the output capacitor. As the output voltage decreases,
the EA’s output begins to rise. When the output voltage
drops enough, the ITH pin is reconnected to the output
of the EA, the sleep signal goes low, and the controller
resumes normal operation by turning on the top external
MOSFET on the next cycle of the internal oscillator.
When the LTC3834 is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (RICMP) turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative, thus
operating in discontinuous operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by the
voltage on the ITH pin, just as in normal operation. In this
mode, the efficiency at light loads is lower than in Burst
Mode operation. However, continuous operation has the
advantages of lower output ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse skipping mode or clocked by an external clock source to
use the phase-locked loop (see Frequency Selection and
Phase-Locked Loop section), the LTC3834 operates in
PWM pulse skipping mode at light loads. In this mode,
constant-frequency operation is maintained down to
approximately 1% of designed maximum output current.
At very light loads, the current comparator ICMP may remain tripped for several cycles and force the external top
MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
3834fc
For more information www.linear.com/LTC3834
11
LTC3834
OPERATION
Frequency Selection and Phase-Locked Loop
(PLLLPF and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to
maintain low output ripple voltage.
The switching frequency of the LTC3834’s controllers can
be selected using the PLLLPF pin.
If the PLLIN/MODE pin is not being driven by an external clock source, the PLLLPF pin can be floated, tied to
INTVCC, or tied to SGND to select 400kHz, 530kHz or
250kHz, respectively.
A phase-locked loop (PLL) is available on the LTC3834
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. In this
case, a series R-C should be connected between the
PLLLPF pin and SGND to serve as the PLL’s loop filter.
The LTC3834 phase detector adjusts the voltage on the
PLLLPF pin to align the turn-on of the external top MOSFET
to the rising edge of the synchronizing signal.
The typical capture range of the LTC3834’s phase-locked
loop is from approximately 115kHz to 800kHz, with a
guarantee to be between 140kHz and 650kHz. In other
words, the LTC3834’s PLL is guaranteed to lock to an
external clock source whose frequency is between 140kHz
and 650kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3834 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with
the LTC3834 in PolyPhase applications. The clock output
12
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal, as summarized in Table 1.
The phases are calculated relative to the zero degrees
phase being defined as the rising edge of the top gate
driver output (TG).
The CLKOUT pin has an open-drain output device. Normally, a 10k to 100k resistor can be connected from this
pin to a voltage supply that is less than or equal to 8.5V.
Table 1
VPHASMD
CLKOUT PHASE
GND
90°
Floating
120°
INTVCC
180°
Output Overvoltage Protection
An overvoltage comparator guards against transient overshoots as well as other more serious conditions that may
overvoltage the output. When the VFB pin rises to more
than 10% higher than its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good (PGOOD) Pin
The PGOOD pin is connected to an open-drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the VFB pin voltage is not within
±10% of the 0.8V reference voltage. The PGOOD pin is also
pulled low when the RUN pin is low (shut down). When
the VFB pin voltage is within the ±10% requirement, the
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source of up to 8.5V.
3834fc
For more information www.linear.com/LTC3834
LTC3834
APPLICATIONS INFORMATION
RSENSE Selection For Output Current
RSENSE is chosen based on the required output current.
The current comparator has a maximum threshold of
100mV/RSENSE and an input common mode range of
SGND to 10V. The current comparator threshold sets the
peak of the inductor current, yielding a maximum average
output current IMAX equal to the peak value less half the
peak-to-peak ripple current, ∆IL.
Allowing a margin for variations in the IC and external
component values yields:
RSENSE =
80mV
IM AX
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆IL decreases with higher
inductance or frequency and increases with higher VIN:
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to the
internal compensation required to meet stability criterion
for buck regulators operating at greater than 50% duty
factor. A curve is provided to estimate this reduction in
peak output current level depending upon the operating
duty factor.
Operating Frequency and Synchronization
The choice of operating frequency, is a trade-off between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses,
both gate charge loss and transition loss. However, lower
frequency operation requires more inductance for a given
amount of ripple current.
The internal oscillator of the LTC3834 runs at a nominal
400kHz frequency when the PLLLPF pin is left floating
and the PLLIN/MODE pin is a DC low or high. Pulling the
PLLLPF to INTVCC selects 530kHz operation; pulling the
PLLLPF to SGND selects 250kHz operation.
Alternatively, the LTC3834 will phase-lock to a clock
signal applied to the PLLIN/MODE pin with a frequency
between 140kHz and 650kHz (see Phase-Locked Loop
and Frequency Synchronization).
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
∆IL =
V
1
VOUT 1– OUT
(f)(L)
VIN
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.3(IMAX). The maximum
∆IL occurs at the maximum input voltage.
The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
10% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
selected. As inductance increases, core losses go down.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
3834fc
For more information www.linear.com/LTC3834
13
LTC3834
APPLICATIONS INFORMATION
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
The MOSFET power dissipations at maximum output
current are given by:
Power MOSFET and Schottky Diode (Optional)
Selection
Two external power MOSFETs must be selected for the
LTC3834: one N-channel MOSFET for the top (main)
switch, and one N-channel MOSFET for the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC voltage.
This voltage is typically 5V during start-up (see EXTVCC Pin
Connection). Consequently, logic-level threshold MOSFETs
must be used in most applications. The only exception is
if low input voltage is expected (VIN < 5V); then, sub-logic
level threshold MOSFETs (VGS(TH) < 3V) should be used.
Pay close attention to the BVDSS specification for the
MOSFETs as well; most of the logic-level MOSFETs are
limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance RDS(ON), Miller capacitance CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the Gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
VOUT
VIN
V –V
Synchronous Switch Duty Cycle = IN OUT
VIN
14
VOUT
(IM AX )2 (1+ δ∆T )RDS(ON ) +
VIN
I
( VIN )2 M AX (RDR ) (CM ILLER ) •
2
1
1
+
V
( f)
INTVCC – VTHM IN VTHM IN
PM AIN =
PSYNC =
VIN – VOUT
(IM AX )2 (1+ δ∆T )RDS(ON )
VIN
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET ’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ∆T) is generally given for a MOSFET in
the form of a normalized RDS(ON) vs Temperature curve,
but δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diode D1 shown in Figure 6 conducts during the dead-time between the conduction of the
two power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead-time and requiring a reverse recovery period that
could cost as much as 3% in efficiency at high VIN. A 1A
to 3A Schottky is generally a good compromise for both
regions of operation due to the relatively small average
current. Larger diodes result in additional transition losses
due to their larger junction capacitance.
3834fc
For more information www.linear.com/LTC3834
LTC3834
APPLICATIONS INFORMATION
CIN and COUT Selection
VOUT
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current must be used. The maximum RMS
capacitor current is given by:
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
1
∆VOUT ≈ IRIPPLE ESR +
8fCOUT
3834 F01
Figure 1. Setting Output Voltage
200
100
0
–100
–200
–300
–400
–500
–600
–700
0
1 2 3 4 5 6 7 8 9
VSENSE COMMON MODE VOLTAGE (V)
10
3835 F02
Figure 2. SENSE Pins Input Bias Current
vs Common Mode Voltage
To improve the frequency response, a feed-forward capacitor, CFF , may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor and the SW line.
SENSE+ and SENSE– Pins
where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
Setting Output Voltage
The LTC3834 output voltage is set by an external feedback
resistor divider carefully placed across the output, as shown
in Figure 1. The regulated output voltage is determined by:
R
VOUT = 0.8V • 1+ B
RA
CFF
RA
1/2
I
≈ M AX ( VOUT ) ( VIN – VOUT )
VIN
This formula has a maximum at VIN = 2VOUT , where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3834, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
RB
VFB
INPUT CURRENT (µA)
CIN Required IRM S
LTC3834
The common mode input range of the current comparator
is from 0V to 10V. Continuous linear operation is provided
throughout this range allowing output voltages from 0.8V
to 10V. The input stage of the current comparator requires
that current either be sourced or sunk from the SENSE pins
depending on the output voltage, as shown in the curve in
Figure 2. If the output voltage is below 1.5V, current will
flow out of both SENSE pins to the main output. In these
cases, the output can be easily pre-loaded by the VOUT
resistor divider to compensate for the current comparator’s
negative input bias current. Since VFB is servoed to the
0.8V reference voltage, RA in Figure 1 should be chosen
to be less than 0.8V/ISENSE, with ISENSE determined from
Figure 2 at the specified output voltage.
3834fc
For more information www.linear.com/LTC3834
15
LTC3834
APPLICATIONS INFORMATION
according to the voltage on the TRACK/SS pin, allowing
VOUT to rise smoothly from 0V to its final regulated value.
The total soft-start time will be approximately:
Tracking and Soft-Start (TRACK/SS Pin)
The start-up of VOUT is controlled by the voltage on the
TRACK/SS pin. When the voltage on the TRACK/SS pin
is less than the internal 0.8V reference, the LTC3834 regulates the VFB pin voltage to the voltage on the TRACK/
SS pin instead of 0.8V. The TRACK/SS pin can be used to
program an external soft-start function or to allow VOUT
to “track” another supply during start-up.
tSS = CSS •
0.8V
1µA
Alternatively, the TRACK/SS pin can be used to track two
(or more) supplies during start-up, as shown qualitatively
in Figures 4a and 4b. To do this, a resistor divider should
be connected from the master supply (VX) to the TRACK/
SS pin of the slave supply (VOUT), as shown in Figure 5.
During start-up VOUT will track VX according to the ratio
set by the resistor divider:
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 3.
An internal 1µA current source charges up the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
The LTC3834 will regulate the VFB pin (and hence VOUT)
LTC3834
TRACK/SS
CSS
R
+ RTRACKB
VX
RA
=
• TRACKA
VOUT RTRACKA
RA + RB
For coincident tracking (VOUT = VX during start-up),
SGND
3834 F03
RA = RTRACKA
Figure 3. Using the TRACK/SS Pin to Program Soft-Start
RB = RTRACKB
VX (MASTER)
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VX (MASTER)
VOUT (SLAVE)
TIME
VOUT (SLAVE)
TIME
3834 F04A
(4a) Coincident Tracking
3834 F04B
(4b) Ratiometric Tracking
Figure 4. Two Different Modes of Output Voltage Tracking
Vx
VOUT
RB
LTC3834
VFB
RA
RTRACKB
TRACK/SS
RTRACKA
3834 F05
Figure 5. Using the TRACK/SS Pin for Tracking
16
For more information www.linear.com/LTC3834
3834fc
LTC3834
APPLICATIONS INFORMATION
INTVCC Regulators
The LTC3834 features two separate internal P-channel low
dropout linear regulators (LDO) that supply power at the
INTVCC pin from either the VIN supply pin or the EXTVCC
pin, respectively, depending on the connection of the
EXTVCC pin. INTVCC powers the gate drivers and much of
the LTC3834’s internal circuitry. The VIN LDO regulates
the voltage at the INTVCC pin to 5.25V and the EXTVCC
LDO regulates it to 7.5V. Each of these can supply a peak
current of 50mA and must be bypassed to ground with a
minimum of 4.7µF ceramic capacitor. The ceramic capacitor
placed directly adjacent to the INTVCC and PGND IC pins is
highly recommended. Good bypassing is needed to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3834 to be
exceeded. The INTVCC current, which is dominated by
the gate charge current, may be supplied by either the 5V
VIN LDO or the 7.5V EXTVCC LDO. When the voltage on
the EXTVCC pin is less than 4.7V, the VIN LDO is enabled.
Power dissipation for the IC in this case is highest and is
equal to VIN • IINTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 3 of the
Electrical Characteristics. For example, the LTC3834 INTVCC
current is limited to less than 41mA from a 24V supply
when in the G package and not using the EXTVCC supply:
TJ = 70°C + (41mA)(36V)(95°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (PLLIN/MODE
= INTVCC) at maximum VIN.
When the voltage applied to EXTVCC rises above 4.7V, the
VIN LDO is turned off and the EXTVCC LDO is enabled. The
EXTVCC LDO remains on as long as the voltage applied to
EXTVCC remains above 4.5V. The EXTVCC LDO attempts
to regulate the INTVCC voltage to 7.5V, so while EXTVCC
is less than 7.5V, the LDO is in dropout and the INTVCC
voltage is approximately equal to EXTVCC. When EXTVCC
is greater than 7.5V up to an absolute maximum of 10V,
INTVCC is regulated to 7.5V.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from the LTC3834 switching
regulator output (4.7V ≤ VOUT ≤ 10V) during normal operation and from the VIN LDO when the output is out of
regulation (e.g., start-up, short circuit). If more current
is required through the EXTVCC LDO than is specified,
an external Schottky diode can be added between the
EXTVCC and INTVCC pins. Do not apply more than 10V to
the EXTVCC pin and make sure that EXTVCC ≤ VIN.
Significant efficiency and thermal gains can be realized by
powering INTVCC from the output, since the VIN current
resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency). For
4.7V to 10V regulator outputs, this means connecting the
EXTVCC pin directly to VOUT . Tying the EXTVCC pin to a 5V
supply reduces the junction temperature in the previous
example from 125°C to:
TJ = 70°C + (24mA)(5V)(95°C/W) = 81°C
However, for 3.3V and other low voltage outputs, additional
circuitry is required to derive INTVCC power from the output.
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC Left Open (or Grounded). This will cause
INTVCC to be powered from the internal 5.25V regulator
resulting in an efficiency penalty of up to 10% at high
input voltages.
2. EXTVCC Connected Directly to VOUT . This is the normal
connection for a 5V regulator and provides the highest
efficiency.
3. EXTVCC Connected to an External supply. If an external
supply is available in the 5V to 7V range, it may be used
to power EXTVCC providing it is compatible with the
MOSFET gate drive requirements.
4. EXTVCC Connected to an Output-Derived Boost Network.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with the capacitive charge
pump shown in Figure 6.
3834fc
For more information www.linear.com/LTC3834
17
LTC3834
APPLICATIONS INFORMATION
Topside MOSFET Driver Supply (CB, DB)
Fault Conditions: Current Limit and Current Foldback
External bootstrap capacitors, CB, connected to the BOOST
pins supply the gate drive voltages for the topside MOSFET.
Capacitor CB in the Functional Diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When the topside MOSFET is to be turned on, the driver
places the CB voltage across the gate-source of the desired
MOSFET. This enhances the MOSFET and turns on the
topside switch. The switch node voltage, SW, rises to VIN
and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: VBOOST
= VIN + VINTVCC. The value of the boost capacitor, CB,
needs to be 100 times that of the total input capacitance
of the topside MOSFET. The reverse breakdown of the
external Schottky diode must be greater than VIN(MAX).
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
improved. If there is no change in input current, then
there is no change in efficiency.
The LTC3834 includes current foldback to help limit load
current when the output is shorted to ground. If the output
falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 100mV
to 30mV. Under short-circuit conditions with very low duty
cycles, the LTC3834 will begin cycle skipping in order to
limit the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less
than in normal operation. The short-circuit ripple current
is determined by the minimum on-time, tON(MIN), of the
LTC3834 (≈200ns), the input voltage and inductor value:
VIN
CIN
LTC3834
1µF
+
BAT85
VIN
SW
BAT85
BAT85
VN2222LL
TG1
EXTVCC
0.22µF
RSENSE
N-CH
VOUT
L1
+
BG1
COUT
N-CH
PGND
3834 F06
Figure 6. Capacitive Charge Pump for EXTVCC
18
∆IL(SC) = tON(MIN) (VIN/L)
The resulting short-circuit current is:
ISC =
30mV 1
– ∆IL (SC )
RSENSE 2
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the controller
is operating.
A comparator monitors the output for overvoltage conditions. The comparator (OV) detects overvoltage faults
greater than 10% above the nominal output voltage. When
this condition is sensed, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared. The bottom MOSFET remains on
continuously for as long as the overvoltage condition
persists; if VOUT returns to a safe level, normal operation
automatically resumes. A shorted top MOSFET will result in
a high current condition which will open the system fuse.
The switching regulator will regulate properly with a leaky
top MOSFET by altering the duty cycle to accommodate
the leakage.
3834fc
For more information www.linear.com/LTC3834
LTC3834
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3834 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET (TG)
to be locked to the rising edge of an external clock signal
applied to the PLLIN/MODE pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the external filter
network connected to the PLLLPF pin. The relationship
between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to PLLIN/
MODE, is shown in Figure 7 and specified in the Electrical
Characteristics table. Note that the LTC3834 can only
be synchronized to an external clock whose frequency
is within range of the LTC3834’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simplified block diagram
is shown in Figure 8.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor CLP holds the voltage.
The loop filter components, CLP and RLP , smooth out
the current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01µF.
Typically, the external clock (on PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is 1.2V.
900
2.4V
800
RLP
FREQUENCY (kHz)
700
CLP
600
500
EXTERNAL
OSCILLATOR
400
PLLIN/
MODE
300
PLLLPF
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
200
100
0
0
0.5
1
1.5
2
PLLLPF PIN VOLTAGE (V)
2.5
3834 F08
Figure 8. Phase-Locked Loop Block Diagram
3835 F07
Figure 7. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
3834fc
For more information www.linear.com/LTC3834
19
LTC3834
APPLICATIONS INFORMATION
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
250kHz
Floating
DC Voltage
400kHz
INTVCC
DC Voltage
530kHz
RC Loop Filter
Clock Signal
Phase-Locked to External Clock
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3834 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
tON(M IN ) <
VOUT
VIN (f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3834 is approximately
200ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
250ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
20
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3834 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1. The VIN current has two components: the first is the
DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control
currents; the second is the current drawn from the 3.3V
linear regulator output. VIN current typically results in
a small (< 0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
Supplying INTVCC power through the EXTVCC switch
input from an output-derived source will scale the VIN
current required for the driver and control circuits by
a factor of (Duty Cycle)/(Efficiency). For example, in a
20V to 5V application, 10mA of INTVCC current results
in approximately 2.5mA of VIN current. This reduces
the mid-current loss from 10% or more (if the driver
was powered directly from VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor, and input and output capacitor ESR. In continuous
mode the average output current flows through L and
RSENSE, but is “chopped” between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs have
approximately the same RDS(ON), then the resistance
of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For
example, if each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE
= 10mΩ and RESR = 40mΩ (sum of both input and
output capacitance losses), then the total resistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
For more information www.linear.com/LTC3834
3834fc
LTC3834
APPLICATIONS INFORMATION
a 5V output, or a 4% to 20% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET, and
become significant only when operating at high input
voltages (typically 15V or greater). Transition losses
can be estimated from:
Transition Loss = (1.7) VIN2 IO(MAX) CRSS f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum
of 20µF to 40µF of capacitance having a maximum of 20mΩ
to 50mΩ of ESR. Other losses including Schottky conduction losses during dead-time and inductor core losses
generally account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT . ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed-loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Typical Application
circuit will provide an adequate starting point for most
applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is in
the feedback loop and is the filtered and compensated
control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop
will be increased by decreasing CC. If RC is increased by
the same factor that CC is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT , causing a rapid drop in VOUT . No regulator can
alter its delivery of current quickly enough to prevent this
3834fc
For more information www.linear.com/LTC3834
21
LTC3834
APPLICATIONS INFORMATION
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF.
At maximum input voltage with T(estimated) = 50°C:
Design Example
As a design example, assume VIN = 12V(nominal), VIN =
22V(max), VOUT = 1.8V, IMAX = 5A, and f = 250kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLLPF
pin to GND, generating 250kHz operation. The minimum
inductance for 30% ripple current is:
V
V
∆IL = OUT 1– OUT
(f)(L)
VIN
VOUT
VIN(M AX ) f
=
1.8V
= 327ns
22V(250kHz)
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
RSENSE ≤
A short-circuit to ground will result in a folded back current of:
ISC =
25mV 1 120ns(22V)
= 2.1A
–
0.01Ω 2 3.3µH
with a typical value of RDS(ON) and δ = (0.005/°C)(20) = 0.1.
The resulting power dissipated in the bottom MOSFET is:
A 4.7µH inductor will produce 23% ripple current and a
3.3µH will result in 33%. The peak inductor current will be
the maximum DC value plus one half the ripple current, or
5.84A, for the 3.3µH value. Increasing the ripple current will
also help ensure that the minimum on-time of 180ns is not
violated. The minimum on-time occurs at maximum VIN:
tON(M IN ) =
1.8V 2
( 5) [1+ (0.005)(50°C – 25°C)] •
22V
5A
( 0.035Ω) + ( 22V )2 ( 4Ω) (215pF ) •
2
1
1
+
5 – 2.3 2.3 ( 300kHz ) = 332mW
PM AIN =
22V – 1.8V
(2.1A )2 (1.125) (0.022Ω)
22V
= 100mW
PSYNC =
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VORIPPLE = RESR (∆IL) = 0.02Ω(1.67A) = 33mVP-P
80mV
≈ 0.012Ω
5.84A
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
22
3834fc
For more information www.linear.com/LTC3834
LTC3834
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 9. The Figure 10 illustrates the
current waveforms present in the various branches of the
synchronous regulator operating in the continuous mode.
Check the following in your layout:
1. Is the top N-channel MOSFET M1 located within 1cm
of CIN?
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Does the LTC3834 VFB pin resistive divider connect to
the (+) terminals of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
4. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
5. Is the INTVCC decoupling capacitor connected close to
the IC, between the INTVCC and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTVCC and PGND pins can help improve
noise performance substantially.
6. Keep the switching node (SW), top gate node (TG), and
boost node (BOOST) away from sensitive small-signal
nodes. All of these nodes have very large and fast
moving signals and therefore should be kept on the
“output side” of the LTC3834 and occupy minimum
PC trace area.
7. Use a modified “star ground” technique: a low impedance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
output voltage as well. Check for proper performance
over the operating voltage and current range expected
in the application. The frequency of operation should be
maintained over the input voltage range down to dropout
and until the output load drops below the low current
operation threshold—typically 10% of the maximum
designed current level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
3834fc
For more information www.linear.com/LTC3834
23
LTC3834
APPLICATIONS INFORMATION
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
C1
1nF
VIN
CB
CIN
M1
VIN
SW
TG
BOOST
RUN
SENSE–
M2
D1
OPTIONAL
VOUT
COUT
EXTVCC
INTVCC
BG
PGND
SGND
DB
VFB
SENSE+
TRACK/SS
PGOOD
ITH
PLLIN/MODE
PLLLPF
PHASMD
CLKOUT
LTC3834EFE
L1
3834 F09
Figure 9. LTC3834 Recommended Printed Circuit Layout Diagram
SW
VIN
RIN
CIN
D1
L1
RSENSE
VOUT
COUT
RL1
3834 F10
BOLD LINES INDICATE HIGH SWITCHING
CURRENT. KEEP LINES TO A MINIMUM LENGTH.
Figure 10. Branch Current Waveforms
24
3834fc
For more information www.linear.com/LTC3834
LTC3834
TYPICAL APPLICATIONS
High Efficiency 9.5V, 3A Step-Down Converter
INTVCC
100k
CLKOUT
VIN
PLLLPF
100k
0.01µF
TG
RUN
PGOOD
TRACK/SS
ITH
560pF
39.2k
CB
0.22µF
L1
7.2µH
BOOST
0.015Ω
SW
LTC3834
100pF
105k
CIN
10µF
M1
VIN
10V TO 36V
DB
CMDSH-3
SGND
INTVCC
PLLIN/MODE
EXTVCC
VFB
VOUT
9.5V
3A
COUT
150µF
4.7µF
M2
BG
SENSE–
432k
SENSE+
22pF
PGND
3834 TA02
M1, M2: Si4840DY
L1: CDEP105-7R2M
COUT: SANYO 10TPD150M
High Efficiency 12V to 1.8V, 2A Step-Down Converter
CLKOUT
PLLLPF
TG
RUN
0.01µF
VIN
PGOOD
TRACK/SS
ITH
1000pF
48.7k
68.1k
SW
20mΩ
DB
CMDSH-3
SGND
INTVCC
PLLIN/MODE
EXTVCC
VFB
M1
L1
3.3µH
BOOST
LTC3834
100pF
CB
0.22µF
VIN
CIN 12V
10µF
BG
VOUT
1.8V
2A
COUT
100µF
CERAMIC
4.7µF
M2
SENSE–
84.5k
100pF
SENSE+
PGND
3834 TA03
M1, M2: Si4840DY
L1: TOKO DS3LC A915AY-3R3M
3834fc
For more information www.linear.com/LTC3834
25
LTC3834
TYPICAL APPLICATIONS
High Efficiency 5V, 5A Step-Down Converter
CLKOUT
PLLLPF
TG
RUN
0.01µF
VIN
PGOOD
TRACK/SS
ITH
560pF
69.8k
SW
INTVCC
PLLIN/MODE
EXTVCC
BG
VOUT
5V
5A
COUT
150µF
4.7µF
M2
SENSE–
365k
39pF
SENSE+
PGND
3834 TA04
M1, M2: Si4840DY
L1: CDEP105-3R2M
COUT: SANYO 10TPD150M
26
0.012Ω
DB
CMDSH-3
SGND
VFB
M1
L1
3.3µH
BOOST
LTC3834
150pF
54k
CB
0.22µF
VIN
CIN 5.5V TO 36V
10µF
3834fc
For more information www.linear.com/LTC3834
LTC3834
TYPICAL APPLICATIONS
High Efficiency 1.2V, 5A Step-Down Converter
INTVCC
CLKOUT
GND
10k
PLLLPF
TG
RUN
0.01µF
VIN
PGOOD
TRACK/SS
ITH
2.2nF
26.1k
68.1k
SW
VIN
4V TO 36V
0.012Ω
DB
CMDSH-3
SGND
INTVCC
PLLIN/MODE
EXTVCC
VFB
M1
L1
2.2µH
BOOST
LTC3834
100pF
CB
0.22µF
CIN
10µF
BG
VOUT
1.2V
5A
COUT
150µF
×2
4.7µF
M2
SENSE–
34k
390pF
SENSE+
PGND
3834 TA05
M1, M2: Si4840DY
L1: CDEP105-2R2M
COUT: SANYO 10TPD150M
3834fc
For more information www.linear.com/LTC3834
27
LTC3834
PACKAGE DESCRIPTION
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20 1918 17 16 15 14 13 12 11
6.60 ± 0.10
2.74
(.108)
4.50 ± 0.10
6.40
2.74 (.252)
(.108) BSC
SEE NOTE 4
0.45 ± 0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
(.0077 – .0118)
TYP
FE20 (CB) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
UFD Package
20-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)
0.75 ± 0.05
4.00 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
C = 0.35
1.50 REF
R = 0.05 TYP
19
0.70 ± 0.05
20
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
4.50 ± 0.05
1.50 REF
3.10 ± 0.05
2.65 ± 0.05
3.65 ± 0.05
2
5.00 ± 0.10
(2 SIDES)
2.50 REF
3.65 ± 0.10
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
2.50 REF
4.10 ± 0.05
5.50 ± 0.05
2.65 ± 0.10
(UFD20) QFN 0506 REV B
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
28
R = 0.115
TYP
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3834fc
For more information www.linear.com/LTC3834
LTC3834
REVISION HISTORY
REV
DATE
DESCRIPTION
C
02/15
Changed VIN to INTVCC in PLLPF pin function description.
PAGE NUMBER
8
3834fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection
its circuits
as described
herein will not infringe on existing patent rights.
Forof more
information
www.linear.com/LTC3834
29
LTC3834
TYPICAL APPLICATION
CLKOUT
PLLLPF
RUN
PGOOD
TRACK/SS
0.01µF
VIN
TG
CB
0.22µF
M1
L1
3.2µH
BOOST
ITH
560pF
54k
SW
68.1k
VIN
4V TO 36V
0.012Ω
VOUT
3.3V
5A
COUT
150µF
DB
CMDSH-3
LTC3834
150pF
CIN
10µF
SGND
INTVCC
PLLIN/MODE
EXTVCC
VFB
BG
4.7µF
M2
SENSE–
215k
SENSE+
39pF
PGND
3834 F11
M1, M2: Si4840DY
L1: CDEP105-2R2M
COUT: SANYO 10TPD150M
Figure 11. High Efficiency Step-Down Converter
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1735
High Efficiency Synchronous Step-Down Switching Regulator
Output Fault Protection, 16-Pin SSOP
LTC1778/
LTC1778-1
No RSENSE Current Mode Synchronous Step-Down
Controllers
Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN),
IOUT Up to 20A
LTC3708
Dual, 2-Phase, DC/DC Controller with Output Tracking
Current Mode, No RSENSE, Up/Down Tracking, Synchronizable
LTC3727/
LTC3727-1
High Efficiency, 2-Phase, Synchronous Step-Down Switching
Regulators
2-Phase Operation; 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 14V,
99% Duty Cycle, 5mm × 5mm QFN, SSOP-28
LTC3728
Dual, 550kHz, 2-Phase Synchronous Step-Down Controller
Dual 180° Phased Controllers, VIN 3.5V to 35V, 99% Duty Cycle,
5mm × 5mm QFN, SSOP-28
LTC3729
20A to 200A, 550kHz PolyPhase Synchronous Controller
Expandable from 2-Phase to 12-Phase, Uses All Surface Mount
Components, VIN Up to 36V
LTC3731
3- to 12-Phase Step-Down Synchronous Controller
60A to 240A Output Current, 0.6V ≤ VOUT ≤ 6V, 4.5V ≤ VIN ≤ 32V
LT3800
High Voltage Synchronous Regulator Controller
VIN up to 60V, IOUT ≤ 20A, Current Mode, Onboard Bias Regulator,
Burst Mode Operation, 16-Lead TSSOP Package
LTC3826/
LTC3826-1
30µA IQ, Dual, 2-Phase Synchronous Step-Down Controller
2-Phase Operation; 30µA One Channel No-Load IQ (50µA Total),
4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V
LTC3827/
LTC3827-1
Low IQ Dual Synchronous Controller
2-Phase Operation; 115µA Total No Load IQ, 4V ≤ VIN ≤ 36V 80µA
No-Load IQ with One Channel On
LTC3835/
LTC3835-1
Low IQ Synchronous Step-Down Controller
80µA No Load IQ, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V
LT3844
High Voltage Current Mode Controller with Programmable
Operating Frequency
VIN up to 60V, IOUT ≤ 5A Onboard Bias Regulator, Burst Mode
Operation, Sync Capability, 16-Lead TSSOP Package
LT3845
Low IQ Synchronous Step-Down Controller
4V ≤ VIN ≤ 60V, 1.23V ≤ VOUT ≤ 36V, 120µA Quiescent Current
LTC3850
Dual, 2-Phase Synchronous Step-Down DC/DC Controller
2-Phase Operation; 4V ≤ VIN ≤ 24V, 95% Efficiency, No RSENSE
Option, IOUT up to 20A, 4mm × 4mm QFN
30 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC3834
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC3834
3834fc
LT 0215 REV C • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2007