LTC3882-1/LTC3882-2
Dual Output PolyPhase
Step-Down DC/DC Voltage Mode Controller
with Digital Power System Management
DESCRIPTION
FEATURES
PMBus/I2C Compliant Serial Interface
– Monitor Voltage, Current, Temperature and Faults
– Program Voltage, Soft-Start/Stop, Sequencing,
Margining, AVP and UV/OV/OC Limits
n 3V ≤ VINSNS ≤ 38V, 0.1V ≤ V
OUT ≤ 5.25V
n ±0.5% Output Voltage Error
n Programmable PWM Frequency or External Clock
Synchronization from 250kHz to 1.25MHz (2.5MHz-2)
n Accurate PolyPhase® Current Sharing
n Internal EEPROM with Fault Logging and ECC
n IC Supply Range: 3V to 13.2V
n Resistor or Inductor DCR Current Sensing
n Power Good Output Voltage Monitor
n Optional Resistor Programming for Key Parameters
n 40-Pin (6mm × 6mm) QFN Package
n AEC-Q100 Qualified for Automotive Applications
n
APPLICATIONS
High Current Distributed Power Systems
Servers, Network and Storage Equipment
n Intelligent Energy Efficient Power Regulation
n
The LTC®3882-1/LTC3882-2 is a dual, PolyPhase DC/DC
synchronous step-down switching regulator controller
with PMBus compliant serial interface. It uses a constant frequency, leading-edge modulation, voltage mode
architecture for excellent transient response and output
regulation. Each PWM channel can produce output voltages
from 0.1V to 5.25V using a wide range of 3.3V compatible
power stages, including power blocks, DrMOS or discrete
FET drivers. Up to four LTC3882-1 devices can operate in
parallel for 2-, 3-, 4-, 6- or 8-phase operation.
System configuration and monitoring is supported by the
LTpowerPlay™ software tool. The LTC3882-1/LTC3882-2
serial interface can read back input voltage, output voltage
and current, temperature and fault status. Most operating
parameters can be set via the digital interface or stored in
internal EEPROM for use at power up. Switching frequency
and phase, output voltage and device address can also be
set using external configuration resistors.
In this document, statements related to the LTC3882-1 apply
to the LTC3882-2 unless specifically noted.
n
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 5396245, 5859606, 6144194, 6937178, 7420359 and 7000125.
TYPICAL APPLICATION
MAX PWM
PWM ENABLE
TG/BG
HW WRITE
DEDICATED
DIFFERENTIAL
OUTPUT
CONTROL PROTECT PGOOD OUTPUT VOUT SENSE FREQUENCY
VOUT0
1.25MHz
LTC3882-1
•
VOUT0 & VOUT1
1.25MHz
LTC3882-2
•
VOUT0 & VOUT1
2.5MHz
LTC3882
VIN
7V TO 13.2V
•
•
•
+
VCC VINSNS V
SENSE0
FB0
SDA
TO/FROM
MCU
LTC3882-1
SCL
ALERT
SYNC
SHARE_CLK
IAVG0
ISENSE0+
ISENSE0–
VSENSE1+
ISENSE1–
ISENSE1+
PWM1
IOUT
10A/DIV
FDMF5820DC
PWM
TSNS1
VSENSE0–
–
GND VSENSE1
VIN
SW
IL0, IL1
10A/DIV
GND
50µs/DIV
INDUCTORS: COOPER FP1007R1-R22
SOME DETAILS OMITTED FOR CLARITY
Document Feedback
Load Step Transient Current Sharing
(Using FDMF5820DC DrMOS)
GND
PWM0
TSNS0
PGOOD1
FAULT1
IAVG_GND
VOUT
1V
70A
SW
COMP1
RUN0
RUN1
IAVG1
PWM
VIN
COMP0
PGOOD0
FAULT0
TO/FROM
EXTERNAL DEVICES
FDMF5820DC
38821 TA01b
38821 TA01a
For more information www.analog.com
Rev. C
1
LTC3882-1/LTC3882-2
TABLE OF CONTENTS
Features...................................................... 1
Applications................................................. 1
Typical Application ......................................... 1
Description.................................................. 1
Absolute Maximum Ratings............................... 5
Order Information........................................... 5
Pin Configuration........................................... 5
Electrical Characteristics.................................. 6
Typical Performance Characteristics................... 10
Pin Functions............................................... 14
Block Diagram.............................................. 16
Test Circuit.................................................. 17
Timing Diagram............................................ 17
Operation................................................... 18
Overview............................................................. 18
Main Control Loop............................................... 18
Power-Up and Initialization.................................. 19
Soft-Start............................................................ 21
Time-Based Output Sequencing.......................... 21
Output Ramping Control...................................... 21
Voltage-Based Output Sequencing......................22
Minimum Output Disable Times..........................22
Output Short Cycle..............................................22
Light Load Current Operation..............................22
Switching Frequency and Phase..........................23
PolyPhase Load Sharing......................................23
Active Voltage Positioning................................... 24
Input Supply Monitoring...................................... 24
Output Voltage Sensing and Monitoring.............. 24
Output Current Sensing and Monitoring.............. 24
External and Internal Temperature Sense............ 24
Resistor Configuration Pins................................. 24
Internal EEPROM with CRC and ECC...................25
Fault Detection.....................................................26
Input Supply Faults..............................................26
Hardwired PWM Response to VOUT Faults..........26
Power Good Indication (Master)..........................26
Power Good Indication (Slave)............................ 27
Hardwired PWM Response to IOUT Faults........... 27
Hardwired PWM Response to Temperature
Faults................................................................27
2
Hardwired PWM Response to Timing Faults....... 27
External Faults..................................................... 28
Fault Handling...................................................... 28
Status Registers and ALERT Masking.................. 28
FAULT Pin I/O.......................................................30
Fault Logging.......................................................30
Factory Default Operation....................................33
Serial Interface....................................................34
Serial Bus Addressing.........................................34
Serial Bus Timeout..............................................38
Serial Communication Errors..............................38
PMBus Command Summary............................. 39
PMBus Commands..............................................39
Data Formats.......................................................39
Applications Information................................. 44
Efficiency Considerations....................................44
PWM Frequency and Inductor Selection..............44
Power MOSFET Selection....................................45
MOSFET Driver Selection....................................46
Using PWM Protocols.........................................46
CIN Selection........................................................46
COUT Selection..................................................... 47
Feedback Loop Compensation.............................48
PCB Layout Considerations................................. 49
Output Current Sensing.......................................50
Output Voltage Sensing....................................... 52
Soft-Start and Stop.............................................53
Time-Based Output Sequencing and Ramping...... 53
Voltage-Based Output Sequencing......................54
Using Output Voltage Servo................................56
Using AVP...........................................................56
PWM Frequency Synchronization........................ 57
PolyPhase Operation and Load Sharing..............58
External Temperature Sense................................ 61
Resistor Configuration Pins.................................62
Internal Regulator Outputs..................................65
IC Junction Temperature.....................................65
Derating EEPROM Retention at Temperature.......66
Configuring Open-Drain Pins...............................66
PMBus Communication and Command
Processing.......................................................... 67
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
TABLE OF CONTENTS
Status and Fault Log Management......................68
LTpowerPlay – An Interactive Digital Power GUI.... 68
Design Example...................................................69
PMBus COMMAND DETAILS.............................. 72
Addressing and Write Protect..................................72
PAGE...................................................................72
PAGE_PLUS_WRITE...........................................72
PAGE_PLUS_READ.............................................73
WRITE_PROTECT................................................73
MFR_ADDRESS.................................................. 74
MFR_RAIL_ADDRESS........................................ 74
General Device Configuration.................................. 74
PMBUS_REVISION.............................................. 74
CAPABILITY......................................................... 74
MFR_CONFIG_ALL_LTC3882-1.......................... 75
On, Off and Margin Control...................................... 75
ON_OFF_CONFIG................................................. 75
OPERATION......................................................... 76
MFR_RESET........................................................ 76
PWM Configuration.................................................77
FREQUENCY_SWITCH.........................................77
MFR_PWM_CONFIG_LTC3882-1........................ 78
MFR_CHAN_CONFIG_LTC3882-1....................... 79
MFR_PWM_MODE_LTC3882-1..........................80
Input Voltage and Limits.......................................... 81
VIN_ON............................................................... 81
VIN_OFF.............................................................. 81
VIN_OV_FAULT_LIMIT......................................... 81
VIN_UV_WARN_LIMIT........................................ 81
Output Voltage and Limits.......................................82
VOUT_MODE.......................................................82
VOUT_COMMAND...............................................82
MFR_VOUT_MAX................................................82
VOUT_MAX.........................................................83
MFR_VOUT_AVP.................................................83
VOUT_MARGIN_HIGH.........................................83
VOUT_MARGIN_LOW.........................................83
VOUT_OV_FAULT_LIMIT.....................................83
VOUT_OV_WARN_LIMIT.....................................84
VOUT_UV_WARN_LIMIT.....................................84
VOUT_UV_FAULT_LIMIT.....................................84
Output Current and Limits.......................................85
IOUT_CAL_GAIN.................................................85
MFR_IOUT_CAL_GAIN_TC..................................85
IOUT_OC_FAULT_LIMIT......................................85
IOUT_OC_WARN_LIMIT......................................85
Output Timing, Delays, and Ramping......................86
MFR_RESTART_DELAY.......................................86
TON_DELAY........................................................86
TON_RISE...........................................................86
TON_MAX_FAULT_LIMIT.................................... 87
VOUT_TRANSITION_RATE.................................. 87
TOFF_DELAY....................................................... 87
TOFF_FALL.......................................................... 87
TOFF_MAX_WARN_LIMIT................................... 87
External Temperature and Limits.............................88
MFR_TEMP_1_GAIN............................................88
MFR_TEMP_1_OFFSET........................................88
OT_FAULT_LIMIT.................................................88
OT_WARN_LIMIT................................................88
UT_FAULT_LIMIT.................................................89
Status Reporting......................................................89
STATUS_BYTE.....................................................89
STATUS_WORD...................................................90
STATUS_VOUT....................................................90
STATUS_IOUT.....................................................90
STATUS_INPUT................................................... 91
STATUS_TEMPERATURE..................................... 91
STATUS_CML...................................................... 91
STATUS_MFR_SPECIFIC.....................................92
MFR_PADS_LTC3882-1......................................92
MFR_COMMON...................................................93
MFR_INFO...........................................................93
CLEAR_FAULTS..................................................93
Telemetry.................................................................94
READ_VIN...........................................................94
MFR_VIN_PEAK..................................................94
READ_VOUT........................................................94
MFR_VOUT_PEAK...............................................94
READ_IOUT.........................................................95
MFR_IOUT_PEAK................................................95
READ_POUT........................................................95
Rev. C
For more information www.analog.com
3
LTC3882-1/LTC3882-2
TABLE OF CONTENTS
READ_TEMPERATURE_1....................................95
MFR_TEMPERATURE_1_PEAK...........................95
READ_TEMPERATURE_2....................................95
MFR_TEMPERATURE_2_PEAK...........................96
READ_DUTY_CYCLE...........................................96
READ_FREQUENCY.............................................96
MFR_CLEAR_PEAKS..........................................96
Fault Response and Communication........................ 97
VIN_OV_FAULT_RESPONSE................................ 97
VOUT_OV_FAULT_RESPONSE.............................98
VOUT_UV_FAULT_RESPONSE.............................98
IOUT_OC_FAULT_RESPONSE..............................99
OT_FAULT_RESPONSE...................................... 100
UT_FAULT_RESPONSE...................................... 100
MFR_OT_FAULT_RESPONSE............................ 100
TON_MAX_FAULT_RESPONSE......................... 101
MFR_RETRY_DELAY......................................... 101
SMBALERT_MASK............................................ 101
MFR_FAULT_PROPAGATE_LTC3882-1............. 102
MFR_FAULT_RESPONSE................................... 103
MFR_FAULT_LOG.............................................. 104
4
Fault Log Operation........................................... 104
MFR_FAULT_LOG_CLEAR................................. 104
EEPROM User Access............................................ 105
STORE_USER_ALL........................................... 105
RESTORE_USER_ALL....................................... 105
MFR_COMPARE_USER_ALL............................ 105
Unit Identification.................................................. 106
MFR_ID............................................................. 106
MFR_MODEL..................................................... 106
MFR_SERIAL..................................................... 106
MFR_FAULT_LOG_STORE................................ 106
MFR_EE_xxxx................................................... 106
USER_DATA_0x................................................ 106
IC_DEVICE_ID................................................... 107
IC_DEVICE_REV................................................ 107
MFR_SPECIAL_ID............................................. 107
Typical Applications..................................... 108
Package Description.................................... 110
Revision History......................................... 111
Typical Application...................................... 112
Related Parts............................................. 112
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
*See Derating EEPROM Retention at Temperature in the
Applications Information section for junction temperatures
in excess of 125°C.
ISENSE1+
ISENSE1–
VSENSE1+
VSENSE1–
VSENSE0–
VSENSE0+
ISENSE0–
ISENSE0+
IAVG0
FB0
TOP VIEW
40 39 38 37 36 35 34 33 32 31
COMP0 1
30 IAVG1
TSNS0 2
29 FB1
TSNS1 3
28 COMP1
VINSNS 4
27 PGOOD1
41
GND
IAVG_GND 5
PGOOD0 6
26 PWM1
25 VCC
PWM0 7
24 VDD33
SYNC 8
23 SHARE_CLK
SCL 9
22 VDD25
SDA 10
21 PHAS_CFG
FREQ_CFG
VOUT1_CFG
VOUT0_CFG
ASEL1
ASEL0
RUN1
RUN0
FAULT1
ALERT
11 12 13 14 15 16 17 18 19 20
FAULT0
VCC Supply Voltage..................................... –0.3V to 15V
VINSNS Voltage.......................................... –0.3V to 40V
VSENSEn –....................................................... –0.3V to 1V
VSENSEn+, ISENSEn+, ISENSEn –......................... –0.3V to 6V
FBn, COMPn, TSNSn, IAVG_GND, IAVGn....... –0.3V to 3.6V
SYNC, FAULTn, PGOODn, SHARE_CLK.........–0.3V to 3.6V
SCL, SDA, RUNn, ALERT............................ –0.3V to 5.5V
ASELn, VOUTn_CFG, FREQ_CFG,
PHAS_CFG............................................... –0.3V to 2.75V
PWMn, VDD25................................................... (Note 13)
VDD33................................................................ (Note 14)
Operating Junction Temperature
(Notes 2, 3)........................................... –40°C to 125°C*
Storage Temperature Range................. –65°C to 150°C*
ABSMAX TJ.......................................................... 125°C*
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 125°C, θJA = 33°C/W , θJC = 2.5°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3882IUJ-1#PBF
LTC3882IUJ-1#TRPBF
LTC3882UJ-1
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 125°C
LTC3882IUJ-2#PBF
LTC3882IUJ-2#TRPBF
LTC3882UJ-2
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 125°C
LTC3882IUJ-1#WTRPBF
LTC3882UJ-1
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 125°C
AUTOMOTIVE PRODUCTS**
LTC3882IUJ-1#WPBF
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. C
For more information www.analog.com
5
LTC3882-1/LTC3882-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0– =
VSENSE1– = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IC Supply
VCC
VCC Voltage Range
VDD33 = Internal LDO
VDD33_EXT
VDD33 Voltage Range
VCC = VDD33 (Note 6)
l
VUVLO
Undervoltage Lockout Threshold
VDD33 Rising
Hysteresis
l
IQ
IC Operating Current
tINIT
Controller Initialization Time
4.5
13.8
V
3
3.6
V
42
Delay from RESTORE_USER_ALL, MFR_RESET or
VDD33 > VUVLO Until TON_DELAY Can Begin
3
V
mV
32
mA
35
ms
VDD33 Linear Regulator
VDD33
VDD33 Regulator Output Voltage
VCC ≥ 4.5V
IDD33
VDD33 Current Limit
VDD33 = 2.8V
VDD33 = 0V
3.2
3.3
3.4
85
40
V
mA
mA
VDD25 Linear Regulator
VDD25
VDD25 Regulator Output Voltage
IDD25
VDD25 Current Limit
2.25
2.5
2.75
95
V
mA
PWM Control Loops
VINSNS
VIN Sense Voltage Range
RVINSNS
VINSNS Input Resistance
VOUT_R0
Range 0 Maximum VOUT
Range 0 Set Point Error (Note 7)
Range 0 Set Point Resolution
VOUT_R1
Range 1 Maximum VOUT
Range 1 Set Point Error (Note 7)
Range 1 Set Point Resolution
3
0.6V ≤ VOUT ≤ 5V
0.6V ≤ VOUT ≤ 5V
0.6V ≤ VOUT ≤ 2.5V
0.6V ≤ VOUT ≤ 2.5V
l
l
–0.5
–0.5
VSENSE+ = 5.5V
VSENSE– = 0V
IVSENSE
VSENSE Input Current
VLINEREG
VCC Line Regulation, No Output Servo
4.5V ≤ VCC ≤ 13.2V (See Test Circuit)
AVP
AVP ∆VOUT
AVP = 10%, VOUT_COMMAND = 1.8V,
ISENSE Differential Step 3mV to 12mV
with IOUT_OC_WARN_LIMIT = 15mV
38
kΩ
5.25
±0.2
V
%
%
mV
1.375
2.65
±0.2
0.6875
0.5
0.5
235
–335
–0.02
l
–118
V
278
–108
V
%
%
mV
µA
µA
0.02
%/V
–96
mV
AV(OL)
Error Amplifier Open-Loop Voltage Gain
87
dB
SR
Error Amplifier Slew Rate
9.5
V/µs
f0dB
Error Amplifier Bandwidth
(Note 12)
30
MHz
ICOMP
Error Amplifier Output Current
Sourcing
Sinking
–2.6
34
mA
mA
RVSFB
Resistance Between VSENSE+ and FB
Range 0
Range 1
VISENSE
ISENSE Differential Input Range
ISENSE± Input Current
0V ≤ VPIN ≤ 5.5V
IAVG_VOS
IAVG Current Sense Offset
Referred to ISENSE Inputs
fSYNC
6
Slave Current Sharing Offset
SYNC Frequency Error
52
37
67
49
–1
±0.1
83
61
±70
IISENSE
VSIOS
l
l
l
–600
l
–800
l
–10
Referred to ISENSE Inputs
250kHz ≤ fSYNC ≤ 1.25MHz LTC3882-1,
250kHz ≤ fSYNC ≤ 2.5MHz LTC3882-2
±175
±300
kΩ
kΩ
mV
1
µA
650
µV
µV
700
µV
µV
10
%
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0– =
VSENSE1– = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Supervisor
VON_TOL
Input ON/OFF Threshold Error
NVON
Input ON/OFF Threshold Resolution
15V ≤ VIN_ON ≤ 35V
l
–2
2
143
%
mV
Output Voltage Supervisors
VUVOV_R0
Range 0 Maximum Threshold
Range 0 Error
Range 0 Threshold Resolution
Range 0 Threshold Hysteresis
VUVOV_R1
Range 1 Maximum Threshold
Range 1 Error
Range 1 Threshold Resolution
Range 1 Threshold Hysteresis
Output Current Supervisors
Output Current Limit Tolerance
VILIM_TOL
ISENSE+ – ISENSE–
2V ≤ VOUT ≤ 5V (Falling for UV and Rising for OV)
1V ≤ VOUT ≤ 2.5V (Falling for UV and Rising for OV)
15mV < ISENSE+ – ISENSE– ≤ 30mV
30mV < ISENSE+ – ISENSE– ≤ 50mV
50mV < ISENSE+ – ISENSE– ≤ 70mV
1LSB
l
l
l
l
l
–1
–1
5.5
11
2.75
5.5
–1.7
–2.5
–5.2
ISENSE+ – ISENSE– Threshold Resolution
NlLIM
ADC Readback Telemetry (Note 8)
VINSNS Readback Resolution
(Note 9)
NVIN
VINSNS Total Unadjusted Readback Error 4.5V ≤ VINSNS ≤ 38V
VIN_TUE
PWM Duty Cycle Resolution
PWM Duty Cycle Total Unadjusted
Readback Error
VOUT Readback Resolution
VOUT Total Unadjusted Readback Error
(Note 9)
PWM Duty Cycle = 12.5%
NISENSE
IOUT Readback Resolution
LSB Step Size (at ISENSE±)
ISENSE_TUE
ISENSE_OS
NTEMP
TEXT_TUE
IOUT Total Unadjusted Readback Error
IOUT Zero-Code Offset Voltage
Temperature Resolution
External Temperature Total Unadjusted
Readback Error
(Note 9)
0mV ≤ |ISENSE+ – ISENSE–| < 16mV
16mV ≤ |ISENSE+ – ISENSE–| < 32mV
32mV ≤ |ISENSE+ – ISENSE–| < 63.9mV
63.9mV ≤ |ISENSE+ – ISENSE–| ≤ 70mV
|ISENSE+ – ISENSE–| ≥ 6mV, 0V ≤ VOUT ≤ 5.5V
NVOUT
VOUT_TUE
Internal Temperature Total Unadjusted
Readback Error
Update Rate
tCONVERT
Internal EEPROM (Notes 4, 6)
Endurance
Number of Write Operations
Retention
Stored Data Retention
Mass Write Time STORE_USER_ALL Execution Duration
1
25
0.4
10
0.5
2
10
–2
0.6V ≤ VOUT ≤ 5.5V, Constant Load
l
TINT_TUE
50
1.7
2.5
5.2
l
NDC
DCTUE
1
–0.5
2
244
±0.2
0.5
10
15.625
31.25
62.5
125
l
–1
1
±32
0.25
TSNS0, TSNS1 ≤ 1.85V (Note 10)
MFR_PWM_MODE_LTC3882-1[6] = 0
MFR_PWM_MODE_LTC3882-1[6] = 1
Internal Diode (Note 10)
l
l
–3
–7
(Note 11)
0°C ≤ TJ ≤ 85°C During All Write Operations
TJ ≤ 125°C
0°C ≤ TJ ≤ 85°C During All Write Operations
3
7
V
%
mV
mV
V
%
mV
mV
mV
mV
mV
mV
Bits
%
%
Bits
%
µV
%
%
Bits
µV
µV
µV
µV
%
µV
°C
±1
°C
°C
°C
90
ms
0.2
Cycles
Years
s
10,000
10
2
Rev. C
For more information www.analog.com
7
LTC3882-1/LTC3882-2
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0– =
VSENSE1– = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
Digital Inputs (SCL, SDA, RUNn, FAULTn, SYNC, SHARE_CLOCK)
Input High Voltage
SCL, SDA, RUN0, RUN1, FAULT0, FAULT1
VIH
SYNC, SHARE_CLK
Input Low Voltage
SCL, SDA, RUN0, RUN1, FAULT0, FAULT1
VIL
SYNC, SHARE_CLK
VHYST
Input Hysteresis
SCL, SDA
CIN
Input Capacitance
SCL, SDA, RUN0, RUN1, FAULT0, FAULT1, SYNC,
SHARE_CLK (Note 12)
tFILT
Input Digital Filter Delay
FAULT0, FAULT1
RUN0, RUN1
MIN
l
l
TYP
MAX
1.35
1.8
0.8
0.6
l
l
80
UNITS
V
V
V
V
mV
10
3
10
pF
µs
µs
Digital Outputs (SCL, SDA, RUNn, FAULTn, SYNC, SHARE_CLOCK, ALERT, PWMn, PGOODn)
VOL
Output Low Voltage
ISINK = 3mA; SDA, SCL, RUN0, RUN1, FAULT0,
FAULT1, SYNC, SHARE_CLK, ALERT,
ISINK = 2mA; PWMn, PGOODn
l
l
0.2
l
0.4
V
0.3
V
1
5
µA
µA
5
µA
VOH
PWMn Output High Voltage
ISOURCE = 2mA
ILKG
Output Leakage Current
0V ≤ PWM0, PWM1, PGOOD0, PGOOD1 ≤ VDD33
0V ≤ FAULT0, FAULT1, SYNC, SHARE_CLK ≤ 3.6V
0V ≤ RUN0, RUN1 ≤ 5.5V
0V ≤ SCL, SDA, ALERT ≤ 5.5V
tRO
PWMn Output Rise Time
CLOAD = 30pF, 10% to 90%
5
ns
tFO
PWMn Output Fall Time
CLOAD = 30pF, 90% to 10%
4
ns
2.7
V
–1
–5
l
–5
Serial Bus Timing
fSMB
Serial Bus Operating Frequency
l
10
tBUF
Bus Free Time Between Stop and Start
l
1.3
µs
tHD,STA
Hold Time After (Repeated) Start
Condition. After This Period, the First
Clock Is Generated
l
0.6
µs
tSU,STA
Repeated Start Condition Setup Time
l
0.6
µs
tSU,STO
Stop Condition Setup Time
l
0.6
µs
tHD,DAT
Data Hold Time:
Receiving Data
Transmitting Data
l
l
0
0.3
tSU,DAT
Input Data Setup Time
l
100
tTIMEOUT
Clock Low Timeout
l
25
35
ms
tLOW
Serial Clock Low Period
l
1.3
10000
µs
tHIGH
Serial Clock High Period
l
0.6
8
400
0.9
kHz
ns
µs
ns
µs
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3882-1/LTC3882-2 is specified over the –40°C to 125°C
operating junction temperature range. High Junction temperatures degrade
operating lifetimes; operating lifetime is derated for junction temperatures
greater than 125°C. Note the maximum ambient temperature consistent
with these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance and
other environmental factors.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: EEPROM endurance, retention and mass write times are
guaranteed by design, characterization and correlation with statistical
process controls. Minimum retention applies only for devices cycled less
than the minimum endurance specification. EEPROM read commands
(e.g. RESTORE_USER_ALL) are valid over the entire specified operating
junction temperature range.
Note 5: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 6: Minimum EEPROM endurance, retention and mass write time
specifications apply when writing data with 3.15V ≤ VDD33 ≤ 3.45V.
EEPROM read commands are valid over the entire specified VDD33
operating range.
Note 7: Specified VOUT error with AVP = 0% requires servo mode to be
set with MFR_PWM_MODE_LTC3882-1 command bit 6. Performance is
guaranteed by testing the LTC3882-1 in a feedback loop that servos VOUT
to a specified value.
Note 8: ADC tested with PWMs disabled. Comparable capability
demonstrated by in-circuit evaluations. Total Unadjusted Error includes all
gain and linearity errors, as well as offsets.
Note 9: Internal 32-bit calculations using 16-bit ADC results are limited to
10-bit resolution by PMBus Linear 11-bit data format.
Note 10: Limits guaranteed by TSNS voltage and current measurements
during test, including ADC readback.
Note 11: Data conversion is done in round robin fashion. All inputs signals
are continuously scanned in sequence resulting in a typical conversion
latency of 90ms.
Note 12: Guaranteed by design.
Note 13: Do not apply a voltage or current source directly to these pins.
They should only be connected to passive RC loads, otherwise permanent
damage may occur.
Note 14: Do not apply a voltage source to this pin unless shorted to VCC.
See Electrical Characteristics for applicable limits beyond which permanent
damage may occur.
Rev. C
For more information www.analog.com
9
LTC3882-1/LTC3882-2
TYPICAL PERFORMANCE CHARACTERISTICS
LTC3882-1 1.0V Regulated Output
vs Temperature
Typical LTC3882-1 Output Voltage
Distribution at 0°C
1000
1.0
0.9995
1200
1094 UNITS
900 VOUT_COMMAND = 1.0V
DIGITAL SERVO
800 ENGAGED
700
NUMBER OF CHANNELS
VOUT (V)
VIN = 12V
VOUT_COMMAND = 1.0V
DIGITAL SERVO ENGAGED
1.0005 I
OUT = 6.5A
600
500
400
300
0.999
1078 UNITS
VOUT_COMMAND = 1.0V
DIGITAL SERVO
ENGAGED
1000
NUMBER OF CHANNELS
1.001
Typical LTC3882-1 Output Voltage
Distribution at 105°C
800
600
400
200
200
100
0.9985
–5
15
35
55
TA (°C)
75
38821 G01
38821 G01a
Efficiency and Loss vs Load
(2-Phase Using FDMF5820DC
DRMOS)
Efficiency vs Load Current
(1-Phase Using D12S1R880A
Power Block)
92
13
95
7
86
85
84
5
83
85
3.3V
2.5V
1.8V
1.5V
1.2V
1.0V
80
VIN = 12V
VOUT = 1V
SYNC = 500kHz
82
81
10
0
20
30 40 50 60
LOAD CURRENT (A)
70
3
80
1
75
0
10
NUMBER OF ICs
NUMBER OF ICs
NUMBER OF ICs
3500
1500
–400 –300–200–100 0 100 200 300 400
CH1 ISENSE OFFSET TO IDEAL (µV)
38821 G06
0
30
50
20
40
LOAD CURRENT (A)
60
70
11783 UNITS
FROM 3 LOTS
TJ = 121°C
CHO MASTER
3000
2500
2000
1500
1000
500
500
10
Typical Distribution of Slave
IOUT Offset (Not Including DCR
Mismatch)
4000
2000
0
38821 G05
4500
1000
1000
10
80
8593 UNITS
FROM 3 LOTS
3000 T = 38°C
J
CHO MASTER
2500
1500
0
82
3500
2000
86
Typical Distribution of Slave
IOUT Offset (Not Including DCR
Mismatch)
9595 UNITS
3500 FROM 3 LOTS
TA = –40°C
3000 TJ = –22°C
CHO MASTER
2500
88
38821 G04
4000
38821 G02
84
40
20
30
LOAD CURRENT (A)
38821 G03
Typical Distribution of Slave
IOUT Offset (Not Including DCR
Mismatch)
2.5
90
EFFICIENCY (%)
87
POWERLOSS (W)
9
EFFICIENCY (%)
90
88
2
VIN = 12V
VOUT = 1.5V
92
89
EFFICIENCY (%)
94
11
90
1.5
Efficiency vs Load Current
(3-Phase Using D12S1R845A
Power Block)
VIN = 12V
91
80
0
–2.5 –2 –1.5 –1 –0.5 0 0.5 1
VOUT ERROR (mV)
0
–1.25 –1 –0.75–0.5–0.25 0 0.25 0.5 0.75 1 1.25
VOUT ERROR (mV)
95
500
–400 –300–200–100 0 100 200 300 400
CH1 ISENSE OFFSET TO IDEAL (µV)
38821 G07
0
–300 –200–100 0 100 200 300 400 500
CH1 ISENSE OFFSET TO IDEAL (µV)
38821 G08
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
TYPICAL PERFORMANCE CHARACTERISTICS
3-Phase DC Output Current
Sharing (Using D12S1R845A
Power Block
20
Load Step Transient Current
Sharing (Using FDMF6707B
DrMOS)
CHANNEL 1
CHANNEL 2
CHANNEL 3
18
16
IOUT
20A/DIV
IOUT
20A/DIV
14
PHASE CURRENT (A)
Load Dump Transient Current
Sharing (Using FDMF6707B
DrMOS)
VOUT
20mV/DIV
VOUT
20mV/DIV
12
IL1, IL2
10A/DIV
10
8
IL1, IL2
10A/DIV
6
4
VOUT = 1V
VIN = 12V
SYNC = 500kHz
L = 320nH
2
0
0
10
20 30 40 50 60
TOTAL RAIL CURRENT (A)
80
70
38821 G10
5µs/DIV
VOUT = 1V
VIN = 12V
SYNC = 500kHz
L = 320nH
38821 G11
5µs/DIV
38821 G09
Efficiency and Power Loss vs
Input Voltage
(1-Phase Using LTC4449)
100
3.0
VO = 1.8V
98
EFFICIENCY (%)
2.0
92
90
1.5
88
1.0
86
84
10
15
20
VIN (V)
IOUT
(10A/DIV)
VSW
(10V/DIV)
VOUT
(10mV/DIV)
25mVP-P
0.5
POWER FET: BSC050N04LS G
SYNC FET: BSC010N04LS
5
POWERLOSS (W)
94
80
VOUT
(20mV/DIV)
2.5
96
82
1-Phase Single Cycle Response
(Using D12S1R860A Power Block
with COUT = 6 × 100µF X5R 1210)
3-Phase Transient Response
(Using D12S1R860A Power Block)
25
30
100µs/DIV
0
38821 G12
3+1 Channel Crosstalk
(Using D12S1R845A Power
Blocks)
VOUT0
(1-PHASE)
20mV/DIV
38821 G13
VOUT = 1V/25A
VIN = 12V
SYNC = 1MHz
L = 210nH
Load Step Transient Response
Using AVP
Line Step Transient Response
(1-phase Using LTC4449)
VIN
2V/DIV
VOUT1
(3-PHASE)
20mV/DIV
25%
LOAD STEP
100µs/DIV
38821 G15
38821 G14
2µs/DIV
VOUT = 0.9V/90A
VIN = 12V
SYNC = 500kHz
L = 210nH
IO
10A/DIV
IOUT1
10A/DIV
IOUT
(10A/DIV)
7V
1.8V
VOUT
50mV/DIV
VOUT
10mV/DIV
200µs/DIV
38821 G16
200µs/DIV
38821 G17
Rev. C
For more information www.analog.com
11
LTC3882-1/LTC3882-2
TYPICAL PERFORMANCE CHARACTERISTICS
Soft-Start Ramp
Start-Up Into a Prebiased Load
VOUT
0.5V/DIV
VOUT
0.5V/DIV
0V
IL1, IL2
10A/DIV
IL1, IL2
10A/DIV
VIN = 12V
1ms/DIV
38821 G18
VOUT
1V/DIV
38821 G19
1ms/DIV
VOUT_COMMAND INL
VOUT_COMMAND DNL
1.0
0.8
1.0
0.6
0.4
1.7985
0.5
DNL (LSB)
INL (LSB)
VOUT (V)
1.7990
0
1.7980
0.2
0
–0.2
–0.4
–0.5
1.7975
–0.6
1.7970
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
–1.0
0.3
100 120
1.1
1.9
38821 G01a
Output Overvoltage Threshold
Error vs Temperature
0
–0.05
–0.10
VOUT_OV_FAULT_LIMIT = 2V
VOUT RANGE = 1
–0.15
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100 120
1.1
500.2
1.0
500.1
0.8
0.6
0.4
0.2
0
4.3
5.1 5.5
38821 G02
500.0
499.9
499.8
499.7
–0.2
499.6
–0.4
–40 –20
499.5
–40 –20
20 40 60 80
TEMPERATURE (°C)
2.7
3.5
VOUT (V)
PWM Frequency vs Temperature
1.2
0
1.9
38821 G01
100 120
38821 G21
12
–0.8
0.3
5.1 5.5
4.3
PWM FREQUENCY (kHz)
OUTPUT OC THRESHOLD ERROR (%)
0.05
2.7
3.5
VOUT (V)
Output Overcurrent Threshold
Error vs Temperature
0.10
VOUT OV THRESHOLD ERROR (%)
38821 G20
5ms/DIV
TOFF_DELAY = 10ms
TOFF_FALL = 5ms
1.5
VOUT_COMMAND = 1.8V
DIGITAL SERVO OFF
1.7995
RUN
2V/DIV
VIN = 12V
Regulated Output vs Temperature
1.8000
Soft-Off Ramp
38821 G22
FREQUENCY_SWITCH = 500kHz
0
20 40 60 80
TEMPERATURE (°C)
100 120
38821 G23
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
TYPICAL PERFORMANCE CHARACTERISTICS
VIN(SNS) ADC TUE
–1
IOUT ADC TUE
8
0.30
MEASUREMENT ERROR (mV)
MEASUREMENT ERROR (mV)
VOUT ADC TUE
0.40
–2
–3
–4
–5
–6
–7
6
MEASUREMENT ERROR (mA)
0
0.20
0.10
0
–0.10
–0.20
–8
–0.30
–9
–0.40
0.5
0
5
10
15 20 25
VINSNS (V)
30
35
40
2
0
–2
–4
–6
38821 G24
1
1.5
2
2.5 3 3.5
VOUT (V)
4
4.5
5
–8
5.5
1.0
10
5
15
OUTPUT CURRENT (A)
0
38821 G25
SHARE_CLK Frequency vs
Temperature
Temperature ADC TUE
20
38821 G26
IC Operating Current vs
Temperature
31.0
110
0.8
VCC = 14V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
ICC OPERATING CURRENT (mA)
30.8
SHARE_CLK FREQUENCY (kHz)
MEASUREMENT ERROR (°C)
4
105
100
95
30.6
30.4
30.2
30.0
29.8
29.6
–0.8
–1.0
–45 –25 –5 15 35 55 75 95 115
ACTUAL TEMPERATURE (°C)
38821 G27
90
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
110
38821 G28
29.4
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100 120
38821 G29
Rev. C
For more information www.analog.com
13
LTC3882-1/LTC3882-2
PIN FUNCTIONS
COMP0/COMP1 (Pin 1/Pin 28): Error Amplifier Outputs.
PWM duty cycle increases with this control voltage. These
are true low impedance outputs and cannot be directly
connected together when active. For PolyPhase operation,
wiring FB to VDD33 will three-state the error amplifier output
of that channel, making it a slave. PolyPhase control is
then implemented in part by connecting all slave COMP
pins together to one master error amplifier output.
TSNS0/TSNS1 (Pin 2/Pin 3): External Temperature Sense
Inputs. The LTC3882-1 supports two methods of calculation of external temperature based on forward-biased P/N
junctions between these pins and GND.
VINSNS (Pin 4): VIN Supply Sense. Connect to the VIN
power supply to provide line feedforward compensation.
A change in VIN immediately modulates the input to the
PWM comparator and inversely changes the pulse width
to provide excellent transient line regulation and fixed
modulator voltage gain. An external lowpass filter can be
added to this pin to prevent noisy signals from affecting
the loop gain.
IAVG_GND (Pin 5): IAVG Ground Reference. The same
IAVG_GND should be shared between all channels of a
PolyPhase rail and connected to system ground at a single
point. IAVG_GND may be wired directly to GND on ICs that
do not share phases with other chips.
PGOOD/PGOOD1 (Pin 6/Pin 27): Power Good Indicator
Open-Drain Outputs. These outputs are driven low through
a 30µs filter when the respective channel output is below
its programmed UV fault limit or above its programmed
OV fault limit. If used, a pull-up resistor is required in the
application. Operating voltage range is GND to VDD33.
PWM0/PWM1 (Pin 7/Pin 26): PWM Three-State Control
Outputs. These pins provide single-wire PWM switching
control for each channel to an external gate driver, DrMOS
or power block. Operating voltage range is GND to VDD33.
SYNC (Pin 8): External Clock Synchronization Input and
Open-Drain Output. If desired, an external clock can be
applied to this pin to synchronize the internal PWM channels. If the LTC3882-1 is configured as a clock master, this
pin will also pull to ground at the selected PWM switching
14
frequency with a 125ns pulse width. A pull-up resistor to
3.3V is required in the application if SYNC is driven by
any LTC3882-1. Minimize the capacitance on this line to
ensure its time constant is fast enough for the application.
SCL (Pin 9): Serial Bus Clock Input. A pull-up resistor to
3.3V is required in the application.
SDA (Pin 10): Serial Bus Data Input and Output. A pull-up
resistor to 3.3V is required in the application.
ALERT (Pin 11): Open-Drain Status Output. This pin may
be connected to the system SMBALERT wire-AND interrupt signal and should be left open if not used. If used, a
pull-up resistor is required in the application. Operating
voltage range is GND to VDD33.
FAULT0/FAULT1 (Pin 12/Pin 13): Programmable Digital
Inputs and Open-Drain Outputs for Fault Sharing. Used
for channel-to-channel fault communication and propagation. These pins should be left open if not used. If used,
a pull-up resistor to 3.3V is required in the application.
RUN0/RUN1 (Pin 14/Pin 15): Run Control Inputs and
Open-Drain Outputs. A voltage above 2V is required on
these pins to enable the respective PWM channel. The
LTC3882-1 will drive these pins low under certain reset/
restart conditions regardless of any PMBus command
settings. A pull-up resistor to 3.3V is required in the application.
ASEL0/ASEL1 (Pin 16/Pin 17): Serial Bus Address Select
Pins. Connect optional 1% resistor dividers between VDD25
and GND to these pins to select the serial bus interface
address. Refer to the Applications Information section
for more detail.
VOUT0_CFG/VOUT1_CFG (Pin 18/Pin 19): Output Voltage
Configuration Pins. Connect optional 1% resistor dividers between VDD25 and GND to these pins to select the
output voltage for each channel. Refer to the Applications
Information section for more detail.
FREQ_CFG (Pin 20): Frequency Configuration Pin. Connect
an optional 1% resistor divider between VDD25 and GND
to this pin to configure PWM switching frequency. Refer
to the Applications Information section for more detail.
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
PIN FUNCTIONS
PHAS_CFG (Pin 21): Phase Configuration Pin. Connect
an optional 1% resistor divider between VDD25 and GND
to this pin to configure the phase of each PWM channel
relative to SYNC. Refer to the Applications Information
section for more detail.
VDD25 (Pin 22): Internal 2.5V Regulator Output. Bypass
this pin to GND with a low ESR 1µF capacitor. Do not load
this pin with external current beyond that required for local
LTC3882-1 configuration pins, if any.
SHARE_CLK (Pin 23): Share Clock Open-Drain Output
(bussed). Share Clock, nominally 100kHz, is used to
sequence multiple rails in a power system utilizing more
than one LTC PSM controller. A pull-up resistor is required
in the application. Minimize the capacitance on this line to
ensure the time constant is fast enough for the application.
Operating voltage range is GND to VDD33.
VDD33 (Pin 24): Internal 3.3V Regulator Output. Bypass this
pin to GND with a low ESR 2.2µF capacitor. The LTC3882-1
may also be powered from an external 3.3V rail attached
to this pin, if also shorted to VCC. Do not overload this pin
with external system current. Local pull-up resistors for
the LTC3882-1 itself may be powered from VDD33. Refer
to the Applications Information section for more detail.
VCC (Pin 25): 3.3V Regulator Input. Bypass this pin to
GND with a capacitor (0.1µF to 1µF ceramic) in close
proximity to the IC.
VSENSE0–/VSENSE1– (Pin 35/Pin 34): Negative Output
Voltage Sense Inputs. These pins must still be properly
connected on slave channels for accurate output current
telemetry.
VSENSE0+/VSENSE1+ (Pin 36/Pin 33): Positive Output Voltage
Sense Inputs. These pins must still be properly connected
on slave channels for accurate output current telemetry.
ISENSE0–/ISENSE1– (Pin 37/Pin 32): Current Sense Amplifier Inputs. The (–) inputs to the amplifiers are normally
connected to the low side of a DCR sensing network or
output current sense resistor for each phase.
ISENSE0+/ISENSE1+ (Pin 38/Pin 31): Current Sense Amplifier Inputs. The (+) inputs are normally connected to the
high side of an output current sense resistor or the R-C
midpoint of a parallel DCR sense circuit.
IAVG0/IAVG1 (Pin 39/Pin 30): Average Current Control Pins.
A capacitor connected between these pins and IAVG_GND
stores a voltage proportional to the average output current
of the master channel. PolyPhase control is then implemented in part by connecting all slave IAVG pins together
to the master IAVG output. This pin should be left open
on channels that control single-phase outputs. Operating
voltage range is GND to 2.1V.
FB0/FB1 (Pin 40/Pin 29): Error Amplifier Inverting Inputs.
These pins provide an internally scaled version of the
output voltage for use in loop compensation. Refer to the
Applications Information section for additional details on
compensating the output voltage control loop with external
components.
GND (Exposed Pad Pin 41): Ground. All small-signal and
compensation components should connect to this pad.
The exposed pad must be soldered to a suitable PCB copper
ground plane for proper electrical operation and to obtain
the specified package thermal resistance.
Rev. C
For more information www.analog.com
15
LTC3882-1/LTC3882-2
BLOCK DIAGRAM
ROM
RAM
EEPROM
VINSNS
R_CONFIG
IAVG0
MCU AND
CUSTOM
LOGIC
SHARE_CLK
PMBus
±
ISENSE0
2.5V
REGULATOR
12-BIT
DAC
PWM0
VSENSE0±
PGOOD0
SYNC
PWM0
PLL
VOLTAGE
REFERENCE
VREF
IAVG_GND
3.3V
REGULATOR
VCC
PWM1
VDD33
PGOOD1
BIAS AND
HOUSEKEEPING
VSENSE1
IAVG1
INTERNAL DATA BUS
VSENSE0±
16-BIT
ADC
ISENSE0±
VSENSE1±
PWM1
ISENSE1±
VINSNS
PWM0
TSNS0
PWM1
12-BIT
DAC
±
VINSNS
ANALOG
MUX
INTERNAL
TEMPERATURE
ISENSE1±
TSNS1
16
3882-1 BD
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
TEST CIRCUIT
(Channel 0 Example)
LTC3882-1/
LTC3882-2
1.024V
VR
12-BIT
D/A
DIGITAL
+
EA
–
VSENSE0–
VSENSE0+
35
FB0
36
COMP0
40
1
+
LTC1055
TARGET = VOUT_COMMAND
–
1V
38821 TC
TIMING DIAGRAM
SDA
tf
tLOW
tr
tSU(DAT)
tHD(SDA)
tf
tSP
tr
tBUF
SCL
tHD(STA)
START
CONDITION
tHD(DAT)
tHIGH
tSU(STA)
tSU(STO)
38821 TD
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Rev. C
For more information www.analog.com
17
LTC3882-1/LTC3882-2
OPERATION
Overview
The LTC3882-1/LTC3882-2 is a dual channel/dual phase,
constant frequency analog voltage mode controller for
DC/DC step-down applications. The LTC3882-1 operates
to 1.25MHz and the LTC3882-2 operates to 2.5MHz. In this
document, statements related to the LTC3882-1 apply to the
LTC3882-2 unless specifically noted. It features a PMBus
compliant digital interface for monitoring and control of
important power system parameters. The chip operates
from an IC power supply between 3V and 13.2V and is
intended for conversion from VIN between 3V and 38V to
output voltages between 0.5V and 5.25V. It is designed
to be used in a switching architecture with external FET
drivers, including higher level integrations such as nonisolated power blocks.
Major features include:
• Digitally Programmable Output Voltage
• Digitally Programmable Output Current Limit
• Digitally Programmable Input Voltage Supervisor
• Digitally Programmable Output Voltage Supervisors
• Digitally Programmable Switching Frequency
• Digitally Programmable On and Off Delay Times
• Digitally Programmable Soft-Start/Stop
• Average Input Voltage
• Average Output Voltages
• Average Output Currents
• Average PWM Duty Cycles
• Internal LTC3882-1 Temperature
• External Sensed Temperatures
• Warning and Fault Status, Including Input and Output
Undervoltage and Overvoltage
The LTC3882-1 supports four serial bus addressing
schemes to access the individual PWM channels separately
or jointly.
Fault communication, reporting and system response
behavior are fully configurable. Two fault I/Os are provided (FAULT0, FAULT1) that can be controlled independently. A separate ALERT pin also provides for a maskable
SMBALERT#. Fault responses for each channel may be
individually programmed, depending on the fault type.
PMBus status commands allow fault reporting over the
serial bus to identify a specific fault event.
Main Control Loop
• Operating Condition Telemetry
• Phase Locked Loop for Synchronous PolyPhase Operation (2, 3, 4, 6, or 8 phases)
• Fully Differential Load Sense
• Non-Volatile Configuration Memory with ECC
• Optional External Configuration Resistors for Key Operating Parameters
• Optional Time-Base Interconnect for Synchronization
Between Multiple Controllers
• Fault Event Data Logging
• Capable of Standalone Operation with Default Factory
Configuration
• PMBus Revision 1.2 Compliant Interface up to 400kHz
18
The PMBus interface provides access to important power
management data during system operation including:
The LTC3882-1 utilizes constant frequency voltage mode
control with leading-edge modulation. This provides
improved response to a load step increase, especially at
larger VIN/VOUT ratios found in the low voltage, high current solutions demanded by modern digital subsystems.
The LTC3882-1 leading-edge modulation architecture
does not have a minimum on-time requirement. Minimum
duty cycle will be determined by performance limits of
the external power stage. The IC is also capable of active
voltage positioning (AVP) to afford the smallest output
capacitors possible for a given output voltage accuracy
over the anticipated full load range. The LTC3882-1 error
amplifiers have high bandwidth, low offset and low output impedance, allowing the control loop compensation
network to be optimized for very high crossover frequencies and excellent transient response. The controller also
achieves outstanding line transient response by using
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
OPERATION
input feedforward compensation to instantaneously
adjust PWM duty cycle and significantly reduce output
under/overshoot during supply voltage changes. This
also has the added advantage of making the DC loop gain
independent of input voltage.
The main PWM control loop used for each channel is
illustrated in Figure 1. During normal operation the top
MOSFET (power switch) driving choke L1 is commanded
off when the clock for that channel resets the RS latch.
The power switch is commanded back on when the main
PWM comparator VC, sets the RS latch. The error amplifier EA output (COMP) controls the PWM duty cycle to
match the FB voltage to the EA positive terminal voltage
in steady state. A patented circuit adjusts this output for
VINSNS line feedforward.
The positive terminal of the EA is connected to the output
of a 12-bit DAC with values ranging from 0V to 1.024V. The
DAC value is determined by the resistor configuration pins
detailed in application Table 8, by values retrieved from internal EEPROM, or by a combination of PMBus commands to
synthesize the desired output voltage. Refer to the following
PMBus Command Details section of this document for more
information. The LTC3882-1 supports two output ranges.
EA can regulate the output voltage to 5.5x the DAC output
(Range 0) or 2.75x the DAC output (Range 1).
VC discriminates its positive input against an internally
generated PWM voltage ramp. The positive input is a composite control based on COMP voltage with line feedforward
compensation, and current sharing if the channel controls
a slave phase. When the ramp falls below this voltage the
comparator trips and sets the PWM latch.
+
If load current increases, VSENSE and FB will droop
slightly with respect to the 12-bit DAC output. This causes
the COMP voltage to increase until the average inductor
current matches the new load current and the desired
output voltage is restored. Programmable comparators
ILIM and IREV monitor peak instantaneous forward and
reverse inductor current for pulse-by-pulse protection.
The top power MOSFET is immediately commanded off if
the programmed positive limit is reached, and the bottom
MOSFET is immediately commanded off if the negative
limit is reached. Repeated peak overcurrent events cause
an overcurrent fault to be set.
When the top MOSFET is commanded off, the bottom
MOSFET is normally commanded on. In continuous conduction mode (CCM) the bottom MOSFET stays on until
comparator VC turns the top MOSFET back on. Otherwise
in discontinuous conduction mode (DCM, also known as
diode emulation) the bottom MOSFET is commanded off
if the IREV comparator detects that the inductor current
has decayed to approximately 0A. In any case the next
PWM cycle starts when the clock for that channel again
clears the RS latch.
Power-Up and Initialization
The LTC3882-1 is designed to provide stand-alone supply
sequencing with controlled turn-on and turn-off functions.
It operates from a single IC input supply of 3V to 13.2V
while two on-chip linear regulators generate internal
2.5V and 3.3V. If VCC is below 4.5V, the VCC and VDD33
pins must be shorted together and limited to a maximum
operating voltage of 3.6V. Controller configuration is
reset by the internal UVLO threshold, where VDD33 must
be at or above 3V and the internal 2.5V supply must be
within about 20% of its regulated value. At that point the
internal microcontroller begins initialization. A PMBus
RESTORE_USER_ALL or MFR_RESET command forces
this same initialization.
The LTC3882-1 features an internal RAM built-in self-test
(BIST) that runs during initialization. Should RAM BIST
fail, the following steps are taken.
• Device responds only at device address 0x7C and global
addresses 0x5A and 0x5B
• A persistent Memory Fault Detected is indicated by
STATUS_CML
• Internal EEPROM is not accessed
• RUNn and SHARE_CLK are driven low continuously
Normal operation can be restored if the RAM BIST subsequently passes, for instance as the result of another
MFR_RESET command issued to address 0x7C.
Rev. C
For more information www.analog.com
19
LTC3882-1/LTC3882-2
OPERATION
LTC3882-1/
LTC3882-2
MODE
OSCILLATOR
CLOCK
R
Q
PWM0
PWM
LOGIC
S
VIN
7
GATE
DRIVER
0V
VOC0
8-BIT DAC
IOUT_OC_FAULT_LIMIT
ILIM
RAMP
VC
VREV
IREV
4
VINSNS
FEED
FORWARD
+
+
CA
–
+
S
–
SLAVE
ENABLE
ISENSE0+
ISENSE0–
IAVG0
IAVG_GND
SLAVE
DETECT
RS
38
L1
CS
VOUT
37
39
COUT
5
MASTER
ENABLE
VOV0
9-BIT DAC
VOUT_OV_FAULT_LIMIT
9-BIT DAC
VOUT_UV_FAULT_LIMIT
OV
UV
VUV0
VSENSE0+
36
9R
(RANGE 0)
–
EA
VSP0
FB0
12-BIT DAC
VOUT_COMMAND
2R
VSENSE0–
+
COMP0
LOOP
COMPENSATION
NETWORK
40
35
1
38821 F01
Figure 1. PWM Control Loop Diagram
20
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
OPERATION
During initialization all PWM outputs are disabled. The
RUNn pins and SHARE_CLK are held low and FAULTn
pins are high impedance. External configuration resistors
are identified and the contents of the onboard EEPROM
are read into the controller command memory space. The
LTC3882-1 can determine key operating parameters from
external configuration resistors according to application
Table 8 through Table 11. See the following Resistor
Configuration Pins section for more detail. The resistor
configuration pins only determine some of the preset
values of the controller. The remaining values, retrieved
from internal EEPROM, are programmed at the factory or
with PMBus commands.
If the configuration resistor pins are all open, the LTC3882-1
will use only EEPROM contents to determine all operating
parameters. If Ignore Resistor Configuration Pins is set (bit
6 of MFR_CONFIG_ALL_LTC3882-1), the LTC3882-1 will
use only its EEPROM contents to determine all operating
parameters except device address. Unless both ASEL pins
are completely open, the LTC3882-1 will always determine
some portion of its device address from the resistors on
these pins. See Serial Bus Addressing later in this section.
The internal microcontroller typically requires 35ms to
complete initialization from VDD33 ≥ 3V. At that point, an
internal comparator monitors VINSNS, which must exceed
the VIN_ON threshold before output power sequencing
can begin (SHARE_CLK released, ready for TON_DELAY).
Accurate readback telemetry can then require an additional
90ms for initial round-robin A/D conversions.
Soft-Start
The RUN pins are released for external control after the
part initializes and VINSNS is greater than the VIN_ON
threshold. If multiple LTC3882-1 ICs are used in an application, shared RUN pins are held low until all units
initialize and VINSNS exceeds the VIN_ON threshold for
all devices. A common SHARE_CLK signal can also ensure
all connected devices use the same time reference for
initial start-up even if RUN pins cannot be shared due to
other design requirements. SHARE_CLK is not released
by each IC until the conditions for power sequencing have
been fully satisfied.
After a channel RUN pin rises above 2V and any specified
turn on delay (TON_DELAY) has expired, the LTC3882-1
performs an initial monotonic soft-start ramp on that channel. This is carried out with a digitally controlled ramp of
the regulated output voltage from 0V to the commanded
voltage set point over the programmed TON_RISE period,
allowing inrush current control. During the soft-start ramp,
the LTC3882-1 does not initiate PWM operation until the
commanded output exceeds the actual rail voltage. This
allows the regulator to start up into a pre-biased load
even when using gate drivers or power blocks that do not
support discontinuous operation. The soft-start feature
is disabled by setting the value of TON_RISE to any time
less than 0.25ms.
Time-Based Output Sequencing
The LTC3882-1 supports time-based on and off output
sequencing using a shared time reference (SHARE_CLK).
Following a valid qualified command to turn on, each output
is enabled after waiting its programmed TON_DELAY. This
can be used to sequence outputs in a prescribed order
that can be preprogrammed as needed without hardware
modification. Channel off-sequencing is accomplished in
a similar way with the TOFF_DELAY command.
Output Ramping Control
The LTC3882-1 supports synchronized output on and off
ramping control using a shared time reference (SHARE_
CLK). Power rail on and off relationships similar to those of
conventional analog tracking functions can be achieved by
using programmed delays and TON_RISE and TOFF_FALL
times. However, with LTC3882-1 digital control, on and
off ramping methods need not be the same, and ramping
configurations can be reprogrammed as needed without
hardware modification.
Programmable fault responses and fault sharing can
ensure that any desired time-based output sequencing
and ramping control is properly accomplished each time
the system powers up or down. Refer to the Applications
Information section for various LTC3882-1 hardware and
PMBus command configurations needed to fully support
synchronization for time-based sequencing and output
ramping when using multiple ICs.
Rev. C
For more information www.analog.com
21
LTC3882-1/LTC3882-2
OPERATION
Voltage-Based Output Sequencing
It is also possible to sequence outputs using cascaded
voltage events. To do this, the PGOOD status output from
one PWM channel can be used to control the RUN pin
of a downstream channel. This keeps the downstream
channel off unless acceptable output conditions exist on
the controlling channel.
Output Disable
Both PWM channels are disabled any time VINSNS is below
the VIN_OFF threshold. The power stages are immediately
shut off to stop the transfer of energy to the load(s) as
quickly as possible.
A PWM channel may also be disabled in response to certain
internal fault conditions, an external fault propagated into
a FAULT pin, or loss of SHARE_CLK. In these cases the
power stage is immediately shut off to stop the transfer
of energy to the load as quickly as possible. Refer to the
following Fault Detection and Handling section for additional details related to fault recovery.
Each PWM channel can be disabled with a PMBus OPERATION command at any time if enabled by ON_OFF_CONFIG.
This will force a controlled turn-off response with defined
delay (TOFF_DELAY) and ramp down rate (TOFF_FALL).
The controller will maintain the programmed mode of
operation for TOFF_FALL. In DCM, the controller will not
draw current from the load and fall time will be set by
output capacitance and load current.
Finally, each PWM channel can be commanded off by
pulling the associated RUN pin low. Pulling the RUN pin
low can force the channel to perform a controlled turn off
or immediately disable the power stage, depending on the
programming of the ON_OFF_CONFIG command.
Minimum Output Disable Times
When a PMBus OPERATION command is used to turn off
an LTC3882-1 channel, a minimum output disable time of
120ms is imposed regardless of how quickly the channel
is commanded back on. If bit 4 of MFR_CHAN_CONFIG is
clear, a PMBus command to turn the channel off also pulses
the RUN pin low. Once the RUN pin is pulled low internally
or externally, a minimum output disable time (RUN forced
22
low) of TOFF_DELAY + TOFF_FALL + 136ms is enforced.
If MFR_RESTART_DELAY is greater than this mandatory
minimum, the larger value of MFR_RESTART_DELAY is
used. In either case the LTC3882-1 holds its own RUN
pin low during the entire disable period. These minimum
off times allow a consistent channel restart with coherent monitor ADC values and make the LTC3882-1 highly
compatible with other LTC PMBus digital power system
management products.
Output Short Cycle
An output short cycle condition is created when a master channel is commanded back on while waiting for
TOFF_DELAY or TOFF_FALL to expire. Any time this
occurs, the LTC3882-1 asserts the Short Cycle bit in
STATUS_MFR_SPECIFIC. Device response at that point
is governed by bits in MFR_CHAN_CONFIG_LTC3882-1
and SMBALERT_MASK. Refer to the detailed descriptions
of those commands for additional details. Generally, the
LTC3882-1 should be controlled so that short cycle conditions are not created during normal operation.
Light Load Current Operation
The LTC3882-1 has two modes of PWM operation: discontinuous conduction mode (DCM) and forced continuous
conduction mode (CCM). Mode selection is made with
the MFR_PWM_MODE command.
In DCM, the inductor current is not allowed to reverse.
The reverse current comparator IREV disables the external
bottom MOSFET (synchronous rectifier) when the inductor current reaches approximately 0A, preventing it from
going substantially negative. The external gate driver or
power block must have short delays to a high impedance
output, relative to the PWM cycle, to support DCM.
Efficiency at light loads in CCM is lower than in DCM.
Continuous conduction mode exhibits less interference
with audio circuitry but may result in reverse inductor
current, for instance at light loads or under large transient
conditions.
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
OPERATION
Switching Frequency and Phase
There is a high degree of flexibility for setting the PWM
operating frequency of the LTC3882-1. The switching
frequency of the PWM can be established with an internal oscillator or an external time base. The internal
phase-locked loop (PLL) synchronizes PWM control to
this timing reference with proper phase relation, whether
the clock is provided internally or externally. The device
can also be configured to provide the master clock to
other ICs through PMBus command, EEPROM setting,
or external configuration resistors as outlined in application Table 10. For PMbus or EEPROM configuration, the
LTC3882-1 is designated as a clock master by clearing
bit 4 of MFR_CONFIG_ALL_LTC3882-1. As clock master,
the LTC3882-1 will drive its open-drain SYNC pin at the
selected rate with a pulse width of 125ns. An external
pull-up resistor between SYNC and VDD33 is required in
this case. Only one device connected to SYNC should be
designated to drive the pin. If more than one LTC3882-1
sharing SYNC is programmed as clock master, just one of
the devices is automatically elected to provide the clock.
The others disable their SYNC outputs and indicate this
with bit 10 of MFR_PADS_LTC3882-1.
The LTC3882-1 will automatically accept an external SYNC
input, disabling is own SYNC drive if necessary, as long
as the external clock frequency is greater than 1/2 of the
programmed internal oscillator. Whether configured to drive
SYNC or not, the LTC3882-1 can continue PWM operation
at the selected frequency (FREQUENCY_SWITCH) using
its own internal oscillator, if an external clock signal is
subsequently lost.
The MFR_PWM_CONFIG_LTC3882-1 command can be
used to configure the phase of each channel. Desired phase
can also be set from EEPROM or external configuration
resistors as outlined in Table 10. Phase designates the
relationship between the falling edge of SYNC and the
internal clock edge that resets the PWM latch. That reset
turns off the top power switch, producing a PWM falling
edge. Additional small propagation delays to the PWM
control pins will apply.
The phase relationships and frequency are independent
of each other, providing numerous application options.
Multiple LTC3882-1 ICs can be synchronized to realize a
PolyPhase array. In this case the phases should be separated by 360/n degrees, where n is the number of phases
driving the output voltage rail.
PolyPhase Load Sharing
Multiple LTC3882-1 ICs can be combined to provide a balanced load-share solution by configuring the necessary
pins. The SHARE_CLK and SYNC pins of all load-sharing
channels should be bussed together. Connecting the
SYNC pins synchronizes the PWM controllers with each
other. Bussing the SHARE_CLK pins together allows the
phases to start synchronously. Refer to the discussion in
the previous Power-Up and Initialization section. The last
device to see all start-up conditions satisfied controls the
initiation of power sequencing for all phases.
Due to the low output impedance of the LTC3882-1 error
amplifiers, PolyPhase applications should use the error
amplifier of only one phase as the master. The FB pins of
each slave channel must be wired to VDD33, and the COMP
pins of each slave phase must be connected to the master
error amplifier COMP output. This disables the slave error
amplifiers and provides a single point of voltage control
and loop stabilization for the PolyPhase output rail.
For PolyPhase load sharing the LTC3882-1 also incorporates
an auxiliary current sharing loop. Referring back to Figure 1,
the instantaneous current of each slave phase is sensed
by current amplifier CA and compared to the IAVG pin. The
IAVG and IAVG_GND pins of each phase are wired together,
and a small capacitor (50pF to 200pF) between IAVG and
IAVG_GND stores a voltage corresponding to the average
master phase output current. The difference in this average and the instantaneous phase current is integrated.
The output of integrator S of each slave phase is then
proportionally summed with the master error amplifier
COMP output to adjust the duty cycle and balance the
current contribution of that phase. Additional hardware
configuration and digital programming requirements apply
in PolyPhase systems. Refer to the Applications Information section for complete details on building PolyPhase
rails with the LTC3882-1.
Rev. C
For more information www.analog.com
23
LTC3882-1/LTC3882-2
OPERATION
Active Voltage Positioning
External and Internal Temperature Sense
Load slope is programmable in the LTC3882-1 via the
MFR_VOUT_AVP PMBus command. The inductor current measured at the ISENSE pins is converted to a voltage
which is then subtracted from the voltage reference at the
positive input of the error amplifier. The final load slope
is defined by the inductor current sense element and the
bits set in the MFR_VOUT_AVP PMBus command. Setting
MFR_VOUT_AVP to a value greater than 0.0% automatically
disables output servo mode for that channel.
External temperature can best be measured using a remote,
diode-connected PNP transistor such as the MMBT3906.
The emitter should be connected to a TSNS pin while the
base and collector terminals of the PNP transistor must be
shorted together and returned directly to the LTC3882-1
GND pin. Two different currents are applied to the diode
(nominally 2μA and 32μA) and the temperature is calculated from a ΔVBE measurement made with the internal
16-bit monitor ADC.
Input Supply Monitoring
The input supply voltage is sensed by the LTC3882-1 at the
VINSNS pin. Undervoltage, overvoltage, valid on and off
levels can be programmed for VIN. Refer to the following
PMBus Command Details section for more information on
programming the input supply thresholds. In addition, the
telemetry ADC monitors the VINSNS voltage relative to
GND. Conversion results are returned by the READ_VIN
PMBus command.
Output Voltage Sensing and Monitoring
The LTC3882-1 also supports direct VBE based external
temperature measurements. In this case the diode or diode network is trimmed to a specific voltage at a specific
current and temperature. In general this method does not
yield as accurate a result as the ΔVBE measurement. Refer
to MFR_PWM_MODE_LTC3882-1 in the PMBus Command
Details section for additional information on programming
the LTC3882-1 for these two external temperature sense
configurations.
The calculated temperature is returned by the PMBus
READ_TEMPERATURE_1 command. Refer to the Applications Information section for details on proper layout
of external temperature sense elements and PMBus
commands that can be used to improve the accuracy of
calculated temperatures.
Both PWM channels allow remote, differential sensing of the
load voltage with VSENSE pins. The channel 1 output sense
pin VSENSE1– is internally shorted to GND (the exposed
pad). The telemetry ADC is fully differential and makes its
measurements of the output voltages of channels 0 and 1
at VSENSE0± and VSENSE1±, respectively. Conversion results
are returned by the READ_VOUT PMBus command.
The READ_TEMPERATURE_2 command returns the
internal junction temperature of the LTC3882-1 using an
on-chip diode with a ΔVBE measurement and calculation.
Output Current Sensing and Monitoring
Resistor Configuration Pins
Both channels allow differential sensing of the inductor
current using either the inductor DCR or a resistor in series
with the inductor across the ISENSE pins. When the ISENSE
pins for a channel are multiplexed to the differential inputs
of the LTC3882-1 monitor ADC, they have an input range
of approximately ±128mV and a noise floor of 7μVRMS.
Peak-peak noise is approximately 46.5μV. The internal ADC
anti-aliasing filter and conversion rate produce an average
reading of the ISENSE differential voltage. The resulting value
is returned by the READ_IOUT PMBus command. Refer to
the Applications Information section for details on sensing
output current using inductor DCR or discrete resistors.
Six input pins can be used to configure key operating parameters with selected 1% resistors arranged between VDD25
and GND as a divider to the pin(s). The pins are ASEL0,
ASEL1, VOUT0_CFG, VOUT1_CFG, FREQ_CFG, and PHAS_CFG.
If any of these pins are left open the value stored in the
corresponding EEPROM command is used. The resistor
configuration pins are only measured during power-up
and execution of RESTORE_USER_ALL or MFR_RESET
commands. If bit 6 of the MFR_CONFIG_ALL_LTC3882-1
24
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
OPERATION
command is set in EEPROM, all resistor inputs except
ASELn are ignored. Per the PMBus specification, all pinprogrammed parameters can be overridden at any time
by commands from the digital interface.
The ASELn pin settings are described in application
Table 11. These pins can be used to select the entire
LTC3882-1 device address. ASEL0 always programs the
bottom four bits of the device address for the LTC3882-1
unless left open. ASEL1 can be used to program the three
most-significant bits. Either portion of the address can also
be retrieved from the MFR_ADDRESS value in EEPROM.
If both pins are left open, the full 7-bit MFR_ADDRESS
value stored in EEPROM is used to determine the device
address. The LTC3882-1 always responds to 7-bit global
addresses 0x5A and 0x5B. MFR_ADDRESS should not be
set to either of these values.
The VOUTn_CFG pin settings are described in application
Table 8. These pins select the output voltages for the
related channel.
The following parameters are also set as a percentage of
the programmed VOUT if resistor configuration pins are
used to determined output voltage:
• VOUT_OV_FAULT_LIMIT: +10%
Internal EEPROM with CRC and ECC
The LTC3882-1 contains internal EEPROM with Error
Correcting Coding (ECC) to store user configuration settings and fault log information. EEPROM endurance and
retention for user space and fault log pages are specified
in the Absolute Maximum Ratings and Electrical Characteristics table.
The integrity of the entire onboard EEPROM is checked with
a CRC calculation each time its data is to be read, such as
after a power-on reset or execution of a RESTORE_USER_
ALL command. If a CRC error occurs, the CML bit is set
in the STATUS_BYTE and STATUS_WORD commands, the
EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC
command is set, and the ALERT and RUN pins pulled
low (PWM channels off). At that point the device will only
respond at special address 0x7C, which is activated only
after an invalid CRC has been detected. The chip will also
respond at the global addresses 0x5A and 0x5B, but use
of these addresses when attempting to recover from a
CRC issue is not recommended. All power supply rails
associated with either PWM channel of a device reporting
an invalid CRC should remain disabled until the issue is
resolved.
LTC recommends that the EEPROM not be written when
die temperature is greater than 85°C. If internal die temperature exceeds 130°C, all EEPROM operations except
RESTORE_USER_ALL and MFR_RESET are disabled. Full
EEPROM operation is not re-enabled until die temperature
falls below 125°C. Refer to the Applications Information
section for equations to predict retention degradation due
to elevated operating temperatures.
• VOUT_OV_WARN_LIMIT: +7.5%
• VOUT_MAX: +7.5%
• VOUT_MARGIN_HIGH: +5%
• VOUT_MARGIN_LOW: –5%
• VOUT_UV_WARN_LIMIT: –6.5%
• VOUT_UV_FAULT_LIMIT: –7%
The FREQ_CFG pin settings are described in application
Table 9. This pin selects the switching frequency of the
internal oscillator and enables the SYNC output if not left
open, shorted to GND or ignored by EEPROM setting.
See the Applications Information section or contact the
factory for details on efficient in-system EEPROM programming, including bulk EEPROM programming, which the
LTC3882-1 also supports.
The PHAS_CFG pin settings are described in Table 10.
This pin selects the phase relationships between the two
channels and the selected clock source.
Rev. C
For more information www.analog.com
25
LTC3882-1/LTC3882-2
OPERATION
Fault Detection
A variety of fault and warning detection, reporting and
handling mechanisms are provided by the LTC3882-1.
Fault or warning detection capabilities include:
• Input Under/Overvoltage
• Output Under/Overvoltage
• Output Overcurrent (Peak and Average)
• Internal and External Overtemperature and External
Undertemperature
• CML Fault (Communication, Memory, or Logic)
• External Fault Detection via Bidirectional FAULT Pins
Reporting is covered in following sections on status commands (registers) and ALERT pin function. Fault handling
mechanisms include hardwired, low-level PWM safety
responses that always occur, and higher-level programmable event management. Both types are covered in the
following sections.
Input Supply Faults
Input undervoltage and overvoltage limits are determined
from multiplexed monitor ADC conversions. Therefore the
input UV/OV response is naturally deglitched by the 90ms
typical conversion cycle of the ADC. There is no hardwired
low-level PWM response for any input supply fault.
Hardwired PWM Response to VOUT Faults
VOUT undervoltage (UV) and overvoltage (OV) faults are
detected by supervisor comparators. The OV and UV fault
limits can be set in three ways:
The output overvoltage comparator guards against transient
overshoots as well as long term overvoltages at the output.
When an output OV fault is detected the top MOSFET for
that channel is commanded off and the bottom MOSFET is
commanded on until the overvoltage condition is cleared
or for PWM control protocol 0, reverse overcurrent is
detected. See IOUT faults below.
UV faults and warnings are masked if the channel has
been commanded off or until all of the following criteria
are achieved.
• TON_DELAY Has Expired
• TON_RISE Ramp Has Completed
• TON_MAX_FAULT_LIMIT Has Been Reached
• IOUT_OC_FAULT_LIMIT Has Not Been Reached
• TOFF_FALL Is Not in Progress
Output UV warnings are determined from multiplexed
monitor ADC conversions. The LTC3882-1 has no hardwired PWM response for output UV faults or warnings.
Power Good Indication (Master)
An LTC3882-1 master phase indicates Power Good on its
PGOOD pin and in PMBus commands STATUS_WORD
(paged) and MFR_PADS_LTC3882-1 based on programmed UV and OV fault limits. Power Good is indicated
on a master phase as long as it is enabled to run and VOUT
is between the UV and OV fault limits. If a master channel is off for any reason, its PGOOD pin is driven low and
Power Not Good is indicated in the status commands.
• As a Percentage of VOUT if Using the Resistor Configuration Pins
• From Stored EEPROM Values
• By PMBus Command
26
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
OPERATION
Power Good Indication (Slave)
As long as they are enabled, slave phases indicate Power
Good on PGOOD and in PMBus status commands, unless
a master error amplifier (EA) fault is detected. An EA fault
indicates the bussed COMP voltage appears to be too high.
When a slave detects an EA fault, its output is immedidately disabled and OV is indicated (see Figure 2). Any
valid higher-level OV fault response and propagation may
be set for a slave channel to handle a detected EA fault. If
the OV fault response is set to ignore, the slave output is
re-enabled when the EA/COMP condition clears.
A slave indicates Power Not Good with PMBus status commands during an EA fault, but its PGOOD pin remains high
impedance. If a slave phase is off for any other reason, its
PGOOD pin is also driven low.
Hardwired PWM Response to IOUT Faults
The LTC3882-1 measures average IOUT from the voltage
across the ISENSE pins, taking into account the sense resistor
or DCR value and its associated temperature coefficient.
Both are provided by PMBus command or EEPROM values.
An output overcurrent (OC) fault condition is detected by
a supervisor comparator for each PWM output when the
sensed instantaneous current for that channel reaches
its maximum allowed value. Refer to the IOUT_OC_
FAULT_LIMIT PMBus command for details. When an OC
fault is detected the controller immediately disables the
top FET, and the bottom FET is normally commanded on
for the remainder of that PWM cycle.
If programmed to operate in CCM, the LTC3882-1 also
uses the negative of IOUT_OC_FAULT_LIMIT to detect
a reverse overcurrent (ROC) fault. When an ROC fault
occurs the controller immediately disables both top and
bottom FETs, unless PWM output protocol 1 is selected
with MFR_PWM_MODE_LTC3882-1.
OC and ROC faults are both handled according to the
IOUT_OC_FAULT_RESPONSE for that channel. Either
hardware response can result in current-limited operation
using pulse truncation or skipping. Because the LTC3882-1
uses leading edge modulation, this will cause a shift in
average phase toward 0° on the faulted channel and an
increase in input ripple current
Output OC warnings are determined from multiplexed
monitor ADC conversions. The LTC3882-1 has no hardwired
PWM response if an output OC warning occurs.
Hardwired PWM Response to Temperature Faults
An internal temperature sensor measured by the monitor ADC protects against EEPROM and other IC damage.
When die temperature rises above 130°C, the LTC3882-1
will NACK any EEPROM-related command except RESTORE_USER_ALL and MFR_RESET and issue a CML
fault for Invalid/Unsupported Command. Normal EEPROM
access is re-enabled when die temperature drops below
125°C. Above 160°C, the part shuts down all PWM outputs
until die temperature is below 150°C. Internal temperature
fault limits cannot be adjusted. Writing to the EEPROM
above a die temperature of 85°C is strongly discouraged.
Refer to the Absolute Maximum Ratings for other important
temperature limitations on internal EEPROM use.
External temperature sensors may also be monitored by
the onboard ADC. There is no hardwired PWM response
for sensed external temperature faults or warnings.
Hardwired PWM Response to Timing Faults
There is no hardwired PWM response to any timing faults.
TON_MAX_FAULT_LIMIT is the time allowed for VOUT to
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
timer, which has a resolution of 10µs, is started after
TON_DELAY has been reached and a soft-start sequence
is started. If the VOUT_UV_FAULT_LIMIT is not reached or
an OC remains within the specified time, fault response is
determined by the value of TON_MAX_FAULT_RESPONSE.
Rev. C
For more information www.analog.com
27
LTC3882-1/LTC3882-2
OPERATION
An internal watchdog detects if SHARE_CLK remains
low for more than 64µs. The part then actively holds
SHARE_CLK low for 120ms, ensuring all devices connected
to this shared control observe a minimum RETRY_DELAY
event.The LTC3882-1 sets the SHARE_CLK_LOW bit in
MFR_COMMON to indicate this fault condition.
External Faults
There are no hardware-level responses to any external
faults propagated into the IC through the FAULTn pins.
Fault Handling
Higher-level input and output fault event handling (response)
can be programmed as described in the following PMBus
Command Details section. For most faults, the LTC3882-1
can manage response in one of three ways: ignore, autonomous recovery (hiccup), or latch off. The device takes no
additional action beyond previously discussed hardwarelevel responses when programmed to ignore a fault.
For autonomous recovery a new soft-start is attempted if
the fault condition is not present after the MFR_RETRY_
DELAY interval has elapsed. MFR_RETRY_DELAY can be
set from 120ms to 83 seconds in 1ms increments. If the
fault persists, the controller will continue to retry with an
interval specified by the MFR_RETRY_DELAY command.
This avoids damage to external regulator components
caused by repetitive, rapid power cycling.
No retry is attempted for a latch off fault response. In the
latch off state the gate drivers for the external MOSFETs
are immediately disabled to stop the transfer of energy
to the load as quickly as possible. The output remains
disabled until the channel is commanded off and then
on, or IC supply power is cycled. Commanding a PWM
channel off and on may require software and/or hardware
intervention depending on its programmed configuration.
The RUN pin must be released by any controlling external
application circuits for that channel to restart from the latch
off state. As the RUN pin for a given channel rises, associated internal fault indications are cleared automatically. The
LTC3882-1 can also be programmed to clear faults for both
outputs based solely on the RUN voltage of just one chan-
28
nel. See the MFR_CONFIG_ALL_LTC3882-1 command. The
CLEAR_FAULTS PMBus command can also be used to clear
all fault bits at any time, independent of PWM channel state.
Handling of some internally generated faults can be digitally
deglitched. See Table 12. External faults propagated into
the chip using FAULTn pins are not deglitched. Refer to
the following section on FAULT functions.
Status Registers and ALERT Masking
Figure 2 summarizes the internal LTC3882-1 status registers accessible by PMBus command. These contain
indication of various faults, warnings and other important
operating conditions. As shown, the STATUS_BYTE and
STATUS_WORD commands also summarize contents of
other status registers. Refer to PMBus Command Details
for specific information.
NONE OF THE ABOVE in STATUS_BYTE indicates that
one or more of the bits in the most-significant nibble of
STATUS_WORD are also set.
In general, any asserted bit in a STATUS_x register also
pulls the ALERT pin low. Once set, ALERT will remain low
until one of the following occurs.
• A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_RESET Command Is Issued
• The Related Status Bit Is Written to a One
• The Faulted Channel Is Properly Commanded Off and
Back On
• The LTC3882-1 Successfully Transmits Its Address
During a PMBus Alert Response Address (ARA)
• IC Supply Power Is Cycled
With some exceptions, the SMBALERT_MASK command
can be used to prevent the LTC3882-1 from asserting
ALERT for bits in these registers on a bit-by-bit basis.
These mask settings are promoted to STATUS_WORD
and STATUS_BYTE in the same fashion as the status bits
themselves. For example, if ALERT is masked for all bits
in Channel 0 STATUS_VOUT, then ALERT is effectively
masked for the VOUT bit in STATUS_WORD for PAGE 0.
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
OPERATION
STATUS_WORD
STATUS_VOUT*
7
6
5
4
3
2
1
0
VOUT_OV Fault
VOUT_OV Warning
VOUT_UV Warning
VOUT_UV Fault
VOUT_MAX Warning
TON_MAX Fault
TOFF_MAX Warning
(reads 0)
15
14
13
12
11
10
9
8
VOUT
IOUT
INPUT
MFR_SPECIFIC
POWER_GOOD#
(reads 0)
(reads 0)
(reads 0)
7
6
5
4
3
2
1
0
BUSY
OFF
VOUT_OV
IOUT_OC
(reads 0)
TEMPERATURE
CML
NONE OF THE ABOVE
STATUS_BYTE
(PAGED)
STATUS_IOUT
7
6
5
4
3
2
1
0
IOUT_OC Fault
(reads 0)
IOUT_OC Warning
(reads 0)
(reads 0)
(reads 0)
(reads 0)
(reads 0)
MFR_COMMON
7
6
5
4
3
2
1
0
Chip Not Driving ALERT Low
Chip Not Busy
Internal Calculations Not Pending
Output Not In Transition
EEPROM Initialized
(reads 0)
SHARE_CLK_LOW
WP Pin High
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EEPROM ECC Status
Reserved
Reserved
Reserved
Reserved
STATUS_TEMPERATURE
OT Fault
OT Warning
(reads 0)
UT Fault
(reads 0)
(reads 0)
(reads 0)
(reads 0)
STATUS_CML
7
6
5
4
3
2
1
0
Invalid/Unsupported Command
Invalid/Unsupported Data
Packet Error Check Failed
Memory Fault Detected
Processor Fault Detected
(reads 0)
Other Communication Fault
Other Memory or Logic Fault
DESCRIPTION
General Fault or Warning Event
General Non-Maskable Event
Dynamic
Status Derived from Other Bits
7
6
5
4
3
2
1
0
Internal Temperature Fault
Internal Temperature Warning
EEPROM CRC Error
Internal PLL Unlocked
Fault Log Present
(reads 0)
VOUT Short Cycled
FAULT Low
(PAGED)
MFR_PADS_LTC3882-1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MFR_INFO
(PAGED)
VIN_OV Fault
(reads 0)
VIN_UV Warning
(reads 0)
Unit Off for Insuffcient VIN
(reads 0)
(reads 0)
(reads 0)
STATUS_MFR_SPECIFIC
(PAGED)
(PAGED)
7
6
5
4
3
2
1
0
STATUS_INPUT
7
6
5
4
3
2
1
0
Channel 1 is Slave
Channel 0 is Slave
(reads 0)
(reads 0)
Invalid ADC Result(s)
SYNC Output Disabled Externally
Channel 1 is POWER_GOOD
Channel 0 is POWER_GOOD
LTC3882-1 Forcing RUN1 Low
LTC3882-1 Forcing RUN0 Low
RUN1 Pin State
RUN0 Pin State
LTC3882-1 Forcing FAULT1 Low
LTC3882-1 Forcing FAULT0 Low
FAULT1 Pin State
FAULT0 Pin State
MASKABLE GENERATES ALERT BIT CLEARABLE
Yes
No
No
No
Yes
Yes
No
Not Directly
Yes
Yes
No
No
*IF THE CHANNEL IS CONFIGURED AS A SLAVE AS INDICATED BY MFR_PADS_LTC3882-1[15:14], VOUT_OV FAULT INDICATES A DETECTED MASTER ERROR
AMPLIFIER FAULT (COMP VOLTAGE TOO HIGH). NO OTHER BITS IN STATUS_VOUT ARE ACTIVE ON SLAVE CHANNELS
38821 F02
Figure 2. LTC3882-1/LTC3882-2 Status Register Summary
Rev. C
For more information www.analog.com
29
LTC3882-1/LTC3882-2
OPERATION
The BUSY bit in STATUS_BYTE also asserts ALERT low
and cannot be masked. This bit can be set as a result of
interaction between internal operation and PMBus communication. This fault occurs when a command is received
that cannot be safely executed with one or both channels
enabled. As discussed in Application Information, BUSY
faults can be avoided by polling MFR_COMMON before
executing some commands.
As noted above, FAULT pins may be configured as inputs
to detect faults external to the controller that require an
immediate response. External faults propagated into the
chip using FAULT pins are not deglitched.
Status information contained in MFR_COMMON and
MFR_PADS_LTC3882-1 can be used to clarify the contents of STATUS_BYTE or STATUS_WORD as shown,
but the contents of these registers do not affect the state
of the ALERT pin and may not directly influence bits in
STATUS_BYTE or STATUS_WORD.
The LTC3882-1 features a fault log, providing telemetry
recording capability. During normal operation log data is
continuously updated in internal RAM. When a fault occurs
that disables either PWM controller, recording to internal
memory is halted, the fault log information is made available from RAM via the MFR_FAULT_LOG command, and
the contents of the RAM log are copied into EEPROM.
Refer to the Fault Log Operation section for more detail.
FAULT Pin I/O
The LTC3882-1 can map various fault indicators to their
respective FAULT pin using the MFR_FAULT_PROPAGATE_LTC3882-1 command.
Channel-to-channel fault dependencies and communication can be created by connecting FAULT pins together. In
the event of an internal fault, one or more of the channels
is configured to pull the bussed FAULT pins low. All channels are then configured to shut down when the bussed
FAULT pins are pulled low (MFR_FAULT_RESPONSE set
to 0xc0). If latch off is the programmed response on the
faulted channel, the FAULT pin remains low until one of
the following occurs:
• A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_RESET Command Is Issued
• The Related Status Bit Is Written to a One
• The Faulted Channel Is Properly Commanded Off and
Back On
• IC Supply Power Is Cycled
For autonomous group retry, the faulted channel is configured to release the FAULT pin(s) after a retry interval,
assuming the original fault has cleared. All the channels
in the group then begin a soft-start sequence.
30
Refer to the MFR_FAULT_PROPAGATE command for additional details.
Fault Logging
EEPROM fault logging is allowed above a die temperature
of 85°C, but 10 years of retention is not guaranteed. When
die temperature exceeds 130°C EEPROM fault logging is
delayed until the temperature drops below 125°C. Faults
generating a log should be fully cleared before the log is
erased to prevent generation of spurious fault logs. Faults
propagated into the IC through FAULTn pins do not trigger
a fault logging event.
When the LTC3882-1 powers up it checks the EEPROM
for a valid fault log. If one is found the Valid Fault Log bit
in the STATUS_MFR_SPECIFIC PMBus command is set.
Additional fault logging will be disabled until the LTC3882-1
receives a CLEAR_FAULTS command. If the Memory Fault
Detected bit is also set in STATUS_CML, then the stored
fault log is partial. Data in one or more event records may
be incomplete or incorrect and MFR_FAULT_LOG_CLEAR
should also be commanded after all faults are cleared in
order to fully enable additional logging functions.
The MFR_FAULT_LOG command uses a block read protocol
with a fixed length of 147 bytes. The LTC3882-1 returns a
block byte count of zero if a fault log is not present.
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
OPERATION
Table 1. LTC3882-1/LTC3882-2 Fault Log Contents
RECORD TYPE
STARTING ENDING
BYTE
BYTE COMMENTS
Header Information
0
26
See Table 2.
Fault Event Record
27
46
Fault may have occurred
anywhere during this event
record. See byte 4 of Table 2
and all of Table 3 and Table 4.
Event Record N-1
47
66
Last complete cyclical data
read before the fault was
detected.
Event Record N-2
67
86
Older data record.
Event Record N-3
87
106
Event Record N-4
107
126
Event Record N-5
127
146
Contents of a fault log are shown in Table 1 through Table 4.
Refer to Table 6 for an explanation of data formats. Each
event record represents one complete conversion cycle
through all multiplexed monitor ADC inputs and related
status. The six most recent event records are maintained
in internal memory in reverse chronological order unless
the part is reset. Then the four most recent events are
maintained in EEPROM. When a fault log is created the
present ADC input cycle is completed and the ADC input
being converted at the time of the fault is noted in the log
header record.
Oldest recorded data.
Table 2. Fault Log Header Information
RECORD
Fault Log Preface
Fault Source
MFR_REAL_TIME
MFR_VOUT_PEAK (PAGE 0)
MFR_VOUT_PEAK (PAGE 1)
MFR_IOUT_PEAK (PAGE 0)
MFR_IOUT_PEAK (PAGE 1)
MFR_VIN_PEAK
READ_TEMPERATURE1 (PAGE 0)
READ_TEMPERATURE1 (PAGE 1)
READ_TEMPERATURE2
BITS
[7:0]
[7:0]
[15:8]
[7:0]
[7:0]
[7:0]
[15:8]
[23:16]
[31:24]
[39:32]
[47:40]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
FORMAT
ASC
Reg
Reg
Reg
L16
L16
L11
L11
L11
L11
L11
L11
BLOCK
BYTE
COUNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DETAILS
Returns LTxx beginning at byte 0 if a partial or complete fault log exists. Word xx is
a factory identifier that may vary part to part.
Refer to Table 3.
48 bit share-clock counter value when fault occurred (200µs resolution).
Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS command.
Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS command.
Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS command.
Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS command.
Peak READ_VIN since last power-on or CLEAR_PEAKS command.
External temperature sensor 0 during last event.
External temperature sensor 1 during last event.
Internal temperature sensor during last event.
Rev. C
For more information www.analog.com
31
LTC3882-1/LTC3882-2
OPERATION
Table 3. Fault Source Values
FAULT SOURCE VALUE
CAUSE OF FAULT LOG
0x00
TON_MAX
0x01
VOUT_OV
0x02
VOUT_UV
0x03
IOUT_OC
0x05
Over temperature
0x06
Under temperature
CHANNEL
0
0x07
VIN_OV
0x0A
Internal temperature
0x10
TON_MAX
0x11
VOUT_OV
0x12
VOUT_UV
0x13
IOUT_OC
0x15
Over temperature
0x16
Under temperature
0x17
VIN_OV
0x1A
Internal temperature
0xFF
MFR_FAULT_LOG_STORE
1
Table 4. Fault Log Event Record
DATA
BITS
FORMAT
RECORD BYTE INDEX
READ_VOUT (PAGE 0)
[15:8]
L16
0
[7:0]
READ_VOUT (PAGE 1)
[15:8]
READ_IOUT (PAGE 0)
[15:8]
READ_IOUT (PAGE 1)
[15:8]
1
L16
2
L11
4
L11
6
[7:0]
3
[7:0]
5
[7:0]
READ_VIN
[15:8]
7
L11
[7:0]
(Not used)
[15:8]
STATUS_VOUT (PAGE 0)
[7:0]
8
9
L11
10
Reg
12
[7:0]
11
STATUS_VOUT (PAGE 1)
[7:0]
Reg
13
STATUS_WORD (PAGE 0)
[15:8]
Reg
14
[7:0]
STATUS_WORD (PAGE 1)
[15:8]
15
Reg
[7:0]
16
17
STATUS_MFR_SPECIFIC (PAGE 0)
[7:0]
Reg
18
STATUS_MFR_SPECIFIC (PAGE 1)
[7:0]
Reg
19
32
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
OPERATION
Factory Default Operation
The LTC3882-1 ships from the factory with a default configuration stored in its non-volatile memory, unless custom
programming has been requested. These command values
are loaded into volatile RAM when the chip is initialized. Prior
to receiving any PMBus commands, a stock LTC3882-1 will
operate in the factory default mode. If a STORE_USER_
ALL command is executed, the contents of the non-volatile
memory are replaced with active command values from
internal RAM, and that will permanently overwrite the factory
defaults. Table 5 summarizes the default factory operation
settings of the LTC3882-1 if all resistor configuration pins
are left open. These defaults allow parameters listed in bold
text in the table to be overridden with configuration resistor
programming. Warning limits are given in Table 5 because
exceeding them will cause the ALERT pin to be asserted even
if the PMBus interface is not being utilized.
Table 5. Factory Default Operation Summary
PARAMETER*
DEFAULT SETTING
UNITS
PMBus Address
All writes enabled to Channel 0 at address 0x4F (no PEC).
–
Operation
OPERATION enabled with RUN pin control and soft-off.
–
Input Voltage OFF Threshold
6.0
V
Input Voltage UV Warning Limit
6.3
V
Input Voltage ON Threshold
6.5
V
Input Voltage OV Fault Limit
15.5
V
Input Voltage OV Fault Response
Latch off.
Soft-Start Time
8 (with no delay).
ms
–
Maximum Start-Up Time (TMAX)
10
ms
TMAX Fault Response
Retry every 350ms.
–
Output Voltage UV Fault/Warning Limits
0.900/0.925
V
Output Voltage UV Fault Response
Retry every 350ms.
–
Output Voltage
1.000
V
Active Voltage Positioning
Disabled.
–
Output Voltage OV Warning/Fault Limits
1.075/1.100
V
Output Voltage OV Fault Response
Retry every 350ms.
–
Shut Down
8ms soft-off.
–
Output Current Sense Element
0.63mΩ with 3930ppm/°C TC.
–
Output Current OC Warning/Fault Limits
20/29.75
A
Output Current OC Fault Response
Ignore
–
PWM Switching Mode
Continuous inductor current only.
–
PWM Control Protocol
Three-State PWM.
–
PWM Switching Frequency
500
Channel 0/1 Phase
0/180
kHz
Degrees
Internal Overtemperature Warning/Fault Limits
130/160
°C
Internal Overtemperature Responses
Warning: EEPROM disabled; Fault: PWM disabled.
–
External Undertemperature Fault Limit
–40
°C
External Undertemperature Fault Response
Retry every 350ms.
–
External Overtemperature Warning/Fault Limits
85/100
°C
External Overtemperature Fault Response
Retry every 350ms.
–
FAULT
Asserts low for the following faults: VOUT UV or OV, VIN OV, external or internal OT,
external UT, TON_MAX, or output short cycle.
–
ALERT Masking
ALERTs are masked for loss of PLL lock and external FAULT inputs.
–
*bold entries can be changed with external configuration resistors
Rev. C
For more information www.analog.com
33
LTC3882-1/LTC3882-2
OPERATION
Serial Interface
• Read Byte
The LTC3882-1 has a PMBus compliant serial interface that
can operate at any frequency between 10kHz and 400kHz.
The LTC3882-1 is a bus slave device that communicates
bidirectionally with a host (master) using standard PMBus
protocols. The Timing Diagram found earlier in this document, along with related Electrical Characteristics table
entries, define the timing relationships of the SDA and SCL
bus signals. SDA and SCL must be high when the bus is
not in use. External pull-up resistors or current sources
are required on these lines.
• Read Word
PMBus, an incremental extension of the SMBus standard,
offers more robust operation than a 2-wire I2C interface. In
addition to adding a protocol layer to improve interoperability and facilitate reuse, PMBus supports bus timeout
recovery for system reliability, optional packet error checking to ensure data integrity, and peripheral hardware alerts
for system fault management. In general, a programmable
device capable of functioning as an I2C bus master can be
configured for PMBus management with little or no change
to hardware. However, not all I2C controllers support repeat
start (restart) required for PMBus reads.
For a description of the minor extensions and exceptions
PMBus makes to the SMBus standard, refer to PMBus
Specification Part I Revision 1.2 Paragraph 5 on Transport.
For a description of the differences between SMBus and
I2C, refer to System Management Bus (SMBus) Specification Version 2.0 Appendix B on Differences Between
SMBus and I2C.
The user is encouraged to reference Part I of the latest
PMBus Power System Management Protocol Specification to understand how to interface the LTC3882-1 to a
PMBus system. This specification can be found at http://
www.pmbus.org/specs.html.
• Block Read
• Block Write – Block Read Process Call
• Alert Response Address
The LTC3882-1 does not require PEC for Quick Command
under any circumstances. The LTC3882-1 also supports
group command protocol (GCP) as required by PMBus
specification Part I, section 5.2.3. GCP is used to send commands to more than one PMBus device in one continuous
transmission. It should not be used with commands that
require the receiving device to respond with data, such as
a STATUS_BYTE command. Refer to Part I of the PMBus
specification for additional details on using GCP.
All LTC3882-1 message transmission types allow for packet
error checking. The later section on Serial Communication
Errors provides more detail on packet error checking.
Figure 4 to Figure 20 illustrate these protocols. Figure 3
provides a key to the protocol diagrams. Not all protocol
elements will be present in every data packet. For instance,
not all packets are required to include the packet error
code. A number shown above a field in these diagrams
indicates the number of bits in that field. All data transfers
are initiated by the present bus master regardless of how
many times data direction flow may change during the
subsequent transmission. The LTC3882-1 never functions
as a bus master.
This device includes handshaking features to ensure robust system communication. Please refer to the PMBus
Communication and Command Processing section in
Applications Information for more details.
Serial Bus Addressing
The LTC3882-1 uses the following standard serial interface
protocols defined in the SMBus and PMBus specifications:
The LTC3882-1 supports four types of serial bus addressing:
• Quick Command
• Global Bus Addressing
• Send Byte
• Power Rail Addressing
• Write Byte
• Individual Device Addressing
• Write Word
• Page+ Channel Addressing
34
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
OPERATION
Global addressing provides a means for the bus master
to communicate with all LTC3882-1 devices on the bus
simultaneously. The LTC3882-1 global addresses of 0x5A
and 0x5B cannot be changed or disabled. Commands sent
to address 0x5A are applied to both channels, as if the
PAGE command were set to 0xFF. Global address 0x5B is
paged, allowing channel-specific control of all LTC3882-1
devices on the bus. Other LTC device types may respond
at one or both of these global addresses. Reading from
global addresses is strongly discouraged.
PolyPhase rail. Different voltage rails should not attempt
to share a rail address. Reading from rail addresses is
also strongly discouraged.
Device addressing is the most common means used by a
bus master to communicate with an LTC3882-1. The value
of the device address is set by the combination of ASEL
pin programming and the MFR_ADDRESS command.
Refer to the previous section on Resistor Configuration
Pins for details.
Individual channel addressing allows the bus master to
communicate directly with a specific LTC3882-1 PWM
channel without first using a PAGE command. Refer to
the PAGE_PLUS commands for additional details.
Rail addressing provides a means for the bus master to
simultaneously communicate with all channels connected
together to produce a single output voltage (PolyPhase).
While similar to global addressing, the rail address can
be dynamically assigned with the paged MFR_RAIL_ADDRESS command, allowing for any logical grouping of
channels that might be required for reliable system control.
Rail addresses should be unique for each single-phase or
Use of any of the four types of addressing requires careful
planning to avoid address-related bus conflicts. Communication to LTC3882-1 devices at global and rail addresses
should be limited to command write operations.
S
START CONDITION
Sr
REPEATED START CONDITION
Rd
READ (BIT VALUE OF 1)
Wr
WRITE (BIT VALUE OF 0)
A
NA
ACKNOWLEDGE (BIT SHOULD BE 0), OR
NOT ACKNOWLEDGE (BIT SHOULD BE 1)
P
STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
...
CONTINUATION OF PROTOCOL
38821 F03
Figure 3. PMBus Packet Protocol Diagram Element Key
1
7
S
1
1
SLAVE ADDRESS Rd/Wr A
1
P
38821 F04
Figure 4. Quick Command Protocol
1
S
1
1
SLAVE ADDRESS Wr A COMMAND CODE A
7
1
1
8
P
38821 F05
Figure 5. Send Byte Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
1
PEC
A
P
38821 F06
Figure 6. Send Byte Protocol with PEC
Rev. C
For more information www.analog.com
35
LTC3882-1/LTC3882-2
OPERATION
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
1
DATA BYTE
A
P
38821 F07
Figure 7. Write Byte Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
1
DATA BYTE
A
PEC
A
P
38821 F08
Figure 8. Write Byte Protocol with PEC
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
1
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
38821 F09
Figure 9. Write Word Protocol
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
8
1
1
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
38821 F10
Figure 10. Write Word Protocol with PEC
1
S
7
1
1
8
1
1
7
1
1
8
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
1
DATA BYTE
1
NA P
38821 F11
Figure 11. Read Byte Protocol
1
S
7
1
1
8
1
1
7
1
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
8
1
1
DATA BYTE
A
PEC
A
P
38821 F12
Figure 12. Read Byte Protocol with PEC
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
1
7
1
1
Sr SLAVE ADDRESS Rd A
8
1
DATA BYTE LOW
A
8
1
1
DATA BYTE HIGH NA P
38821 F13
Figure 13. Read Word Protocol
1
S
7
1
1
8
1
1
7
1
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
DATA BYTE LOW
A
8
1
DATA BYTE HIGH A
8
1
1
PEC
A
P
38821 F14
Figure 14. Read Word Protocol with PEC
1
S
7
1
1
8
1
1
7
1
1
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
8
DATA BYTE 1
A
DATA BYTE 2
1
…
A …
8
DATA BYTE N
8
1
BYTE COUNT = N A
1
…
1
NA P
38821 F15
Figure 15. Block Read Protocol
36
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
OPERATION
1
S
7
1
1
8
1
1
7
1
1
8
SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A
8
1
8
DATA BYTE 1
A
DATA BYTE 2
1
…
A …
1
BYTE COUNT = N A
8
1
8
DATA BYTE N
A
PEC
1
…
1
NA P
38821 F16
Figure 16. Block Read Protocol with PEC
1
S
7
1
1
8
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A
8
1
DATA BYTE 2
1
7
1
8
A …
1
Sr SLAVE ADDRESS Rd A
1
8
A …
…
1
BYTE COUNT = N A
8
DATA BYTE 2
1
A
A …
DATA BYTE M
8
8
DATA BYTE 1
8
1
DATA BYTE 1
A
1
DATA BYTE N
…
1
NA P
38821 F17
Figure 17. Block Write – Block Read Process Call
1
S
7
1
1
8
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A
8
DATA BYTE 2
1
7
1
1
Sr SLAVE ADDRESS Rd A
8
1
DATA BYTE 2
1
…
A …
A …
8
1
A
…
1
DATA BYTE M
8
8
DATA BYTE 1
A …
1
BYTE COUNT = N A
8
DATA BYTE 1
8
1
8
DATA BYTE N
A
PEC
A
1
…
1
NA P
38821 F18
Figure 18. Block Write – Block Read Process Call with PEC
1
7
1
1
8
1
1
S ALERT RESPONSE Rd A DEVICE ADDRESS NA P
ADDRESS
38821 F19
Figure 19. Alert Response Address Protocol
1
7
1
1
8
1
S ALERT RESPONSE Rd A DEVICE ADDRESS A
ADDRESS
8
PEC
1
1
NA P
38821 F20
Figure 20. Alert Response Address Protocol with PEC
Rev. C
For more information www.analog.com
37
LTC3882-1/LTC3882-2
OPERATION
Serial Bus Timeout
Serial Communication Errors
The LTC3882-1 implements a timeout feature to avoid
hanging the serial interface. The data packet timer begins running at the first START event before the SLAVE
ADDRESS write byte and ends with the STOP bit. Packet
transmission must be completed before the timer expires,
or the LTC3882-1 will tri-state the bus and ignore all message data. The data packet includes the SLAVE ADDRESS
byte, COMMAND CODE byte, repeated START and SLAVE
ADDRESS byte (if a read operation), all ACKNOWLEDGE
and flow control bits (R/W) and all data bytes.
The LTC3882-1 supports the optional PMBus packet error
checking protocol. This protocol appends a packet error
code (PEC) to the end of applicable message transfers to
improve communication reliability. The PEC is a CRC-8
error-checking byte calculated by the bus device sending
the last data byte. Refer to SMBus specification 1.2 or
higher for additional implementation details. All LTC3882-1
read operations will return a valid PEC if the bus master
requests it. If bit 2 in the MFR_CONFIG_ALL_LTC3882-1
command is set, the IC will not act in response to a bus
write operation unless a valid PEC is also received from
the host.
The packet timer is typically set to 30ms. If bit 3 of MFR_
CONFIG_ALL_LTC3882-1 is set, this period is extended
to 255ms. The LTC3882-1 automatically allows a packet
transmission time of 255ms for MFR_FAULT_LOG block
reads regardless of the setting of this bit. In no circumstances will the timeout period be less than the tTIMEOUT
specification (25ms minimum).
The LTC3882-1 supports the full PMBus frequency range
of 10kHz to 400kHz.
38
PEC errors on command writes, attempts to access unsupported commands, or writing invalid data to supported
commands all cause the LTC3882-1 to generate a CML
fault. The CML bit is then set in the STATUS_BYTE and
STATUS_WORD commands, and the appropriate bit is set
in the STATUS_CML command.
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
PMBus COMMAND SUMMARY
PMBus Commands
Table 7 lists supported PMBus commands and manufacturer specific commands. Additional information about
these commands can be found in Revision 1.2 of Part II of
the PMBus Power System Management Protocol Specification that can be found at http://www.pmbus.org/specs.html.
Users are encouraged to reference that manual. Exceptions
or manufacturer-specific implementations are detailed in
the tables below. All standard PMBus commands from
0x00 through 0xCF not listed in this table are implicitly
not supported by the LTC3882-1. All commands from
0xD0 through 0xFF not listed in this table are implicitly
reserved by the manufacturer. The LTC3882-1 may execute
additional commands not listed in this table, and these
can change without notice. Reading these unlisted commands is harmless to the operation of the IC. Writes to any
unsupported or reserved command should be avoided, as
they may result in a CML fault and/or undesired operation
of the part.
If PMBus commands are received faster than they are being processed, the part may become too busy to handle
new commands. In these cases the LTC3882-1 follows the
protocols defined in the PMBus Specification V1.2, Part
II, Section 10.8.7, to communicate that it is busy. This
device includes handshaking features to eliminate busy
responses, simplify error handling software and ensure
robust communication and system behavior. Please refer
to PMBus Communication and Command Processing in
the Applications Information section for further details.
LTC has made an effort to establish PMBus command
compatibility and functional uniformity among its family
of parts. However, differences may occur due to specific
product requirements. Compatibility of PMBus commands
among any ICs should not be assumed based simply on
command name. Always refer to the manufacturer’s data
sheet of each device for a complete definition of a command function.
Data Formats
PMBus supports specific floating point number formats
and allows for a wide range of other data formats.
Table 6 describes the data formats used by the LTC3882-1.
Abbreviations of these formats appear throughout this
document.
Table 6. Abbreviations of Supported Data Formats
PMBus
TERMINOLOGY
SPECIFICATION
LTC
REFERENCE TERMINOLOGY DEFINITION
L11
Linear
Part II ¶7.1
Linear_5s_11s
L16
Linear VOUT_MODE
Part II ¶8.2
Linear_16u
CF
DIRECT
Part II ¶7.2
varies
Reg
register bits
Part II ¶10.3
Reg
ASC
text characters
Part II ¶22.2.1
ASCII
Floating point 16-bit data: value = Y • 2N,
where N = b[15:11] and Y = b[10:0], both
two’s compliment binary integers.
EXAMPLE
b[15:0] = 0x9807 = 10011_000_0000_0111
value = 7 • 2–13 = 854E-6
Floating point 16-bit data: value = Y • 2–12, b[15:0] = 0x4C00 = 0100_1100_0000_0000
where Y = b[15:0], an unsigned integer.
value = 19456 • 2–12 = 4.75
16-bit data with a custom format
defined in the detailed PMBus command
description.
Often an unsigned or two’s compliment
integer.
Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command.
command description.
ISO/IEC 8859-1 [A05]
LTC (0x4C5443)
Rev. C
For more information www.analog.com
39
LTC3882-1/LTC3882-2
PMBus COMMAND SUMMARY
Table 7. PMBus Command Summary
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
DATA
PAGED FORMAT
UNITS NVM
DEFAULT
VALUE
SEE
PAGE
0x00
72
PAGE
0x00 Channel (page) presently selected for
any paged command.
R/W Byte
N
Reg
OPERATION
0x01 On, off and margin control.
R/W Byte
Y
Reg
l
0x80
76
ON_OFF_CONFIG
0x02 RUN pin and PMBus on/off command
configuration.
R/W Byte
Y
Reg
l
0x1E
75
CLEAR_FAULTS
0x03 Clear all set fault bits.
Send Byte
N
93
PAGE_PLUS_WRITE
0x05 Write a command directly to a specified
page.
W Block
N
72
PAGE_PLUS_READ
0x06 Read a command directly from a
specified page.
Block R/W
Process
N
73
WRITE_PROTECT
0x10 Protect the device against unintended
PMBus modifications.
R/W Byte
N
STORE_USER_ALL
0x15 Store entire operating memory in
EEPROM.
Send Byte
N
105
RESTORE_USER_ALL
0x16 Restore entire operating memory from
EEPROM.
Send Byte
N
105
CAPABILITY
0x19 Summary of supported optional PMBus
features.
R Byte
N
Reg
SMBALERT_MASK
0x1B Mask ALERT activity
Block R/W
Y
Reg
VOUT_MODE
0x20 Voltage-related format (Linear) and
exponent.
R Byte
Y
Reg
VOUT_COMMAND
0x21 Nominal VOUT value.
R/W Word
Y
L16
V
VOUT_MAX
0x24 Maximum VOUT that can be set by any
command, including margin.
R/W Word
Y
L16
VOUT_MARGIN_HIGH
0x25 VOUT at high margin, must be greater
than VOUT_COMMAND.
R/W Word
Y
VOUT_MARGIN_LOW
0x26 VOUT at low margin, must be less than
VOUT_COMMAND.
R/W Word
VOUT_TRANSITION_RATE
0x27 VOUT slew rate for programmed output
changes.
FREQUENCY_SWITCH
Reg
l
0x00
73
0xB0
74
see CMD
details
101
0x14
2–12
82
l
1.0V
0x1000
82
V
l
5.5V
0x5800
83
L16
V
l
1.05V
0x10CD
83
Y
L16
V
l
0.95V
0x0F33
83
R/W Word
Y
L11
V/ms
l
0.25
0xAA00
87
0x33 PWM frequency control.
R/W Word
N
L11
kHz
l
500kHz
0xFBE8
77
VIN_ON
0x35 Minimum input voltage to begin power
conversion.
R/W Word
N
L11
V
l
6.5V
0xCB40
81
VIN_OFF
0x36 Decreasing input voltage at which power R/W Word
conversion stops.
N
L11
V
l
6.0V
0xCB00
81
IOUT_CAL_GAIN
0x38 Ratio of ISENSE± voltage to sensed
current.
R/W Word
Y
L11
mΩ
l
0.63mΩ
0xB285
85
VOUT_OV_FAULT_LIMIT
0x40 VOUT overvoltage fault limit.
R/W Word
Y
L16
V
l
1.1V
0x119A
83
l
VOUT_OV_FAULT_RESPONSE
0x41 VOUT overvoltage fault response.
R/W Byte
Y
Reg
l
0xB8
98
VOUT_OV_WARN_LIMIT
0x42 VOUT overvoltage warning limit.
R/W Word
Y
L16
V
l
1.075V
0x1133
84
VOUT_UV_WARN_LIMIT
0x43 VOUT undervoltage warning limit.
R/W Word
Y
L16
V
l
0.925V
0x0ECD
84
40
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
PMBus COMMAND SUMMARY
Table 7. PMBus Command Summary
COMMAND NAME
CMD
CODE DESCRIPTION
VOUT_UV_FAULT_LIMIT
0x44 VOUT undervoltage fault limit.
R/W Word
Y
L16
VOUT_UV_FAULT_RESPONSE
R/W Byte
Y
Reg
IOUT_OC_FAULT_LIMIT
0x45 VOUT undervoltage fault response.
0x46 Output overcurrent fault limit.
R/W Word
Y
L11
IOUT_OC_FAULT_RESPONSE
0x47 Output overcurrent fault response.
R/W Byte
Y
Reg
IOUT_OC_WARN_LIMIT
0x4A Output overcurrent warning limit.
R/W Word
Y
L11
OT_FAULT_LIMIT
0x4F External overtemperature fault limit.
R/W Word
Y
L11
TYPE
DATA
PAGED FORMAT
DEFAULT
VALUE
SEE
PAGE
l
0.9V
0x0E66
84
l
0xB8
98
l
29.75A
0xDBB8
85
l
0x00
99
A
l
20.0A
0xDA80
85
°C
l
100.0°C
0xEB20
88
UNITS NVM
V
A
OT_FAULT_RESPONSE
0x50 External overtemperature fault response.
R/W Byte
Y
Reg
l
0xB8
100
OT_WARN_LIMIT
0x51 External overtemperature warning limit.
R/W Word
Y
L11
°C
l
85.0°C
0xEAA8
88
UT_FAULT_LIMIT
0x53 External undertemperature fault limit.
R/W Word
Y
L11
°C
l
–40.0°C
0xE580
89
UT_FAULT_RESPONSE
0x54 External undertemperature fault
response.
R/W Byte
Y
Reg
l
0xB8
100
VIN_OV_FAULT_LIMIT
0x55 VIN overvoltage fault limit.
R/W Word
N
L11
l
15.5V
0xD3E0
81
VIN_OV_FAULT_RESPONSE
0x56 VIN overvoltage fault response.
R/W Byte
Y
Reg
l
0x80
97
VIN_UV_WARN_LIMIT
0x58 VIN undervoltage warning limit.
R/W Word
N
L11
V
l
6.3V
0xCB26
81
TON_DELAY
0x60 Delay from RUN pin or OPERATION ON
command to TON_RISE ramp start.
R/W Word
Y
L11
ms
l
0.0ms
0x8000
86
TON_RISE
0x61 Time for VOUT to rise from 0.0V to
VOUT_COMMAND after TON_DELAY.
R/W Word
Y
L11
ms
l
8.0ms
0xD200
86
TON_MAX_FAULT_LIMIT
0x62 Maximum time for VOUT to rise above
VOUT_UV_FAULT_LIMIT after
TON_DELAY.
R/W Word
Y
L11
ms
l
10.0ms
0xD280
87
TON_MAX_FAULT_RESPONSE
0x63 Fault response when TON_MAX_FAULT_
LIMIT is exceeded.
R/W Byte
Y
Reg
l
0xB8
101
TOFF_DELAY
0x64 Delay from RUN pin or OPERATION OFF
command to TOFF_FALL ramp start.
R/W Word
Y
L11
ms
l
0.0ms
0x8000
87
TOFF_FALL
0x65 Time for VOUT to fall to 0.0V from
VOUT_COMMAND after TOFF_DELAY.
R/W Word
Y
L11
ms
l
8.0ms
0xD200
87
TOFF_MAX_WARN_ LIMIT
0x66 Maximum time for VOUT to decay below
12.5% of VOUT_COMMAND after
TOFF_FALL completes.
R/W Word
Y
L11
ms
l
150ms
0xF258
87
STATUS_BYTE
0x78 One-byte channel status summary.
R/W Byte
Y
Reg
89
STATUS_WORD
0x79 Two-byte channel status summary.
R/W Word
Y
Reg
90
STATUS_VOUT
0x7A VOUT fault and warning status.
R/W Byte
Y
Reg
90
STATUS_IOUT
0x7B IOUT fault and warning status.
0x7C Input supply fault and warning status.
R/W Byte
Y
Reg
90
R/W Byte
N
Reg
91
R/W Byte
Y
Reg
91
STATUS_INPUT
STATUS_TEMPERATURE
0x7D External temperature fault and warning
status.
V
Rev. C
For more information www.analog.com
41
LTC3882-1/LTC3882-2
PMBus COMMAND SUMMARY
Table 7. PMBus Command Summary
COMMAND NAME
CMD
CODE DESCRIPTION
TYPE
DATA
PAGED FORMAT
UNITS NVM
DEFAULT
VALUE
SEE
PAGE
STATUS_CML
0x7E Communication, memory and logic fault
and warning status.
R/W Byte
N
Reg
91
STATUS_MFR_ SPECIFIC
0x80 LTC3882-1-specific status.
R/W Byte
Y
Reg
92
READ_VIN
0x88 Measured VIN.
R Word
N
L11
V
94
READ_VOUT
R Word
Y
L16
V
94
READ_IOUT
0x8B Measured VOUT.
0x8C Measured IOUT.
R Word
Y
L11
A
95
READ_TEMPERATURE_1
0x8D Measured external temperature.
R Word
Y
L11
°C
95
READ_TEMPERATURE_2
0x8E Measured internal temperature.
R Word
N
L11
°C
95
READ_DUTY_CYCLE
0x94 Measured commanded PWM duty cycle.
R Word
Y
L11
%
96
READ_FREQUENCY
0x95 Measured PWM input clock frequency.
R Word
Y
L11
kHz
96
READ_POUT
0x96 Calculated output power.
R Word
Y
L11
W
95
PMBUS_REVISION
0x98 Supported PMBus version.
R Byte
N
Reg
0x22
V1.2
74
MFR_ID
0x99 Manufacturer identification.
R String
N
ASC
LTC
106
MFR_MODEL
0x9A LTC model number.
R String
N
ASC
LTC3882-1
LTC3882-2
106
MFR_SERIAL
0x9E Device serial number.
R Block
N
ASC
IC_DEV_ID (LTC3882-2 only)
0xAD LTC3882-2 model number
R String
N
ASC
LTC3882-2
106
106
IC_DEVICE_REV
(LTC3882-2 only)
0xAE LTC3882-2 device revision code
R String
N
ASC
A4802
106
R Word
Y
L16
5.6V
0x599A
82
LTC3882-1/LTC3882-2 Custom Commands
MFR_VOUT_MAX
0xA5 Maximum value of any VOUT related
command.
V
USER_DATA_00
0xB0 EEPROM word reserved for LTpowerPlay. R/W Word
N
Reg
l
106
USER_DATA_01
0xB1 EEPROM word reserved for LTpowerPlay. R/W Word
Y
Reg
l
106
USER_DATA_02
0xB2 EEPROM word reserved for OEM use.
R/W Word
N
Reg
l
106
USER_DATA_03
0xB3 EEPROM word available for general data
storage.
R/W Word
Y
Reg
l
0x0000
106
USER_DATA_04
0xB4 EEPROM word available for general data
storage.
R/W Word
N
Reg
l
0x0000
106
R Word
N
Reg
MFR_INFO
0xB6 Manufacturing Specific Information
MFR_EE_UNLOCK
0xBD (contact the factory)
NA
106
93
MFR_EE_ERASE
0xBE (contact the factory)
106
MFR_EE_DATA
0xBF (contact the factory)
106
MFR_CHAN_CONFIG_LTC3882-1 0xD0 LTC3882-1 channel-specific
configuration.
R/W Byte
Y
Reg
l
0x1D
79
MFR_CONFIG_ALL_LTC3882-1
0xD1 LTC3882-1 device-level configuration.
R/W Byte
N
Reg
l
0x01
75
MFR_FAULT_PROPAGATE_
LTC3882-1
0xD2 Configure LTC3882-1 status propagation R/W Word
via FAULTn pins.
Y
Reg
l
0x6993
102
MFR_VOUT_AVP
0xD3 Specify VOUT load line.
R/W Word
Y
L11
l
0%
0x8000
83
MFR_PWM_MODE_LTC3882-1
0xD4 LTC3882-1 channel-specific PWM mode
control.
R/W Byte
Y
Reg
l
0xC8
80
42
%
Rev. C
For more information www.analog.com
LTC3882-1/LTC3882-2
PMBus COMMAND SUMMARY
Table 7. PMBus Command Summary
COMMAND NAME
CMD
CODE DESCRIPTION
MFR_FAULT_RESPONSE
0xD5 PWM response when FAULTn pin is low.
TYPE
DATA
PAGED FORMAT
R/W Byte
Y
Reg
UNITS NVM
l
DEFAULT
VALUE
SEE
PAGE
0xC0
103
0xC0
100
MFR_OT_FAULT_RESPONSE
0xD6 Internal overtemperature fault response.
R Byte
N
Reg
MFR_IOUT_PEAK
0xD7 Maximum IOUT measurement since last
MFR_CLEAR_PEAKS.
R Word
Y
L11
A
MFR_RETRY_DELAY
0xDB Minimum time before retry after a fault.
R/W Word
Y
L11
ms
l
350ms
0xFABC
101
MFR_RESTART_DELAY
0xDC Minimum time RUN pin is held low by
the LTC3882-1.
R/W Word
Y
L11
ms
l
500ms
0xFBE8
86
MFR_VOUT_PEAK
0xDD Maximum VOUT measurement since last
MFR_CLEAR_PEAKS.
R Word
Y
L16
V
94
MFR_VIN_PEAK
0xDE Maximum VIN measurement since last
MFR_CLEAR_PEAKS.
R Word
N
L11
V
94
MFR_TEMPERATURE_1_PEAK
0xDF Maximum external temperature
measurement since last MFR_CLEAR_
PEAKS.
R Word
Y
L11
°C
95
MFR_CLEAR_PEAKS
0xE3 Clear all peak values.
Send Byte
N
MFR_PADS_LTC3882-1
0xE5 State of selected LTC3882-1 pads.
R Word
N
Reg
MFR_ADDRESS
0xE6 Specify right-justified 7-bit device
address.
R/W Byte
N
Reg
MFR_SPECIAl_ID
0xE7 Manufacturer code representing the
LTC3882-1
R Word
N
Reg
MFR_FAULT_LOG_STORE
0xEA Force transfer of fault log from operating Send Byte
memory to EEPROM.
N
106
MFR_FAULT_LOG_CLEAR
0xEC Clear existing EEPROM fault log.
N
104
MFR_FAULT_LOG
0xEE Read fault log data.
R Block
N
Reg
104
MFR_COMMON
0xEF LTC-generic device status reporting.
R Byte
N
Reg
93
MFR_COMPARE_USER_ALL
0xF0 Compare operating memory with
EEPROM contents.
Send Byte
N
MFR_TEMPERATURE_2_PEAK
0xF4 Maximum internal temperature
measurement since last
MFR_CLEAR_PEAKS.
R Word
N
L11
MFR_PWM_CONFIG_LTC3882-1
0xF5 LTC3882-1 PWM configuration common
to both channels.
R/W Byte
N
Reg
MFR_IOUT_CAL_GAIN_TC
0xF6 Output current sense element
temperature coefficient.
R/W Word
Y
CF
MFR_TEMP_1_GAIN
0xF8 Slope for external temperature
calculations.
R/W Word
Y
CF
MFR_TEMP_1_OFFSET
0xF9 Offset addend for external temperature
calculations.
R/W Word
Y
L11
MFR_RAIL_ADDRESS
0xFA Specify unique right-justified 7-bit
address for channels comprising a
PolyPhase output.
R/W Byte
Y
Reg
MFR_RESET
0xFD Force full reset without removing power.
Send Byte
N
Send Byte
95
96
92
l
0x4F
74
0x424X(-1)
0x452X(-2)
107
105
°C
ppm/°C
°C or V
96
l
0x14
78
l
3900ppm/°C
0x0F3C
85
l
1.0
0x4000
88
l
0.0
0x8000
88
l
0x80
74
76
NVM l Indicates a command value stored to internal EEPROM using STORE_USER_ALL or restored to RAM from internal EEPROM at power-up or
execution of RESTORE_USER_ALL or MFR_RESET.
Rev. C
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43
LTC3882-1/LTC3882-2
APPLICATIONS INFORMATION
Efficiency Considerations
Normally, one of the primary goals of any LTC3882-1 application will be to obtain the highest practical conversion
efficiency. The efficiency of a switching regulator is equal
to the output power divided by the input power. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and to ascertain which change would
produce the most improvement. Balancing or limiting these
individual losses plays a dominant role in the component
selection process outlined over the next few sections.
Percent efficiency can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, et al, are the individual losses as a percentage of input power: 100 • PLn /PIN.
Although all dissipative elements in the system produce
losses, four main sources usually account for most of
the losses in LTC3882-1 applications: IC supply current,
I2R losses, topside power MOSFET transition losses and
total gate drive current.
1. The LTC3882-1 IC supply current is a DC value given
in the Electrical Characteristics table. The absolute loss
created by the IC itself is approximately this current
times the VCC supply voltage. IC supply current typically
results in a small loss (> VOUT, the top MOSFET on-resistance
MILLER EFFECT
VGS
QA
QB
QIN
CMILLER = (QB – QA)/VDS
38821 F21
Figure 21. Typical MOSFET Gate Charge Curve
CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is
not directly specified on MOSFET data sheets. CMILLER is
equal to the increase in gate charge along the horizontal
axis of Figure 21 while the curve is approximately flat,
divided by the specified change in VDS. This result is
then multiplied by the ratio of the actual application VDS
to the VDS specified on the gate charge curve. When the
controller is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
V
Main Switch Duty Cycle = OUT
VIN
V –V
Synchronous Switch Duty Cycle = IN OUT
VIN
Rev. C
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45
LTC3882-1/LTC3882-2
APPLICATIONS INFORMATION
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
PMAIN =
VOUT
2
(IMAX ) (1+δ)RDS(ON) +
VIN
VIN
2 IMAX
2
MOSFET Driver Selection
(RDR ) (CMILLER ) •
⎡
1 ⎤
1
⎢
⎥( fPWM )
+
⎢⎣ VGG – VTH(IL) VTH(IL) ⎥⎦
PSYNC =
VIN – VOUT
2
(IMAX ) (1+δ)RDS(ON)
VIN
where δ is the temperature dependency of RDS(ON), RDR
is the effective top driver resistance, VIN is the drain potential and the change in drain potential in the particular
application. VGG is the applied gate voltage, VTH(IL) is
the typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current, and
CMILLER is the capacitance calculated using the technique
previously described.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) versus temperature curve.
Typical values for δ range from 0.005/°C to 0.01/°C depending on the particular MOSFET used.
Both MOSFETs have I2R losses while the topside N-channel
losses also include transition losses, which are highest
at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while
for VIN > 20V the transition losses rapidly increase to
the point that the use of a higher RDS(ON) device with
lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
Multiple MOSFETs can be used in parallel to lower RDS(ON)
and meet the current and thermal requirements if desired.
If using discrete drivers and MOSFETs, check the stress
on the MOSFETs by independently measuring the drainto-source voltages directly across the device terminals.
Beware of inductive ringing that could exceed the maximum
46
voltage rating of the MOSFET. If this ringing cannot be
avoided and exceeds the maximum rating of the device,
choose a higher voltage rated MOSFET.
Gate driver ICs, DrMOS devices and power blocks with an
interface compatible with the LTC3882-1 3.3V three-state
PWM control output(s) can be used. An external resistor
divider may be needed to set three-state control voltage
outputs to mid-rail while in the high impedance state, depending on the driver selected. These external driver/power
circuits do not typically present a heavy capacitive load to
the LTC3882-1 PWM outputs. Suitable drivers such as the
LTC4449 are capable of driving large gate capacitances at
high transition rates. In fact, when driving MOSFETs with
very low gate charge, it is sometimes helpful to slow down
the drivers by adding small gate resistors (5Ω or less) to
reduce noise and EMI caused by fast transitions.
Using PWM Protocols
For successful utilization of the driver selected, the
appropriate LT3882-1 PWM control protocol must be
programmed. The LTC3882-1 supports two three-state
PWM control protocols. See bit 1, of the MFR_PWM_
MODE_LTC3882-1 PMBus command.
The first of these protocols (bit 1=0) is for drivers controlled
by a single 3-state input that have sufficiently short delay
to the diode emulation state (both top and bottom power
MOSFETs disabled in a fraction of a PWM cycle), such
as the LTC4449. The second protocol (bit 1=1) handles
all other 3.3V compatible drivers with a single 3-state
control input.
CIN Selection
The input bypass capacitance for an LTC3882-1 circuit
needs to have ESR low enough to keep the supply drop
low as the top MOSFETs turn on, RMS current capability
adequate to withstand the ripple current at the input, and
a capacitance value large enough to maintain the input
voltage until the input supply can make up the difference.
Generally, a capacitor that meets the first two requirements (particularly a non-ceramic type) will have far more
Rev. C
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LTC3882-1/LTC3882-2
APPLICATIONS INFORMATION
capacitance than is required to keep capacitance-based
droop under control.
The input capacitance voltage rating should be at least 1.4
times the maximum input voltage. Power loss due to ESR
occurs as I2R dissipation in the capacitor itself. The input
capacitor RMS current and its impact on any preceding
input network is reduced by PolyPhase architecture. It can
be shown that the worst case RMS current occurs when
only one controller is operating. The controller with the
highest (VOUT)(IOUT) product should be used to determine
the maximum RMS current requirement. Increasing the
output current drawn from the other out-of-phase controller will decrease the input RMS ripple current from this
maximum value. Two channel out-of-phase operation
typically reduces the input capacitor RMS ripple current
by a factor of 30% to 70%.
In continuous inductor conduction mode, the source current of the top power MOSFET is approximately a square
wave of duty cycle VOUT/VIN. The maximum RMS capacitor
current in this case is given by:
IRMS ≈IOUT(MAX)
from higher inductance, larger case size and limited surface
mount applicability; and electrolytic capacitors have higher
ESR and can dry out. Sanyo OS-CON SVP(D) series, Sanyo
POSCAP TQC series, or Panasonic EE-FT series aluminum
electrolytic capacitors can be used in parallel with a couple
of high performance ceramic capacitors as an effective
means of achieving low ESR and high bulk capacitance.
In addition to PWM bulk input capacitance, a small (0.01μF
to 1μF) bypass capacitor between the chip VINSNS pin
and ground, placed close to the LTC3882-1, is also suggested. A small resistor placed between the bulk CIN and
the VINSNS pin provides further isolation between the two
channels. However, if the time constant of any such R-C
network on the VINSNS pin exceeds 30ns, dynamic line
transient response can be adversely affected.
COUT Selection
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step transients.
The output ripple ΔVOUT is approximately bounded by:
⎛
⎞
1
ΔVOUT ≤ ΔIL ⎜ESR+
⎟
8 • f PWM •COUT ⎠
⎝
VOUT ( VIN – VOUT )
VIN
This formula has a maximum at VIN = 2VOUT, where
where ΔIL is the inductor ripple current.
IRMS = IOUT/2
This simple worst-case condition is commonly used for
design because even significant deviations do not offer
much relief.
Note that manufacturer ripple current ratings for capacitors
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
manufacturer if there is any question.
Ceramic, tantalum, semiconductor electrolyte (OS-CON),
hybrid conductive polymer (SUNCON) and switcher-rated
electrolytic capacitors can be used as input capacitors, but
each has drawbacks. Ceramics have high voltage coefficients of capacitance and may have audible piezoelectric
effects; tantalums need to be surge-rated; OS-CONs suffer
ΔIL =
VOUT ⎛ VOUT ⎞
⎜1–
⎟
L • f PWM ⎝
VIN ⎠
Since ΔIL increases with input voltage, the output ripple
voltage is highest at maximum input voltage. Typically
once the ESR requirement is satisfied, the capacitance is
adequate for filtering and has the necessary RMS current
rating.
Manufacturers such as Sanyo, Panasonic and Cornell Dubilier should be considered for high performance throughhole capacitors. The OS-CON semiconductor electrolyte
capacitor available from Sanyo has a good (ESR)(size)
product. An additional ceramic capacitor in parallel with
polarized capacitors is recommended to offset the effect
of lead inductance.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or transient current
Rev. C
For more information www.analog.com
47
LTC3882-1/LTC3882-2
APPLICATIONS INFORMATION
The LTC3882-1 is a voltage mode controller with a second,
dedicated current sharing loop to provide excellent phaseto-phase current sharing in PolyPhase applications. The
current sharing loop is internally compensated.
While Type 2 compensation for the voltage control loop
may be adequate in some applications (such as with the
use of high ESR bulk capacitors), Type 3 compensation
and ceramic capacitors are recommended for optimum
transient response.
Figure 22 shows a simplified view of the error amplifier EA
for one LTC3882-1 channel. The positive input of the error
amplifier is connected to the output of an internal 12-bit
DAC fed by a 1.024V reference, while the negative input is
connected to the FB pin and other internal circuits (not all
shown). R1 is internal to the IC with a value range given
by the RVSFB parameter in the Electrical Characteristics
table. The output is connected to COMP, from which the
PWM controller derives the required output duty cycle. To
speed up overshoot recovery time, the maximum potential
at the COMP pin is internally clamped.
Unlike many regulators that use a transconductance (gm)
amplifier, the LTC3882-1 is designed to use an inverting
summing amplifier topology with the FB pin configured
as a virtual ground. This allows feedback gain to be tightly
controlled by external components, which is not possible
with a simple gm amplifier. The voltage feedback amplifier
also provides flexibility in choosing pole and zero locations. In particular, it allows the use of Type 3 compensa-
48
C2
VOUT
C3
R1
R3
–
FB
INTERNAL
C1
R2
+
VDAC
EA
COMP
3882 F22
Figure 22. Type 3 Compensation Circuit
0
–1
GAIN
+1
–1
PHASE (DEG)
Feedback Loop Compensation
tion to provide phase boost at the LC pole frequency for
significantly improving the control loop phase margin,
as shown in Figure 23.
GAIN (dB)
handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer surface
mount capacitors offer very low ESR also but have much
lower capacitive density per unit volume. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent output capacitor choices include the Sanyo POSCAP TPD/E/F
series, the Kemet T520, T530 and A700 series, NEC/Tokin
NeoCapacitors and Panasonic SP series. Other suitable
capacitor types include Nichicon PL series and Sprague
595D series. Consult the manufacturer for other specific
recommendations.
FREQ
–90
PHASE
–180
BOOST
–270
–380
38821 F23
Figure 23. Type 3 Compensation Frequency Response
In a typical LTC3882-1 circuit, the feedback loop closed
around this control amplifier and compensation network
consists of the line feedforward circuit, the modulator,
the external inductor and the output capacitor. All these
components affect loop behavior and need to be accounted
for in the frequency compensation.
The modulator consists of the PWM generator, the output
MOSFET drivers and the external MOSFETs themselves.
Step-down modulator gain varies linearly with the input
voltage. The line feedforward circuit compensates for this
change in gain, and provides a constant gain AMOD of 4V/V
from the error amplifier output COMP to the inductor input
(average DC voltage) regardless of VIN. The combination
of the line feedforward circuit and the modulator looks
like a linear voltage transfer function from COMP to the
inductor input with a fairly benign AC behavior at typical
loop compensation frequencies. Significant phase shift
will not begin to occur in this transfer function until half
the switching frequency.
Rev. C
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LTC3882-1/LTC3882-2
APPLICATIONS INFORMATION
The external inductor/output capacitor combination makes
a more significant contribution to loop behavior. These
components cause a 2nd order amplitude roll-off that filters
the PWM waveform, resulting in the desired DC output
voltage. But the additional 180° phase shift produced by
this filter causes stability issues in the feedback loop and
must be frequency compensated. At higher frequencies,
the reactance of the output capacitor will approach its
ESR, and the roll-off due to the capacitor will stop, leaving
–20dB/decade and 90° of phase shift.
The transfer function of the Type 3 circuit shown in
Figure 22 is given by the following equation:
VCOMP
VOUT
=
–(1+ sC1R2)[1+ s(R1+ R3)C3]
sR1(C1+ C2)[1+ s(C1//C2)R2](1+ sC3R3)
The RC network across the error amplifier and the feedforward components R3 and C3 introduce two pole-zero
pairs to obtain a phase boost at the system unity-gain
(crossover) frequency, fC. In theory, the zeros and poles are
placed symmetrically around fC, and the spread between the
zeros and the poles is adjusted to give the desired phase
boost at fC. However, in practice, if the crossover frequency
is much higher than the LC double-pole frequency, this
method of frequency compensation normally generates
a phase dip within the unity bandwidth and creates some
concern regarding conditional stability.
If conditional stability is a concern, move the error amplifier zero to a lower frequency to avoid excessive phase
dip. The following equations can be used to compute the
feedback compensation component values:
1
fLC =
2π LCOUT
fESR =
choose:
1
2πRESRCOUT
fC =crossover frequency =
fPWM
10
1
2πR2C1
f
1
fZ2(RES) = C =
5 2π(R1+R3)C3
1
fP1(ERR) =fESR =
2πR2(C1//C2)
1
fP2(RES) =5fC =
2πR3C3
fZ1(ERR) =fLC =
Required error amplifier gain at frequency fC is:
⎛ f ⎞2
⎛ f ⎞2
C
≈ 40log 1+ ⎜ ⎟ – 20log 1+ ⎜ C ⎟ – 15.56
⎝ fLC ⎠
⎝ fESR ⎠
Once the value of resistor R1 (function of selected VOUT
range) and pole/zero locations have been decided, the
value of R2, C1, C2, R3 and C3 can be obtained from the
previous equations.
Compensating a switching power supply feedback loop is
a complex task. The applications shown in this data sheet
provide typical values, optimized for the power components
shown. Though similar power components should suffice,
substantially changing even one major power component
may degrade performance significantly. Stability also may
depend on circuit board layout. To verify the calculated
component values, all new circuit designs should be
prototyped and tested for stability.
The LTPowerCAD software tool can be used as a guide
through the entire power supply design process, including optimization of circuit component values according to
system requirements.
PCB Layout Considerations
To prevent magnetic and electrical field radiation or high
frequency resonant problems and to ensure correct IC
operation, proper layout of the components connected
to the LTC3882-1 is essential. Refer to Figure 24, which
also illustrates current waveforms typically present in the
circuit branches. RSENSE will be replaced with a dead short
if DCR sensing is used. For maximum efficiency, the switch
Rev. C
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49
LTC3882-1/LTC3882-2
APPLICATIONS INFORMATION
node rise and fall times should be minimized. The following
PCB design priority list will help ensure proper topology.
sensing is used, place the top resistor (R1, Figure 25)
close to the switch node.
1. Place a ground or DC voltage layer between a power
layer and a small-signal layer. Generally, power planes
should be placed on the top layer (4-layer PCB), or top
and bottom layer if more than 4 layers are used. Use
wide/short copper traces for power components and
avoid improper use of thermal relief around power
plane vias to minimize resistance and inductance.
6. Place low ESR output capacitors adjacent to the sense
resistor output and ground. Output capacitor ground
connections must feed into the same copper that connects to the input capacitor ground before connecting
back to system ground.
2. Low ESR input capacitors should be placed as close
as possible to switching FET supply and ground connections with the shortest copper traces possible. The
switching FETs must be on the same layer of copper
as the input capacitors with a common topside drain
connection at CIN. Do not attempt to split the input
decoupling for the two channels, as a large resonant
loop can result. Vias should not be used to make these
connections. Avoid blocking forced air flow to the
switching FETs with large size passive components.
3. If using a discrete FET driver, place that IC close to the
switching FET gate terminals, keeping the connecting
traces short to produce clean drive signals. This rule
also applies to driver IC supply and ground pins that
connect to the switching FET source pins. The driver
IC can be placed on the opposite side of the PCB from
the switching FETs.
4. Place the inductor input as close as possible to the
switching FETs. Minimize the surface area of the switch
node. Make the trace width the minimum needed to
support the maximum output current. Avoid copper
fills or pours. Avoid running the connection on multiple
copper layers in parallel. Minimize capacitance from
the switch node to any other trace or plane.
5. Place the output current sense resistor (if used) immediately adjacent to the inductor output. PCB traces
for remote voltage and current sense should be run
together back to the LTC3882-1 in pairs with the smallest spacing possible on any given layer on which they
are routed. Avoid high frequency switching signals
and ideally shield with ground planes. Locate any filter
component on these traces next to the LTC3882-1,
and not at the Kelvin sense location. However, if DCR
50
7. Connection of switching ground to system ground,
small-signal analog ground or any internal ground plane
should be single-point. If the system has an internal
system ground plane, a good way to do this is to cluster
vias into a single star point to make the connection. This
cluster should be located directly beneath the IC GND
paddle, which serves as both analog signal ground and
the negative sense for VOUT1. A useful CAD technique
is to make separate ground nets and use a 0Ω resistor
to connect them to system ground.
8. Place all small-signal components away from high
frequency switching nodes. Place decoupling capacitors for the LTC3882-1 immediately adjacent to the IC.
9. A good rule of thumb for via count in a given high current path is to use 0.5A per via. Be consistent when
applying this rule.
10. Copper fills or pours are good for all power connections except as noted above in rule 3. Copper planes
on multiple layers can also be used in parallel. This
helps with thermal management and lowers trace
inductance, which further improves EMI performance.
Output Current Sensing
The ISENSE+ and ISENSE– pins are high impedance inputs to
internal current comparators, the current-sharing loop and
telemetry ADC. The common mode range of the current
sense inputs is approximately 0V to 5.5V. Continuous linear
operation is provided throughout this range. Maximum
differential current sense input (ISENSE+ – ISENSE–) is 70mV,
including any variation over temperature. These inputs
must be properly connected in the application at all times.
To maximize efficiency at full load the LTC3882-1 is designed
to sense current through the inductor’s DCR, as shown in
Figure 25. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
Rev. C
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LTC3882-1/LTC3882-2
APPLICATIONS INFORMATION
SW1
L1
RSENSE1
D1
VOUT1
COUT1
RL1
VIN
RIN
CIN
SW0
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
L0
RSENSE0
D0
VOUT0
COUT0
RL0
38821 F24
Figure 24. High Frequency Paths and Branch Current Waveforms
for most inductors suitable to LTC3882-1 applications, is
between 0.3mΩ and 1mΩ. If the filter RC time constant is
chosen to be exactly equal to the L/DCR time constant of
the inductor, the voltage drop across the external capacitor is equal to the voltage drop across the inductor DCR.
Check the manufacturer’s data sheet for specifications
regarding the inductor DCR in order to properly dimension
the external filter components. The DCR of the inductor
can also be measured using a good RLC meter.
Use the nominal or measured value of DCR to program
IOUT_CAL_GAIN (in mΩ). The temperature coefficient
of the inductor’s DCR is typically high, like copper. Again,
consult the manufacturer’s data sheet. The LTC3882-1 can
adjust for this non-ideality if the correct MFR_IOUT_CAL_
GAIN_TC value is programmed. Typically this coefficient
is around 3900ppm/°C.
Resistor R1 should be placed close to the switch node,
to prevent noise from coupling into sensitive small-signal
nodes. Capacitor C1 should be placed close to the IC pins.
An example of discrete resistor sensing of output current is
shown in Figure 26. Previously, the parasitic inductance of
the sense resistor could represent a relatively small error.
New high current density solutions may utilize low sense
resistor values producing sense voltages less than 20mV.
In addition, inductor ripple currents greater than 50%
with operation up to 1MHz are becoming more common.
Under these conditions, the voltage drop across the sense
resistor’s parasitic inductance is no longer negligible. An
RC filter can be used to extract the resistive component
of the current sense signal in the presence of parasitic
inductance. For example, Figure 27 illustrates the voltage
Rev. C
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51
LTC3882-1/LTC3882-2
APPLICATIONS INFORMATION
waveform across a 2mΩ resistor with a 2010 footprint.
The waveform is the superposition of a purely resistive
component and a purely inductive component. If the
RC time constant is chosen to be close to the parasitic
inductance divided by the sense resistor (L/R), the resultant waveform looks resistive, as shown in Figure 28.
If low value (