LTC3890
60V Low IQ, Dual, 2-Phase
Synchronous Step-Down
DC/DC Controller
DESCRIPTION
FEATURES
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Wide VIN Range: 4V to 60V (65V Abs Max)
Low Operating IQ: 50µA (One Channel On)
Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 24V
RSENSE or DCR Current Sensing
Out-of-Phase Controllers Reduce Required Input
Capacitance and Power Supply Induced Noise
Phase-Lockable Frequency (75kHz to 850kHz)
Programmable Fixed Frequency (50kHz to 900kHz)
Selectable Continuous, Pulse-Skipping or Low Ripple
Burst Mode® Operation at Light Loads
Selectable Current Limit
Very Low Dropout Operation: 99% Duty Cycle
Adjustable Output Voltage Soft-Start or Tracking
Power Good Output Voltage Monitors
Output Overvoltage Protection
Low Shutdown IQ : < 14µA
Internal LDO Powers Gate Drive from VIN or EXTVCC
No Current Foldback During Start-Up
Small Low Profile (0.75mm) 5mm × 5mm QFN Package
The LTC®3890 is a high performance dual step-down
switching regulator DC/DC controller that drives all
N-channel synchronous power MOSFET stages. A constant
frequency current mode architecture allows a phaselockable frequency of up to 850kHz. Power loss and noise
due to the ESR of the input capacitor are minimized by
operating the two controller output stages out-of-phase.
The 50μA no-load quiescent current extends operating run
time in battery-powered systems. OPTI-LOOP® compensation allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
LTC3890 features a precision 0.8V reference and power
good output indicators. A wide 4V to 60V input supply
range encompasses a wide range of intermediate bus
voltages and battery chemistries.
Independent TRACK/SS pins for each controller ramp the
output voltages during start-up. Current foldback limits
MOSFET heat dissipation during short-circuit conditions.
The PLLIN/MODE pin selects among Burst Mode operation,
pulse-skipping mode, or continuous conduction mode at
light loads. For a leaded package version (28-lead Narrow
SSOP), see the LTC3890-1 data sheet.
APPLICATIONS
Automotive Always-On Systems
Battery Operated Digital Devices
n Distributed DC Power Systems
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L, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by U.S.
Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258,
7230497.
TYPICAL APPLICATION
High Efficiency Dual 8.5V/3.3V Output Step-Down Converter
22µF
4.7µF
0.1µF
INTVCC
SW1
BG1
TG2
BOOST2
0.1µF
8µH
SW2
LTC3890
BG2
PGND
SENSE1+
SENSE2+
SENSE1–
VFB1
ITH1
SENSE2–
VFB2
ITH2
0.01Ω
0.008Ω
VOUT1
3.3V
5A
100k
470µF
1000pF
31.6k
34.8k
TRACK/SS1 SGND TRACK/SS2
0.1µF
0.1µF
100k
1000pF
34.8k
10.5k
10000
80
1000
70
100
60
50
10
40
30
20
VOUT2
8.5V
3A
330µF
POWER LOSS (mW)
BOOST1
100
VIN = 12V
90 VOUT = 3.3V
EFFICIENCY (%)
TG1
4.7µH
VIN
Efficiency and Power Loss
vs Output Current
VIN
9V TO 60V
1
10
0
0.0001
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
0.1
10
3890 TA01b
3890 TA01a
3890fc
1
LTC3890
PIN CONFIGURATION
Input Supply Voltage (VIN).......................... –0.3V to 65V
Topside Driver Voltages
BOOST1, BOOST2 ..................................–0.3V to 71V
Switch Voltage (SW1, SW2) .......................... –5V to 65V
(BOOST1-SW1), (BOOST2-SW2) ................. –0.3V to 6V
RUN1, RUN2 ................................................ –0.3V to 8V
Maximum Current Sourced into Pin from
Source > 8V ......................................................100µA
SENSE1+, SENSE2+, SENSE1–
SENSE2– Voltages...................................... –0.3V to 28V
PLLIN/MODE, INTVCC Voltages.................... –0.3V to 6V
FREQ Voltage......................................... –0.3V to INTVCC
ILIM, PHASMD Voltages ........................ –0.3V to INTVCC
EXTVCC ...................................................... –0.3V to 14V
ITH1, ITH2, VFB1, VFB2 Voltages.................... –0.3V to 6V
PGOOD1, PGOOD2 Voltages ........................ –0.3V to 6V
TRACK/SS1, TRACK/SS2 Voltages .............. –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 3)
LTC3890E, LTC3890I.......................... –40°C to 125°C
LTC3890H........................................... –40°C to 150°C
LTC3890MP........................................ –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
SW1
TG1
PGOOD1
ILIM
TRACK/SS1
ITH1
VFB1
SENSE1+
TOP VIEW
32 31 30 29 28 27 26 25
SENSE1– 1
24 BOOST1
FREQ 2
23 BG1
PHASMD 3
22 VIN
CLKOUT 4
21 PGND
33
SGND
PLLIN/MODE 5
20 EXTVCC
SGND 6
19 INTVCC
RUN1 7
18 BG2
17 BOOST2
RUN2 8
SW2
TG2
PGOOD2
ITH2
TRACK/SS2
SENSE2–
9 10 11 12 13 14 15 16
VFB2
(Note 1)
SENSE2+
ABSOLUTE MAXIMUM RATINGS
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 150°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3890EUH#PBF
LTC3890EUH#TRPBF
3890
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3890IUH#PBF
LTC3890IUH#TRPBF
3890
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
LTC3890HUH#PBF
LTC3890HUH#TRPBF
3890
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 150°C
LTC3890MPUH#PBF
LTC3890MPUH#TRPBF
3890
32-Lead (5mm × 5mm) Plastic QFN
–55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN1,2 = 5V, EXTVCC = 0V unless otherwise noted.
(Note 2)
SYMBOL
PARAMETER
VIN
Input Supply Operating Voltage Range
VFB1,2
Regulated Feedback Voltage
CONDITIONS
MIN
TYP
4
(Note 4) ITH1,2 Voltage = 1.2V
–40°C to 85°C, All Grades
LTC3890E, LTC3890I
LTC3890H, LTC3890MP
l
l
0.792
0.788
0.786
0.800
0.800
0.800
MAX
UNITS
60
V
0.808
0.812
0.812
V
V
V
3890fc
2
LTC3890
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN1,2 = 5V, EXTVCC = 0V unless otherwise noted.
(Note 2)
SYMBOL
PARAMETER
CONDITIONS
IFB1,2
Feedback Current
(Note 4)
VREFLNREG
Reference Voltage Line Regulation
(Note 4) VIN = 4.5V to 60V
VLOADREG
Output Voltage Load Regulation
(Note 4)
Measured in Servo Loop,
∆ITH Voltage = 1.2V to 0.7V
(Note 4)
Measured in Servo Loop,
∆ITH Voltage = 1.2V to 2V
gm1,2
Transconductance Amplifier gm
(Note 4) ITH1,2 = 1.2V, Sink/Source = 5µA
IQ
Input DC Supply Current
(Note 5)
Pulse-Skipping or Forced Continuous
Mode (One Channel On)
RUN1 = 5V and RUN2 = 0V, VFB1 = 0.83V or
RUN1 = 0V and RUN2 = 5V, VFB2 = 0.83V
Pulse-Skipping or Forced Continuous
Mode (Both Channels On)
UVLO
TYP
MAX
UNITS
±5
±50
nA
0.002
0.02
%/V
l
0.01
0.1
%
l
–0.01
–0.1
%
2
mmho
1.3
mA
RUN1,2 = 5V, VFB1,2 = 0.83V (No Load)
2
mA
Sleep Mode (One Channel On)
RUN1 = 5V and RUN2 = 0V, VFB1 = 0.83V (No Load) or
RUN1 = 0V and RUN2 = 5V, VFB2 = 0.83V (No Load)
50
75
µA
Sleep Mode (Both Channels On)
RUN1,2 = 5V, VFB1,2 = 0.83V (No Load)
60
100
µA
Shutdown
RUN1,2 = 0V
14
25
µA
Undervoltage Lockout
INTVCC Ramping Up
INTVCC Ramping Down
3.6
3.92
3.80
4.2
4.0
V
V
7
10
Feedback Overvoltage Protection
Measured at VFB1,2, Relative to Regulated VFB1,2
ISENSE+
SENSE+ Pin Current
Each Channel
ISENSE–
SENSE– Pins Current
Each Channel
VSENSE– < INTVCC – 0.5V
VSENSE– > INTVCC + 0.5V
Maximum TG1, 2 Duty Factor
ITRACK/SS1,2 Soft-Start Charge Current
VRUN1
VRUN2
MIN
RUN1 Pin On Threshold
RUN2 Pin On Threshold
l
l
700
%
µA
±1
µA
µA
In Dropout
98
99
VTRACK/SS1,2 = 0V
0.7
1.0
1.4
µA
1.27
1.30
V
V
VRUN1 Rising
VRUN2 Rising
l
l
1.15
1.20
1.21
1.25
VFB1,2 = 0.7V, VSENSE1–,2– = 3.3V, ILIM = 0
VFB1,2 = 0.7V, VSENSE1–,2– = 3.3V, ILIM = INTVCC
VFB1,2 = 0.7V, VSENSE1–,2– = 3.3V, ILIM = FLOAT
l
l
l
22
43
64
30
50
75
RUN1,2 Pin Hysteresis
VSENSE(MAX) Maximum Current Sense Threshold
13
±1
%
50
mV
36
57
85
mV
mV
mV
Gate Driver
TG1,2 Pull-Up On-Resistance
TG1,2 Pull-Down On-Resistance
2.5
1.5
Ω
Ω
BG1,2 Pull-Up On-Resistance
BG1,2 Pull-Down On-Resistance
2.4
1.1
Ω
Ω
TG1,2 tr
TG1,2 tf
TG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
16
ns
ns
BG1,2 tr
BG1,2 tf
BG Transition Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
28
13
ns
ns
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver
30
ns
TG/BG t1D
3890fc
3
LTC3890
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN1,2 = 5V, EXTVCC = 0V unless otherwise noted.
(Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
BG/TG t1D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver
30
ns
tON(MIN)
Minimum On-Time
(Note 7)
95
ns
INTVCC Linear Regulator
VINTVCCVIN
Internal VCC Voltage
6V < VIN < 60V, VEXTVCC = 0V
VLDOVIN
INTVCC Load Regulation
ICC = 0mA to 50mA, VEXTVCC = 0V
VINTVCCEXT
Internal VCC Voltage
6V < VEXTVCC < 13V
VLDOEXT
INTVCC Load Regulation
ICC = 0mA to 50mA, VEXTVCC = 8.5V
VEXTVCC
EXTVCC Switchover Voltage
EXTVCC Ramping Positive
VLDOHYS
EXTVCC Hysteresis
4.85
4.85
4.5
5.1
5.35
V
0.7
1.1
%
5.1
5.35
V
0.6
1.1
%
4.7
4.9
V
250
mV
105
kHz
Oscillator and Phase-Locked Loop
f25kΩ
Programmable Frequency
RFREQ = 25k, PLLIN/MODE = DC Voltage
f65kΩ
Programmable Frequency
RFREQ = 65k, PLLIN/MODE = DC Voltage
f105kΩ
Programmable Frequency
RFREQ = 105k, PLLIN/MODE = DC Voltage
fLOW
Low Fixed Frequency
VFREQ = 0V, PLLIN/MODE = DC Voltage
fHIGH
High Fixed Frequency
VFREQ = INTVCC, PLLIN/MODE = DC Voltage
fSYNC
Synchronizable Frequency
PLLIN/MODE = External Clock
375
440
505
835
l
kHz
kHz
320
350
380
kHz
485
535
585
kHz
850
kHz
75
PGOOD1 and PGOOD2 Outputs
VPGL
PGOOD Voltage Low
IPGOOD = 2mA
IPGOOD
PGOOD Leakage Current
VPGOOD = 5V
VPG
PGOOD Trip Level
VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
Hysteresis
–13
VFB with Respect to Set Regulated Voltage
VFB Ramping Positive
Hysteresis
7
tPG
Delay for Reporting a Fault
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Ratings for extended periods may affect device reliability and
lifetime.
Note 2: The LTC3890 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3890E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3890I is guaranteed
over the –40°C to 125°C operating junction temperature range, the
LTC3890H is guaranteed over the –40°C to 150°C operating junction
temperature range and the LTC3890MP is tested and guaranteed over the
–55°C to 150°C operating junction temperature range.
High junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
0.2
0.4
V
±1
µA
–10
2.5
–7
%
%
10
2.5
13
%
%
25
µs
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • 34°C/W)
Note 4: The LTC3890 is tested in a feedback loop that servos VITH1,2 to
a specified voltage and measures the resultant VFB. The specification at
85°C is not tested in production and is assured by design, characterization
and correlation to production testing at other temperatures (125°C for
the LTC3890E/LTC3890I, 150°C for the LTC3890H/LTC3890MP). For the
LTC3890MP, the specification at –40°C is not tested in production and is
assured by design, characterization and correlation to production testing
at –55°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥ 40% of IMAX (See Minimum On-Time
Considerations in the Applications Information section).
3890fc
4
LTC3890
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current
VIN = 12V
90 VOUT = 3.3V
Efficiency vs Output Current
BURST EFFICIENCY
90
1000
CCM LOSS
100
60
40
BURST LOSS
PULSE-SKIPPING
LOSS
10
30
CCM EFFICIENCY
20
PULSE-SKIPPING
EFFICIENCY
10
0
0.0001
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
FIGURE 13 CIRCUIT
EFFICIENCY (%)
70
VOUT = 8.5V
50
40
30
FIGURE 13 CIRCUIT
Load Step
Burst Mode Operation
94
92
90
86
82
10
80
Load Step
Pulse-Skipping Mode
VOUT
100mV/DIV
ACCOUPLED
IL
2A/DIV
IL
2A/DIV
IL
2A/DIV
VIN = 12V
VOUT = 3.3V
FIGURE 13 CIRCUIT
Inductor Current at Light Load
FORCED
CONTINUOUS
MODE
0
5 10 15 20 25 30 35 40 45 50 55 60
INPUT VOLTAGE (V)
3890 G05
50µs/DIV
VIN = 12V
VOUT = 3.3V
FIGURE 13 CIRCUIT
Soft Start-Up
Tracking Start-Up
VOUT2
2V/DIV
3890 G06
50µs/DIV
VIN = 12V
VOUT = 3.3V
FIGURE 13 CIRCUIT
Burst Mode
OPERATION
1A/DIV
3890 G03
Load Step
Forced Continuous Mode
VOUT
100mV/DIV
ACCOUPLED
3890 G04
ILOAD = 2A
FIGURE 13 CIRCUIT
3890 G02
VOUT
100mV/DIV
ACCOUPLED
50µs/DIV
VOUT1 = 3.3V
88
84
Burst Mode OPERATION
VIN = 12V
0
0.0001 0.001
0.01
0.1
1
OUTPUT CURRENT (A)
3890 G01
VOUT2 = 8.5V
96
60
10
0.1
10
98
VOUT = 3.3V
70
20
1
Efficiency vs Input Voltage
100
80
POWER LOSS (mW)
EFFICIENCY (%)
80
50
100
10000
EFFICIENCY (%)
100
VOUT2
2V/DIV
VOUT1
2V/DIV
VOUT1
2V/DIV
PULSE-SKIPPING
MODE
5µs/DIV
VIN = 12V
VOUT = 3.3V
ILOAD = 200µA
3890 G07
2ms/DIV
FIGURE 13 CIRCUIT
3890 G08
2ms/DIV
FIGURE 13 CIRCUIT
3890 G09
3890fc
5
LTC3890
TYPICAL PERFORMANCE CHARACTERISTICS
Total Input Supply Current
vs Input Voltage
VOUT = 3.3V
FIGURE 13 CIRCUIT
200
300µA LOAD
150
100
NO LOAD
50
0
5.5
5.8
EXTVCC AND INTVCC VOLTAGE (V)
SUPPLY CURRENT (µA)
250
5.6
5.0
5.4
INTVCC
5.2
5.0
EXTVCC RISING
4.8
EXTVCC FALLING
4.6
4.4
20
ILIM = GND
ILIM = INTVCC
500
400
300
200
100
ILIM = FLOAT
0
FORCED CONTINUOUS MODE
0
0.2
0.4
0.6 0.8
VITH (V)
1.0
1.2
1.4
–100
0
5
25
20
VSENSE COMMON MODE VOLTAGE (V)
3890 G13
75
QUIESCENT CURRENT (µA)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
ILIM = FLOAT
60
ILIM = INTVCC
50
40
30
ILIM = GND
20
10
0
100 200 300 400 500 600
FEEDBACK VOLTAGE (MV)
700 800
3890 G16
ILIM = FLOAT
60
ILIM = INTVCC
50
40
ILIM = GND
30
20
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3890 G15
INTVCC vs Load Current
5.50
VIN = 12V
65
60
55
50
45
40
30
–75 –50 –25
VIN = 12V
5.25
70
EXTVCC = 0V
5.00
EXTVCC = 8.5V
4.75
EXTVCC = 5V
4.50
4.25
35
0
70
Quiescent Current vs Temperature
80
70
15
80
3890 G14
Foldback Current Limit
80
10
INTVCC VOLTAGE (V)
–20
–40
MAXIMUM CURRENT SENSE VOLTAGE (mV)
600
SENSE– CURRENT (µA)
CURRENT SENSE THESHOLD (mV)
700
60
Burst Mode
OPERATION
0 5 10 15 20 25 30 35 40 45 50 55 60 65
INPUT VOLTAGE (V)
Maximum Current Sense
Threshold vs Duty Cycle
800
PULSE-SKIPPING MODE
ILOAD = 10mA
3890 G12
SENSE– Pin Input Bias Current
5% DUTY CYCLE
0
3.0
0 25 50 75 100 125 150
TEMPERATURE (°C)
3890 G11
Maximum Current Sense Voltage
vs ITH Voltage
40
4.0
3.5
4.0
–75 –50 –25
5 10 15 20 25 30 35 40 45 50 55 60 65
INPUT VOLTAGE (V)
4.5
4.2
3890 G10
80
INTVCC Line Regulation
6.0
INTVCC VOLTAGE (V)
300
EXTVCC Switchover and INTVCC
Voltages vs Temperature
0 25 50 75 100 125 150
TEMPERATURE (°C)
3890 G17
4.00
0
20
60
80
40
LOAD CURRENT (mA)
100
3890 G18
3890fc
6
LTC3890
TYPICAL PERFORMANCE CHARACTERISTICS
TRACK/SS Pull-Up Current
vs Temperature
Regulated Feedback Voltage
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
808
1.05
RUN PIN VOLTAGE (V)
TRACK/SS CURRENT (µA)
1.35
1.00
0.95
1.30
RUN1 RISING
RUN2 RISING
1.25
1.20
1.15
RUN1 FALLING
1.10
RUN2 FALLING
1.05
0.90
–75 –50 –25
1.00
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
300
200
100
VOUT < INTVCC – 0.5V
0
–100
–75 –50 –25
25
550
20
500
15
10
356
3.7
3.6
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3890 G25
400
FREQ = GND
350
300
–75 –50 –25
5 10 15 20 25 30 35 40 45 50 55 60 65
INPUT VOLTAGE (V)
Shutdown Current vs Temperature
22
FREQ = GND
VIN = 12V
20
354
352
350
348
346
344
0 25 50 75 100 125 150
TEMPERATURE (°C)
3890 G24
SHUTDOWN CURRENT (µA)
OSCILLATOR FREQUENCY (kHz)
INTVCC VOLTAGE (V)
3.8
450
Oscillator Frequency
vs Input Voltage
4.2
FALLING
0 25 50 75 100 125 150
TEMPERATURE (°C)
FREQ = INTVCC
3890 G23
Undervoltage Lockout Threshold
vs Temperature
RISING
794
600
3890 G22
3.9
796
30
0
0 25 50 75 100 125 150
TEMPERATURE (°C)
4.0
798
Oscillator Frequency
vs Temperature
5
4.1
800
3890 G21
FREQUENCY (kHz)
SENSE– CURRENT (µA)
SHUTDOWN CURRENT (µA)
VOUT > INTVCC + 0.5V
400
802
Shutdown Current
vs Input Voltage
800
500
804
3890 G20
SENSE– Pin Total Input Bias Current
vs Temperature
600
806
792
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3890 G19
700
REGULATED FEEDBACK VOLTAGE (mV)
1.40
1.10
18
16
14
12
10
5 10 15 20 25 30 35 40 45 50 55 60 65
INPUT VOLTAGE (V)
3890 G26
8
–75 –50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
3890 G27
3890fc
7
LTC3890
PIN FUNCTIONS
SENSE1–, SENSE2– (Pin 1, Pin 9): The (–) Input to the
Differential Current Comparators. When greater than
INTVCC – 0.5V, the SENSE– pin supplies current to the
current comparator.
FREQ (Pin 2): The frequency control pin for the internal
VCO. Connecting the pin to GND forces the VCO to a fixed
low frequency of 350kHz. Connecting the pin to INTVCC
forces the VCO to a fixed high frequency of 535kHz.
Other frequencies between 50kHz and 900kHz can be
programmed using a resistor between FREQ and GND.
An internal 20µA pull-up current develops the voltage to
be used by the VCO to control the frequency.
PHASMD (Pin 3): Control Input to Phase Selector which
determines the phase relationships between controller 1, controller 2 and the CLKOUT signal. Pulling this
pin to ground forces TG2 and CLKOUT to be out of phase
180° and 60° with respect to TG1. Connecting this pin to
INTVCC forces TG2 and CLKOUT to be out of phase 240°
and 120° with respect to TG1. Floating this pin forces TG2
and CLKOUT to be out of phase 180° and 90° with respect
to TG1. Refer to Table 1.
CLKOUT (Pin 4): Output clock signal available to daisychain other controller ICs for additional MOSFET driver
stages/phases. The output levels swing from INTVCC to
ground.
PLLIN/MODE (Pin 5): External Synchronization Input to
Phase Detector and Forced Continuous Mode Input. When
an external clock is applied to this pin, the phase-locked
loop will force the rising TG1 signal to be synchronized
with the rising edge of the external clock. When not synchronizing to an external clock, this input, which acts on
both controllers, determines how the LTC3890 operates at
light loads. Pulling this pin to ground selects Burst Mode
operation. An internal 100k resistor to ground also invokes
Burst Mode operation when the pin is floated. Tying this pin
to INTVCC forces continuous inductor current operation.
Tying this pin to a voltage greater than 1.2V and less than
INTVCC – 1.3V selects pulse-skipping operation.
SGND (Pins 6, Exposed Pad Pin 33): Small-signal ground
common to both controllers, must be routed separately
from high current grounds to the common (–) terminals
of the CIN capacitors. The exposed pad must be soldered
to PCB ground for rated thermal performance.
RUN1, RUN2 (Pin 7, Pin 8): Digital Run Control Inputs
for Each Controller. Forcing RUN1 below 1.16V or RUN2
below 1.20V shuts down that controller. Forcing both of
these pins below 0.7V shuts down the entire LTC3890,
reducing quiescent current to approximately 14µA.
INTVCC (Pin 19): Output of the Internal Linear Low Dropout
Regulator. The driver and control circuits are powered from
this voltage source. Must be decoupled to power ground
with a minimum of 4.7µF ceramic or other low ESR capacitor. Do not use the INTVCC pin for any other purpose.
EXTVCC (Pin 20): External Power Input to an Internal LDO
Connected to INTVCC. This LDO supplies INTVCC power,
bypassing the internal LDO powered from VIN whenever
EXTVCC is higher than 4.7V. See EXTVCC Connection in the
Applications Information section. Do not float or exceed
14V on this pin.
PGND (Pin 21): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs
and the (–) terminal(s) of CIN.
VIN (Pin 22): Main Supply Pin. A bypass capacitor should
be tied between this pin and the signal ground pin.
BG1, BG2 (Pin 23, Pin 18): High Current Gate Drives
for Bottom (Synchronous) N-Channel MOSFETs. Voltage
swing at these pins is from ground to INTVCC.
BOOST1, BOOST2 (Pin 24, Pin 17): Bootstrapped Supplies
to the Topside Floating Drivers. Capacitors are connected
between the BOOST and SW pins and Schottky diodes are
tied between the BOOST and INTVCC pins. Voltage swing
at the BOOST pins is from INTVCC to (VIN + INTVCC).
SW1, SW2 (Pin 25, Pin 16): Switch Node Connections
to Inductors.
3890fc
8
LTC3890
PIN FUNCTIONS
TG1, TG2 (Pin 26, Pin 15): High Current Gate Drives for
Top N-Channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to INTVCC – 0.5V
superimposed on the switch node voltage SW.
PGOOD1, PGOOD2 (Pin 27, Pin 14): Open-Drain Logic
Output. PGOOD1,2 is pulled to ground when the voltage
on the VFB1,2 pin is not within ±10% of its set point.
ILIM (Pin 28): Current Comparator Sense Voltage Range
Inputs. Tying this pin to SGND, FLOAT or INTVCC sets the
maximum current sense threshold to one of three different
levels for both comparators.
TRACK/SS1, TRACK/SS2 (Pin 29, Pin 13): External
Tracking and Soft-Start Input. The LTC3890 regulates the
VFB1,2 voltage to the smaller of 0.8V or the voltage on the
TRACK/SS1,2 pin. An internal 1µA pull-up current source
is connected to this pin. A capacitor to ground at this
pin sets the ramp time to final regulated output voltage.
Alternatively, a resistor divider on another voltage supply
connected to this pin allows the LTC3890 output to track
the other supply during start-up.
ITH1, ITH2 (Pin 30, Pin 12): Error Amplifier Outputs and
Switching Regulator Compensation Points. Each associated channel’s current comparator trip point increases
with this control voltage.
VFB1, VFB2 (Pin 31, Pin 11): Receives the remotely sensed
feedback voltage for each controller from an external
resistive divider across the output.
SENSE1+, SENSE2+ (Pin 32, Pin 10): The (+) input to the
differential current comparators are normally connected
to DCR sensing networks or current sensing resistors.
The ITH pin voltage and controlled offsets between the
SENSE– and SENSE+ pins in conjunction with RSENSE set
the current trip threshold.
3890fc
9
LTC3890
FUNCTIONAL DIAGRAM
VIN
INTVCC
PGOOD1
27
0.88V
PHASMD
CLKOUT
3
4
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
VFB1
DROP
OUT
DET
+
–
+
–
+
PGOOD2
14
0.72V
0.88V
VFB2
S
Q
R
Q
–
BOT
SWITCH
LOGIC BOT
SHDN
INTVCC
0.72V
–
VCO
CLK2
0.425V
+
ICMP
PFD
+
SYNC
DET
+
–+
+–
–
SLOPE COMP
VFB
31, 11
+
EA
VIN
–
22
–
20
7µA (RUN1)
0.5µA (RUN2) SHDN
RST
2(VFB)
11V
–
33 SGND
19 INTVCC
0.80V
TRACK/SS
+
OV
EXTVCC
5.1V
LDO
EN
RSENSE
SENSE–
1, 9
CURRENT
LIMIT
+
VOUT
SENSE+
32, 10
2.7V
0.65V
100k
4.7V
COUT
IR
5
LDO
EN
BG
23, 18
L
3mV
5.1V
CIN
SLEEP
–
–
CLP
28
CB
21
CLK1
ILIM
TG
26, 15
PGND
2
PLLIN/MODE
DB
SW
25, 16
TOP ON
+
20µA
FREQ
TOP
BOOST
24, 17
FOLDBACK
RA
ITH
30, 12
0.88V
1µA
RB
TRACK/SS
29, 13
CC
CC2
RC
CSS
SHDN
RUN
7, 8
3890 FD
3890fc
10
LTC3890
OPERATION (Refer to the Functional Diagram)
Main Control Loop
The LTC3890 uses a constant frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out-of-phase. During normal operation, each external top MOSFET is turned on when the
clock for that channel sets the RS latch, and is turned off
when the main current comparator, ICMP, resets the RS
latch. The peak inductor current at which ICMP trips and
resets the latch is controlled by the voltage on the ITH pin,
which is the output of the error amplifier, EA. The error
amplifier compares the output voltage feedback signal at
the VFB pin, (which is generated with an external resistor
divider connected across the output voltage, VOUT , to
ground) to the internal 0.800V reference voltage. When the
load current increases, it causes a slight decrease in VFB
relative to the reference, which causes the EA to increase
the ITH voltage until the average inductor current matches
the new load current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is tied to a voltage less than 4.7V,
the VIN LDO (low dropout linear regulator) supplies 5.1V
from VIN to INTVCC. If EXTVCC is taken above 4.7V, the VIN
LDO is turned off and an EXTVCC LDO is turned on. Once
enabled, the EXTVCC LDO supplies 5.1V from EXTVCC to
INTVCC. Using the EXTVCC pin allows the INTVCC power
to be derived from a high efficiency external source such
as one of the LTC3890 switching regulator outputs.
Each top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each
cycle through an external diode when the top MOSFET
turns off. If the input voltage, VIN, decreases to a voltage
close to VOUT , the loop may enter dropout and attempt
to turn on the top MOSFET continuously. The dropout
detector detects this and forces the top MOSFET off for
about one twelfth of the clock period every tenth cycle to
allow CB to recharge.
Shutdown and Start-Up (RUN1, RUN2 and
TRACK/ SS1, TRACK/SS2 Pins)
The two channels of the LTC3890 can be independently
shut down using the RUN1 and RUN2 pins. Pulling either of
these pins below 1.15V shuts down the main control loop
for that controller. Pulling both pins below 0.7V disables
both controllers and most internal circuits, including the
INTVCC LDOs. In this state, the LTC3890 draws only 14µA
of quiescent current.
Releasing either RUN pin allows a small internal current to
pull up the pin to enable that controller. The RUN1 pin has
a 7µA pull-up current while the RUN2 pin has a smaller
0.5µA. The 7µA current on RUN1 is designed to be large
enough so that the RUN1 pin can be safely floated (to
always enable the controller) without worry of condensation or other small board leakage pulling the pin down.
This is ideal for always-on applications where one or both
controllers are enabled continuously and never shut down.
The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low impedance
source, do not exceed the absolute maximum rating of
8V. The RUN pin has an internal 11V voltage clamp that
allows the RUN pin to be connected through a resistor to a
higher voltage (for example, VIN), so long as the maximum
current into the RUN pin does not exceed 100µA.
The start-up of each controller’s output voltage VOUT is
controlled by the voltage on the TRACK/SS pin for that
channel. When the voltage on the TRACK/SS pin is less
than the 0.8V internal reference, the LTC3890 regulates
the VFB voltage to the TRACK/SS pin voltage instead of the
0.8V reference. This allows the TRACK/SS pin to be used
to program a soft-start by connecting an external capacitor
from the TRACK/SS pin to SGND. An internal 1µA pull-up
current charges this capacitor creating a voltage ramp on
the TRACK/SS pin. As the TRACK/SS voltage rises linearly
from 0V to 0.8V (and beyond up to 5V), the output voltage
VOUT rises smoothly from zero to its final value.
Alternatively the TRACK/SS pin can be used to cause the
start-up of VOUT to track that of another supply. Typically,
this requires connecting to the TRACK/SS pin an external
resistor divider from the other supply to ground (see the
Applications Information section).
3890fc
11
LTC3890
OPERATION (Refer to the Functional Diagram)
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode)
(PLLIN/MODE Pin)
The LTC3890 can be enabled to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode,
or forced continuous conduction mode at low load currents.
To select Burst Mode operation, tie the PLLIN/ MODE pin
to a DC voltage below 0.8V (e.g., SGND). To select forced
continuous operation, tie the PLLIN/MODE pin to INTVCC.
To select pulse-skipping mode, tie the PLLIN/MODE pin to
a DC voltage greater than 1.2V and less than INTVCC – 1.3V.
When a controller is enabled for Burst Mode operation, the
minimum peak current in the inductor is set to approximately 25% of the maximum sense voltage even though
the voltage on the ITH pin indicates a lower value. If the
average inductor current is higher than the load current,
the error amplifier, EA, will decrease the voltage on the
ITH pin. When the ITH voltage drops below 0.425V, the
internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3890 draws.
If one channel is shut down and the other channel is in
sleep mode, the LTC3890 draws only 50µA of quiescent
current. If both channels are in sleep mode, the LTC3890
draws only 60µA of quiescent current. In sleep mode,
the load current is supplied by the output capacitor. As
the output voltage decreases, the EA’s output begins to
rise. When the output voltage drops enough, the ITH pin
is reconnected to the output of the EA, the sleep signal
goes low, and the controller resumes normal operation
by turning on the top external MOSFET on the next cycle
of the internal oscillator.
When a controller is enabled for Burst Mode operation, the
inductor current is not allowed to reverse. The reverse current comparator, IR, turns off the bottom external MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous operation.
In forced continuous operation or clocked by an external
clock source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop section), the inductor current is allowed to reverse at light loads or under
large transient conditions. The peak inductor current is
determined by the voltage on the ITH pin, just as in normal
operation. In this mode, the efficiency at light loads is lower
than in Burst Mode operation. However, continuous operation has the advantage of lower output voltage ripple and
less interference to audio circuitry. In forced continuous
mode, the output ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3890 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator, ICMP, may remain tripped for several
cycles and force the external top MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3890’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTVCC or programmed through an external resistor. Tying
FREQ to SGND selects 350kHz while tying FREQ to INTVCC
selects 535kHz. Placing a resistor between FREQ and SGND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 10.
3890fc
12
LTC3890
OPERATION (Refer to the Functional Diagram)
A phase-locked loop (PLL) is available on the LTC3890
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3890’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of controller 1’s external top MOSFET to the rising edge of the synchronizing signal. Thus, the turn-on
of controller 2’s external top MOSFET is 180 degrees out
of phase to the rising edge of the external clock source.
The VCO input voltage is prebiased to the operating frequency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the phase-locked loop is from
approximately 55kHz to 1MHz, with a guarantee to be
between 75kHz and 850kHz. In other words, the LTC3890’s
PLL is guaranteed to lock to an external clock source whose
frequency is between 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.1V (falling).
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3890 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with
the LTC3890 in PolyPhase applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal as well as the relative phases
between the two internal controllers, as summarized in
Table 1. The phases are calculated relative to the zero
degrees phase being defined as the rising edge of the top
gate driver output of controller 1 (TG1).
Table 1
VPHASMD
CONTROLLER 2 PHASE
CLKOUT PHASE
GND
180°
60°
Floating
180°
90°
INTVCC
240°
120°
Output Overvoltage Protection
An overvoltage comparator guards against transient overshoots as well as other more serious conditions that may
overvoltage the output. When the VFB pin rises by more
than 10% above its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good (PGOOD1 and PGOOD2) Pins
Each PGOOD pin is connected to an open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the corresponding VFB pin
voltage is not within ±10% of the 0.8V reference voltage.
The PGOOD pin is also pulled low when the corresponding
RUN pin is low (shut down). When the VFB pin voltage
is within the ±10% requirement, the MOSFET is turned
off and the pin is allowed to be pulled up by an external
resistor to a source no greater than 6V.
Foldback Current
When the output voltage falls to less than 70% of its
nominal level, foldback current limiting is activated, progressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the VFB voltage is keeping up with the
TRACK/SS voltage).
Theory and Benefits of 2-Phase Operation
Why the need for 2-phase operation? Up until the 2‑phase
family, constant-frequency dual switching regulators
operated both channels in phase (i.e., single phase
operation). This means that both switches turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current flowing from the
input capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.
3890fc
13
LTC3890
OPERATION (Refer to the Functional Diagram)
Figure 1 compares the input waveforms for a representative single-phase dual switching regulator to the LTC3890
2-phase dual switching regulator. An actual measurement of
the RMS input current under these conditions shows that
2-phase operation dropped the input current from 2.53ARMS
to 1.55ARMS. While this is an impressive reduction in itself,
remember that the power losses are proportional to IRMS2,
meaning that the actual power wasted is reduced by a factor of 2.66. The reduced input ripple voltage also means
less power is lost in the input power path, which could
include batteries, switches, trace/connector resistances
and protection circuitry. Improvements in both conducted
and radiated EMI also directly accrue as a result of the
reduced RMS input current and voltage.
voltage VIN (Duty Cycle = VOUT/VIN). Figure 2 shows how
the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
It can readily be seen that the advantages of 2-phase operation are not just limited to a narrow operating range,
for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle.
Of course, the improvement afforded by 2-phase operation is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
3.0
SINGLE PHASE
DUAL CONTROLLER
2.5
INPUT RMS CURRENT (A)
With 2-phase operation, the two channels of the dual
switching regulator are operated 180 degrees out-of-phase.
This effectively interleaves the current pulses drawn by the
switches, greatly reducing the overlap time where they add
together. The result is a significant reduction in total RMS
input current, which in turn allows less expensive input
capacitors to be used, reduces shielding requirements for
EMI and improves real world operating efficiency.
2.0
1.5
2-PHASE
DUAL CONTROLLER
1.0
0.5
0
VO1 = 5V/3A
VO2 = 3.3V/3A
0
10
20
30
INPUT VOLTAGE (V)
40
3890 F02
Figure 2. RMS Input Current Comparison
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
IIN(MEAS) = 2.53ARMS
IIN(MEAS) = 1.55ARMS
3890 F01
Figure 1. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators
Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator Allows
Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency
3890fc
14
LTC3890
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic LTC3890
application circuit. LTC3890 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
power MOSFETs and Schottky diodes are selected. Finally,
input and output capacitors are selected.
Current Limit Programming
The ILIM pin is a tri-level logic input which sets the maximum current limit of the controller. When ILIM is grounded,
the maximum current limit threshold voltage of the current comparator is programmed to be 30mV. When ILIM
is floated, the maximum current limit threshold is 75mV.
When ILIM is tied to INTVCC, the maximum current limit
threshold is set to 50mV.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode voltage range on
these pins is 0V to 28V (abs max), enabling the LTC3890
to regulate output voltages up to a nominal 24V (allowing
margin for tolerances and transients).
The SENSE+ pin is high impedance over the full common
mode range, drawing at most ±1µA. This high impedance
allows the current comparators to be used in inductor
DCR sensing.
The impedance of the SENSE– pin changes depending on
the common mode voltage. When SENSE– is less than
INTVCC – 0.5V, a small current of less than 1µA flows out
of the pin. When SENSE– is above INTVCC + 0.5V, a higher
current (~700µA) flows into the pin. Between INTVCC –
0.5V and INTVCC + 0.5V, the current transitions from the
smaller current to the higher current.
Filter components mutual to the sense lines should be
placed close to the LTC3890, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 3). Sensing current elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If inductor DCR
sensing is used (Figure 4b), sense resistor R1 should be
TO SENSE FILTER,
NEXT TO THE CONTROLLER
3890 F03
COUT
INDUCTOR OR RSENSE
Figure 3. Sense Lines Placement with Inductor or Sense Resistor
VIN
INTVCC
VIN
BOOST
TG
RSENSE
SW
LTC3890
VOUT
BG
SENSE+
SENSE–
R1*
C1* PLACE CAPACITOR NEAR
SENSE PINS
SGND
*R1 AND C1 ARE OPTIONAL.
3890 F04a
(4a) Using a Resistor to Sense Current
VIN
INTVCC
VIN
BOOST
INDUCTOR
TG
L
SW
LTC3890
DCR
VOUT
BG
R1
SENSE+
C1*
R2
SENSE–
SGND
*PLACE C1 NEAR
SENSE PINS
(R1||R2) • C1 =
L
DCR
RSENSE(EQ) = DCR
R2
R1 + R2
3890 F04b
(4b) Using the Inductor DCR to Sense Current
Figure 4. Current Sensing Methods
3890fc
15
LTC3890
APPLICATIONS INFORMATION
placed close to the switching node, to prevent noise from
coupling into sensitive small-signal nodes.
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 4a. RSENSE is chosen based on the required
output current.
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIM setting. The current
comparator threshold voltage sets the peak of the inductor current, yielding a maximum average output current,
IMAX, equal to the peak value less half the peak-to-peak
ripple current, ∆IL. To calculate the sense resistor value,
use the equation:
RSENSE =
VSENSE(MAX)
∆I
IMAX + L
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the Maximum Current Sense Threshold
(VSENSE(MAX)) in the Electrical Characteristics table (30mV,
50mV or 75mV, depending on the state of the ILIM pin).
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability criterion for buck regulators operating at greater than 50%
duty factor. A curve is provided in the Typical Performance
Characteristics section to estimate this reduction in peak
inductor current depending upon the operating duty factor.
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC3890 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 4b. The DCR of the inductor represents the small
amount of DC resistance of the copper wire, which can be
less than 1mΩ for today’s low value, high current inductors.
In a high current application requiring such an inductor,
power loss through a sense resistor would cost several
points of efficiency compared to inductor DCR sensing.
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
RSENSE(EQUIV) =
VSENSE(MAX)
∆I
IMAX + L
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the Maximum Current Sense Threshold
(VSENSE(MAX)) in the Electrical Characteristics table (30mV,
50mV or 75mV, depending on the state of the ILIM pin).
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value (RD), use the divider ratio:
RD =
RSENSE(EQUIV)
DCRMAX at TL(MAX)
C1 is usually selected to be in the range of 0.1µF to 0.47µF.
This forces R1|| R2 to around 2k, reducing error that might
have been caused by the SENSE+ pin’s ±1µA current.
3890fc
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LTC3890
APPLICATIONS INFORMATION
The equivalent resistance R1|| R2 is scaled to the room
temperature inductance and maximum DCR:
R1|| R2 =
L
(DCR at 20°C) • C1
The sense resistor values are:
R1=
R1|| R2
R1• RD
; R2 =
RD
1– RD
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PLOSS R1=
( VIN(MAX) – VOUT ) • VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET switching and gate charge losses. In addition to
this basic trade-off, the effect of inductor value on ripple
current and low current operation must also be considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current, ∆IL, decreases with higher inductance or higher frequency and increases with higher VIN:
∆IL =
V
1
VOUT 1– OUT
VIN
( f) (L)
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.3(IMAX). The maximum
∆IL occurs at the maximum input voltage.
The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode
(Optional) Selection
Two external power MOSFETs must be selected for each
controller in the LTC3890: one N-channel MOSFET for the
top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
3890fc
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LTC3890
APPLICATIONS INFORMATION
The peak-to-peak drive levels are set by the INTVCC voltage.
This voltage is typically 5.1V during start-up (see EXTVCC
Pin Connection). Consequently, logic-level threshold
MOSFETs must be used in most applications. Pay close
attention to the BVDSS specification for the MOSFETs as well.
Selection criteria for the power MOSFETs include the
on-resistance, RDS(ON), Miller capacitance, CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
VOUT
VIN
Synchronous Switch Duty Cycle =
VIN − VOUT
VIN
The MOSFET power dissipations at maximum output
current are given by:
PMAIN =
PSYNC
VOUT
(IMAX )2 (1+ δ) RDS(ON) +
VIN
I
( VIN )2 MAX (RDR ) (CMILLER ) •
2
1
1
+
( f)
VINTVCC – VTHMIN VTHMIN
V –V
2
= IN OUT (IMAX ) (1+ δ) RDS(ON)
VIN
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1+ δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes D3 and D4 shown in
Figure 11 conduct during the dead-time between the
conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on,
storing charge during the dead-time and requiring a
reverse recovery period that could cost as much as 3%
in efficiency at high VIN. A 1A to 3A Schottky is generally
a good compromise for both regions of operation due
to the relatively small average current. Larger diodes
result in additional transition losses due to their larger
junction capacitance.
CIN and COUT Selection
The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can be
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
the highest (VOUT)(IOUT) product needs to be used in the
formula shown in Equation 1 to determine the maximum
3890fc
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LTC3890
APPLICATIONS INFORMATION
RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually
decrease the input RMS ripple current from its maximum
value. The out-of-phase technique typically reduces the
input capacitor’s RMS ripple current by a factor of 30%
to 70% when compared to a single phase power supply
solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈
IMAX
1/ 2
( VOUT ) ( VIN – VOUT ) (1)
VIN
This formula has a maximum at VIN = 2VOUT , where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3890, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
The benefit of the LTC3890 2-phase operation can be calculated by using Equation 1 for the higher power controller
and then calculating the loss that would have resulted if
both controller channels switched on at the same time.
The total RMS power lost is lower when both controllers
are operating due to the reduced overlap of current pulses
required through the input capacitor’s ESR. This is why
the input capacitor’s requirement calculated above for the
worst-case controller is adequate for the dual controller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2‑phase
system. The overall benefit of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The drains of the top MOSFETs should be placed within
1cm of each other and share a common CIN(s). Separating
the drains and CIN may produce undesirable voltage and
current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3890, is also
suggested. A 10Ω resistor placed between CIN (C1) and
the VIN pin provides further isolation between the two
channels.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
1
∆VOUT ≈ ∆IL ESR +
8 • f • COUT
where f is the operating frequency, COUT is the output
capacitance and ∆IL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ∆IL increases with input voltage.
Setting Output Voltage
The LTC3890 output voltages are each set by an external
feedback resistor divider carefully placed across the output, as shown in Figure 5. The regulated output voltage
is determined by:
R
VOUT = 0.8V 1+ B
RA
To improve the frequency response, a feedforward capacitor, CFF , may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
VOUT
1/2 LTC3890
RB
CFF
VFB
RA
3890 F05
Figure 5. Setting Output Voltage
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LTC3890
APPLICATIONS INFORMATION
Tracking and Soft-Start (TRACK/SS Pins)
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 6.
An internal 1µA current source charges the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
The LTC3890 will regulate the VFB pin (and hence VOUT)
according to the voltage on the TRACK/SS pin, allowing
VOUT to rise smoothly from 0V to its final regulated value.
The total soft-start time will be approximately:
t SS = CSS •
0.8V
1µA
1/2 LTC3890
TRACK/SS
CSS
SGND
OUTPUT VOLTAGE
VX(MASTER)
VOUT(SLAVE)
3890 F07a
TIME
(7a) Coincident Tracking
VX(MASTER)
OUTPUT VOLTAGE
The start-up of each VOUT is controlled by the voltage on
the respective TRACK/SS pin. When the voltage on the
TRACK/SS pin is less than the internal 0.8V reference,
the LTC3890 regulates the VFB pin voltage to the voltage
on the TRACK/SS pin instead of 0.8V. The TRACK/SS pin
can be used to program an external soft-start function
or to allow VOUT to track another supply during start-up.
VOUT(SLAVE)
3890 F07b
TIME
(7b) Ratiometric Tracking
Figure 7. Two Different Modes of Output Voltage Tracking
3890 F06
Figure 6. Using the TRACK/SS Pin to Program Soft-Start
Alternatively, the TRACK/SS pin can be used to track two
(or more) supplies during start-up, as shown qualitatively
in Figures 7a and 7b. To do this, a resistor divider should
be connected from the master supply (VX) to the TRACK/
SS pin of the slave supply (VOUT), as shown in Figure 8.
During start-up VOUT will track VX according to the ratio
set by the resistor divider:
R
+ RTRACKB
VX
RA
=
• TRACKA
VOUT RTRACKA
RA + RB
Vx VOUT
RB
1/2 LTC3890
VFB
RA
RTRACKB
TRACK/SS
RTRACKA
3890 F08
Figure 8. Using the TRACK/SS Pin for Tracking
For coincident tracking (VOUT = VX during start-up):
RA = RTRACKA
RB = RTRACKB
3890fc
20
LTC3890
APPLICATIONS INFORMATION
INTVCC Regulators
The LTC3890 features two separate internal P-channel low
dropout linear regulators (LDO) that supply power at the
INTVCC pin from either the VIN supply pin or the EXTVCC
pin depending on the connection of the EXTVCC pin.
INTVCC powers the gate drivers and much of the LTC3890’s
internal circuitry. The VIN LDO and the EXTVCC LDO regulate
INTVCC to 5.1V. Each of these can supply a peak current of
50mA and must be bypassed to ground with a minimum
of 4.7µF ceramic capacitor. No matter what type of bulk
capacitor is used, an additional 1µF ceramic capacitor
placed directly adjacent to the INTVCC and PGND pins is
highly recommended. Good bypassing is needed to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3890 to be
exceeded. The INTVCC current, which is dominated by
the gate charge current, may be supplied by either the
VIN LDO or the EXTVCC LDO. When the voltage on the
EXTVCC pin is less than 4.7V, the VIN LDO is enabled. Power
dissipation for the IC in this case is highest and is equal
to VIN • IINTVCC. The gate charge current is dependent on
operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated
by using the equations given in Note 3 of the Electrical
Characteristics. For example, the LTC3890 INTVCC current
is limited to less than 32mA from a 40V supply when not
using the EXTVCC supply at a 70°C ambient temperature:
TJ = 70°C + (32mA)(40V)(43°C/W) = 125°C
To prevent the maximum junction temperature from being exceeded, the input supply current must be checked
while operating in forced continuous mode (PLLIN/MODE
= INTVCC) at maximum VIN.
When the voltage applied to EXTVCC rises above 4.7V, the
VIN LDO is turned off and the EXTVCC LDO is enabled. The
EXTVCC LDO remains on as long as the voltage applied to
EXTVCC remains above 4.5V. The EXTVCC LDO attempts
to regulate the INTVCC voltage to 5.1V, so while EXTVCC
is less than 5.1V, the LDO is in dropout and the INTVCC
voltage is approximately equal to EXTVCC. When EXTVCC
is greater than 5.1V, up to an absolute maximum of 14V,
INTVCC is regulated to 5.1V.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from one of the LTC3890’s
switching regulator outputs (4.7V ≤ VOUT ≤ 14V) during
normal operation and from the VIN LDO when the output
is out of regulation (e.g., start-up, short-circuit). If more
current is required through the EXTVCC LDO than is specified, an external Schottky diode can be added between the
EXTVCC and INTVCC pins. In this case, do not apply more
than 6V to the EXTVCC pin and make sure that EXTVCC ≤ VIN.
Significant efficiency and thermal gains can be realized
by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
For 5V to 14V regulator outputs, this means connecting
the EXTVCC pin directly to VOUT . Tying the EXTVCC pin to
an 8.5V supply reduces the junction temperature in the
previous example from 125°C to:
TJ = 70°C + (32mA)(8.5V)(43°C/W) = 82°C
However, for 3.3V and other low voltage outputs, additional
circuitry is required to derive INTVCC power from the output.
3890fc
21
LTC3890
APPLICATIONS INFORMATION
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC Grounded. This will cause INTVCC to be powered
from the internal 5.1V regulator resulting in an efficiency
penalty of up to 10% at high input voltages.
2. EXTVCC Connected Directly to VOUT . This is the normal
connection for a 5V to 14V regulator and provides the
highest efficiency.
3. EXTVCC Connected to an External Supply. If an external
supply is available in the 5V to 14V range, it may be
used to power EXTVCC providing it is compatible with the
MOSFET gate drive requirements. Ensure that EXTVCC
< VIN.
4. EXTVCC Connected to an Output-Derived Boost Network.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with the capacitive charge
pump shown in Figure 9. Ensure that EXTVCC < VIN.
CIN
BAT85
VIN
BAT85
MTOP
1/2 LTC3890
EXTVCC
BAT85
NDS7002
TG1
L
SW
RSENSE
VOUT
MBOT
COUT
BG1
PGND
3890 F09
Figure 9. Capacitive Charge Pump for EXTVCC
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors, CB, connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor CB in the Functional Diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the top MOSFET switch
and turns it on. The switch node voltage, SW, rises to VIN
and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: VBOOST =
VIN + VINTVCC. The value of the boost capacitor, CB, needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the external
Schottky diode must be greater than VIN(MAX).
The external diode DB can be a Schottky diode or silicon
diode, but in either case it should have low-leakage and
fast recovery. Pay close attention to the reverse leakage
current specification for this diode, especially at high
temperatures where it generally increases substantially.
For applications with output voltages greater than ~5V
that are switching infrequently, a leaky diode DB can fully
discharge the bootstrap capacitor CB, creating a current
path from the output voltage to the BOOST pin to INTVCC.
Not only does this increase the quiescent current of the
converter, but it can cause INTVCC to rise to dangerous
levels if the leakage exceeds the current consumption on
INTVCC.
Particularly, this is a concern in Burst Mode operation at
no load or very light loads, where the part is switching
very infrequently and the current draw on INTVCC is very
low (typically about 35µA). Generally, pulse-skipping and
forced continuous modes are less sensitive to leakage,
since the more frequent switching keeps the bootstrap
capacitor CB charged, preventing a current path from the
output voltage to INTVCC.
However, in cases where the converter has been operating (in any mode) and then is shut down, if the leakage
of diode DB fully discharges the bootstrap capacitor CB
before the output voltage discharges to below ~5V, then
the leakage current path can be created from the output
voltage to INTVCC. In shutdown, the INTVCC pin is able to
sink about 30µA. To accommodate diode leakage greater
than this amount in shutdown, INTVCC can be loaded
with an external resistor or clamped with a Zener diode.
Alternatively, the PGOOD resistor can be used to sink the
current (assuming the resistor pulls up to INTVCC) since
PGOOD is pulled low when the converter is shut down.
Nonetheless, using a low-leakage diode is the best choice
to maintain low quiescent current under all conditions.
3890fc
22
LTC3890
APPLICATIONS INFORMATION
Fault Conditions: Current Limit and Current Foldback
Phase-Locked Loop and Frequency Synchronization
The LTC3890 includes current foldback to help limit
load current when the output is shorted to ground. If
the output voltage falls below 70% of its nominal output
level, then the maximum sense voltage is progressively
lowered from 100% to 45% of its maximum selected
value. Under short-circuit conditions with very low duty
cycles, the LTC3890 will begin cycle skipping in order to
limit the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less
than in normal operation. The short-circuit ripple current
is determined by the minimum on-time, tON(MIN), of the
LTC3890 (≈95ns), the input voltage and inductor value:
The LTC3890 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked to
the rising edge of an external clock signal applied to the
PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET
is thus 180 degrees out of phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
The resulting average short-circuit current is:
1
ISC = 45% • ILIM(MAX) – ∆IL(SC)
2
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the controller is operating.
A comparator monitors the output for overvoltage conditions. The comparator detects faults greater than 10%
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously for
as long as the overvoltage condition persists; if VOUT returns
to a safe level, normal operation automatically resumes.
A shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than fOSC,
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP , holds the voltage at the VCO input.
1000
900
800
FREQUENCY (kHz)
V
∆IL(SC) = tON(MIN) IN
L
700
600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
3890 F10
Figure 10. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
3890fc
23
LTC3890
APPLICATIONS INFORMATION
Note that the LTC3890 can only be synchronized to an
external clock whose frequency is within range of the
LTC3890’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Typically, the external clock (on the PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is 1.1V.
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchronization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchronization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2
FREQ PIN
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
350kHz
INTVCC
DC Voltage
535kHz
Resistor
DC Voltage
50kHz to 900kHz
Any of the Above
External Clock
Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3890 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
VOUT
VIN ( f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3890 is approximately
95ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
3890fc
24
LTC3890
APPLICATIONS INFORMATION
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3890 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) topside MOSFET
transition losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. VIN current typically results
in a small (1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT , causing a rapid drop in VOUT . No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
3890fc
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LTC3890
APPLICATIONS INFORMATION
Design Example
As a design example for one channel, assume VIN = 12V
(nominal), VIN = 22V (max), VOUT = 3.3V, IMAX = 5A,
VSENSE(MAX) = 75mV and f = 350kHz.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF. At
maximum input voltage with T(estimated) = 50°C:
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the FREQ pin
to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
∆IL =
VOUT
V
1– OUT
( f) (L) VIN(NOM)
A 4.7µH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 95ns is not violated. The minimum on-time occurs at
maximum VIN:
tON(MIN) =
VOUT
VIN(MAX) ( f)
=
3.3V
= 429ns
22V (350kHz )
The equivalent RSENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (64mV):
RSENSE ≤
64mV
≈ 0.01Ω
5.73A
Choosing 1% resistors: RA = 25k and RB = 78.7k yields
an output voltage of 3.32V.
PMAIN =
3.3V
(5A )2 1+ (0.005) (50°C – 25°C)
22V
5A
(0.035Ω) + (22V )2 (2.5Ω) (215pF ) •
2
1
1
+
(350kHz ) = 331mW
5V – 2.3V 2.3V
A short-circuit to ground will result in a folded back current of:
ISC =
34mV 1 95ns (22V )
–
= 3.18A
0.01Ω 2 4.7µH
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
2
PSYNC = (3.28A ) (1.125) (0.022Ω)
= 250mW
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VORIPPLE = RESR (∆IL) = 0.02Ω(1.45A) = 29mVP-P
3890fc
27
LTC3890
APPLICATIONS INFORMATION
TRACK/SS1
ITH1
PGOOD2
VFB1
PGOOD1
RPU2
PGOOD2
VPULL-UP
RPU1
VPULL-UP
PGOOD1
R1*
L1
SENSE1+
C1*
SENSE1–
SW1
LTC3890
FREQ
BOOST1
PHASMD
CLKOUT
fIN
PLLIN/MODE
RUN1
CB1
M1
VIN
CVIN
PGND
EXTVCC
SENSE2–
INTVCC
SENSE2+
BG2
TRACK/SS2
1µF
CERAMIC
+
CINTVCC
D1*
VIN
M3
COUT1
+
GND
+
CIN
COUT2
1µF
CERAMIC
BOOST2
VFB2
ITH2
M2
RIN
SGND
R2*
VOUT1
BG1
RUN2
C2*
RSENSE
TG1
M4
D2*
CB2
SW2
RSENSE
TG2
ILIM
VOUT2
L2
3890 F11
*R1, R2, C1, C2, D1, D2 ARE OPTIONAL.
Figure 11. Recommended Printed Circuit Layout Diagram
3890fc
28
LTC3890
APPLICATIONS INFORMATION
SW1
L1
D1
RSENSE1
VOUT1
COUT1
RL1
VIN
RIN
CIN
SW2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
D2
L2
RSENSE2
VOUT2
COUT2
RL2
3890 F12
Figure 12. Branch Current Waveforms
3890fc
29
LTC3890
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 11. Figure 12 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
connection at CIN? Do not attempt to split the input
decoupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3890 VFB pins’ resistive dividers connect to
the (+) terminals of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
4. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
5. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers’ current peaks. An additional 1µF ceramic capacitor placed
immediately next to the INTVCC and PGND pins can help
improve noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on
the output side of the LTC3890 and occupy minimum
PC trace area.
7. Use a modified star ground technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the INTVCC decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the SGND pin of the IC.
3890fc
30
LTC3890
APPLICATIONS INFORMATION
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the
internal oscillator and probe the actual output voltage as
well. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over the
input voltage range down to dropout and until the output
load drops below the low current operation threshold—
typically 15% of the maximum designed current level in
Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can
suggest noise pickup at the current or voltage sensing
inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout
if regulator bandwidth optimization is not required. Only
after each controller is checked for its individual performance should both controllers be turned on at the same
time. A particularly difficult region of operation is when
one controller channel is nearing its current comparator
trip point when the other channel is turning on its top
MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
3890fc
31
LTC3890
TYPICAL APPLICATIONS
C1
1nF
RB1
100k
RA1
31.6k
SENSE1+
INTVCC
SENSE1–
PGOOD1
VFB1
PGOOD2
CITH1A 100pF
MBOT1
SW1
L1
4.7µH
BOOST1
ITH1
CB1
0.1µF
LTC3890
CSS1 0.01µF
TRACK/SS1
TG1
ILIM
PHSMD
CLKOUT
PLLIN/MODE
VIN
SGND
EXTVCC
RUN1
RUN2
FREQ
VOUT2
RFREQ
41.2k
CSS2 0.01µF
TRACK/SS2
RITH2
34.8k
CITH2 470pF
100k
BG1
RITH1
34.8k
CITH1 1000pF
100k
ITH2
RA2
10.5k
VFB2
RB2
100k
RSENSE1
8mΩ
VOUT1
3.3V
5A
COUT1
470µF
MTOP1
D1
INTVCC
CINT
4.7µF
PGND
VIN
9V TO 60V
CIN
220µF
D2
TG2
MTOP2
CB2 0.1µF
L2
8µH
BOOST2
SW2
RSENSE2
10mΩ
VOUT2
8.5V
3A
COUT2
330µF
MBOT2
BG2
SENSE2–
C2
1nF
SENSE2+
3890 TA02a
MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB
L1: COILCRAFT SER1360-472KL
L2: COILCRAFT SER1360-802KL
COUT1: SANYO 6TPE470M
COUT2: SANYO 10TPE330M
D1, D2: DFLS1100
Figure 13. High Efficiency Dual 8.5V/3.3V Step-Down Converter
Efficiency and Power Loss
vs Output Current
BURST EFFICIENCY
90
1000
CCM LOSS
100
60
50
40
PULSE-SKIPPING
LOSS
BURST LOSS
10
30
20
10
0
0.0001
CCM EFFICIENCY
PULSE-SKIPPING
EFFICIENCY
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
1
0.1
10
3890 TA02b
80
POWER LOSS (mW)
EEFICIENCY (%)
80
70
100
Efficiency vs Input Voltage
100
VOUT = 8.5V
98
VOUT = 3.3V
70
60
50
40
30
94
92
90
86
84
10
82
10
3890 TA02c
VOUT1 = 3.3V
88
20
VIN = 12V
0
0.0001 0.001
0.01
0.1
1
OUTPUT CURRENT (A)
VOUT2 = 8.5V
96
EEFICIENCY (%)
VIN = 12V
90 VOUT = 3.3V
Efficiency vs Load Current
10000
EEFICIENCY (%)
100
80
ILOAD = 2A
0
5 10 15 20 25 30 35 40 45 50 55 60
INPUT VOLTAGE (V)
3890 TA02d
3890fc
32
LTC3890
TYPICAL APPLICATIONS
High Efficiency 8.5V Dual-Phase Step-Down Converter
RB1
100k
RA1
10.5k
C1
1nF
SENSE1+
INTVCC
SENSE1–
PGOOD1
VFB1
PGOOD2
CITH1A 100pF
MBOT1
BG1
L1
8µH
SW1
RITH1 34.8k
LTC3890
INTVCC RMODE
100k
TRACK/SS1
TG1
ILIM
PHSMD
CLKOUT
PLLIN/MODE
VIN
SGND
RRUN
V
1000k OUT
EXTVCC
RUN1
RUN2
FREQ
RFREQ 41.2k
INTVCC
VFB2
COUT1
330µF
MTOP1
VIN
CIN 9V TO 60V
220µF
CINT
4.7µF
PGND
D2
TG2
BOOST2
ITH2
CB1
0.1µF
D1
TRACK/SS2
CITH2
100pF
VOUT1
8.5V
6A
RSENSE1
10mΩ
BOOST1
ITH1
CITH1 C
SS1 0.01µF
470pF
VIN
100k
SW2
BG2
CB2 0.1µF
MTOP2
L2
8µH
RSENSE2
10mΩ
COUT2
330µF
MBOT2
SENSE2–
C2
1nF
SENSE2+
3890 TA03
MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB
L1, L2: COILCRAFT SER1360-802KL
COUT1, COUT2: SANYO 10TPE330M
D1, D2: DFLS1100
3890fc
33
LTC3890
TYPICAL APPLICATIONS
High Efficiency Dual 12V/5V Step-Down Converter
RB1
100k
RA1
6.98k
C1
1nF
SENSE1+
INTVCC
SENSE1–
PGOOD1
VFB1
PGOOD2
CITH1A 100pF
CITH1 470pF
100k
BG1
RITH1
34.8k
MBOT1
SW1
LTC3890
TRACK/SS1
ILIM
PHSMD
CLKOUT
PLLIN/MODE
SGND
EXTVCC
RUN1
RUN2
FREQ
RFREQ
41.2k
TG1
TRACK/SS2
CB1
0.47µF
COUT1
180µF
INTVCC
CIN
220µF
CINT
4.7µF
PGND
VOUT1
12V
3A
MTOP1
VIN
VIN
12.5V TO 60V
D2
TG2
CB2 0.47µF
BOOST2
MTOP2
L2
4.7µH
SW2
RSENSE2
10mΩ
VOUT2
5V
5A
COUT2
470µF
ITH2
BG2
RA2
18.7k
RSENSE1
9mΩ
D1
CSS2 0.01µF
RITH2
20k
L1
8µH
BOOST1
ITH1
CSS1 0.01µF
CITH2 470pF
100k
MBOT2
VFB2
RB2
100k
SENSE2–
C2
1nF
SENSE2+
3890 TA04
MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB
L1: COILCRAFT SER1360-802KL
L2: COILCRAFT SER1360-472KL
COUT1: 16SVP180MX
COUT2: SANYO 6TPE470M
D1, D2: DFLS1100
3890fc
34
LTC3890
TYPICAL APPLICATIONS
High Efficiency Dual 24V/5V Step-Down Converter
RB1
487k
C1
1nF
CF1 33pF
RA1
16.9k
SENSE1–
PGOOD1
100k
100k
BG1
RITH1
46k
MBOT1
L1
22µH
RSENSE1
25mΩ
SW1
TRACK/SS1
ILIM
PHSMD
CLKOUT
PLLIN/MODE
SGND
EXTVCC
RUN1
RUN2
FREQ
CSS2 0.01µF
TRACK/SS2
RITH2
20k
ITH2
TG1
MTOP1
D1
VIN
INTVCC
CIN
220µF
CINT
4.7µF
PGND
VIN
28V TO 60V
D2
TG2
CB2 0.47µF
BOOST2
MTOP2
L2
4.7µH
SW2
BG2
RA2
18.7k
COUT1
22µF
×2 CERAMIC
CB1
0.47µF
LTC3890
RFREQ
60k
VOUT1
24V
1A
BOOST1
ITH1
CSS1 0.01µF
CITH2 470pF
INTVCC
PGOOD2
VFB1
CITH1A 100pF
CITH1 680pF
SENSE1+
RSENSE2
10mΩ
VOUT2
5V
5A
COUT2
470µF
MBOT2
VFB2
RB2
100k
SENSE2–
C2
1nF
SENSE2+
3890 TA05
MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB
L1: SUMIDA CDR7D43MN
L2: COILCRAFT SER1360-472KL
COUT1: KEMET T525D476MO16E035
COUT2: SANYO 6TPE470M
D1, D2: DFLS1100
3890fc
35
LTC3890
TYPICAL APPLICATIONS
12V SEPIC and 3.3V Step-Down Converter
INTVCC
1k
L1
2k
2k
VOUT1
6.8µF
0.1µF
RB1
100k
C1
1nF
511Ω
RA1
6.98k
PGOOD1
PGOOD2
SENSE1–
BOOST1
CB1
0.1µF
LTC3890
TRACK/SS1
INTVCC
ILIM
PHSMD
CLKOUT
PLLIN/MODE
SGND
VOUT1
EXTVCC
RUN1
RUN2
FREQ
RFREQ
41.2k
CSS2
0.01µF
TRACK/SS2
RITH2
7.15k
COUT
68µF
6.8µF
VOUT1
12V
2A
RSNS1
6mΩ
SW1
RMODE
100k
D2
511Ω
ITH1
CSS1
0.01µF
CITH2 4.7nF
M1
TG1
BG1
RITH1
12.1k
10µH
6.8µF
VFB1
CITH1A
47pF
CITH1
10nF
SENSE1+
10µH
• •
VIN
INTVCC
CIN
100µF
CINT
4.7µF
PGND
VIN
5V TO 35V
D1
TG2
BOOST2
CB2 0.1µF
MTOP2
L2
3.3µH
SW2
RSENSE2
4mΩ
VOUT2
3.3V
10A
ITH2
BG2
COUT2
470µF
MBOT2
CITH2A 47pF
VFB2
RA2
31.6k
SENSE2–
RB2
100k
C2
1nF
SENSE2+
3890 TA06
M1, MBOT1, MBOT2: RJK0651DPB
L1: WÜRTH 7448709100
L2: WÜRTH 7443320330
COUT1: SANYO 16TQC68M
COUT2: SANYO 6TPE470M
D1: DFLS1100
D2: PDS560
3890fc
36
LTC3890
TYPICAL APPLICATIONS
High Efficiency 12V at 25A Dual-Phase Step-Down Converter
RB1
499k
10pF
C1
1nF
RA1
35.7k
SENSE1–
MBOT1
L1
10µH
SW1
VOUT
12V
25A
TRACK/SS1
SGND
FREQ
COUT1
150µF
CB1
0.1µF
LTC3890
RRUN1
1000k
RSENSE1
3mΩ
BOOST1
ITH1
CSS1
0.1µF
ILIM
PHSMD
CLKOUT
PLLIN/MODE
VIN
PGOOD1
BG1
RITH1
9.76k
RFREQ
30.1k
INTVCC
100k
PGOOD2
VFB1
CITH1A 100pF
CITH1
4.7nF
SENSE1+
TG1
MTOP1
D1
VIN
INTVCC
CIN
100µF
CINT
4.7µF
PGND
VIN
16V TO 60V
D2
RUN1
RUN2
RRUN2
57.6k
TRACK/SS2
ITH2
VOUT
EXTVCC
TG2
CB2 0.1µF
BOOST2
MTOP2
L2
10µH
SW2
BG2
RSENSE2
3mΩ
COUT2
150µF
MBOT2
VFB2
SENSE2–
C2
1nF
SENSE2+
3890 TA07
MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB
L1, L2: WÜRTH 7443631000
COUT1, COUT2: SANYO 16SVPC150M
CIN: SUN ELECT. 63CE100BS
D1, D2: DFLS1100
3890fc
37
LTC3890
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
3.45 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
3890fc
38
LTC3890
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/11
Added MP-grade and H-grade. Changes reflected throughout the data sheet.
B
04/12
Clarified the Electrical Characteristics specifications. Added Typical Application schematics.
C
10/12
Added INTVCC to Absolute Maximum Ratings
1-38
3, 36, 37
2
3890fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
39
LTC3890
TYPICAL APPLICATION
High Efficiency Dual 12V/3.3V Step-Down Converter
C1
1nF
RB1
100k
RA1
6.98k
SENSE1+
INTVCC
SENSE1–
PGOOD1
VFB1
PGOOD2
CITH1A 100pF
L1
8µH
BOOST1
ITH1
CB1
0.47µF
LTC3890
TRACK/SS1
ILIM
PHSMD
CLKOUT
PLLIN/MODE
SGND
VOUT1
TG1
COUT1
180µF
INTVCC
CIN
220µF
CINT
4.7µF
VIN
12.5V TO 60V
D2
TG2
TRACK/SS2
CB2 0.47µF
BOOST2
MTOP2
L2
4.7µH
SW2
RSENSE2
10mΩ
ITH2
CITH2A
100pF
VOUT1
12V
3A
MTOP1
VIN
CSS2 0.01µF
RITH2
34.8k
RSENSE1
9mΩ
D1
PGND
EXTVCC
RUN1
RUN2
FREQ
RFREQ
41.2k
RA2
31.6k
MBOT1
SW1
CSS1 0.01µF
CITH2 1000pF
100k
BG1
RITH1
34.8k
CITH1 470pF
100k
BG2
MBOT2
VOUT2
3.3V
5A
COUT2
470µF
VFB2
RB2
100k
SENSE2–
MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB
L1: COILCRAFT SER1360-802KL
L2: COILCRAFT SER1360-472KL
COUT1: 16SVP180MX
COUT2: SANYO 6TPE470M
D1, D2: DFLS1100
C2
1nF
SENSE2+
3890 TA08
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3891
60V, Low IQ, Synchronous Step-Down DC/DC Controller
with 99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,
0.8V ≤ VOUT ≤ 24V, TSSOP-20E, 3mm × 4mm QFN-20
LTC3857/LTC3857-1/
LTC3858/LTC3858-1
Low IQ, Dual Output 2-Phase Synchronous Step-Down
DC/DC Controllers with 99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 24V, IQ = 50µA/170µA
LTC3834/LTC3834-1/
LTC3835/LTC3835-1
Low IQ, Single Output Synchronous Step-Down
DC/DC Controllers with 99% Duty Cycle
PLL Fixed Frequency 140kHz to 650kHz, 4V ≤ VIN ≤ 36V,
0.8V ≤ VOUT ≤ 10V, IQ = 30µA/80µA
LTC3810
100V Synchronous Step-Down DC/DC Controller
Constant On-Time Valley Current Mode, 4V ≤ VIN ≤ 100V,
0.8V ≤ VOUT ≤ 0.93VIN, SSOP-28
LTC3859A
Low IQ, Triple Output Buck/Buck/Boost Synchronous
DC/DC Controller with Improved Burst Mode Operation
Outputs (≥5V) Remain in Regulation Through Cold Crank,
2.5V ≤ VIN ≤ 38V, VOUT(BUCKS) Up to 24V, VOUT(BOOST) Up to 60V
3890fc
40 Linear Technology Corporation
LT 1012 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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