LTC4012/
LTC4012-1/LTC4012-2
High Efficiency,
Multi-Chemistry Battery Charger
with PowerPath Control
Description
Features
General Purpose Battery Charger Controller
Efficient 550kHz Synchronous Buck PWM Topology
±0.5% Output Float Voltage Accuracy
Programmable Charge Current: 4% Accuracy
Programmable AC Adapter Current Limit:
3% Accuracy
No Audible Noise with Ceramic Capacitors
n INFET Low Loss Ideal Diode PowerPath™ Control
n Wide Input Voltage Range: 6V to 28V
n Wide Output Voltage Range: 2V to 28V
n Indicator Outputs for AC Adapter Present, Charging,
C/10 Current Detection and Input Current Limiting
n Analog Charge Current Monitor
n Micropower Shutdown
n 20-Pin 4mm × 4mm × 0.75mm QFN Package
n
n
n
n
n
n
Applications
Notebook Computers
Portable Instruments
n Battery Backup Systems
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 5723970.
The LTC4012 is a constant-current /constant-voltage battery charger controller. It uses a synchronous
quasi-constant frequency PWM control architecture
that will not generate audible noise with ceramic bulk
capacitors. Charge current is set by external resistors and can be monitored as an output voltage.
With no built-in termination, the LTC4012 family charges
a wide range of batteries under external control.
The LTC4012 features fully adjustable output voltage, while
the LTC4012-1 and LTC4012-2 can be pin-programmed for
Lithium-Ion/Polymer battery packs of 1-, 2-, 3- or 4-series
cells. The LTC4012-1 provides output voltage of 4.1V/cell
and the LTC4012-2 is a 4.2V/cell version.
The device includes AC adapter input current limiting, which
maximizes charge rate for a fixed input power level. An
external sense resistor programs the input current limit,
and the ICL status pin indicates reduced charge current as
a result of AC adapter current limiting. Ideal diode control
at the adaptor input improves charger efficiency.
The CHRG status pin is active during all charging modes,
including special indication for low charge current.
Typical Application
FROM
ADAPTER
13V TO 28V
25mΩ
0.1µF
DCIN
CLN
BOOST
0.1µF
TO/FROM
MCU
6.04k
CHRG
SW
INTVDD
ICL
BGATE
SHDN
GND
ITH
CSP
LTC4012
0.1µF
CSN
PROG
26.7k
4.7nF
BAT
FBDIV
100
10000
EFFICIENCY
95
0.1µF
TGATE
ACP
5.1k
EFFICIENCY (%)
CLP
Efficiency at DCIN = 20V
POWER TO
SYSTEM
2µF
6.8µH
90
POWER LOSS
85
80
VOUT = 12.3V
RSENSE = 33mΩ
RIN = 3.01k
RPROG = 26.7k
75
3.01k
70
33mΩ
3.01k
1000
0
0.5
1
1.5
2
CHARGE CURRENT (A)
2.5
3
POWER LOSS (mW)
INFET
20µF
100
PIN NAME
301k
VFB
32.8k
20µF
+
PART INFET DCDIV
LTC4009
X
LTC4012
X
12.3V
Li-Ion
BATTERY
4012 TA02
4012 TA01
4012fa
LTC4012/
LTC4012-1/LTC4012-2
Absolute Maximum Ratings
(Note 1)
DCIN.............................................................–14V to 30V
DCIN to CLP................................................. –32V to 20V
CLP, CLN or SW to GND.............................. –0.3V to 30V
CLP to CLN.............................................................±0.3V
CSP, CSN or BAT to GND............................ –0.3V to 28V
CSP to CSN.............................................................±0.3V
BOOST to GND............................................ –0.3V to 36V
BOOST to SW............................................... –0.3V to 7V
SHDN, FVS0, FVS1 or VFB to GND................ –0.3V to 7V
ACP, CHRG or ICL to GND........................... –0.3V to 30V
Operating Temperature Range
(Note 2).............................................. –40°C to 125°C
Junction Temperature (Note 3).............................. 125°C
Storage Temperature Range................... –65°C to 150°C
Pin Configuration
LTC4012-1
LTC4012-2
21
GND
DCIN 4
8
CHRG
ICL
12 ITH
DCIN 4
11 BAT
ACP 5
9 10
VFB
7
INFET 3
FBDIV
6
SHDN
ACP 5
13 PROG
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
TJMAX = 125°C, JA = 37°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
BGATE
15 CSP
14 CSN
21
GND
13 PROG
12 ITH
11 BAT
6
7
8
9 10
FVS1
CLP 2
FVS0
CLN 1
14 CSN
ICL
15 CSP
CLP 2
CHRG
CLN 1
INFET 3
INTVDD
20 19 18 17 16
SHDN
20 19 18 17 16
SW
BOOST
TOP VIEW
BGATE
INTVDD
SW
TGATE
BOOST
TOP VIEW
TGATE
LTC4012
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
TJMAX = 125°C, JA = 37°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4012CUF#PBF
LTC4012CUF#TRPBF
4012
20-Lead (4mm × 4mm) Plastic QFN
0°C to 85°C
LTC4012CUF-1#PBF
LTC4012CUF-1#TRPBF
40121
20-Lead (4mm × 4mm) Plastic QFN
0°C to 85°C
LTC4012CUF-2#PBF
LTC4012CUF-2#TRPBF
40122
20-Lead (4mm × 4mm) Plastic QFN
0°C to 85°C
LTC4012IUF#PBF
LTC4012IUF#TRPBF
4012
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LTC4012IUF-1#PBF
LTC4012IUF-1#TRPBF
40121
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LTC4012IUF-2#PBF
LTC4012IUF-2#TRPBF
40122
20-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4012fa
LTC4012/
LTC4012-1/LTC4012-2
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. DCIN = 20V, BAT = 12V, GND = 0V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Charge Voltage Regulation
VTOL
VBAT Accuracy (See Test Circuits)
LTC4012
C-Grade
I-Grade
l
l
–0.5
–0.8
–1.0
0.5
0.8
1.0
%
%
%
LTC4012-1/LTC4012-2
C-Grade
FVS1 = 0V, FVS0 = 0V, I-Grade
FVS1 = 0V, FVS1 = 5V, I-Grade
FVS1 = 5V, FVS0 = 0V, I-Grade
FVS1 = 5V, FVS1 = 5V, I-Grade
l
l
l
l
l
–0.6
–0.8
–1.1
–1.15
–1.25
–1.35
0.6
0.8
1.1
1.15
1.25
1.35
%
%
%
%
%
%
IVFB
VFB Input Bias Current
VFB = 1.2V
±20
nA
RON
FBDIV On Resistance
ILOAD = 100µA
l
85
190
Ω
ILEAK-FBDIV
FBDIV Output Leakage Current
SHDN = 0V, FBDIV = 0V
l
–1
0
1
µA
VBOV
VFB Overvoltage Threshold
LTC4012
l
1.235
1.281
1.32
V
BAT Overvoltage Threshold
LTC4012-1/LTC4012-2, Relative to
Selected Output Voltage
l
103
106
109
%
RPROG = 26.7k
C-Grade
I-Grade
l
l
–4
–5
–9.5
4
5
9.5
%
%
%
Charge Current Regulation
ITOL
Charge Current Accuracy with RIN = 3.01k,
6V < BAT < 18V (LTC4012)
6V < BAT < 15V (LTC4012-1, LTC4012-2)
VSENSE = 0mV, PROG = 1.2V
–12.75
–11.67
–10.95
µA
–1.78
–1.66
–1.54
µA
140
125
195
325
250
265
430
mV
mV
mV
AI
Current Sense Amplifier Gain (PROG ∆I) with
RIN = 3.01k, 6V < BAT < 18V (LTC4012)
6V < BAT < 15V (LTC4012-1, LTC4012-2)
VSENSE Step from 0mV to 5mV,
PROG = 1.2V
VCS-MAX
Maximum Peak Current Sense Threshold Voltage
per Cycle (RIN = 3.01k)
ITH = 2V, C-Grade
ITH = 2V, I-Grade
ITH = 5V
VC10
C/10 Indicator Threshold Voltage
PROG Falling
340
400
460
mV
VREV
Reverse Current Threshold Voltage
PROG Falling
180
253
295
mV
97
96
92
100
100
103
104
108
mV
mV
mV
l
l
l
Input Current Regulation
VCL
Current Limit Threshold
CLP – CLN
C-Grade
I-Grade
ICLN
CLN Input Bias Current
CLN = CLP
VICL
ICL Indicator Threshold
(CLP – CLN) – VCL
l
l
±100
–8
–5
nA
–2
mV
28
V
CLP Supply
OVR
Operating Voltage Range
6
VUVLO
CLP Undervoltage Lockout Threshold
VUV(HYST)
UVLO Threshold Hysteresis
ICLPO
CLP Operating Current
CLP = 20V, No Gate Loads
VACP
AC Present Threshold Voltage
DCIN – BAT, DCIN Rising
C-Grade
I-Grade
CLP Increasing
l
4.65
4.85
5.25
200
V
mV
2
3
mA
500
650
700
mV
mV
Shutdown
l
l
VACP(HYST)
ACP Threshold Hysteresis Voltage
VIL
SHDN Input Voltage Low
l
VIH
SHDN Input Voltage High
l
350
300
200
mV
300
1.4
mV
V
4012fa
LTC4012/
LTC4012-1/LTC4012-2
Electrical
Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. DCIN = 20V, BAT = 12V, GND = 0V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
RIN
SHDN Pull-Down Resistance
CONDITIONS
MIN
ICLPS
CLP Shutdown Current
CLP = 12V, DCIN = 0V
SHDN = 0V
l
ILEAK-BAT
BAT Leakage Current
SHDN = 0V or DCIN = 0V,
0V ≤ CSP = CSN = BAT ≤ 18V
l
ILEAK-CSN
CSN Leakage Current
SHDN = 0V or DCIN = 0V,
0V ≤ CSP = CSN = BAT ≤ 20V
ILEAK-CSP
CSP Leakage Current
ILEAK-SW
SW Leakage Current
TYP
MAX
40
UNITS
kΩ
15
350
26
500
µA
µA
–1.5
0
1.5
µA
l
–1.5
0
1.5
µA
SHDN = 0V or DCIN = 0V,
0V ≤ CSP = CSN = BAT ≤ 20V
l
–1.5
0
1.5
µA
SHDN = 0V or DCIN = 0V,
0V ≤ SW ≤ 20V
l
–1
0
2
µA
l
4.85
5
5.15
V
INTVDD Regulator
INTVDD
Output Voltage
No Load
ΔVDD
Load Regulation
IDD = 20mA
IDD
Short-Circuit Current (Note 5)
INTVDD = 0V
50
–0.4
–1
%
85
130
mA
633
kHz
Switching Regulator
IITH
ITH Current
fTYP
Typical Switching Frequency
ITH = 1.4V
–40/+90
µA
fMIN
Minimum Switching Frequency
DCMAX
Maximum Duty Cycle
tR-TG
TGATE Rise Time
CLOAD = 3.3nF, 10% – 90%
60
110
ns
tF-TG
TGATE Fall Time
CLOAD = 3.3nF, 90% – 10%
50
110
ns
tR-BG
BGATE Rise Time
CLOAD = 3.3nF, 10% – 90%
60
110
ns
tF-BG
BGATE Fall Time
CLOAD = 3.3nF, 90% – 10%
60
110
ns
tNO
TGATE, BGATE Non-Overlap Time
CLOAD = 3.3nF, 10% – 10%
110
467
550
CLOAD = 3.3nF
20
25
kHz
CLOAD = 3.3nF
98
99
%
ns
PowerPath Control
IDCIN
DCIN Input Current
0V ≤ DCIN ≤ CLP
l
–10
60
µA
VFTO
Forward Turn-On Voltage (DCIN Detection Threshold)
DCIN-CLP, DCIN rising
l
15
60
mV
VFR
Forward Regulation Voltage
DCIN-CLP
l
15
25
35
mV
VRTO
Reverse Turn-Off Voltage
DCIN-CLP, DCIN falling
l
–45
–25
–15
mV
VOL(INFET)
INFET Output Low Voltage, Relative to CLP
DCIN-CLP = 0.1V, IINFET =1µA
–6.5
–5
V
VOH(INFET)
INFET Output High Voltage, Relative to CLP
DCIN-CLP = –0.1V, IINFET =–5µA
–250
250
mV
tIF(ON)
INFET Turn-On Time
To CLP-INFET > 3V, CINFET = 1nF
85
180
µs
tIF(OFF)
INFET Turn-Off Time
To CLP-INFET < 1.5V, CINFET = 1nF
2.5
6
µs
0.5
V
Float Voltage Select Inputs (LTC4012-1/LTC4012-2 Only)
VIL
Input Voltage Low
VIH
Input Voltage High
IIN
Input Current
3.5
0V ≤ VIN ≤ 5V
V
–10
10
µA
500
mV
10
µA
38
µA
Indicator Outputs
VOL
Output Voltage Low
ILOAD = 100µA, PROG = 1.2V
ILEAK
Output Leakage
SHDN = 0V, DCDIV = 0V,
VOUT = 20V
l
–10
IC10
CHRG C/10 Current Sink
CHRG = 2.5V
l
15
25
4012fa
LTC4012/
LTC4012-1/LTC4012-2
Electrical Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC4012C is guaranteed to meet performance specifications
over the 0°C to 85°C operating temperature range. The LTC4012I is
guaranteed to meet performance specifications over the –40°C to 125°C
operating temperature range.
Note 3: Operating junction temperature TJ (in °C) is calculated from
the ambient temperature TA and the total continuous package power
dissipation PD (in watts) by the formula TJ = TA + (θJA • PD). Refer to the
Applications Information section for details.
Note 4: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND, unless otherwise
specified.
Note 5: Output current may be limited by internal power dissipation. Refer
to the Applications Information section for details.
Test Circuits
LTC4012
FROM ICL
(CLP = CLN)
1.2085V
PROG
13
–
–
–
+
EA
VFB
ITH
9
12
+
1.2085V
TARGET
LTC1055
–
0.6V
40012 TC01
LTC4012-1
LTC4012-2
FROM ICL
(CLP = CLN)
1.2085V
PROG
13
–
–
–
+
EA
BAT
ITH
11
12
TARGET VARIES
WITH FVSO,1
+
LTC1055
–
0.6V
40012 TC02
4012fa
LTC4012/
LTC4012-1/LTC4012-2
Typical Performance Characteristics
(TA = 25°C unless otherwise noted. L = IHLP-2525 6.8µH)
Efficiency at DCIN = 20V, BAT = 8V
100
Efficiency at DCIN = 20V, BAT = 12V
10000
RSENSE = 33mΩ
RIN = 3.01k
100
EFFICIENCY
95
EFFICIENCY (%)
1000
POWER LOSS
85
POWER LOSS
90
85
0
0.5
1
1.5
2
CHARGE CURRENT (A)
2.5
100
3
80
0
Efficiency at DCIN = 20V, BAT = 16V
0.10
EFFICIENCY
VFB ERROR (%)
1000
POWER LOSS
POWER LOSS(mW)
EFFICIENCY (%)
3
100
4012 G02
0.06
95
2.5
0.02
0
–0.02
–0.06
RSENSE = 33mΩ
RIN = 3.01k
1
1.5
2
CHARGE CURRENT (A)
0.04
–0.04
85
0.5
2.5
LTC4012 TEST CIRCUIT
0.08
0
1
1.5
2
CHARGE CURRENT (A)
VFB Line Regulation
10000
90
0.5
4012 G01
100
80
1000
POWER LOSS(mW)
EFFICIENCY
90
POWER LOSS(mW)
EFFICIENCY (%)
95
80
10000
RSENSE = 33mΩ
RIN = 3.01k
–0.08
3
100
–0.10
10
5
4012 G03
20
25
15
CLP PIN VOLTAGE (V)
30
4012 G04
2
250
RON (Ω)
225
200
175
LOAD
STATE
150
1A
12.1V
1A
3A
RECONNECT
DISCONNECT
TIME (1ms/DIV)
CLP = 20V
VOUT = 12.3V
125
100
75
1
2A
0
5
20
15
10
BATTERY VOLTAGE (V)
25
4012 G05
4012 G06
CHARGE CURRENT ERROR (%)
BATTERY VOLTAGE
(500mV/DIV)
CLP = BAT + 3V
(CLP ≥ 6V)
275
Charge Current Accuracy
Battery Load Dump
FBDIV Pin RON vs Battery Voltage
300
0
DCIN = 24V
RPROG = 35.7k
–1
–2
DCIN = 12V
RPROG = 26.7k
–3
–4
RSENSE = 33mΩ
RIN = 3.01k
–5
–6
0
2
4
6 8 10 12 14 16 18 20 22 24
BATTERY VOLTAGE (V)
4012 G07
4012fa
LTC4012/
LTC4012-1/LTC4012-2
Typical Performance Characteristics
(TA = 25°C unless otherwise noted. L = IHLP-2525 6.8µH)
Charge Current Line Regulation
ICHG = 2A
0
ICHG = 3A
–0.2
–0.3
–0.5
2.5
ICHG = 2A
2.0
1.5
ICHG = 1A
1.0
0.5
ICHG
1.5
1.0
0.5
2.5A BULK CHARGE
2.1A INPUT CURRENT LIMIT
0
DCIN = 20V
RSENSE = 33mΩ
RIN = 3.01k
–0.5
11.0
25
15
10
20
DCIN PIN VOLTAGE (V)
5
IIN
2.0
0
–0.4
2.5
CURRENT (A)
0.1
3.0
ICHG = 3A
3.0
CHARGE CURRENT (A)
CHARGE CURRENT ERROR (%)
BAT = 6V
0.4 RSENSE = 33mΩ
RIN = 3.01k
0.3
ICHG = 1A
0.2
–0.1
Input Current Limit
Charge Current Load Regulation
3.5
0.5
11.4
–0.5
12.6
11.8
12.2
BATTERY VOLTAGE (V)
–1.0
13.0
ICL STATE
0
0.5
1.0
1.5
SYSTEM LOAD (A)
2.5
4012 G09
4012 G08
PWM Soft-Start
4012 G10
PWM Frequency vs Duty Cycle
Gate Drive Non-Overlap
600
EXTERNAL FET DRIVE (1V/DIV)
ITH
1V/DIV
PROG
1V/DIV
SHDN
5V/DIV
BGATE
TGATE
4012 G11
ICHG = 750mA
500
PWM FREQUENCY (kHz)
ICHG
2A/DIV
TIME (500µs/DIV)
2.0
4012 G12
TIME (80ns/DIV)
400
300
200
CLP = 6V
CLP = 12V
CLP = 20V
CLP = 25V
100
0
0
20
40
60
DUTY CYCLE (%)
100
80
4012 G13
PWM Frequency
vs Charge Current
25
600
PWM FREQUENCY (kHz)
BATTERY CURRENT (µA)
BAT = 5V
500
BAT = 12V
400
CLP = 15V
RSENSE = 33mΩ
RIN = 3.01k
300
200
0
0.5
1.0
1.5
2.0
CHARGE CURRENT (A)
DC1256-CLASS
APPLICATION
DCIN = 0V
20
2.5
3.0
LTC4012,
ALL PINS
DCIN = 0V
10
4012 G14
0
VGS = 0V
PFET VGS (1V/DIV)
IDCIN, REVERSE
(5A/DIV)
15
0A
LTC4012,
BAT PINS
DCIN = 20V
5
BAT = 14.5V
100
0
INFET Response Time to
DCIN Short to Ground
Battery Shutdown Current
0
5
20
10
15
BATTERY VOLTAGE (V)
25
TIME (1µs/DIV)
DCIN = 15V
INFET = Si7423DN
IOUT = 20V, top gate
transition losses increase rapidly to the point that using
a topside NFET with higher RDS(ON) but lower CRSS can
actually provide higher efficiency. If the charger will be
operated with a duty cycle above 85%, overall efficiency
is normally improved by using a larger top FET.
The synchronous (bottom) FET losses are greatest at high
input voltage or during a short circuit, which forces a low
side duty cycle of nearly 100%. Increasing the size of this
FET lowers its losses but increases power dissipation in the
LTC4012. Using asymmetrical FETs will normally achieve
cost savings while allowing optimum efficiency.
Select FETs with BVDSS that exceeds the maximum VCLP
voltage that will occur. Both FETs are subjected to this level
of stress during operation. Many logic-level MOSFETs are
limited to 30V or less.
The LTC4012 uses an improved adaptive TGATE and
BGATE drive that is insensitive to MOSFET inertial delays,
td(ON/OFF), to avoid overlap conduction losses. Switching
characteristics from power MOSFET data sheets apply
only to a specific test fixture, so there is no substitute for
bench evaluation of external FETs in the target application.
In general, MOSFETs with lower inertial delays will yield
higher efficiency.
Diode Selection
A Schottky diode in parallel with the bottom FET and/or
top FET in an LTC4012 application clamps SW during the
non-overlap times between conduction of the top and
bottom FET switches. This prevents the body diode of the
MOSFETs from forward biasing and storing charge, which
could reduce efficiency as much as 1%. One or both diodes
can be omitted if the efficiency loss can be tolerated. A 1A
Schottky is generally a good size for 3A chargers due to the
low duty cycle of the non-overlap times. Larger diodes can
actually result in additional efficiency (transition) losses
due to larger junction capacitance.
Loop Compensation and Soft-Start
The three separate PWM control loops of the LTC4012
can be compensated by a single set of components attached between the ITH pin and GND. As shown in the
typical LTC4012 application, a 6.04k resistor in series
with a capacitor of at least 0.1µF provides adequate loop
compensation for the majority of applications.
4012fa
23
LTC4012/
LTC4012-1/LTC4012-2
Applications Information
The LTC4012 can be soft-started with the compensation
capacitor on the ITH pin. At start-up, ITH will quickly rise
to about 0.25V, then ramp up at a rate set by the compensation capacitor and the 40µA ITH bias current. The
full programmed charge current will be reached when ITH
reaches approximately 2V. With a 0.1µF capacitor, the time
to reach full charge current is usually greater than 1.5ms.
This capacitor can be increased if longer start-up times
are required, but loop bandwidth and dynamic response
will be reduced.
INTVDD Regulator Output
Bypass the INTVDD regulator output to GND with a low
ESR X5R or X7R ceramic capacitor with a value of 0.47µF
or larger. The capacitor used to build the BOOST supply
(C2 in Figure 11) can serve as this bypass. Do not draw
more than 30mA from this regulator for the host system,
governed by IC power dissipation.
Calculating IC Power Dissipation
The user should ensure that the maximum rated junction
temperature is not exceeded under all operating conditions.
The thermal resistance of the LTC4012 package (θJA) is
37°C/W, provided the Exposed Pad is in good thermal
contact with the PCB. The actual thermal resistance in the
application will depend on forced air cooling and other heat
sinking means, especially the amount of copper on the PCB
to which the LTC4012 is attached. The following formula
may be used to estimate the maximum average power dissipation PD (in watts) of the LTC4012, which is dependent
upon the gate charge of the external MOSFETs. This gate
charge, which is a function of both gate and drain voltage
swings, is determined from specifications or graphs in the
manufacturer’s data sheet. For the equation below, find the
gate charge for each transistor assuming 5V gate swing and
a drain voltage swing equal to the maximum VCLP voltage.
Maximum LTC4012 power dissipation under normal operating conditions is then given by:
PD = DCIN(3mA + IDD + 665kHz(QTGATE + QBGATE))
– 5IDD
where:
IDD = Average external INTVDD load current, if any
QTGATE = Gate charge of external top FET in Coulombs
QBGATE = Gate charge of external bottom FET in
Coulombs
PCB Layout Considerations
To prevent magnetic and electrical field radiation and
high frequency resonant problems, proper layout of the
components connected to the LTC4012 is essential. Refer
to Figure 12. For maximum efficiency, the switch node
rise and fall times should be minimized. The following
PCB design priority list will help insure proper topology.
Layout the PCB using this specific order.
1. Input capacitors should be placed as close as possible
to switching FET supply and ground connections with
the shortest copper traces possible. The switching
FETs must be on the same layer of copper as the input
capacitors. Vias should not be used to make these
connections.
2. Place the LTC4012 close to the switching FET gate
terminals, keeping the connecting traces short to
produce clean drive signals. This rule also applies to IC
supply and ground pins that connect to the switching
FET source pins. The IC can be placed on the opposite
side of the PCB from the switching FETs.
SWITCH NODE
L1
VIN
CIN
HIGH
FREQUENCY
CIRCULATING
PATH
RSENSE
VBAT
COUT
D1
+
BAT
ANALOG
GROUND
GND
SWITCHING GROUND
4012 F12
SYSTEM
GROUND
Figure 12. High Speed Switching Path
4012fa
24
LTC4012/
LTC4012-1/LTC4012-2
Applications Information
3. Place the inductor input as close as possible to the
switching FETs. Minimize the surface area of the switch
node. Make the trace width the minimum needed to
support the programmed charge current. Use no copper fills or pours. Avoid running the connection on
multiple copper layers in parallel. Minimize capacitance
from the switch node to any other trace or plane.
4. Place the charge current sense resistor immediately
adjacent to the inductor output, and orient it such
that current sense traces to the LTC4012 are not long.
These feedback traces need to be run together as a
single pair with the smallest spacing possible on any
given layer on which they are routed. Locate any filter
component on these traces next to the LTC4012, and
not at the sense resistor location.
5. Place output capacitors adjacent to the sense resistor
output and ground.
6. Output capacitor ground connections must feed into
the same copper that connects to the input capacitor
ground before connecting back to system ground.
7. Connection of switching ground to system ground,
or any internal ground plane, should be single-point.
If the system has an internal system ground plane,
a good way to do this is to cluster vias into a single
star point to make the connection.
8. Route analog ground as a trace tied back to the LTC4012
GND paddle before connecting to any other ground.
Avoid using the system ground plane. A useful CAD
technique is to make analog ground a separate ground
net and use a 0Ω resistor to connect analog ground
to system ground.
9. A good rule of thumb for via count in a given high
current path is to use 0.5A per via. Be consistent when
applying this rule.
10. If possible, place all the parts listed above on the same
PCB layer.
11. Copper fills or pours are good for all power connections
except as noted above in Rule 3. Copper planes on
multiple layers can also be used in parallel. This helps
with thermal management and lowers trace inductance,
which further improves EMI performance.
12. For best current programming accuracy, provide a
Kelvin connection from RSENSE to CSP and CSN. See
Figure 13 for an example.
13. It is important to minimize parasitic capacitance on
the CSP and CSN pins. The traces connecting these
pins to their respective resistors should be as short
as possible.
DIRECTION OF CHARGING CURRENT
RSENSE
4012 F13
TO CSP
RIN
TO CSN
RIN
Figure 13. Kelvin Sensing of Charge Current
4012fa
25
LTC4012/
LTC4012-1/LTC4012-2
Package Description
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.00 REF
2.45 ± 0.05
2.45 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
0.75 ± 0.05
R = 0.05
TYP
R = 0.115
TYP
19 20
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
4.00 ± 0.10
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 s 45°
CHAMFER
BOTTOM VIEW—EXPOSED PAD
1
2.00 REF
2.45 ± 0.10
2
2.45 ± 0.10
(UF20) QFN 01-07 REV A
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4012fa
26
LTC4012/
LTC4012-1/LTC4012-2
Revision History
REV
DATE
DESCRIPTION
PAGE NUMBER
A
3/10
I-Grade Parts Added. Reflected Throughout the Data Sheet
1 to 28
4012fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC4012/
LTC4012-1/LTC4012-2
Typical Application
12.6V 4 Amp Charger
FROM
ADAPTER
15V AT 4A
R7
25mΩ
Q5
C1
0.1µF
R
D1
7
4
3
CHRG
DCIN
INFET
CLP
CLN
C4
0.1µF
2
20
TGATE
LTC4012
18
SW
5
17
INTVDD
ACP
8
16
ICL
BGATE
6
SHDN
21
GND
15
12
ITH
CSP
C2
0.1µF
R4
6.04k
13
C3
4.7nF
R5
26.7k
Q1
CSN
14
11
BAT
10
FBDIV
PROG
VFB
D5
C8
10µF
R15
0Ω*
C5
0.1µF
19
TO/FROM
MCU
R8
5.1k
1
BOOST
BULK
CHARGE
POWER TO SYSTEM
R1
3k
9
R6
53.6k
D3
Q2
D4
Q3
C6
2µF
L1
4.7µH
OR
R14
100k
D6
18V
ZENER
Q4
TO POWER SYSTEM LOAD
WHEN ADAPTER IS NOT
PRESENT, USE
SCHOTTKY DIODE D5 OR
THE COMBINATION OF R14,
D6 AND Q4
R9 3.01k
R11
25mΩ
R10 3.01k
R12
294k
C10
10pF
R13
31.2k
C9
10µF
+
12.6V
Li-Ion
BATTERY
4012 TA03
D3: CMDSH-3
D4: MBR230LSFT1
Q1: 2N7002
Q2, Q3: Si7212DN OR SiA914DJ
OR Si4816BDY (OMIT D4)
Q4, Q5: Si7423DN
L1: 1HLP-2525CZER4R7M11
*: SEE TGATE BOOST SUPPLY IN
APPLICATIONS INFORMATION
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC4006
Small, High Efficiency, Fixed Voltage, Lithium-Ion
Battery Chargers with Termination
Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current
Limit and Thermistor Sensor, 16-pin SSOP Package
LTC4007
High Efficiency, Programmable Voltage, Lithium-Ion
Battery Charger with Termination
Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current
Limit, Thermistor Sensor and Indicator Outputs
LTC4008/LTC4008-1
High Efficiency, Programmable Voltage/Current Battery
Chargers
Constant-Current/Constant-Voltage Switching Regulator, Resistor
Voltage/Current Programming, Thermistor Sensor and Indicator
Outputs, AC Adapter Current Limit (Omitted on 4008-1)
LTC4009/LTC4009-1
LTC4009-2
High Efficiency, Multichemistry Battery Charger
Constant-Current/Constant-Voltage Switching Regulator in a 20-Lead
QFN Package, AC Adapter Current Limit, Indicator Outputs
LTC4411
2.6A Low Loss Ideal Diode
No External MOSFET, Automatic Switching Between DC sources, 140mΩ
On Resistance in ThinSOTTM package
LTC4412/LTC4412HV
Low Loss PowerPath Controllers
Very Low Loss Replacement for Power Supply ORing Diodes Using
Minimal External Complements, Operates up to 28V (36V for HV)
LTC4413
Dual 2.6A, 2.5V to 5.5V Ideal Diodes
Low Loss Replacement for ORing Diodes, 100mΩ On Resistance
LTC4414
36V, Low Loss PowerPath Controller for Large PFETs
Low Loss Replacement for ORing Diodes, Operates up to 36V
LTC4416
Dual Low Loss PowerPath Controllers
Low Loss Replacement for ORing Diodes, Operates up to 36V, Drives
Large PFETs, Programmable, Autonomous Switching
4012fa
28 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
LT 0610 • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2009
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