LTC4040
2.5A Battery Backup
Power Manager
Features
Description
Step-Up Backup Supply and Step-Down Battery
Charger
nn 6.5A Switches for 2.5A Backup from 3.2V Battery
nn Input Current Limit Prioritizes Load Over Charge
Current
nn Input Disconnect Switch Isolates Input During Backup
nn Automatic Seamless Switch-Over to Backup Mode
nn Input Power Loss Indicator
nn System Power Loss Indicator
nn Pin Selectable Battery: Li-Ion (3.95V/4.0V/4.05V/4.1V)
or LiFePO4 (3.45V/3.5V/3.55V/3.6V)
nn Optional OVP Circuitry Protects Device to >60V
nn Constant Frequency Operation
nn Low Profile (0.75mm) 24-Lead 4mm × 5mm QFN Package
The LTC®4040 is a complete 3.5V to 5.5V supply rail battery backup system. It contains a high current step-up
DC/DC regulator to back up the supply from a single-cell
Li-Ion or LiFePO4 battery. When external power is available, the step-up regulator operates in reverse as a stepdown battery charger.
nn
The LTC4040’s adjustable input current limit function
reduces charge current to protect the main supply from
overload while an external disconnect switch isolates the
external supply during backup. When the input supply
drops below the adjustable PFI threshold, the 2.5A boost
regulator delivers power from the battery to the system
output.
An optional input overvoltage protection (OVP) circuit
protects the LTC4040 from high voltage damage at the
VIN pin. One logic input selects either the Li-Ion or the
LiFePO4 battery option, and two other logic inputs program the battery charge voltage to one of four levels suitable for backup applications. The LTC4040 is available in a
low profile (0.75mm) 24-Lead 4mm × 5mm QFN package.
Applications
Fleet and Asset Tracking
Automotive GPS Data Loggers
nn Automotive Telematics Systems
nn Toll Collection Systems
nn Security Systems
nn USB Powered Devices
nn
nn
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
and PowerPath is a trademark of Analog Devices, Inc. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 6522118, 6570372, 6700364,
8139329.
Typical Application
Normal
to Backup
Transition
Normal
to Backup
ModeMode
Transition
Waveform
4.5V Backup Application with 4.22V PFI Threshold
(Charge Current Setting: 1A, Input Current Limit Setting: 2A)
1A
4.5V
2.2µF
60.4k
VIN CLN
OVSNS
PFI
FAULT
PFO
RST
CHRG
CLPROG
IGATE
LTC4040
CHGOFF BSTOFF
VSYS
BSTFB
RSTFB
SW
BAT
324k
2.2µH
3
VIN
2
VBAT = 3.3V
ISYS = 1A
CSYS = 100µF
RPROG = 2k
IBAT
1
2k
VSYS
+
NTC
LiFePO4
3.6V
–1
–0.4
8
6
4
2
0
0
NTC
F0 F1 F2 PROG
10
VSYS
4
10µF
VIN
Waveform (LiFePO4 App.)
CURRENT (A)
154k
1500k
SYSTEM
LOAD
100µF
VOLTAGE (V)
12mΩ
4.5V INPUT
SUPPLY
5
0
0.4
TIME (ms)
0.8
–2
1.2
4040 TA01b
4040 TA01a
4040fb
For more information www.linear.com/LTC4040
1
LTC4040
PF0
SW
SW
BAT
TOP VIEW
VSYS
24 23 22 21 20
VSYS 1
19 PFI
PROG 2
18 BSTFB
CLPROG 3
17 NTC
25
GND
CHGOFF 4
BSTOFF 5
16 OVSNS
15 IGATE
VIN 6
14 F0
9 10 11 12
13 F1
F2
8
RST
CLN 7
RSTFB
VIN (Transient) t < 1ms, Duty Cycle < 1%..... –0.3V to 7V
VIN (Steady State), BAT, CLN, VSYS,
BSTFB, NTC, OVSNS,
CHRG, PFO, RST, FAULT................................ –0.3V to 6V
F0, F1, F2, BSTOFF, RSTFB,
PFI, CHGOFF .......–0.3V to Max (VIN, VBAT, VSYS) + 0.3V
IOVSNS................................................................... ±10mA
ICHRG , IPFO, IRST, IFAULT...........................................10mA
IPROG, ICLPROG....................................................... 1.1mA
Operating Junction Temperature Range
(Note 3)....................................................... –40 to 125°C
Storage Temperature Range....................... –65 to 125°C
Pin Configuration
CHRG
(Notes 1, 2)
FAULT
Absolute Maximum Ratings
UFD PACKAGE
24-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
Order Information
http://www.linear.com/product/LTC4040#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4040EUFD#PBF
LTC4040EUFD#TRPBF
4040
24-Lead (4mm × 5mm × 0.75mm) Plastic QFN –40°C to 125°C
LTC4040IUFD#PBF
LTC4040IUFD#TRPBF
4040
24-Lead (4mm × 5mm × 0.75mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
4040fb
For more information www.linear.com/LTC4040
LTC4040
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 3) VIN = 5V, VBAT = 3.6V, RPROG = 2k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Input Voltage Range
VBAT
Battery Voltage Range (Backup Boost Input)
IINQ
VIN Quiescent Current
Normal Mode (VPFI = 2V), Battery Charger Timed Out
Shutdown (BSTOFF = CHGOFF=1)
IBATQ
BAT Quiescent Current
Normal Mode (VPFI = 2V), Battery Charger Timed Out
l
Backup Mode (VIN = VPFI = 0V), No System Load
Shutdown (BSTOFF = CHGOFF = 1)
l
TYP
MAX
UNITS
3.5
5.5
V
2.7
5
V
570
3.5
7
µA
µA
45
40
1.5
70
3
µA
µA
µA
Battery Charger
VCHG
ICHG
BAT Regulated Output Voltage for LiFePO4
Option (F2 = 0)
F2 = 0, F1 = 0, F0 = 0
F2 = 0, F1 = 0, F0 = 1
F2 = 0, F1 = 1, F0 = 0
F2 = 0, F1 = 1, F0 = 1
l
l
l
l
3.42
3.47
3.52
3.57
3.45
3.50
3.55
3.60
3.48
3.53
3.58
3.63
V
V
V
V
BAT Regulated Output Voltage for Li-Ion
Option (F2 = 1)
F2 = 1, F1 = 0, F0 = 0
F2 = 1, F1 = 0, F0 = 1
F2 = 1, F1 = 1, F0 = 0
F2 = 1, F1 = 1, F0 = 1
l
l
l
l
3.92
3.97
4.02
4.07
3.95
4.00
4.05
4.10
3.98
4.03
4.08
4.13
V
V
V
V
Regulated Battery Charge Current
RPROG = 2k
950
1000
1050
mA
VSYS-to-VBAT Differential Undervoltage
Lockout Threshold (Falling)
40
50
60
mV
VSYS-to-BAT Differential Undervoltage
Lockout Threshold (Rising)
125
145
165
mV
VPROG
PROG Pin Servo Voltage
800
mV
hPROG
Ratio of Battery Current to PROG Pin Current
2500
mA/
mA
ITRKL
Trickle Charge Current
VBAT = 2.5V, RPROG = 2k
125
mA
PROG Pin Servo Voltage at Trickle Charge
VBAT = 2.5V, RPROG = 2k
Input Current Limit Threshold Voltage
VIN – VCLN
Input Current Limit Amplifier Gain
Ratio of CLPROG Voltage to (VIN – VCLN)
CLN Input Bias Current
VCLN = VIN
VRECHG
Recharge Battery Threshold Voltage
Threshold Voltage Relative to VCHG if F2 = 0 and F1 = 1
Threshold Voltage Relative to VCHG All Other Cases
94.2
96.7
tTERMINATE
Safety Timer Termination Period
Timer Starts When VBAT = VCHG
F2 = 1 (Li-Ion)
F2 = 0 (LiFePO4)
VLOWBAT
Low Battery Threshold Voltage for Trickle Charge VBAT Rising
�VLOWBAT
Low Battery Hysteresis
tBADBAT
Bad-Battery Termination Time
VBAT < (VLOWBAT − ΔVLOWBAT)
VC/8
End-of-Charge Indication
PROG Pin Average Voltage
fOSC(BUCK)
Step-Down (Buck) Converter Switching
Frequency
Normal Mode (VPFI > 1.21V)
RP(BUCK)
High Side Switch On-Resistance
Normal Mode (VPFI > 1.21V)
130
mΩ
RN(BUCK)
Low Side Switch On-Resistance
Normal Mode (VPFI > 1.21V)
120
mΩ
ILIM(BUCK)
PMOS Switch Current Limit
4.3
A
ACLPROG
100
l
23.5
25
mV
26.5
32
mV
V/V
300
nA
95
97.5
95.8
98.3
%
%
3.7
1.85
4.25
2.13
5
2.5
Hours
Hours
2.75
2.85
2.95
150
0.47
0.54
V
mV
0.64
Hours
90
100
110
mV
1.96
2.25
2.65
MHz
3
4040fb
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3
LTC4040
Electrical
Characteristics
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 3) VIN = 5V, VBAT = 3.6V, RPROG = 2k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCOLD
Cold Temperature Fault Threshold Voltage
Rising Voltage Threshold
Hysteresis
75.0
76.5
1.5
78
%VIN
%VIN
VHOT
Hot Temperature Fault Threshold Voltage
Falling Voltage Threshold
Hysteresis
33.4
34.9
1.73
36.4
%VIN
%VIN
VDIS
NTC Disable Threshold Voltage
Falling Threshold
Hysteresis
0.7
1.7
50
2.7
%VIN
mV
INTC
NTC Leakage Current
20
nA
NTC
–20
Backup Mode Boost Switching Regulator
VBSTFB
BSTFB Reference Voltage
0.82
V
IBSTFB
BSTFB Input Bias Current
–20
20
nA
VSYS
Step-up (Boost) Converter Output Voltage
Range
3.5
5
V
fOSCBST
Step-Up Converter Switching Frequency
ILIMBST
NMOS Switch Current Limit
RPBST
Boost High Side Switch On-Resistance
75
mΩ
RNBST
Boost Low Side Switch On-Resistance
70
mΩ
VOVSD
VSYS Overvoltage Shutdown Threshold
l
Backup Mode (VPFI < 1.17V)
VSYS Rising
0.78
0.98
1.125
1.33
5.5
6.5
7.5
5.3
Overvoltage Shutdown Hysteresis
VUVLO
DMAX
BAT Pin Undervoltage Lockout
0.8
5.5
5.7
100
VBAT Falling
2.45
BAT Pin Undervoltage Lockout Hysteresis
150
Maximum Boost Duty Cycle
88
MHz
A
V
mV
2.6
V
mV
93
%
NMOS Switch Leakage
BSTOFF = 1, CHGOFF = 1
1
µA
PMOS Switch Leakage
BSTOFF = 1, CHGOFF = 1
1
µA
Reset Comparator
RSTFB Threshold (Falling)
l
0.72
RSTFB Hysteresis
RSTFB Pin Leakage Current
0.74
0.76
20
VRSTFB = 0.9V
–50
RST Delay (RSTFB Rising)
V
mV
50
232
nA
ms
Power-Fail Comparator
PFI Input Threshold (Falling Edge)
Initiates Backup Mode
l
1.17
PFI Input Hysteresis
1.19
1.21
30
–100
V
mV
PFI Pin Leakage Current
VPFI = 1.3V
PFI Delay to PFO
PFI Falling
0.5
100
nA
µs
PFO Pin Leakage Current
VPFO = 5V
10
µA
PFO Pin Output Low Voltage
IPFO = 5mA
65
mV
Logic Input (CHGOFF, BSTOFF, F0, F1, F2)
VIL
Logic Low Input Voltage
l
l
0.4
V
VIH
Logic High Input Voltage
IIL
Logic Low Input Leakage
–1
1
µA
IIH
Logic High Input Leakage
–1
1
µA
4
1.2
V
4040fb
For more information www.linear.com/LTC4040
LTC4040
Electrical
Characteristics
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 3) VIN = 5V, VBAT = 3.6V, RPROG = 2k, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Open-Drain Output (CHRG, RST, FAULT)
Pin Leakage Current
V = 5V
Pin Output Low Voltage
I = 5mA
1
65
µA
mV
Overvoltage Protection
VOV(CUTOFF) Overvoltage Protection Threshold
VOVGT
IGATE Output Voltage Active
VOVGT(LOAD) IGATE Voltage Under Load
IOVSNSQ
Rising Threshold, ROVSNS = 6.2k
6.1
Input Voltage < VOV(CUTOFF)
5V Through 6.2k Into OVSNS, IIGATE = 1µA
6.7
V
1.88 •
VOVSNS
12
V
8.6
V
OVSNS Quiescent Current
VOVSNS = 5V
40
µA
OVSNS Quiescent Current at Shutdown
BSTOFF = H, CHGOFF = H
25
µA
IGATE Time to Reach Regulation
CIGATE = 2.2nF
3.5
ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
8
6.4
Note 3: The LTC4040E is tested under pulsed load conditions such that
TJ ≈ TA. The LTC4040E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process control. The
LTC4040I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The junction temperature (TJ in °C) is calculated from
the ambient temperature (TA, in °C) and power dissipation (PD, in watts)
according to the formula:
TJ = TA + (PD • θJA)
where the package thermal impedance θJA = 43°C/W.
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
4040fb
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5
LTC4040
Typical Performance Characteristics
(Li–Ion)with
withDifferent
IBAT
BAT vs VBAT
BAT (Li-Ion)
Different
ChargeSettings
Voltage Settings
Charge
Voltage
TA = 25°C, unless otherwise noted.
IBAT vs VBAT (LiFePO4) with
Different Charge Voltage Settings
1000
1000
100
Step–Down
Step-Down Charger Efficiency
vs VBAT
BAT
95
VSYS = 5V
RPROG = 2k
F2 = 1, F1 = 0, F0 = 0
F2 = 1, F1 = 0, F0 = 1
F2 = 1, F1 = 1, F0 = 0
F2 = 1, F1 = 1, F0 = 1
3
3.3
3.6
VBAT (V)
400
3.9
0
2.7
4.2
3000
VSYS = 5V
F2, F1, F0 = 1
RPROG = 0.8k
IBAT (mA)
1500
0
2.7
3.0
3.3
3.6
VBAT (V)
3.9
2.30
200
RESISTANCE (mΩ)
FREQUENCY (MHz)
2.10
1.90
1.80
–45
VIN = 5.5V
VIN = 5.0V
VIN = 3.6V
VBAT = 3.2V
–10
25
60
TEMPERATURE (°C)
130
4040 G07
6
3.90
3.80
3.75
3.5
3.7
4040 G05
4040 G06
Step-Down Charger NMOS
90°C
140
25°C
130°C
–10°C
120
overRDS(ON)
On-Resistance
vs VSYS
Step–Down
Charger
NMOS
vs
VSYS over Temperature
Temperature
180
60°C
80
3.6
200
130°C
160
VSYS = 5V
F2 = F1 = F0 = 1
3.70
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
On-Resistance
vs VSYS
overRds(ON)
Step–Down
Charger
PMOS
Temperature
vs
VSYS over Temperature
–45°C
160
90°C
140
60°C
120
25°C
–10°C
100
100
95
3.95
3.85
3.1
3.3
VBAT (V)
180
2.20
2.00
4.00
Step-Down Charger PMOS
Step-Down Charger Oscillator
Step–Down
Frequency vs Temperature
3.8
4
4.2 4.4
VSYS (V)
4040 G03
4.05
RPROG = 4k
4040 G04
4.0
4.10
RPROG = 1.33k
2.9
3.8
4.15
1500
0
2.7
4.2
3.4
3.6
VBAT (V)
4.20
RPROG = 1k
500
3.2
VSYS = 5V
F2 = F1 = F0 = 1
Battery
BatteryCharge
ChargeVoltage
Voltage(Li-Ion)
(Li-Ion)
vsvsTemperature
Temperature
RPROG = 2k
RPROG = 4K
3.0
4040 G02
1000
RPROG = 2k
500
60
2.8
3.7
2000
RPROG = 1.33k
1000
3.5
RPROG = 0.8k
RPROG = 1k
RPROG = 4k
RPROG = 2k
RPROG = 1.33k
RPROG = 1k
RPROG = 0.8k
75
65
VSYS = 5V
F2 = 0, F1 = F0 = 0
2500
2000
80
IBAT vs VBAT (LiFePO4) with
Different PROG
PROGResistor
ResistorValues
Values
IBAT (mA)
2500
3.1
3.3
VBAT (V)
4040 G01
vs VVBAT
(Li–Ion)with
withDifferent
IIBAT
BAT vs
BAT (Li-Ion)
Different
PROGValues
Resistor Values
PROG
Resistor
3000
2.9
85
70
F2 = 0, F1 = 0, F0 = 0
F2 = 0, F1 = 0, F0 = 1
F2 = 0, F1 = 1, F0 = 0
F2 = 0, F1 = 1, F0 = 1
200
VBAT (V)
0
2.7
600
RESISTANCE (mΩ)
200
90
EFFICIENCY (%)
600
400
VSYS = 5V
RPROG = 2k
800
IBAT (mA)
IBAT (mA)
800
4.6
4.8
5.0
4040 G08
80
3.6
–45°C
3.8
4
4.2 4.4
VSYS (V)
4.6
4.8
5.0
4040 G09
4040fb
For more information www.linear.com/LTC4040
LTC4040
Typical Performance Characteristics
Li-Ion Battery
Li–Ion
Battery Charging
Charging Profile
Profile
VBAT
3.60
3.6
1000
3.5
800
3.4
600
600
IBAT
VSYS = 5V
400
RPROG = 2k
F2 = F1 = F0 = 1
200
3.40
3.20
0
1
2
3
4
TIME (h)
5
VSYS = 5V
RPROG = 2k
F2 = 0, F1 = F0 = 1
3.3
3.1
0
0.5
1
1.5
2 2.5
TIME (h)
3
3.5
4040 G11
Charge Current Reduction Due to
Input Current Limit Set by RSS
Normal
Normal to
to Backup
Backup Mode
Mode
Transition
Transition Waveform
Waveform (Li-Ion)
(Li–Ion)
VIN
4
VOLTAGE (V)
VSYS = 5V
RPROG = 2k
RS = 12 mΩ
IBAT
3
0
IBAT
500
1000
1500
2000
SYSTEM LOAD CURRENT (mA)
0
–1
–500
2500
–250
0
250
500
TIME (µs)
4040 G12
PROG
PROG Voltage
Voltage Transient
Transient Response
Response
by
to System Step Load
VSYS
VOLTAGE (V)
2
1.0
4
0.5
3
2
IBAT
1
1
0
5
VIN
–1
–200–100 0
ZERO
0
–1
100 200 300 400 500 600 700
TIME (ms)
VBAT = 3.7V
RPROG = 2k
RS = 12mΩ
6
5
VPROG
4
3
0.0
ISYS
–0.5
2
IBAT
–1.0
1
0
–1.5
–2.0
CURRENT (A)
3
1.5
CURRENT (A)
VBAT = 3.7V
RPROG = 2k
ISYS = 1A
6
PROG VOLTAGE (V)
6
4
–2
1000
750
4040 G13
Backup to
to Normal
Normal Mode
Mode
Backup
Transition Waveform
Waveform
Transition
5
6
2
0
0
8
4
2
1
500
10
VBAT = 3.6V
ISYS = 1A
RPROG = 2k
CSYS = 100µF
CURRENT (A)
CURRENT (mA)
VSYS
5
2000
1000
12
6
TOTAL INPUT CURRENT
1500
0
4.5
4
4040 G10
2500
400
200
3.2
0
6
1200
CHARGE CURRENT (mA)
1000
800
3.80
3.00
3.7
CHARGE CURRENT (mA)
BATTERY VOLTAGE (V)
4.00
LiFePO
LiFePO44 Battery
Battery Charging
Charging Profile
Profile
1200
BATTERY VOLTAGE (V)
4.20
TA = 25°C, unless otherwise noted.
0
200
4040 G14
400
600
800
TIME (µs)
1000
–1
1200
4040 G15
4040fb
For more information www.linear.com/LTC4040
7
LTC4040
Typical Performance Characteristics
5.10
Back–Up
Back-Up Boost Output Voltage
(V
(VSYS
vs Temperature
Temperature
SYS)) vs
Backup Boost Oscillator
Frequency vs Temperature
1.15
5.00
FREQUENCY (MHz)
1.10
4.90
VSYS (V)
TA = 25°C, unless otherwise noted.
4.80
4.70
VSYS = Set to 5V
VBAT = 3.6V
ISYS = 1mA
4.60
4.50
–45
–10
1.05
1.00
VBAT = 4.1V
VBAT = 3.6V
VBAT = 2.7V
VSYS = 5V
0.95
25
60
TEMPERATURE (°C)
95
0.90
–45
130
–10
25
60
TEMPERATURE (°C)
95
130
4040 G16
4040 G17
Backup Boost Maximum
Duty Cycle vs Temperature
Backup Boost Efficiency
vs Load Current
90
100
VBAT = 3.6V
90
80
EFFICIENCY (%)
MAX DUTY CYCLE (%)
88
86
84
82
70
60
50
40
30
VSYS SET TO 5V
VBAT = 3.2V
VBAT = 3.7V
VBAT = 4.1V
20
10
80
–45
–10
25
60
TEMPERATURE (°C)
95
0
130
1
10
100
LOAD CURRENT (mA)
4040 G18
110
100
Backup Boost
Boost PMOS
PMOS ROn-Resistance
Backup
DS(ON)
vs VVSYS
over Temperature
Temperature
vs
SYS over
100
90°C
RESISTANCE (mΩ)
RESISTANCE (mΩ)
60°C
70
25°C
60
–10°C
50
3.5
8
90°C
80
4.1
4.4
VSYS (V)
90
60°C
80
25°C
70
40
–10°C
–45°C
35
VBAT = 4.1V
VBAT = 3.6V
VBAT = 2.7V
30
60
–45°C
3.8
45
SLEEP Mode (Backup)
IBATQ vs Temperature
130°C
130°C
90
4.7
5.0
4040 G20
50
3.5
3k
4040 G19
CURRENT (µA)
110
On-Resistance
Backup Boost NMOS R
DS(ON)
vs VSYS over Temperature
1k
3.8
4.1
4.4
VSYS (V)
4.7
5.0
4040 G21
25
–45
–10
25
60
TEMPERATURE (°C)
95
130
4040 G22
4040fb
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LTC4040
Typical Performance Characteristics
Burst Mode to Constant Frequency
Mode Transition Waveform
Backup Boost Transient
Response to Load Step
VBAT = 3.6V
CSYS = 100µF
L = 2.2µH
5.2
VOLTAGE (V)
6
5.2
5
5.1
4
4.9
3
ISYS
4.8
2
4.7
1
4.6
–0.4
0.0
0.4
0.8
TIME (ms)
6
5
VSYS
5.0
4
3
4.9
ISYS
4.8
2
1
4.7
0
1.6
1.2
7
VBAT = 3.6V
CSYS = 100µF
L = 2.2µH
LOAD CURRENT (A)
5.0
VSYS
5.3
LOAD CURRENT (A)
5.1
7
VOLTAGE (V)
5.3
TA = 25°C, unless otherwise noted.
4.6
–0.4
0.0
0.4
0.8
TIME (ms)
1.2
4040 G23
0
1.6
4040 G24
OVP Module Shutdown Voltage
(Through 6.2k) vs Temperature
OVSNS Pin Quiescent Current
vs Temperature
6.50
50
INPUT = 5V
6.45
CURRENT (µA)
VOLTAGE (V)
45
6.40
6.35
6.30
40
35
6.25
6.20
–45
–10
25
60
95
TEMPERATURE (°C)
130
30
–45
–10
4040 G25
25
60
95
TEMPERATURE (°C)
130
4040 G26
4040fb
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9
LTC4040
Pin Functions
VSYS (Pins 1, 24): System Voltage Output Pin. This pin
is used to provide power to an external load from either
the primary input supply or the backup battery if the primary input supply is not available. In addition to supplying
power to the load, this pin provides power to charge the
battery when input power is available. VSYS should be
bypassed with a low ESR ceramic capacitor of at least
100µF to GND.
PROG (Pin 2): Charge Current Program Pin. An external
resistor from the PROG pin to ground programs the fullscale charge current. At full scale, the PROG pin servos
to 0.8V. The ratio of BAT pin current to PROG pin current
is internally set to 2500.
CLPROG (Pin 3): VSYS Current Monitoring Pin. The ratio
between the CLPROG pin voltage and the differential voltage between VIN and CLN is internally set to 32. Charge
current is reduced when the CLPROG pin voltage reaches
0.8V.
CHGOFF (Pin 4): Disable Pin for the Battery Charger. Tie
this pin to GND to enable the charger or to a voltage above
1.2V to disable it. Do not leave this pin unconnected.
BSTOFF (Pin 5): Disable Pin for the Backup Boost
Converter. Tie this pin to GND to enable the boost backup
or to a voltage above 1.2V to disable backup. Do not leave
this pin unconnected.
VIN (Pin 6): Input Pin. Power can be applied directly to
this pin if the optional overvoltage protection (OVP) feature is not used. For applications where the OVP feature
is required, connect an external N-channel FET between
the power supply output VPWR and this pin.
CLN (Pin 7): Negative terminal pin for an external current limit sense resistor connected between VIN and this
pin. This resistor is used to monitor the current from
VIN to VSYS. The LT4040 reduces charge current in order
to maintain 25mV across this sense resistor. However,
it does not limit the system current if the drop exceeds
25mV.
10
CHRG (Pin 8): Open-Drain Charge Status Output; typically pulled up through a resistor to a reference voltage.
During a battery charging cycle, CHRG is pulled low until
the charge current drops below C/8 when the CHRG pin
becomes high impedance.
FAULT (Pin 9): Open-Drain Fault Status Output; typically
pulled up through a resistor to a reference voltage. This
pin indicates charge cycle fault conditions during a battery charging cycle. A temperature fault or a bad-battery
fault causes this pin to be pulled low. If no fault conditions
exist, the FAULT pin remains high impedance.
RSTFB (Pin 10): Reset Comparator Input. High Impedance
input to an accurate comparator with a 0.74V falling
threshold and 20mV hysteresis. This pin controls the state
of the RST output pin. An external resistor divider is used
between VSYS, RSTFB and GND. It can be the same resistor divider as the BSTFB divider to monitor the system
output voltage VSYS. See the Applications Information
section.
RST (Pin 11): Open-Drain Status Output of the Reset
Comparator. This pin is pulled to ground by an internal
N-channel MOSFET whenever the RSTFB pin falls below
0.74V. Once the RSTFB pin voltage recovers, the pin
becomes high impedance after a 232ms delay.
F2 (Pin 12): Logic Input to Select Battery Chemistry. A
logic high on this pin selects Li-Ion and a logic low selects
LiFePO4. Do not leave this pin unconnected.
F1, F0 (Pins 13, 14): Logic inputs to select one of the four
possible charge voltage settings for each battery chemistry. Do not leave these pins unconnected.
F0
F1
F2 = 1: Li-Ion (V)
F2 = 0: LiFePO4 (V)
0
0
3.95
3.45
1
0
4.00
3.50
0
1
4.05
3.55
1
1
4.10
3.60
4040fb
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LTC4040
Pin Functions
IGATE (Pin 15): Gate Pin for the External N-Channel FETs.
This pin is driven by an internal charge pump to develop
sufficient overdrive to fully enhance the pass transistors.
The first pass transistor is connected between the supply
output VPWR and VIN and is part of the optional overvoltage protection module. The second pass transistor, connected between VIN and VSYS, is mandatory and is used
to disconnect the system from the input supply during
backup mode.
PFI (Pin 19): Power-Fail Input. High impedance input to
an accurate comparator (power-fail) with a 1.19V falling
threshold and 30mV hysteresis. PFI controls the state of
the PFO output pin and sets the input voltage threshold
below which the boost backup is initiated. This threshold
voltage also represents the minimum voltage above which
the step-down battery charger is enabled and the part
allows power to flow from the input to the output through
the external pass transistors.
OVSNS (Pin 16): Overvoltage Protection Sense Input. If
the overvoltage feature is used, the OVSNS pin should be
connected through a 6.2k resistor to an input power connector and the drain of an N-channel MOS pass transistor.
If not, this pin should be shorted to VIN. When voltage is
detected on OVSNS, it draws a small amount of current to
power a charge pump which then provides gate drive to
IGATE to energize the external transistor. When the voltage
on this pin exceeds typically 6V, IGATE is pulled to GND
to disable the pass transistor and protect the LTC4040
from high voltage.
PFO (Pin 20): Open-Drain Power-Fail Status Output. This
pin is pulled to ground by an internal N-channel MOSFET
when the PFI input is below the falling threshold of the
power-fail comparator. Once the PFI input rises above the
rising threshold, this pin becomes high impedance.
NTC (Pin 17): Input to the Thermistor Monitoring Circuits.
The NTC pin connects to a battery’s thermistor to determine if the battery is too hot or too cold to charge. If the
battery’s temperature is out of range, charging is paused
until it re-enters the valid range. A low drift bias resistor
is required from VIN to NTC and a thermistor is required
from NTC to ground. If the NTC function is not desired,
the NTC pin should be grounded.
BSTFB (Pin 18): Feedback Input for the Backup Boost
Regulator. During steady-state backup operation, voltage
on this pin servos to 0.8V.
SW (Pins 21, 22): Power Transmission Pin for the Buck
Switching Charger and the Boost Switching Backup
Converter. A 1µH to 2.2µH inductor should be connected
from SW to BAT.
BAT (Pin 23): Single Cell Li-Ion or LiFePO4 Battery Pin.
Depending on the availability of input power, the battery
will either deliver power to VSYS via the boost converter
or be charged from VSYS via the buck charger. BAT should
be bypassed with a low ESR ceramic capacitor of at least
10µF to GND.
GND (Exposed Pad Pin 25): The exposed pad must
be soldered to the PCB to provide a low electrical and
thermal impedance connection to the printed circuit
board’s ground. A continuous ground plane on the second layer of a multilayer printed circuit board is strongly
recommended.
4040fb
For more information www.linear.com/LTC4040
11
LTC4040
Block Diagram
INPUT
VPWR
RS
MN1
SYSTEM
MN2
6.2k
15
IGATE
16
6
7
VIN
VSYS
1, 24
CLN
OVSNS
6V
–+ +
–
RST
CP1
+
–
OVERVOLTAGE PROTECTION
–
+
PFI
1.19V
AV = 32
A1
POWER-FAIL
COMPARATOR
8
9
CHRG
+
–
FAULT
5 BSTOFF
4 CHGOFF
6.4k
R3
NTC
–
+
+
–
RNTC
R5
0.1V
+
–
RFB1
18
RFB2
L1
SW
PWM
21, 22
A3
0.8V
CHARGER
LOGIC
+
–
PROG
0.8V
CBAT
BAT
A4
BAT
0.8V
CLPROG
3
23
R1
R2
8
CHARGE
VOLTAGE
SELECTOR
F0
F1
F2
GND
2
RPROG
2.85V
BAD-BATTERY
DETECTOR
OVERTEMP
25
12
– A2 +
UNDERTEMP
NTC ENABLE
10
CHARGER
CTRL
VIN
R4
17
PROG
0.1V
C/8 DETECTOR
VIN
RBIAS
BUCK CHARGER
BOOST BACKUP
11
0.8V
BOOST
CTRL
BUCK/BOOST
RSTFB
BSTFB
A6
– +
RPF2
+ –
– +
19
232ms
DELAY
+
–
RPF1
20
PFO
0.74V
14
+
Li-Ion/
LiFePO4
BATTERY
13
12
4040 F01
4040fb
For more information www.linear.com/LTC4040
LTC4040
Operation
The LTC4040 is a complete battery backup system manager
for a 3.5V to 5.5V supply rail. The system has three principal circuit components: a full-featured step-down (buck)
battery charger, a step-up (boost) backup converter with
automatic burst feature to deliver power to the system load
when external input power is lost and a power-fail comparator to decide which one to activate. The LTC4040 has
several other auxiliary components: an input current limit
(CLPROG) amplifier, an optional input overvoltage protection (OVP) circuit and a reset comparator.
The LTC4040 has three modes of operation: normal,
backup and shutdown. If the input supply is above an
externally programmable PFI threshold voltage, the part
is considered to be in normal mode in which power flows
from input to output (VSYS) while the step-down switching regulator charges the battery to one of eight charge
voltage settings programmed by the F0, F1, and F2 digital inputs. Please refer to the Block Diagram. The total
system load is monitored by the CLPROG amplifier via
an external series resistor, RS, connected between the
VIN and CLN pins. This amplifier can reduce the charge
current from its programmed value (set by the PROG
pin external resistor RPROG) if the external load demand
increases beyond a programmable level set by RS. When
the input supply falls below the PFI threshold, backup
mode disconnects the switches (MN1 and MN2) to isolate the system (VSYS) from the input while the boost
converter powers the system load from the battery using
the same external inductor, L1.
THE BATTERY CHARGER
The LTC4040 includes a full-featured constant-current
(CC)/constant-voltage (CV) battery charger with automatic recharge, automatic termination by safety timer,
low voltage trickle charging, bad-battery detection and
thermistor sensor input for out-of-temperature charge
pausing. The battery charger is a high efficiency buck
switching converter used to transfer charge from VSYS
to BAT via the SW pin. The charger can be disabled by
pulling the CHGOFF pin above 1.2V.
Buck Switching Charger
The LTC4040 battery charger is a constant frequency
(2.25MHz) synchronous buck converter capable of
directly charging the battery to its charge voltage with an
externally programmable charge current up to 2.5A from
an input supply as high as 5.5V. A zero current comparator monitors the inductor current and shuts off the
NMOS synchronous rectifier once the current reduces to
approximately 250mA. This prevents the inductor current
from reversing and improves efficiency for low charging
current.
Battery Preconditioning (Trickle Charge)
and Bad-Battery Fault
When a battery charge cycle begins, the battery charger first determines if the battery is deeply discharged. If
the battery voltage is below VLOWBAT, typically 2.85V, an
automatic trickle charge feature sets the charge current
to 1/8th or 12.5% of the programmed value. To improve
charge current accuracy at this low level, the buck switching charger is turned off and a secondary linear charger
is used to deliver charge to the battery. If the low voltage
persists for more than half an hour, the battery charger
automatically terminates and indicates, via the CHRG and
FAULT pins, that the battery is in bad-battery fault.
Constant-Current Mode Charging
Once the battery voltage is above VLOWBAT, the charger
begins charging in full power constant-current mode. The
current delivered to the battery will try to reach 2000V/
RPROG. Depending on the external load condition, the battery charger may or may not be able to charge at the full
programmed rate. The external load will always be prioritized over the battery charge current. The battery charger
will charge at the full programmed rate only if the sum of
the external load and the charger input current is less than
or equal to the input current limit set by RS.
4040fb
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13
LTC4040
Operation
Charge Termination
The battery charger has a built-in safety timer. Once the
voltage on the battery reaches the charge voltage set by
the F0, F1 and F2 pins, the charger will regulate the battery
voltage there and the charge current will decrease naturally. The safety timer (approximately 4-hour for Li-Ion
and approximately 2-hour for LiFePO4 batteries) starts
once the charger detects that the battery has reached the
charge voltage. After the safety timer expires, charging
of the battery will discontinue and no more current will
be delivered unless the battery voltage falls below the
automatic recharge threshold.
Automatic Recharge
Once the battery charger terminates, it will remain off
drawing only microamperes of current from the battery. If
the product remains in this state long enough, the battery
will eventually self-discharge. To ensure that the battery is
always topped off, a charge cycle will automatically begin
when the battery voltage falls below VRECHRG. In the event
that the safety timer is running when the battery voltage
falls below VRECHRG, it will reset back to zero. To prevent
brief excursions below VRECHRG from resetting the safety
timer, the battery voltage must be below VRECHG for more
than 2.4ms.
Charge Status Indication via the CHRG and FAULT Pins
The status of the battery charger is indicated via the CHRG
and FAULT pins according to the fallowing table:
Table 1. Charge Status Indication
CHRG
FAULT
0
0
STATUS
NTC Fault and C/8 Not Reached
0
1
Charging (No Fault)
1
0
Bad Battery Fault
1
1
Charging Nearly Complete – C/8 Reached
When charging begins, CHRG is pulled low and remains
low for the duration of a normal charging cycle. When
charge current drops to 1/8th the value programmed by
RPROG, the CHRG pin is released (Hi-Z). The CHRG pin
does not respond to the C/8 threshold if the LTC4040 is
in input current limit. This prevents false end-of-charge
14
indications due to insufficient power available to the battery charger.
If a battery is found to be unresponsive to charging (i.e.,
its voltage remains below 2.85V for more than 1/2 hour),
the CHRG pin will be released and the FAULT pin will be
pulled low, indicating that the charging has been terminated. However, if there is a fault due to NTC, only the
FAULT pin is pulled low while the CHRG pin remains low,
indicating a pause in charging.
Battery Thermal Protection with NTC Thermistor
The LTC4040 monitors the battery temperature during the
charging cycle by using a negative temperature coefficient
(NTC) thermistor, placed close to the battery pack. If the
battery temperature moves outside a safe charging range,
the IC suspends charging and signals a fault condition
until the temperature returns to the safe charging range.
The safe charging range is determined by two comparators that monitor the voltage at the NTC pin as shown
in the Block Diagram. To use this feature, connect the
thermistor, RNTC, between the NTC pin and ground and a
bias resistor, RBIAS, from VIN to NTC. RBIAS should be a
1% resistor with a value equal to the value of the chosen
thermistor at 25°C (R25).
Thermistor manufacturers usually include either a temperature lookup table identified with a characteristic curve
number, or a formula relating temperature to the resistor
value. Each thermistor is also typically designated by a
thermistor gain value ß25/85.
The LTC4040 will pause charging when the resistance of
the thermistor increases to 325% of the RBIAS resistor as
the temperature drops. For a Vishay Curve 2 thermistor
with ß25/85 = 3490K and 25°C resistance of 10k, this corresponds to a temperature of about 0°C. The LTC4040 also
pauses charging if the thermistor resistance decreases to
53.6% of the RBIAS resistor. For the same Vishay Curve 2
thermistor, this corresponds to approximately 40°C. If the
battery charger is in constant-voltage mode, the safety
timer also pauses until the thermistor indicates a return
to a valid temperature. The hot and cold comparators each
have approximately 2°C of hysteresis to prevent oscillation about the trip point. Grounding the NTC pin disables
all NTC functionality.
4040fb
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LTC4040
Operation
Differential Undervoltage Lockout
VBAT Undervoltage Lockout
An undervoltage lockout circuit monitors the differential
voltage between VSYS and BAT and shuts off the charger if
the BAT voltage reaches within 50mV of the VSYS voltage.
Charging does not resume until this difference increases to
145mV.
To prevent the battery from discharging too deeply, the
LTC4040 incorporates an undervoltage lockout circuit
which shuts down the boost regulator when VBAT drops
below 2.45V.
BACKUP BOOST CONVERTER
If the BSTFB node were inadvertently shorted to ground,
then the boost converter output would increase indefinitely with the maximum current that could be sourced
from BAT. The LTC4040 protects against this by shutting
off both switches if the output voltage exceeds 5.5V.
To supply the system load from the battery in backup
mode, the LTC4040 contains a 1.125MHz constant-frequency current-mode synchronous boost switching regulator with output disconnect and automatic Burst Mode
features. The regulator can provide a maximum load of
2.5A from a battery as low as 3.2V and the system output
voltage (VSYS) can be programmed up to a maximum of 5V
via the BSTFB pin. See the Applications Information section
for details. The converter can be disabled by pulling the
BSTOFF pin high. The boost regulator includes safety features like short-circuit current protection, input undervoltage lockout, and output overvoltage protection.
Zero Current Comparator
The LTC4040 boost converter includes a zero current
comparator which monitors the inductor current and
shuts off the PMOS synchronous rectifier once the current
drops to approximately 250mA. This prevents the inductor current from reversing in polarity thereby improving
efficiency at light loads.
PMOS Synchronous Rectifier
To prevent the inductor current from running away,
the PMOS synchronous rectifier is only enabled when
VSYS > (VBAT – 200mV). Additionally, if the current through
the synchronous FET (PMOS) ever exceeds 8A, the converter skips the next two clock cycles so that the inductor
current has a chance to discharge safely below this level.
Short-Circuit Protection
The output disconnect feature enables the LTC4040 boost
converter to survive a short circuit at its output. It incorporates internal features such as current limit foldback
and thermal shutdown for protection from excessive
power dissipation during short circuit.
Boost Overvoltage Protection
Burst Mode Operation
To improve battery life during backup, the LTC4040 boost
converter provides automatic Burst Mode operation which
increases the efficiency of power conversion at very light
loads. Burst Mode operation is initiated if the output load
current falls below an internally set threshold. Once Burst
Mode operation is initiated, only the circuitry required
to monitor the output is kept alive. This is referred to
as the sleep state in which the backup boost consumes
only 40µA from the battery. When the VSYS pin voltage
drops by about 1% from its nominal value, the part wakes
up and commences normal PWM operation. The output
capacitor recharges and causes the part to re-enter the
sleep state if the output load remains less than the Burst
Mode threshold. The frequency of this intermittent PWM
or Burst Mode operation depends on the load current;
that is, as the load current drops further below the burst
threshold, the boost converter turns on less frequently.
When the load current increases above the burst threshold, the converter seamlessly resumes continuous PWM
operation. Thus, Burst Mode operation maximizes the
efficiency at very light loads by minimizing switching
and quiescent losses. However, the output ripple typically increases to about 2% peak-to-peak. Burst Mode
ripple can be reduced, in some circumstances, by placing a small phase-lead capacitor (CPL) between the VSYS
and BSTFB pins. However, this may adversely affect the
efficiency and the quiescent current at light loads. Typical
values of CPL range from 15pF to 100pF.
For more information www.linear.com/LTC4040
4040fb
15
LTC4040
Operation
VBAT > VSYS Operation
The LTC4040 boost converter will maintain voltage regulation even if its input voltage is above the output voltage.
This is achieved by terminating the switching of the synchronous PMOS and applying VBAT voltage statically on
its gate. This ensures that the slope of the inductor current
will reverse during the time current is flowing to the output. Since the PMOS no longer acts as a low impedance
switch in this mode, there will be more power dissipation
within the IC. This will cause a sharp drop in the efficiency.
The maximum output current should be limited in order
to maintain an acceptable junction temperature.
INPUT CURRENT LIMIT AND CLPROG MONITOR
The LTC4040 contains an input current limit circuit which
monitors the total system current (the external load plus
the charger input current) via an external series resistor,
RS, connected between the pins VIN and CLN. The part
does not actually limit the external load but as the external load demand increases, it reduces charge current, if
necessary, in an attempt to maintain a maximum of 25mV
across the VIN and CLN pins. Please refer to Programming
the Input Current Limit and CLPROG Monitor section in
Applications Information. However, if the external load
demand exceeds the limit set by RS, the part does not
reduce the load current but the charge current will drop
to zero. In all scenarios, the voltage on the CLPROG pin
will correctly represent the total system current. 800mV
on the CLPROG pin represents the full-scale current set
by the external series resistor, RS.
Power-Fail COMPARATOR AND MODE SWITCHING
The LTC4040 contains a fast power-fail comparator which
switches the part from normal to backup mode in the
event the input supply voltage falls below an externally
programmed threshold voltage. This threshold voltage
is programmed by an external resistor divider via the PFI
pin. See the Applications Information section for details of
how to choose values for the resistor divider. The output
of the power-fail comparator also directly drives the gate
of an open-drain NMOS to report the status of the availability of input power via the PFO pin. If input power is
16
available, the PFO pin is high impedance; otherwise, the
pin is pulled down to ground.
At the onset of backup mode, the battery charger shuts
off, the external NMOS pass transistors (MN1 and MN2
in Block Diagram) are quickly turned off by discharging IGATE to ground thereby disconnecting the system
output VSYS from the input and the backup boost converter activates promptly to deliver load from the battery.
Although the power-fail comparator has a hysteresis of
approximately 30mV, it may not be able to overcome the
input voltage spike resulting from the sudden collapse of
the forward current from the input to VSYS. To prevent
repeated unwanted mode switching, once activated, the
backup boost stays on for at least half a second. During
this time, the power-fail comparator output is ignored and
an internal switch of approximately 270Ω pulls down the
OVSNS pin to help discharge the input. After the halfsecond timer expires, if the power-fail comparator output
indicates that power is still not available, the backup boost
continues to deliver the load but the pull-down on the
OVSNS pin is released. When the power-fail comparator detects that input power is available, the OVP charge
pump starts to charge up the IGATE pin but the backup
boost converter continues to deliver system load until
IGATE is approximately 8V. This ensures that the forward
conduction path through the external NFET pass transistors has been established. At this point, the backup boost
gets deactivated and the charger turns back on to charge
the battery while the system load gets delivered directly
from the input to VSYS through the pass transistors.
Reset COMPARATOR
The LTC4040 contains a reset comparator which monitors VSYS under all operating modes via the RSTFB pin
and reports the status via an open-drain NMOS transistor
on the RST pin. At any time, if VSYS falls 7.5% from its
programmed value, the RST pin pulls low almost instantaneously. However, the comparator waits approximately
232ms after VSYS rises above the threshold before making
the RST pin high impedance. Please refer to Programming
the Reset Comparator Threshold section in Applications
Information.
4040fb
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LTC4040
Operation
OPTIONAL INPUT OVERVOLTAGE PROTECTION (OVP)
The LTC4040 can protect itself from the inadvertent
application of excessive voltage with just two external
components: an N-channel FET (MN1) and a 6.2k resistor as shown in the Block Diagram. The maximum safe
overvoltage magnitude will be determined by the choice
of external NMOS and its associated drain breakdown
voltage.
The optional overvoltage protection (OVP) module consists of two pins. The first, OVSNS, is used to measure the
applied voltage through an external resistor. The second,
IGATE, is an output used to drive the gate pins of two external N-channel FETs, MN1 and MN2 (Block Diagram). The
voltage at the OVSNS pin will be lower than the OVP input
voltage by about 250mV due to the OVP circuit’s quiescent
current flowing through the OVSNS resistor. When OVSNS
is below 6V, an internal charge pump will drive IGATE
to approximately 1.88 • VOVSNS. This will enhance the
N‑channel FETs and provide a low impedance connection
to VSYS and power the chip. If OVSNS should rise above
6V due to a fault, IGATE will be pulled down to ground, disabling the external FETs to protect downstream circuitry.
At the same time, the backup boost converter will be activated to supply the system load from the battery. When
the voltage drops below 6V again, the external FETs will be
re-enabled. If the OVP feature is not desired, remove MN1,
short OVSNS to VIN and apply external power directly to
VIN.
SHUTDOWN MODE OPERATION
The LTC4040 can be shutdown almost entirely by pulling
both CHGOFF and BSTOFF pin above 1.2V. In this mode,
the internal charge pump is shutdown and IGATE is pulled
to ground disconnecting the forward path from input to
output via the external FETs. Only the internal OVP shunt
regulator remains active to monitor the input supply for
any possible overvoltage condition and consumes about
25µA via the OVSNS pin. Total current draw from the BAT
pin drops to below 3µA during shutdown.
4040fb
For more information www.linear.com/LTC4040
17
LTC4040
Applications Information
Choosing a Charge Voltage for the Battery:
The input voltage threshold below which the power-fail
status pin PFO indicates a power-fail condition and the
LTC4040 activates the backup boost operation can be
programmed by using a resistor divider from the supply
to GND via the PFI pin such that:
⎛ R ⎞
⎛ R ⎞
VSUPP(PFO) = VPFI • ⎜1+ PF1 ⎟ =1.19V • ⎜1+ PF1 ⎟
⎝ RPF2 ⎠
⎝ RPF2 ⎠
VPFI is approximately 1.19V. See Block Diagram. The PFI
threshold voltage should be set to a level between 200mV
to 300mV below the nominal input supply voltage so that
the supply transients do not trip the comparator. On the
other hand, it should be set high enough so that the VSYS
voltage does not drop too much to trip the reset comparator during the transition to backup mode.
130
Programming the Battery Charge Current
1750
120
1500
110
Battery charge current is programmed using a single
resistor from the PROG pin to ground. To set a charge
current of ICHG, the PROG pin resistor value can be determined using the following equation:
CAPACITY
1250
100
1000
90
750
80
500
70
NUMBER OF CYCLES
250
0
4
4.1
4.2
4.3
4.4
CHARGE VOLTAGE (V)
60
50
4.5
4040 F01
Figure 1. Battery Cycle Life and Capacity
as a Function of Charge Voltage
18
Programming the Input Voltage Threshold
for the Power-Fail Comparator
2000
BATTERY CAPACITY (%)
CHARGE/ DISCHARGE CYCLES
The LTC4040 offers 4 different charge voltage options for
each of the two battery chemistries (Li-Ion and LiFePO4)
and these levels are selected by the digital inputs F0, F1
and F2. Choosing a higher charge voltage increases the
battery capacity to provide a longer product run-time but
reduces the battery lifetime, usually measured by the
number of charge/ discharge cycles. Battery manufacturers usually consider the end of life for a battery to be when
the battery capacity drops to 80% of the rated capacity.
The curves in Figure 1 show the relationship between
cell capacity and cycle life for a typical Li-Ion battery cell.
Using 4.2V as the charge voltage, a typical Li-Ion battery
is considered at 100% initial capacity but delivers about
500 charge/ discharge cycles before the capacity drops
to 80%. However, if the same battery uses 4.1V as the
charge voltage, it is at 85% initial capacity but the number
of charge/discharge cycles can be almost doubled to 1000
before the capacity drops to 80%. Lowering the charge
voltage even further to 4.0V can increase the battery lifetime more than three times to 1800 charge/ discharge
cycles. Since LTC4040 is a backup product, the battery
is likely to spend the majority of its lifetime fully charged.
This makes it even more critical to charge at a lower
charge voltage to maximize battery lifetime since battery
capacity degrades even faster when batteries remain fully
charged. Because of the different Li-Ion battery chemistries and other conditions that can affect battery lifetime,
the curves shown here are only estimates of the number
of charge cycles and battery-capacity levels.
RPROG = 2500 •
0.8V 2000V
=
ICHG
ICHG
For example, to set the charge current to 1A, the value
of the PROG pin resistor should be 2k. The minimum
recommended charge current is 500mA, below which the
accuracy of the charge current suffers. This corresponds
to a maximum RPROG resistor of 4k.
4040fb
For more information www.linear.com/LTC4040
LTC4040
Applications Information
Programming the Input Current Limit
and CLPROG Monitor
The input current limit is programmed by connecting a
series resistor between the VIN and CLN pins. To limit the
total system current to ISYSLIM, the value of the required
resistor can be calculated using the following equation:
RS =
25mV
Programming the Reset Comparator
Threshold
ISYSLIM
For example, to set the current limit to 2A, the series
resistor should be 12.5mΩ. As discussed in the
Operations section, the part does not limit the system
current but reduces the charge current to zero in case the
system load exceeds this limit.
The voltage on the CLPROG pin always represents the
total system current ISYS through the external series resistance, RS. 800mV on CLPROG represents the full-scale
current set by RS. The system current can be calculated
from the CLPROG pin voltage by using the following
equation:
ISYS =
VBSTFB is 0.8V. See the Block Diagram. Typical values for
RFB1 and RFB2 are in the range of 40k to 2M. Too small a
resistor will result in a large quiescent current whereas
too large a resistor coupled with any parasitic BSTFB pin
capacitance will create an additional pole and may cause
loop instability.
VCLPROG
32 •RS
For example, if the CLPROG pin voltage is 600mV and
RS is 12.5mΩ, then the total system current is 1.5A. As
shown in the block diagram, the CLPROG pin is not buffered internally. So it is important to isolate this pin before
connecting to an ADC or any other monitoring device.
Failure to do so would degrade the accuracy of this circuit.
Programming the Boost Output Voltage
The boost converter output voltage in backup mode can
be programmed for any voltage from 3.5V to 5V by using
a resistor divider from the VSYS pin to GND via the BSTFB
pin such that:
The threshold for the reset comparator can be programmed by using a resistor divider from the VSYS pin
to GND via the RSTFB pin such that:
⎛ R ⎞
⎛ R ⎞
VSYS(RST) = VRSTFB • ⎜ 1+ FB1 ⎟ = 0.74V • ⎜ 1+ FB1 ⎟
⎝ RFB2 ⎠
⎝ RFB2 ⎠
VRSTFB is 0.74V. See the Block Diagram. Typical values
for RFB1 and RFB2 are in the range of 40k to 2M. In most
applications, the BSTFB and RSTFB pins can be shorted
together and only one resistor divider between VSYS and
GND is needed to set the VSYS voltage during backup
mode and the reset threshold 7.5% below the VSYS programmed voltage.
Choosing the External Resistor for the
overvoltage Protection (OVP) Module
In an overvoltage condition, the OVSNS pin will be clamped
at 6V. The external 6.2k resistor must be sized appropriately to dissipate the resultant power. For example, a 1/8W
6.2k resistor can have at most PMAX • 6.2kΩ = 28V
applied across its terminals. With the 6V at OVSNS, the
maximum overvoltage magnitude that this resistor can
withstand is 34V. A 1/4W 6.2k resistor raises the value to
45V. The OVSNS pin’s absolute maximum current rating
of 10mA imposes an upper limit of 68V protection.
⎛ R ⎞
⎛ R ⎞
VSYS = VBSTFB • ⎜ 1+ FB1 ⎟ = 0.8V • ⎜ 1+ FB1 ⎟
⎝ RFB2 ⎠
⎝ RFB2 ⎠
4040fb
For more information www.linear.com/LTC4040
19
LTC4040
Applications Information
Choosing the External Transistors
(MN1 and MN2) for the OVP Module and the
Input-to-Output Disconnect Switch
The LTC4040 uses a weak internal charge pump to pump
IGATE above the input voltage so that N-channel external FETs can be used as pass transistors. However, these
transistors should be carefully chosen so that they are
fully enhanced with a VGS of 3V. Since one of these pass
transistors is the OVP FET, its breakdown voltage (BVDSS)
determines the maximum voltage the LTC4040 can withstand at its input. Also, care must be taken to avoid any
leakage on the IGATE pin, as it may adversely affect the
FET operation. See Table 2 for a list of recommended
transistors.
Table 2. Recommended NMOS FETs for Overvoltage Protection
and Disconnect Switch
NMOS FET
SIR424DP (Vishay)
BVDSS
RON
20V
7.4mΩ
SiS488DN (Vishay)
40V
7.5mΩ
SiS424DN (Vishay)
20V
8.9mΩ
Choosing the Inductor for the Switching
Regulators
Since the same inductor is used to charge the battery in
normal mode and to deliver the system load in backup
mode, its inductance should be low enough so that the
inductor current can reverse quickly as soon as the
backup mode is initiated. On the other hand, the inductance should not be so low that the inductor current is
discontinuous at the lowest charge current setting since
charge current accuracy suffers greatly if the inductor
current is discontinuous. Inductor current ripple (ΔIL) can
be computed using the following equation:
⎛ V ⎞
1
∆IL = VBAT • ⎜ 1– BAT ⎟ •
⎝ VSYS ⎠ L • fOSC
The other considerations when choosing an inductor is
the maximum DC current (IDC) and the maximum DC
resistance (DCR) rating as shown in Table 3 below. The
chosen inductor should have a max IDC rating which is
greater than the current limit specification of the part in
order to prevent an inductor current runaway situation.
For the LTC4040, the maximum current that the inductor
can experience is approximately 8A in backup mode. It is
also important to keep the max DCR as low as possible
in order to minimize conduction loss and help improve
the converter’s efficiency.
Table 3. Recommended Inductors for the LTC4040
INDUCTOR
L
TYPE
(µH)
XAL-5020-122 1.2
MAX MAX
IDC DCR
(A) (MΩ)
8.3
20.5
XAL-6030-122
1.2
10.8
7.5
XAL-6020-132
1.3
9
15.4
XAL-6030-182
1.8
14
10.52
XAL-5030-222
2.2
9.2
14.5
XAL-6030-222
2.2
15.9
13.97
SIZE IN mm
(L × W × H)
5.68 × 5.68
×2
6.76 × 6.76
× 3.1
6.76 × 6.76
× 2.1
6.76 × 6.76
× 3.1
5.3 × 5.5
× 3.1
6.38 × 6.58
× 3.1
MANUFACTURER
Coilcraft
www.coilcraft.com
Coilcraft
www.coilcraft.com
Coilcraft
www.coilcraft.com
Coilcraft
www.coilcraft.com
Coilcraft
www.coilcraft.com
Coilcraft
www.coilcraft.com
Choosing VSYS Capacitor
Since the lowest recommended charge current setting is 500mA, inductor current will be discontinuous if
the ripple is more than twice that amount, i.e, 1A. For
VSYS = 5V, VBAT = 3.2V, fOSC = 2.25MHz (buck mode),
20
and ΔIL = 1A, the theoretical minimum inductor size to
avoid discontinuous operation can be computed by using
the above equation to be 0.5µH. To account for inaccuracies in the system and component values, the practical
low limit should be 1µH. Since the backup boost operates at half the frequency (1.125MHz), the inductor current ripple with a 1µH inductor using the same equation
will be approximately 1A in backup mode. If this seems
excessive, inductors up to 2.2µH can be used to lower the
inductor current ripple.
The worst-case delay for the backup boost converter to
meet the system load demand can happen if the PFI input
falls below the externally set threshold at a time when the
buck charger is charging at the highest setting of 2.5A
4040fb
For more information www.linear.com/LTC4040
LTC4040
Applications Information
and the system load is also very high, e.g., 2.5A. Under
this scenario, as soon as the part initiates the backup
mode, the inductor current will have to reverse from 2.5A
(from SW to BAT) to as high as the boost current limit
of approximately 6.5A (from BAT to SW). That is a 9A
current change in the inductor with a slope of VBAT/L. At
a low battery voltage of 3.2V, this might take almost 3µs
even with a 1µH inductor. During this transition, CSYS, the
capacitor on the VSYS pin, will have to deliver the shortfall
until the inductor current is caught up with the system
load demand, and the capacitor will deplete according to
the following equation:
CSYS =ILOAD •
∆t
∆V
The size of the capacitor should be big enough to hold the
system voltage, VSYS, up above the reset threshold during
this transition. For a system load ILOAD = 2.5A, transition
time ∆t = 3µs, if the maximum droop ∆V allowed in the
system output is 100mV, the required capacitance at the
VSYS pin should be at least 75µF.
The other consideration for choosing VSYS capacitor size
is the maximum acceptable output voltage ripple during
steady-state backup boost operation. For a given duty
cycle of D and load of ILOAD, the output ripple VRIP of a
boost converter is calculated using the following equation:
VRIP =
ILOAD
1
•D•
CSYS
fOSC
If the maximum allowable ripple is 20mV under 2.5A
steady-state load while boosting from 3.2V to 5V
(D = 36%), the required capacitance at VSYS is calculated to be at least 40µF using the above equation. Please
refer to Table 4 for recommended ceramic capacitor
manufacturers.
Table 4. Recommended Ceramic Capacitor Manufacturers
AVX
www.avxcorp.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
Vishay Siliconix
www.vishay.com
TDK
www.tdk.com
Battery Charger Stability Considerations
The LTC4040’s switching battery charger contains three
control loops: constant-voltage, constant-current, and
input current limit loop, all of which are internally compensated. However, various external conditions like load
and component values may interfere with the internal
compensation and cause instability. For example, the constant-voltage loop may become unstable due to reduced
phase margin if more than 100µF capacitance is added in
parallel with the actual battery at the BAT pin.
In constant-current mode, the PROG pin is in the feedback
loop rather than the BAT pin. Because of the additional
pole created by any PROG pin capacitance, capacitance on
this pin must be kept to a minimum. For the constant-current loop to be stable, the pole frequency at the PROG pin
should be kept above 1MHz. Therefore, if the PROG pin
has a parasitic capacitance, CPROG, the following equation should be used to calculate the maximum resistance
value for RPROG:
RPROG ≤
1
2π •1MHz •CPROG
Alternatively, for RPROG = 4k (500mA setting), the maximum allowable capacitance on the PROG pin is 40pF. If
any measuring device is attached to the PROG pin for
monitoring the charge current, a 1M isolation resistor
should be inserted between the PROG pin and the device.
Backup Boost Stability Considerations
The LTC4040’s backup boost converter is internally compensated. However, system capacitance less than 100µF
or over 1000µF will adversely affect the phase margin and
hence the stability of the converter.
Also, if the right-half-plane (RHP) zero moves down in
frequency due to external load conditions and the choice
of the inductor value, that may also reduce the phase
margin and cause instability. If the output power is POUT,
inductor value is L, efficiency is η and the input to the
4040fb
For more information www.linear.com/LTC4040
21
LTC4040
Applications Information
boost converter is VBAT, the RHP zero frequency can be
expressed as follows:
fRHP =
( VBAT )
2
2 • π •L •POUT
•η
For the LTC4040’s backup boost to be able to supply
12.5W of output power (2.5A at 5V) from a 3.2V battery, the maximum inductor size should not exceed 2.2µH
because of the RHP zero consideration. Also, too much
lead resistance between the battery and the BAT pin can
lower the effective input voltage of the boost converter
causing the RHP zero to shift downward and cause instability. This is why it is important to minimize the lead
resistance and place the battery as close to the BAT pin
as possible.
Alternate NTC Thermistors and Biasing
The hot and cold trip points may be adjusted using a
different type of thermistor, or a different RBIAS resistor,
or by adding a desensitizing resistor RADJ as shown in
Figure 2, or by a combination of these measures. For
example, by increasing RBIAS to 12.4k from the default
value of 10k, with the same Vishay Curve 2 thermistor,
the cold trip point moves down to –5°C, and the hot trip
point moves down to 34°C. If a Vishay Curve 1 thermistor with ß25/85 = 3950K and resistor of 100k at 25°C is
used, a 1% RBIAS resistor of 118k and a 1% RADJ resistor
of 12.1k results in a cold trip point of 0°C, and a hot trip
point of 39°C.
LTC4040
TOO COLD
+
–
TOO HOT
+
–
IGNORE NTC
+
–
BAT
VIN
RBIAS
NTC
RADJ
OPT
74% VIN
29% VIN
RNTC
1.7% VIN
4040 F01
Figure 2. NTC Connections
22
+
Li-Ion
PCB Layout Considerations
Since the LTC4040 includes a high-current high-frequency
switching converter, the following guidelines should
be used during printed circuit board (PCB) layout in
order to achieve optimum performance and minimum
electromagnetic interference (EMI).
1. Even though the converter can operate in both stepdown (buck) and step-up (boost) mode, there is only
one hot-loop containing high-frequency switching
currents. The simplified diagram in Figure 3 can be
used to explain the hot-loop in the LTC4040 switching
converter. Current follows the blue loop when switch
S2 (NMOS) is closed and the red loop when switch
S1 (PMOS) is closed. So it is evident that the current
in the CBAT capacitor is continuous whereas the CSYS
current is discontinuous forming a hot loop with VSYS
pins and GND as indicated by the green loop. Since
the amount of EMI is directly proportional to the area
of this loop, the VSYS capacitor, prioritized over all
else, should be placed as close to the VSYS pins as
possible and the ground side of the capacitor should
return to the ground plane through an array of vias.
VSYS
L1
VBAT
+
S1
HOT LOOP
CBAT
CSYS
S2
4040 F03
Figure 3. Hot-Loop Illustration for the LTC4040 Switching Converter
2. To minimize parasitic inductance, the ground plane
should be as close as possible to the top plane of the
PC board (Layer 2). High frequency currents in the hot
loop tend to flow along a mirror path on the ground
plane which is directly beneath the incident path on
the top plane of the board as illustrated in Figure 4. If
there are slits or cuts or drill-holes in this mirror path
on the ground plane due to other traces, the current
will be forced to go around the slits. When high frequency currents are not allowed to flow back through
their natural least-area path, excessive voltage will
4040fb
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LTC4040
Applications Information
build up and radiated emissions will occur. So every
effort should be made to keep the hot-loop current
path as unbroken as possible.
currents as high as the NMOS current limit (typ. 6.5A)
in backup boost mode.
4. Locate the VSYS dividers for BSTFB and RSTFB near
the part but away from the switching components.
Kelvin the top of the resistor dividers to the positive
terminal of CSYS. The bottom of the resistor dividers
should return to the ground plane away from the hotloop current path. The same is true for the PFI divider.
5. The exposed pad on the backside of the LTC4040
package must be securely soldered to the PC board
ground and also must have a group of vias connecting it to the ground plane for optimum thermal
performance. Also this is the only ground pin in the
package, and it serves as the return path for both the
control circuitry and the switching converter.
3586 F04
Figure 4. High Frequency Ground Currents Follow Their Incident Path.
Slices in the Ground Plane Cause High Voltage and Increased EMI
3. The other important components that need to be
placed close to the pins are the CBAT capacitor and
the inductor L1. Even though the current through
these components is continuous, they can change
very abruptly due to a sudden change in load demand.
Also, their traces should be wide enough to handle
6. The IGATE pin for controlling the gates of the external
pass transistors has extremely limited drive current.
Care must be taken to minimize leakage to adjacent
PC board traces. To minimize leakage, the trace can
be guarded on the PC board by surrounding it with
VSYS connected metal.
Typical Application
5V Backup System with 12V Buck for Automotive Application
(Charge Current Setting: 1A, Input Current Limit Setting: 2A)
VIN
12V
4.7µF
10nF
VIN
EN/UV
PG
LT8610
SYNC
TR/SS
1µF
BST
0.1µF
4.7µH
SW
BIAS
FB
INTVCC
RT PGND GND
18.2k
1M
10pF
243k
RS
12mΩ
VOUT
5V
5V
47µF
MN2
178k
60.4k
VIN CLN
OVSNS
PFI
FAULT
PFO
RST
CHRG
CLPROG
IGATE
LTC4040
SYSTEM
LOAD
100µF
1690k
VSYS
BSTFB
RSTFB
SW
BAT
324k
2.2µH
10µF
VOUT
NTC
CHGOFF BSTOFF GND F0 F1 F2 PROG
2k
VSYS
NTC
+
Li-Ion
4.1V
4040 TA02
L1: COILCRAFT XAL-5030-222
MN2: VISHAY/SILICONIX SIR424DP-T1-GE3
4040fb
For more information www.linear.com/LTC4040
23
LTC4040
Package Description
Please refer to http://www.linear.com/product/LTC4040#packaging for the most recent package drawings.
UFD Package
24-Lead Plastic
QFN (4mm × 5mm)
UFD Package
(ReferencePlastic
LTC DWG
# 05-08-1696
Rev A)
24-Lead
QFN
(4mm × 5mm)
(Reference LTC DWG # 05-08-1696 Rev A)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.00 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.00 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
R = 0.05 TYP
2.00 REF
R = 0.115
TYP
23
0.75 ±0.05
PIN 1 NOTCH
R = 0.20 OR C = 0.35
24
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.00 REF
3.65 ±0.10
2.65 ±0.10
(UFD24) QFN 0506 REV A
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
24
4040fb
For more information www.linear.com/LTC4040
LTC4040
Revision History
REV
DATE
DESCRIPTION
A
07/15
Added new Applications section, Charge Voltage
PAGE NUMBER
Modified Figure 2
22
Re-assigned new figure numbers
B
08/17
18
Changed Maximum Boost Duty Cycle maximum limit.
22 – 23
4
4040fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC4040
25
LTC4040
Typical Application
5V Backup Application with OVP Protection and Non-Backed Up Load Option
(Charge Current Setting: 2.5A, Input Current Limit Setting: 4A)
4.35V TO 5V
INPUT SUPPLY
(PROTECTED
TO 40V)
VPWR
RS
6mΩ
MN1
2.2µF
6.2k 1/4W
OVP OPT
178k
MN2
VIN CLN
OVSNS
PFI
60.4k
FAULT
PFO
RST
CHRG
CLPROG
TO NON-BACKED-UP
LOAD
VSYS
4.35V TO 5V
100µF
1690k
VSYS
BSTFB
RSTFB
IGATE
SW
BAT
LTC4040
TO BACKED-UP
SYSTEM LOAD
324k
2.2µH
10µF
VIN
RBIAS
NTC
CHGOFF BSTOFF GND F0 F1 F2 PROG
VSYS
800Ω
NTC
+
Li-Ion
BATTERY
4.1V
4040 TA03
L1: COILCRAFT XAL-5030-222
MN1: VISHAY/SILICONIX SiS488DN
MN2: VISHAY/SILICONIX SIR424DP-T1-GE3
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PART NUMBER
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Switching Power Manager with USB On-The-Go and
Overvoltage Protection
1.2A Charge Current
26
COMMENTS
4040fb
LT 0817 REV B • PRINTED IN USA
For more information www.linear.com/LTC4040
www.linear.com/LTC4040
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