LTC4218
Hot Swap Controller
Features
Description
Wide Operating Voltage Range: 2.9V to 26.5V
Adjustable, 5% Accurate 15mV Current Limit
Current Monitor Output
Adjustable Current Limit Timer Before Fault
Power Good and Fault Outputs
Adjustable Inrush Current Control
2% Accurate Undervoltage and Overvoltage
Protection
n Available in 16-Lead SSOP and 16-Pin 5mm × 3mm
DFN Packages
The LTC®4218 is a Hot Swap controller that allows a board
to be safely inserted and removed from a live backplane.
An internal high side switch driver controls the gate of an
external N-channel MOSFET for supply voltages from 2.9V
to 26.5V. A dedicated 12V version (LTC4218-12) contains
preset 12V specific thresholds, while the standard LTC4218
allows adjustable thresholds.
n
n
n
n
n
n
n
The LTC4218 provides an accurate (5%) current limit with
current foldback limiting. The current limit threshold can
be adjusted dynamically using an external pin. Additional
features include a current monitor output that amplifies
the sense voltage for ground referenced current sensing.
Overvoltage, undervoltage and power good monitoring
are also provided.
Applications
RAID Systems
ATCA, AMC, µTCA Systems
n Server I/O Cards
n Industrial
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
12V, 6A Card Resident Application
2mΩ
12V
Power-Up Waveform
Si7108DN
+
*
10Ω
SENSE–
GATE SOURCE
LTC4218DHC-12
1µF
IIN
1A/DIV
VOUT
10V/DIV
PG
10V/DIV
10k
PG
FLT
25ms/DIV
ISET
TIMER
0.1µF
CONTACT BOUNCE
0.01µF
VDD
OV
UV
VIN
10V/DIV
330µF
1k
SENSE+
AUTO
RETRY
VOUT
12V
6A
IMON
INTVCC
GND
4218 TA01b
ADC
20k
2V = 7.5A
4218 TA01a
*TVS: DIODES INC SMAJ17A
4218fh
For more information www.linear.com/LTC4218
1
LTC4218
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (VDD).................................. –0.3V to 35V
Input Voltages
FB, OV, UV.............................................. –0.3V to 12V
TIMER.................................................... –0.3V to 3.5V
SENSE–..............................VDD – 10V or –0.3V to VDD
SENSE+..............................VDD – 10V or –0.3V to VDD
SOURCE......................................... – 5V to VDD + 0.3V
Output Voltages
ISET, IMON.................................................. –0.3V to 3V
PG, FLT................................................... –0.3V to 35V
INTVCC................................................... –0.3V to 3.5V
GATE (Note 3)......................................... –0.3V to 35V
Operating Ambient Temperature Range
LTC4218C................................................. 0°C to 70°C
LTC4218I..............................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
GN Package Only............................................... 300°C
Pin Configuration
TOP VIEW
TOP VIEW
NC
1
16 SENSE+
VDD
2
15 SENSE–
UV
3
14 ISET
OV
4
13 IMON
TIMER
5
INTVCC
NC
1
16 SENSE+
VDD
2
15 SENSE–
UV
3
14 ISET
OV
4
12 FB
13 IMON
TIMER
5
12 FB
6
11 FLT
6
11 FLT
GND
7
10 PG
INTVCC
GND
7
10 PG
SOURCE
8
9
SOURCE
8
9
17
GATE
DHC PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 17) IS SUBSTRATE GND
GATE
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 135°C/W
Order Information
(http://www.linear.com/product/LTC4218#orderinfo)
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4218CDHC-12#PBF
LTC4218CDHC-12#TRPBF
421812
16-Lead (5mm × 3mm) Plastic DFN
0°C to 70°C
LTC4218IDHC-12#PBF
LTC4218IDHC-12#TRPBF
421812
16-Lead (5mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4218CGN#PBF
LTC4218CGN#TRPBF
4218
16-Lead Plastic SSOP
0°C to 70°C
LTC4218IGN#PBF
LTC4218IGN#TRPBF
4218I
16-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
4218fh
2
For more information www.linear.com/LTC4218
LTC4218
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
26.5
V
DC Characteristics
VDD
Input Supply Range
IDD
Input Supply Current
FET On
l
VDD(UVL)
Input Supply Undervoltage Lockout
VDD Rising
l
l
2.9
1.6
5
2.65
2.73
2.85
mA
V
VDD(UVTH)
Input Supply Undervoltage Threshold
LTC4218-12 Only VDD Rising
l
9.6
9.88
10.2
V
ΔVDD(UVHYST)
Input Supply Undervoltage Hysteresis
LTC4218-12 Only
l
520
640
760
mV
VDD(OVTH)
Input Supply Overvoltage Threshold
LTC4218-12 Only VDD Rising
l
14.7
15.05
15.4
V
ΔVDD(OVHYST)
Input Supply Overvoltage Hysteresis
LTC4218-12 Only
l
183
244
305
mV
VSOURCE(PGTH)
SOURCE Power Good Threshold
LTC4218-12 Only VSOURCE Rising
l
10.2
10.5
10.8
V
ΔVSOURCE(PGHYST) SOURCE Power Good Hysteresis
LTC4218-12 Only
l
127
170
213
mV
ΔVSNS(TH)
Current Limit Sense Voltage Threshold
(VSENSE+ – VSENSE–)
VFB = 1.23V
VFB = 0V
VFB = 1.23V, RSET = 20kΩ
l
l
l
14.25
2.8
6.7
15
3.75
7.5
15.75
4.7
8.325
mV
mV
mV
ISENSE–(IN)
SENSE– Input Current
VSENSE– = 12V
l
4
±10
µA
ISENSE (IN)
ΔVGATE
SENSE+ Input Current
VSENSE+ = 12V
l
External N-Channel Gate Drive
(VGATE – VSOURCE)
VDD = 2.9V to 26.5V (Note 3)
IGATE = 0, –1µA
ΔVGATE-HIGH(TH)
Gate High Threshold (VGATE – VSOURCE)
IGATE(UP)
External N-Channel Gate Pull-Up Current
IGATE(FST)
IGATE(DN)
+
5.5
±20
µA
l
5
6.15
6.5
V
l
3.5
4.2
4.8
V
Gate Drive On, VGATE = VSOURCE = 12V
l
–19
–24
–29
µA
External N-Channel Gate Fast Pull-Down
Current
Fast Turn Off, VGATE = 18V,
VSOURCE =12V
l
100
170
220
mA
External N-Channel Gate Pull-Down Current
Gate Drive Off, VGATE = 18V,
VSOURCE =12V
l
200
250
400
µA
IIN
OV, UV, FB Input Current
VPIN = 1.2V, LTC4218 Only
l
0
±1
µA
RIN
OV, UV, FB Input Resistance
LTC4218-12 Only
l
13
18
23
kΩ
V(TH)
OV, UV, FB Threshold Voltage
VPIN Rising
l
1.21
1.235
1.26
ΔVOV(HYST)
OV Hysteresis
l
10
20
30
mV
ΔVUV(HYST)
UV Hysteresis
l
50
80
110
mV
VUV(RTH)
UV Reset Threshold Voltage
l
0.55
0.62
0.7
V
ΔVFB(HYST)
FB Power Good Hysteresis
l
10
20
30
mV
RISET
ISET Internal Resistor
l
19.5
20
20.5
kΩ
ISOURCE
SOURCE Input Current
VSOURCE = VGATE = 12V, LTC4218-12 Only
VSOURCE = VGATE = 12V, LTC4218 Only
VSOURCE = VGATE = 0V
l
l
l
50
1
70
2
0
90
4
±1
µA
µA
µA
Inputs
VUV Falling
V
Outputs
VINTVCC
INTVCC Output Voltage
ISINK = 0mA, –10mA
VOL
PG, FLT Output Low Voltage
ISINK = 2mA
l
3.1
0.4
0.8
V
V
IOH
PG, FLT Input Leakage Current
V = 30V
l
0
±10
µA
VTIMER(H)
TIMER High Threshold
VTIMER Rising
l
1.2
1.235
1.28
V
VTIMER(L)
TIMER Low Threshold
VTIMER Falling
l
0.1
0.21
0.3
V
ITIMER(UP)
TIMER Pull Up Current
VTIMER = 0V
l
–80
–100
–120
µA
ITIMER(DN)
TIMER Pull-Down Current
VTIMER = 1.2V
l
1.4
2
2.6
µA
4218fh
For more information www.linear.com/LTC4218
3
LTC4218
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
ITIMER(RATIO)
TIMER Current Ratio ITIMER(DN)/ITIMER(UP)
CONDITIONS
IMON(FS)
IMON Full-Scale Output Current
VSENSE+ – VSENSE– = 15mV
IMON(OFF)
IMON Offset Current
GIMON
IMON Gain
VSENSE+ – VSENSE– = 1mV
VSENSE+ – VSENSE– = 15mV and 1mV
BWIMON
IMON Bandwidth
MIN
TYP
MAX
l
1.6
2
2.7
%
l
94
100
106
µA
±0
±6
µA
6.67
6.87
l
l
6.47
250
UNITS
µA/mV
kHz
AC Characteristics
tPHL(GATE)
Input High (OV), Input Low (UV) to GATE
Low Propagation Delay
VGATE < 16.5V Falling
tPHL(SENSE)
VSENSE+ – VSENSE– High to GATE Low
Propagation Delay
VFB = 0, Step (VSENSE+ – VSENSE–) to
60mV, CGATE = 1.5nF, VGATE < 16.5V
Falling
tD(ON)
Turn-On Delay
Step VUV to 2V, VGATE > 13V
tD(FAULT)
UV Low to Clear Fault Latch Delay
l
3
5
µs
l
0.2
1
µs
100
150
ms
l
50
1
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
µs
Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V above
the SOURCE pin. Driving either GATE or SOURCE pin to voltages beyond
the clamp may damage the device.
4218fh
4
For more information www.linear.com/LTC4218
LTC4218
Typical Performance Characteristics
3.5
INTVCC (V)
IDD (mA)
1.6
25°C
1.4
–40°C
VDD = 3.3V
2.0
1.5
1.0
1.2
0
5
10
15
VDD (V)
20
25
0
30
0
–2
–4
4218 G01
1.230
1.228
–6
–8
ILOAD (mA)
–10
–12
–14
TIMER PULL-UP CURRENT (µA)
0.08
0.06
–25
0
25
50
TEMPERATURE (°C)
75
100
–100
–95
–25
50
0
25
TEMPERATURE (°C)
75
4218 G04
14
14
10
8
6
4
2
0
0.2
0.4
0.6
0.8
FB VOLTAGE (V)
1.0
1.2
4218 G07
100
CGATE = 10nF
100
100
10
1
0.1
0
15
30
45
60
CURRENT LIMIT SENSE VOLTAGE
(VSENSE+ – VSENSE–) (mV)
75
4218 G06
Internal ISET Resistor (RISET)
vs Temperature
22
12
21
10
RISET (kΩ)
CURRENT LIMIT SENSE VOLTAGE
(VDD – VSENSE) (mV)
16
12
1000
Current Limit Adjustment
16
75
4218 G03
4218 G05
Current Limit Threshold Foldback
50
0
25
TEMPERATURE (°C)
Current Limit Delay
–105
–90
–50
–25
4218 G02
–110
0.04
–50
1.226
–50
Timer Pull-Up Current
vs Temperature
0.10
CURRENT LIMIT SENSE VOLTAGE
(VSENSE+ – VSENSE–) (mV)
1.232
0.5
UV Hysteresis vs Temperature
0
UV LOW-HIGH HRESHOLD (V)
2.5
85°C
UV HYSTERESIS (V)
1.234
VDD = 5V
3.0
1.8
1.0
UV Low-High Threshold
vs Temperature
INTVCC Load Regulation
CURRENT LIMIT PROPAGATION DELAY (µs)
2.0
IDD vs VDD
TA = 25°C, VDD = 12V unless otherwise noted.
8
6
20
19
4
2
0
1k
10k
100k
RSET (Ω)
1M
10M
4218 G08
18
–50
–25
50
0
25
TEMPERATURE (°C)
75
100
4218 G09
4218fh
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5
LTC4218
Typical Performance Characteristics
GATE Pull-Up Current
vs Temperature
Gate Drive vs
Gate Pull-Up Current
–25.0
–24.5
–24.0
–50
–25
50
0
25
TEMPERATURE (°C)
75
VDD = 12V
6
5
4
3
VDD = 3.3V
2
1
0
100
6.2
0
–5
–10
4218 G10
Gate Drive vs Temperature
14
6.15
–25
–15
–20
IGATE (µA)
–30
6.12
6.11
0
25
50
TEMPERATURE (°C)
75
100
5.4
5.2
PG
10
5
0
10
15
VDD (V)
20
25
30
4218 G12
IMON vs Temperature and VDD
105
VDD = 3.3V, 12V, 24V
VSENSE+ – VSENSE– = 15mV
100
FLT
8
6
95
90
4
85
0
0
2
4218 G13
4
6
8
ILOAD (mA)
10
12
80
–50
4218 G14
IMON vs Sense
–25
0
25
50
TEMPERATURE (°C)
75
100
4218 G15
VIMON vs Sense
4
75
3
VIMON (V)
100
IMON (µA)
5.6
PG, FLT VOUT Low vs ILOAD
2
–25
5.8
IMON (µA)
PG, FLT VOUT LOW (V)
6.13
6.0
4218 G11
12
6.14
6.10
–50
∆ VGATE (VGATE – VSOURCE) (V)
∆ VGATE (VGATE – VSOURCE) (V)
–25.5
IGATE PULL-UP (µA)
Gate Drive vs VDD
7
–26.0
GATE DRIVE (VGATE – VSOURCE) (V)
TA = 25°C, VDD = 12V unless otherwise noted.
50
25
RIMON = 100k
RIMON = 40k
RIMON = 20k
2
1
RIMON = 10k
0
0
5
10
SENSE VOLTAGE (mV)
15
0
0
4218 G16
5
10
SENSE VOLTAGE (mV)
15
4218 G17
4218fh
6
For more information www.linear.com/LTC4218
LTC4218
Pin Functions
Exposed Pad: Exposed pad may be left open or connected
to device ground.
FB: Foldback and Power Good Comparator Input. Connect
this pin to an external resistive divider from SOURCE for
the LTC4218 (adjustable version). The LTC4218-12 version
uses a fixed internal divider with optional external adjustment. Open the pin if the LTC4218-12 thresholds for 12V
operation are desired. If the voltage falls below 0.6V, the
output power is considered bad and the current limit is
reduced. If the voltage falls below 1.21V the PG pin will
pull low to indicate the power is bad.
FLT: Overcurrent Fault Indicator. Open drain output pulls
low when an overcurrent fault has occurred and the circuit
breaker trips. For overcurrent auto-retry tie to UV pin (see
Applications Information for details).
GATE: Gate Drive for External N-Channel FET. An internal
24µA current source charges the gate of the external
N-channel MOSFET. A resistor and capacitor network
from this pin to ground sets the turn-on rate. During an
undervoltage or overvoltage generated turn-off a 250µA
pull-down current turns the MOSFET off. During a short
circuit or undervoltage lockout, a 170mA pull-down current
source between GATE and SOURCE is activated.
GND: Device Ground.
IMON: Current Monitor Output. The current sourced from
this pin is defined as the current sense voltage (between
the SENSE+ and SENSE– pins) multiplied by 6.67µA/mV.
Placing a 20k resistor from this pin to GND creates a 0V to
2V voltage swing when the current sense voltage ranges
from 0mV to 15mV.
INTVCC: Internal 3.1V Supply Decoupling Output. This pin
must have a 1µF or larger capacitor. Overloading this pin
can disrupt internal operation.
ISET: Current Limit Adjustment Pin. For 15mV current limit
threshold, open this pin. This pin is driven by a 20k resistor
in series with a voltage source. The pin voltage is used to
generate the current limit threshold. The internal 20k resistor
(RISET) and an external resistor (RSET) between ISET and
ground create an attenuator that lowers the current limit
value. Due to circuit tolerance, the ISET resistor should not
be less than 2k.
NC: No Connection
OV: Overvoltage Comparator Input. Connect this pin to an
external resistive divider from VDD for the LTC4218 (adjustable version). The LTC4218-12 version uses a fixed internal
divider with optional external adjustment for 12V operation.
Open the pin if the LTC4218-12 thresholds are desired. If
the voltage at this pin rises above 1.235V, an overvoltage
is detected and the switch turns off. Tie to GND if unused.
PG: Power Good Indicator. Open drain output pulls low
when the FB pin drops below 1.21V indicating the power
is bad. If the FB pin rises above 1.23V and the GATE to
SOURCE voltage exceeds 4.2V, the open-drain pull-down
releases the PG pin to go high.
SENSE–: Current Sense Minus Input. Connect this pin to
the opposite of VDD current sense resistor side. The current limit circuit controls the GATE pin to limit the sense
voltage between the SENSE+ and SENSE– pins to 15mV
or less depending on the voltage at the FB pin.
SENSE+: Current Sense Plus Input. Connect this pin to
the VDD side of the current sense resistor.
SOURCE: N-Channel MOSFET Source Connection. Connect
this pin to the source of the external N-channel MOSFET
switch. This pin provides a return for the gate pull-down
circuit. In the LTC4218‑12 version, the power good comparator monitors an internal resistive divider between the
SOURCE pin and GND.
TIMER: Timer Input. Connect a capacitor between this pin
and ground to set a 12ms/µF duration for current limit
before the switch is turned off. If the UV pin is toggled
low while the MOSFET switch is off, the switch will turn on
again following a cool down time of 518ms/µF duration.
UV: Undervoltage Comparator Input. Tie high if unused.
Connect this pin to an external resistive divider from VDD
for the LTC4218 (adjustable version). The LTC4218-12
version drives the UV pin with an internal resistive divider
from VDD. Open the pin if the preset LTC4218-12 thresholds for 12V operation are desired. If the UV pin voltage
falls below 1.15V, an undervoltage is detected and the
switch turns off. Pulling this pin below 0.62V resets the
overcurrent fault and allows the switch to turn back on
(see Applications Information for details). If overcurrent
auto-retry is desired then tie this pin to the FLT pin.
VDD: Supply Voltage. This pin has an undervoltage lockout
threshold of 2.73V.
4218fh
For more information www.linear.com/LTC4218
7
LTC4218
Functional Diagram
SENSE+
VDD
SENSE–
GATE
6.15V
IMON
ISET
CLAMP
–
CHARGE
PUMP
AND GATE
DRIVER
CS
+–
SOURCE
+
20k
0.6V
REFERENCE
RISET
X1
FB
CM
FOLDBACK
0.6V
140k
+
UV
*
PG
–
20k
–
UV
1.235V
LOGIC
OV
224k
*
+
–
0.2V
FLT
+
TM1
*
–
+
20k
20k
PG
RST
VDD
*
1.235V
*
0.62V
150k
+
VDD
SOURCE
INTVCC
100µA
OV
*
1.235V
2µA
–
+
TM2
VDD
–
1.235V
–
INTVCC
3.1V
GEN
UVLO1
+
–
2.73V
VDD
TIMER
UVLO2
EXPOSED PAD*
+
GND
2.65V
4218 BD
* DFN ONLY
4218fh
8
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LTC4218
Operation
The Functional Diagram displays the main circuits of the
device. The LTC4218 is designed to turn a board’s supply voltage on and off in a controlled manner, allowing
the board to be safely inserted and removed from a live
backplane. During normal operation, the charge pump
and gate driver turn on the external N-channel pass FET’s
gate to provide power to the load.
The current sense (CS) amplifier monitors the load current
using the voltage sensed across the current sense resistor.
The CS amplifier limits the current in the load by reducing
the GATE-to-SOURCE voltage in an active control loop. It
is simple to adjust the current limit threshold using the
current limit adjustment (ISET) pin. This allows a different
threshold during other times such as startup.
A short circuit on the output to ground causes significant
power dissipation during active current limiting. To limit
this power, the foldback amplifier reduces the current limit
value from 15mV to 3.75mV (referred to the SENSE+ minus
SENSE– voltage) in a linear manner as the FB pin drops
below 0.6V (see Typical Performance Characteristics).
If an overcurrent condition persists, the TIMER pin ramps
up with a 100µA current source until the pin voltage exceeds
1.2V (comparator TM2). This indicates to the logic that it
is time to turn off the MOSFET to prevent overheating. At
this point the TIMER pin ramps down using the 2µA current source until the voltage drops below 0.2V (Comparator TM1) which tells the logic to start an internal 100ms
timer. At this point, the pass transistor has cooled and it
is safe to turn it on again. Latchoff is the normal operating
condition following overcurrent turn-off. Retry is initiated
by pulling the UV pin low for a minimum of 1µs then high.
Autoretry is implemented by tying the FLT to the UV pin.
The fixed 12V version, LTC4218-12, uses two separate
internal dividers from VDD to drive the UV and OV pins.
This version also features a divider from the SOURCE pin
to drive the FB pin. The LTC4218-12 is available in a DFN
package while the LTC4218 (adjustable version) is in a
SSOP package.
The output voltage is monitored using the FB pin and the
PG comparator to determine if the power is available for
the load. The power good condition is signaled by the PG
pin using an open-drain pull-down transistor.
The Functional Diagram shows the monitoring blocks of
the LTC4218. The comparators on the left side include
the UV and OV comparators. These comparators are used
to determine if the external conditions are valid prior to
turning on the MOSFET. But first, the undervoltage lockout
circuits (UVLO1 and UVLO2) must validate the input supply
and internally generated 3.1V supply (INTVCC) and generate the power up initialization to the logic circuits. If the
external conditions remain valid for 100ms the MOSFET
is allowed to turn on.
Other monitoring features include the IMON current monitor.
The current monitor (CM) outputs a current proportional
to the sense resistor current. This current can drive an
external resistor or other circuits for monitoring purposes.
4218fh
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9
LTC4218
Applications Information
The typical LTC4218 application is in a high availability
system that uses a positive voltage supply to distribute
power to individual cards. The basic application circuit
is shown in Figure 1. External component selection is
discussed in detail in the following sections.
RS
2mΩ
12V
SENSE– GATE SOURCE
SENSE+
VDD
FLT
R5
20k
R3
20k
CT
0.1µF
FB
RGATE
1k
CGATE
0.01µF
R6
150k
INTVCC
GND
IMON
RSET
20k
RMON
20k
t2
4218 F02
Figure 2. Supply Turn-On
C2
0.1µF
ADC
4218 F01
*TVS Z1: DIODES INC SMAJ17A
t1
The voltage at the GATE pin rises with a slope equal to
24µA/CGATE and the supply inrush current is set at:
PG
ISET
TIMER
C1
1µF
R8
10k
LTC4218GN
OV
SOURCE
CL
330µF
UV = 9.88V
OV = 15.2V
PG = 10.5V
R7
20k
UV
R2
226k
GATE
SLOPE = 24µA/CGATE
VOUT
12V
3A
+
R1
10Ω
R4
140k
VDD + 6.15V
VDD
Q1
Si7108DN
Z1*
The pass transistor is turned on by charging up the GATE
with a 24µA charge pump generated current source
(Figure 2).
Figure 1. 3A, 12V Card Resident Application
Turn-On Sequence
The power supply on a board is controlled by placing
an external N-channel pass transistor (Q1) in the power
path. Note the sense resistor (RS) detects current and
the capacitor (CGATE) controls gate slew rate. Resistor R1
prevents high frequency oscillations in Q1 and resistor
RGATE isolates CGATE during fast turn-off.
Several conditions must be present before the external
pass transistor can be turned on. First, the supply VDD
must exceed its undervoltage lockout level. Next, the
internally generated supply INTVCC must cross its 2.65V
undervoltage threshold. This generates a 25µs poweron-reset pulse which clears the logic’s fault register and
initializes internal latches.
After the power-on-reset pulse, the UV and OV pins must
indicate that the input voltage is within the acceptable
range. All of these conditions must be satisfied for a duration of 100ms to ensure that any contact bounce during
the insertion has ended.
IINRUSH =
CL
CGATE
• 24µA
When the GATE voltage reaches the MOSFET threshold
voltage, the switch begins to turn on and the SOURCE
voltage follows the GATE voltage as it increases. Once
SOURCE reaches VDD, the GATE will ramp up until clamped
by the 6.15V zener between GATE and SOURCE.
As the SOURCE pin voltage rises, so will the FB pin which
is monitoring it. If the voltage across the current sense
resistor (RS) gets too high, the inrush current will be limited
by the internal current limiting circuitry. Once the FB pin
crosses its 1.235V threshold and the GATE to SOURCE
voltage exceeds 4.2V, the PG pin will cease to pull low and
indicate that the power is good.
Turn-Off Sequence
The switch can be turned off by a variety of conditions. A
normal turn-off is initiated by the UV pin going below its
1.235V threshold. Additionally, several fault conditions will
turn off the switch. These include an input overvoltage (OV
pin) and overcurrent circuit breaker (SENSE pin). Normally,
the switch is turned off with a 250µA current pulling down
the GATE pin to ground. With the switch turned off, the
SOURCE pin voltage drops which pulls the FB pin below
its threshold. The PG then pulls low to indicate output
power is no longer good.
4218fh
10
For more information www.linear.com/LTC4218
LTC4218
Applications Information
If VDD drops below 2.65V for greater than 5µs or INTVCC
drops below 2.5V for greater than 1µs, a fast shutdown
of the switch is initiated. The GATE is pulled down with a
170mA current to the SOURCE pin.
Overcurrent Fault
The LTC4218 features an adjustable current limit with
foldback that protects the MOSFET when excessive load
current happens. To protect the switch during active current limit, the available current is reduced as a function
of the output voltage sensed by the FB pin. A graph in the
Typical Performance Characteristics shows the Current
Limit Threshold Foldback.
An overcurrent fault occurs when the current limit circuitry
has been engaged for longer than the time-out delay set by
the TIMER. Current limiting begins when the current sense
voltage between the SENSE+ and SENSE– pins reaches
3.75mV to 15mV (depending on the foldback). The GATE
pin is then brought down with a 170mA GATE-to-SOURCE
current. The voltage on the GATE is regulated in order to
limit the current sense voltage to less than 15mV. At this
point, a circuit breaker time delay starts by charging the
external timing capacitor with a 100µA pull-up current from
the TIMER pin. If the TIMER pin reaches its 1.2V threshold,
the external switch turns off (with a 250µA current from
GATE to ground). Next, the FLT pin is pulled low to indicate an overcurrent fault has turned off the MOSFET. For
a given circuit breaker time delay, the equation for setting
the timing capacitor’s value is as follows:
CT = TCB • 0.083[µF/ms]
After the switch is turned off, the TIMER pin begins discharging the timing capacitor with a 2µA pull-down current. When the TIMER pin reaches its 0.2V threshold, the
switch is allowed to turn on again if the overcurrent fault
latch has been cleared. Bringing the UV pin below 0.6V for
a minimum of 1µs and then high will clear the fault latch.
Tying the FLT pin to the UV pin allows the part to self-clear
the fault and turn the MOSFET on as soon as TIMER pin has
ramped below 0.2V. In this auto retry mode, the LTC4218
repeatedly tries to turn on after an overcurrent at a period
determined by the capacitor on the TIMER pin.
The waveform in Figure 3 shows how the output latches
off following a short circuit. The drop across the sense
resistor is 3.75mV as the timer ramps up.
VOUT
10V/DIV
IOUT
2A/DIV
∆VGATE
10V/DIV
TIMER
2V/DIV
1ms/DIV
4218 F03
Figure 3. Short-Circuit Waveform
Current Limit Stability
The CGATE value is chosen to set the inrush current. The
RGATE value should be chosen to stabilize the current limit
large signal response. For most large MOSFETs 1k is a
suitable value. Smaller sized MOSFETs may require RGATE
values up to 100k. To determine stability create a load
step using a resistive load equal to half supply divided by
the current limit value. Increase RGATE until the GATE pin
voltage is devoid of ringing during the load step.
Current Limit Adjustment
The default value of the active current limiting signal threshold is 15mV. The current limit threshold can be adjusted
lower by placing a resistor on the ISET pin. As shown in
the Functional Block Diagram the voltage at the ISET pin
(via the clamp circuit) sets the CS amplifier’s built-in offset
voltage. This offset voltage directly determines the active
current limit value. With the ISET pin open, the voltage at
the ISET pin is determined by the buffered reference voltage. This voltage is set to 0.618V which corresponds to
a 15mV current limit threshold.
An external RSET resistor placed between the ISET pin and
ground forms a resistive divider with the internal 20k RISET
sourcing resistor. The divider acts to lower the voltage at
the ISET pin and therefore lower the current limit threshold.
The overall current limit threshold precision is reduced
4218fh
For more information www.linear.com/LTC4218
11
LTC4218
Applications Information
to ±11% when using a 20k resistor to half the threshold.
This pin’s 20k sourcing impedance allows noise to couple
to this pin and disturb the current limit threshold. Place
a 0.1µF capacitor between the ISET pin and ground when
a board trace is connected to this pin.
Using a switch (connected to ground) in series with RSET
allows the active current limit to change only when the
switch is closed. This feature can be used to program a
reduced running current while the maximum current limit
is used at start-up.
Monitor MOSFET Current
The current in the MOSFET passes through the sense
resistor. The voltage on the sense resistor is converted to
a current that is sourced out of the IMON pin. The gain of
the ISENSE amplifier is 100µA from IMON for 15mV on the
sense resistor. This output current can be converted to a
voltage using an external resistor to drive a comparator
or ADC. The voltage compliance for the IMON pin is from
0V to INTVCC – 0.7V.
A microcontroller with a built-in comparator can build a
simple integrating single-slope ADC by resetting a capacitor that is charged with this current. When the capacitor
voltage trips the comparator and the capacitor is reset, a
timer is started. The time between resets will indicate the
MOSFET current.
Monitor OV and UV Faults
Protecting the load from an overvoltage condition is the
main function of the OV pin. In the LTC4218-12 an internal
resistive divider (driving the OV pin) connects to a comparator to turn off the MOSFET when the VDD voltage exceeds
15.05V. If the VDD pin subsequently falls back below 14.8V,
the switch will be allowed to turn on immediately. In the
LTC4218, the OV pin threshold is 1.235V when rising and
1.215V when falling out of overvoltage.
The UV pin functions as an undervoltage protection pin or
as an “on” pin. In the LTC4218-12 the MOSFET turns off
when VDD falls below 9.23V. If the VDD pin subsequently
rises above 9.88V for 100ms, the switch will be allowed
to turn on again. The LTC4218 UV turn on/off threshold
is 1.235V (rising) and 1.155V (falling).
In the case of an undervoltage or overvoltage, the MOSFET
turns off and there is indication on the PG status pin. When
the overvoltage is removed, the MOSFET’s gate ramps up
immediately.
Power Good Indication
In addition to setting the foldback current limit threshold,
the FB pin is used to determine a power good condition.
The LTC4218-12 uses an internal resistive divider on the
SOURCE pin to drive the FB pin. The PG comparator indicates logic high when SOURCE pin rises above 10.5V. If
the SOURCE pin subsequently falls below 10.3V, the comparator toggles low. On the LTC4218, the PG comparator
drives high when the FB pin rises above 1.23V and low
when falls below 1.215V.
Once the PG comparator is high, the GATE pin voltage
is monitored with respect to the SOURCE pin. Once the
GATE minus SOURCE voltage exceeds 4.2V, the PG pin
goes high. This indicates to the system that it is safe to
load the Output while the MOSFET is completely turned
“on”. The PG pin goes low when the GATE is commanded
off (using the UV, OV or SENSE+/SENSE– pins) or when
the PG comparator drives low.
12V Fixed Version
In the LTC4218-12, the UV, OV and FB pins are driven by
internal dividers which may need to be filtered to prevent
false faults. By placing a bypass capacitor on these pins
the faults are delayed by the RC time constant. Use the RIN
value from the electrical table for this calculation.
In cases where the fixed thresholds need a slight adjustment, placing a resistor from the UV or OV pins to VDD
or GND will adjust the threshold up or down. Likewise,
placing a resistor between FB pin to OUT or GND adjusts
the threshold. Again, use the RIN value from the electrical
table for this calculation.
An example in Figure 4 raises the UV turn-on voltage from
9.88V to 10.5V. Increasing the UV level requires adding a
resistor between UV and ground. The resistor, (RSHUNT1),
4218fh
12
For more information www.linear.com/LTC4218
LTC4218
Applications Information
Use the equation for RSHUNT1 for increasing the OV and
FB thresholds. Likewise, use the equation for RSHUNT2 for
decreasing the UV and FB thresholds.
can be calculated using electrical table parameters as
follows:
RSHUNT1 =
R(IN ) • VOLD
18k • 9.88V
=
= 287k
( VNEW – VOLD ) (10.5V – 9.88V )
LTC4218-12
Design Example
Consider the following design example (Figure 5): VIN =
12V, IMAX = 7.5A. IINRUSH = 1A, CL = 330µF, VUVON = 9.88V,
VOVOFF = 15.05V, VPGTHRESHOLD = 10.5V. A current limit fault
triggers an automatic restart of the power up sequence.
VDD
OV
RSHUNT2
The selection of the sense resistor, (RS), is set by the
overcurrent threshold of 15mV:
UV
RS = 15mV/IMAX = 15mV/7.5A = 0.002Ω
RSHUNT1
The MOSFET should be sized to handle the power dissipation during the inrush charging of the output capacitor
COUT. The method used to determine the power in Q1 is
the principal:
4218 F04
Figure 4. Adjusting LTC4218-12 Thresholds
In this same figure the OV threshold is lowered from
15.05V to 13.5V. Decreasing the OV threshold requires
adding a resistor between VDD and OV. This resistor can
be calculated as follows:
(
R(IN ) • VOLD VNEW – VOV( TH )
RSHUNT2 =
V( TH ) ( VOLD – VNEW )
EC = Energy in CL = Energy in Q1
Thus:
) =
EC = ½ CV2 = ½ (330µF)(12)2 = 0.024J
Calculate the time it takes to charge up COUT:
18k • 15.05V (13.5V – 1.235V )
= 1.736M
1.235V (15.05V – 13.5V )
CL • VIN 330µF • 12V
=
= 4ms
IINRUSH
1A
Q1
Si7108DN
RS
2mΩ
12V
tCHARGUP =
Z1*
+
R1
10Ω
SENSE–
SENSE
GATE SOURCE
+
RGATE
1k
CGATE
0.01µF
VDD
UV
CT
0.1µF
*TVS Z1: DIODES INC SMAJ17A
C1
1µF
CL
330µF
UV = 9.88V
OV = 15.05V
PG = 10.5V
R8
10k
LTC4218DHC-12
FLT
VOUT
12V
6A
PG
TIMER
IMON
INTVCC
GND
ADC
RMON
20k
4218 F05
Figure 5. 6A, 12V Card Resident Application
4218fh
For more information www.linear.com/LTC4218
13
LTC4218
Applications Information
The inrush current is set to 1A using CGATE:
CGATE = CL
IGATE(UP)
24µA
= 330µF
≅ 0.01µF
IINRUSH
1A
The average power dissipated in the MOSFET:
PDISS = EC/tCHARGUP = 0.024J/4ms = 6W
The SOA (safe operating area) curves of candidate MOSFETs must be evaluated to ensure that the heat capacity
of the package can stand 6W for 4ms. The SOA curves of
the Vishay Siliconix Si7108DN provide 1.5A at 10V (15W)
for 100ms, satisfying the requirement.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
for the sense resistor is recommended. The PCB layout
should be balanced and symmetrical to minimize wiring
errors. In addition, the PCB layout for the sense resistors
and the power MOSFETs should include good thermal
management techniques for optimal device power dissipation. A recommended PCB layout for the sense resistor
and power MOSFET is illustrated in Figure 6.
Next, the power dissipated in the MOSFET during overcurrent must be limited. The active current limit uses a timer
to prevent excessive energy dissipation in the MOSFET. The
worst-case power occurs when the voltage versus current
profile of the foldback current limit is at the maximum.
This occurs when the current is 6A and the voltage is one
half of 12V or (6V). See the Current Limit Sense Voltage vs
FB Voltage in the Typical Performance curves to view this
profile. In order to survive 36W, the MOSFET SOA dictates
a maximum time at this power level. The Si7108DN allows
60W for 10ms or less. Therefore, it is acceptable to set
the current limit timeout using CT to be 1.2ms:
R1
LTC4218
C
4218 F06
Figure 6. Recommended Layout
CT = 1.2ms/12[ms/µF] = 0.1µF
After the 1.2ms timeout the FLT pin needs to pull down on
the UV pin to restart the power-up sequence.
Since the default values for overvoltage, undervoltage and
power good thresholds for the 12V fixed version match
the requirements, no external components are required
for the UV, OV and FB pins.
The final schematic results in very few external components. Resistor R1 (10Ω) prevents high frequency
oscillations in Q1 while RGATE of 1k isolates CGATE during
fast turn-off. The pull-up resistor, (R2), connects to the
PG pin while the 20k (R3) converts the IMON current to a
voltage at a ratio:
µA mV
V
VIMON = 6.67 • 2 • 20k •IOUT = 0.267 •IOUT
mV A
A
Q1
RS
In Hot Swap applications where load currents can be 6A,
narrow PCB tracks exhibit more resistances than wider
tracks and operate at elevated temperatures. The minimum
trace width for 1oz copper foil is 0.02” per amp to make sure
the trace stays at a reasonable temperature. Using 0.03”
per amp or wider is recommended. Note that 1oz copper
exhibits a sheet resistance of about 0.5mΩ/square. Small
resistances add up quickly in high current applications.
It is also important to put C1, the bypass capacitor for the
INTVCC pin, as close as possible between the INTVCC and
GND. Place the 10Ω resistor as close as possible to Q1.
This will limit the parasitic trace capacitance that leads to
Q1 self-oscillation. The traces connecting the LTC4218
to components should overlay a plane connected to the
ground pin of the part (pin 7).
In addition, there is a 0.1µF bypass (C1) on the INTVCC pin.
4218fh
14
For more information www.linear.com/LTC4218
LTC4218
Applications Information
Additional Applications
The last page includes a 24V application with a UV
threshold of 19.8V, an OV threshold of 28.3V and a PG
threshold of 20.75V. Figure 7 shows a 3.3V application with a UV threshold of 2.87V, an OV threshold of
3.77V and a PG threshold of 3.05V. Figure 8 shows a
backplane resident application, where load insertion
activates turn-on.
The LTC4218 has a wide operating range from 2.9V to
26.5V. The UV, OV and PG thresholds are set with a few
resistors. All other functions are independent of supply
voltage.
RS
2mΩ
3.3V
Q1
Si7102DN
Z1*
R6
14.7k
R1
10Ω
RGATE
1k
CGATE
0.01µF
SENSE– GATE SOURCE
+
SENSE
R2
17.4k
VDD
UV
R3
3.16k
FLT
FB
CL
330µF
UV = 2.87V
OV = 3.77V
PG = 3.05V
R7
10k
LTC4218GN
+
VOUT
3.3V
6A
R8
10k
OV
R4
10k
CT
0.1µF
TIMER
PG
INTVCC
IOUT
C1
1µF
ADC
RMON
20k
GND
4218 F07
*TVS Z1: DIODES INC SMAJ17A
Figure 7. 3.3V, 6A Card Resident Application
Q1
Si7108DN
RS
2mΩ
12V
Z1*
VOUT
12V
6A
12V
R1
10Ω
SENSE– GATE SOURCE
SENSE+
VDD
FB
OV
UV
LTC4218GN
R8
10k
FLT
PG
CT
0.1µF
RGATE
1k
CGATE
0.01µF
R6
150k
R7
20k
R4
140k
LOAD
UV = 9.88V
OV = 15.2V
PG = 10.5V
R5
20k
TIMER
C1
1µF
INTVCC
IMON
GND
RMON
20k
ADC
4218 F08
*TVS Z1: DIODES INC SMAJ17A
Figure 8. 12V, 6A Backplane Resident Application with Insertion Activated Turn -On
4218fh
For more information www.linear.com/LTC4218
15
LTC4218
Package Description
Please refer to http://www.linear.com/product/LTC4218#packaging for the most recent package drawings.
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
5.00 ±0.10
(2 SIDES)
0.65 ±0.05
1.65 ±0.05
2.20 ±0.05 (2 SIDES)
9
R = 0.20
TYP
3.00 ±0.10
(2 SIDES)
1.65 ± 0.10
(2 SIDES)
3.50 ±0.05
PACKAGE
OUTLINE
R = 0.115
TYP
0.40 ± 0.10
16
PIN 1
TOP MARK
(SEE NOTE 6)
4.40 ±0.05
(2 SIDES)
PIN 1
NOTCH
8
0.25 ± 0.05
0.50 BSC
(DHC16) DFN 1103
4.40 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1)
IN JEDEC PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ±.004
× 45°
(0.38 ±0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
.0532 – .0688
(1.35 – 1.75)
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 REV B 0212
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
4218fh
16
For more information www.linear.com/LTC4218
LTC4218
Revision History
(Revision history begins at Rev D)
REV
DATE
DESCRIPTION
PAGE NUMBER
D
12/09
Revised Order Information.
2
Revised Equation in Applications Information.
14
E
4/10
Revised Storage Temperature Range in Absolute Maximum Ratings section.
2
Revised Additional Applications section and inserted Figure 8 in Applications Information.
15
F
1/12
Updated Typical Applications.
1
Revised Inputs and Outputs sections of Electrical Characteristics.
3
Updated INTVCC and PG pin descriptions.
7
Changed value of R2 in Figure 1.
10
Deleted text from Overcurrent & Fault section and updated values in Monitor OV and UV Faults section.
G
H
7/14
2/16
11, 12
Revised Typical Application and Related Parts list.
18
IGATE(DN) Specification: Changed maximum from 340µA to 400µA
3
ISET Pin Function: Added note that resistor should not be less than 2k
7
Added SMAJ17A TVS to application circuit
Changed INTVCC capacitor to 1µF in application circuit
1, 10, 13, 15
1, 10, 13, 15, 18
Clarified that operating temperature range refers to ambient
2
Added BWIMON and tD(FAULT) specifications
4
Updated INTVCC and ISET pin functions
7
Figure 1: Added C2
10
Added section titled Current Limit Stability
11
Added recommendation for a 0.1µF ISET capacitor
12
4218fh
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC4218
Typical Application
24V, 6A Card Resident Application with Auto-Retry
2mΩ
24V
*
Si7788DP
10Ω
158k
+
VOUT
24V
6A
330µF
1k
SENSE–
GATE SOURCE
SENSE+
215k
0.01µF
FB
VDD
UV
FLT
4.32k
UV = 19.8V
OV = 28.3V
PG = 20.75V
10k
LTC4218GN
10k
OV
10k
PG
0.1µF
TIMER
ISET
INTVCC
IMON
GND
1µF
ADC
20k
*DIODES INC SMAJ24A
4218 TA02
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC4210
Hot Swap Controller
Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6
LTC4211
Hot Swap Controller
Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10
LTC4212
Hot Swap Controller
Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10
LTC4214
Negative Voltage Hot Swap Controller
Operates from 0V to –16V, MSOP-10
LTC4215
Hot Swap Controller with ADC and I2C
Operates from 2.9V to 15V, Digitally Monitors Voltage and Current with 8-Bit ADC
LT4220
Positive and Negative Voltage, Dual Channel,
Hot Swap Controller
Operates from ±2.7V to ±16.5V, SSOP-16
LTC4221
Dual Hot Swap Controller/Sequencer
Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16
LTC4230
Triple Channel Hot Swap Controller
Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20
LTC4245
Quad Hot Swap Controller with ADC and I2C
Interface
3.3V, 5V and ±12V for CompactPCI, or 3.3V, 3.3V Auxiliary and 12V for PCIExpress, Monitors Voltage and Current with 8-Bit ADC
LTC4232
5A Integrated Hot Swap Controller
2.9V to 15V Operation, 10% Accurate Current Limit
LTC4217
2A Integrated Hot Swap Controller
Operates from 2.9V to 26.5V, Adjustable 5% Accurate Current Limit
LTC4233
10A Guaranteed SOA Hot Swap Controller
Operates from 2.9V to 15V, Adjustable 11% Current Limit
LTC4234
20A Guaranteed SOA Hot Swap Controller
Operates from 2.9V to 15V, Adjustable 11% Current Limit
Interface
4218fh
18 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC4218
(408) 432-1900 ● FAX: (408) 434-0507
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www.linear.com/LTC4218
LT 0216 REV H • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2007
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