LTC4251BIS6-2#TRPBF

LTC4251B/LTC4251B-1/ LTC4251B-2 Negative Voltage Hot Swap Controllers in SOT-23 FEATURES DESCRIPTION n The LTC®4251B/LTC4251B-1/LTC4251B-2 negative voltage Hot Swap™ controllers allow a board to be safely inserted and removed from a live backplane. Output current is controlled by three stages of current limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. n n n n n n n Allows Safe Board Insertion and Removal from a Live –48V Backplane Floating Topology Permits Very High Voltage Operation Programmable Analog Current Limit with Circuit Breaker Timer Fast Response Time Limits Peak Fault Current Improved Ruggedness Shunt Regulator Programmable Timer Programmable Undervoltage/Overvoltage Protection Low Profile 6-Lead SOT-23 (ThinSOT™) Package Programmable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the desired operating range. The supply input is shunt regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial start-up and controls the circuit breaker’s response time. APPLICATIONS n n n n n n n n The LTC4251B UV/OV thresholds are designed to match the standard telecom operating range of – 43V to –75V. The LTC4251B-1 UV/OV thresholds extend the operating range to encompass –36V to –72V. The LTC4251B-2 implements a UV threshold of –43V only. The LTC4251B improves the ruggedness of the LTC4251 shunt regulator. Hot Board Insertion Electronic Circuit Breaker –48V Distributed Power Systems Negative Power Supply Control Central Office Switching Programmable Current Limiting Circuit High Availability Servers Disk Arrays L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION –48V, 2.5A Hot Swap Controller Start-Up Behavior –48RTN RIN* 10k 500mW –48RTN (SHORT PIN) R1 402k 1% DIN† DDZ13B** R2 32.4k 1% + LOAD GATE 5V/DIV VOUT CIN 1μF VIN UV/OV C1 10nF CL 100μF GATE Q1 IRF530S SENSE 2.5A/DIV 1 RS 0.02Ω VOUT 20V/DIV LTC4251B 3 TIMER SENSE VEE CT 150nF RC 10Ω CC 18nF 2 4 –48V 4251b12 TA01a 1ms/DIV 4251b12 TA01b *TWO 0.25W RESISTORS IN SERIES FOR RIN ON THE PCB ARE RECOMMENDED. **DIODES, INC. †RECOMMENDED FOR HARSH ENVIRONMENTS 4251b12f 1 LTC4251B/LTC4251B-1/ LTC4251B-2 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1), All Voltages are Referred to VEE Current into VIN (100μs Pulse) .............................100mA Minimum VIN Voltage ............................................ – 0.3V Gate, UV/OV, Timer Voltage........................ –0.3V to 16V Sense Voltage ............................................ –0.6V to 16V Current Out of Sense Pin (20μs Pulse).............. –200mA Maximum Junction Temperature .......................... 125°C Operating Temperature Range LTC4251BC/LTC4251BC-1/LTC4251BC-2....0°C to 70°C LTC4251BI/LTC4251BI-1/LTC4251BI-2 .. –40°C to 85°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec)................... 300°C TOP VIEW SENSE 1 6 GATE VEE 2 5 UV/OV* VIN 3 4 TIMER S6 PACKAGE 6-LEAD PLASTIC SOT-23 *UV FOR LTC4251B-2 TJMAX = 125°C, θJA = 192°C/W ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4251BCS6#TRMPBF LTC4251BCS6#TRPBF LTGCT 6-Lead Plastic SOT-23 0°C to 70°C LTC4251BIS6#TRMPBF LTC4251BIS6#TRPBF LTGCT 6-Lead Plastic SOT-23 –40°C to 85°C LTC4251BCS6-1#TRMPBF LTC4251BCS6-1#TRPBF LTGDV 6-Lead Plastic SOT-23 0°C to 70°C LTC4251BIS6-1#TRMPBF LTC4251BIS6-1#TRPBF LTGDV 6-Lead Plastic SOT-23 –40°C to 85°C LTC4251BCS6-2#TRMPBF LTC4251BCS6-2#TRPBF LTGDW 6-Lead Plastic SOT-23 0°C to 70°C LTC4251BIS6-2#TRMPBF LTC4251BIS6-2#TRPBF LTGDW 6-Lead Plastic SOT-23 TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ –40°C to 85°C ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 3) SYMBOL PARAMETER CONDITIONS l MIN TYP MAX 11.5 13 14.5 VZ VIN to VEE Zener Voltage IIN = 2mA rZ VIN to VEE Zener Dynamic Impedance IIN = 2mA to 30mA IIN VIN Supply Current UV/OV = 4V, VIN = (VZ – 0.3V) l 0.8 2 VLKO VIN Undervoltage Lockout Coming Out of UVLO (Rising VIN) l 9.2 11.5 VLKH VIN Undervoltage Lockout Hysteresis 5 UNITS V Ω 1 mA V V VCB Circuit Breaker Current Limit Voltage VCB = (VSENSE – VEE) l 40 50 60 mV VACL Analog Current Limit Voltage VACL = (VSENSE – VEE) l 80 100 120 mV VFCL Fast Current Limit Voltage VFCL = (VSENSE – VEE) l 150 200 300 mV IGATE GATE Pin Output Current UV/OV = 4V, VSENSE = VEE, VGATE = 0V (Sourcing) UV/OV = 4V, VSENSE – VEE = 0.15V, VGATE = 3V (Sinking) UV/OV = 4V, VSENSE – VEE = 0.3V, VGATE = 1V (Sinking) l 40 58 17 190 80 μA mA mA VGATE External MOSFET Gate Drive VGATE – VEE, IIN = 2mA l 10 12 VZ V 4251b12f 2 LTC4251B/LTC4251B-1/ LTC4251B-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VGATEL Gate Low Threshold (Before Gate Ramp-Up) 0.5 VUVHI UV Threshold High LTC4251B/LTC4251B-2 LTC4251B-1 l l 3.075 2.300 3.225 2.420 3.375 2.540 V V VUVLO UV Threshold Low LTC4251B/LTC4251B-2 LTC4251B-1 l l 2.775 2.050 2.925 2.160 3.075 2.270 V V VUVHST UV Hysteresis LTC4251B/LTC4251B-2 LTC4251B-1 VOVHI OV Threshold High LTC4251B LTC4251B-1 l l 5.85 5.86 6.15 6.17 6.45 6.48 V V VOVLO OV Threshold Low LTC4251B LTC4251B-1 l l 5.25 5.61 5.55 5.91 5.85 6.21 V V VOVHST OV Hysteresis LTC4251B LTC4251B-1 ISENSE SENSE Input Current UV/OV = 4V, VSENSE = 50mV l IINP UV/OV Input Current UV/OV = 4V l VTMRH Timer Voltage High Threshold 4 V VTMRL Timer Voltage Low Threshold 1 V ITMR Timer Current tPLLUG UV Low to GATE Low tPHLOG OV High to GATE Low 0.30 0.26 IIN vs Temperature 1000 VIN = (VZ – 0.3V) 10 1000 800 ±1 μA 5.8 28 230 5.8 μA mA μA μA 0.7 μs 1 μs rZ vs Temperature IIN = 2mA 8 10 TA = 85°C 7 6 5 600 TA = 125°C 1 400 4 3 200 0 –55 –35 –15 μA 9 rZ (Ω) IIN (mA) IIN (μA) IIN vs VIN TA = 25°C 1200 –15 UV/OV = 4V refers to UV = 4V for the LTC4251B-2. 100 1400 V V Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified. Note 3: UV/OV = 4V refers to UV = 4V for the LTC4251B-2. TA = –40°C 1600 V V 0.60 0.26 ±0.1 LTC4251B/LTC4251B-1 TYPICAL PERFORMANCE CHARACTERISTICS 1800 –30 Timer On (Initial Cycle, Sourcing), VTMR = 2V Timer Off (Initial Cycle, Sinking), VTMR = 2V Timer On (Circuit Breaker, Sourcing), VTMR = 2V Timer Off (Cooling Cycle, Sinking), VTMR = 2V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. 2000 V 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G01 0.1 0 2 4 6 8 10 12 14 16 18 20 22 VIN (V) 4251b12 G02 2 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G03 4251b12f 3 LTC4251B/LTC4251B-1/ LTC4251B-2 TYPICAL PERFORMANCE CHARACTERISTICS Undervoltage Lockout VLKO vs Temperature VZ vs Temperature 14.0 VZ (V) VLKO (V) 13.5 13.0 12.0 1.6 11.5 1.4 11.0 1.2 10.5 1 10.0 12.5 12.0 –55 –35 –15 VLKH IIN = 2mA 0.6 9.0 0.4 8.5 0.2 8.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G05 Circuit Breaker Current Limit Voltage VCB vs Temperature 60 120 58 115 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G06 Analog Current Limit Voltage VACL vs Temperature 56 Fast Current Limit Voltage VFCL vs Temperature 300 275 110 54 250 50 48 VFCL (mV) 105 52 VACL (V) VCB (mV) 0.8 9.5 4251b12 G04 100 95 46 225 200 90 44 175 85 42 40 –55 –35 –15 80 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G07 150 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G08 IGATE (Source) vs Temperature 30 UV/0V = 4V TIMER = 0V 65 VSENSE = VEE VGATE = 0V 25 IGATE (FCL, Sink) vs Temperature 400 UV/0V = 4V TIMER = 0V VSENSE – VEE = 0.15V VGATE = 3V 350 300 20 IGATE (mA) 60 55 15 50 10 45 5 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G09 IGATE (ACL, Sink) vs Temperature 70 IGATE (μA) Undervoltage Lockout Hysteresis VLKH vs Temperature IGATE (mA) 14.5 UV/OV = 4V refers to UV = 4V for the LTC4251B-2. UV/0V = 4V TIMER = 0V VSENSE – VEE = 0.3V VGATE = 1V 250 200 150 100 40 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G10 0 –55 –35 –15 50 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G11 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G12 4251b12f 4 LTC4251B/LTC4251B-1/ LTC4251B-2 TYPICAL PERFORMANCE CHARACTERISTICS VGATE vs Temperature 14.0 13.5 VGATEL vs Temperature 0.8 UV/0V = 4V VTMR = 0V VSENSE = VEE 0.7 0.6 VGATEL (V) VGATE (V) 13.0 12.5 12.0 11.5 UV Threshold vs Temperature 3.375 UV/0V = 4V, VTMR = 0V, GATE THRESHOLD BEFORE RAMP-UP LTC4251B/LTC4251B-2 3.275 UV THRESHOLD (V) 14.5 0.5 0.4 0.3 10.0 –55 –35 –15 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 3.075 2.975 VUVL 2.775 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G13 4251b12 G15 OV Threshold vs Temperature UV Threshold vs Temperature OV Threshold vs Temperature 6.45 6.51 LTC4251B 6.25 VOVH VUVHI OV THRESHOLD (V) 2.40 2.35 2.30 2.25 2.20 5.85 5.65 LTC4251B-1 6.31 6.05 VOVL VUVLO 2.15 6.41 OV THRESHOLD (V) LTC4251B-1 2.45 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G14 2.55 UV THRESHOLD (V) 3.175 2.875 0.1 10.5 6.21 VOVHI 6.11 6.01 VOVLO 5.91 5.81 5.45 5.71 2.10 2.05 –55 –35 –15 5.25 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) 5.61 –55 –35 –15 4251b12 G18 ISENSE vs (VSENSE – VEE) ISENSE vs Temperature –10 TIMER Threshold vs Temperature 0.01 5.0 –12 4.5 0.1 4.0 –ISENSE (mA) –16 –20 –22 1.0 10 –24 –26 –28 –30 –55 –35 –15 UV/0V = 4V TIMER = 0V GATE = HIGH VSENSE – VEE = 50mV 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G19 100 UV/0V = 4V TIMER = 0V GATE = HIGH TA = 25°C 1000 –1.5 –1.0 –0.5 0 0.5 1.0 (VSENSE – VEE) (V) 1.5 2.0 4251b12 G20 TIMER THRESHOLD (V) –14 –18 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G17 4251b12 G16 ISENSE (μA) VUVH 0.2 11.0 2.50 UV/OV = 4V refers to UV = 4V for the LTC4251B-2. VTMRH 3.5 3.0 2.5 2.0 1.5 1.0 VTMRL 0.5 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G21 4251b12f 5 LTC4251B/LTC4251B-1/ LTC4251B-2 TYPICAL PERFORMANCE CHARACTERISTICS ITMR (Initial Cycle, Sourcing) vs Temperature ITMR (Circuit Breaking, Sourcing) vs Temperature ITMR (Initial Cycle, Sinking) vs Temperature 10 50 9 45 8 280 260 40 ITMR (mA) 6 5 4 3 35 ITMR (μA) 7 ITMR (μA) UV/OV = 4V refers to UV = 4V for the LTC4251B-2. 30 25 20 2 240 220 200 15 1 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 10 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G22 4251b12 G24 t PLLUG and tPHLOG vs Temperature 10 1.3 9 1.2 8 1.1 7 tPHLOG (LTC4251B/LTC4251B-1) DELAY (μs) ITMR (μA) 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G23 ITMR (Cooling Cycle, Sinking) vs Temperature 6 5 4 1.0 0.9 0.8 tPLLUG 3 0.7 2 0.6 1 0 –55 –35 –15 180 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G25 0.5 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 4251b12 G26 4251b12f 6 LTC4251B/LTC4251B-1/ LTC4251B-2 PIN FUNCTIONS UV/OV refers to the UV pin for the LTC4251B-2. The OV comparator in the LTC4251B-2 is disabled. All references in the text to overvoltage, OV, VOVHI and VOVLO do not apply to the LTC4251B-2. SENSE (Pin 1): Circuit Breaker/Current Limit SENSE Pin. Load current is monitored by sense resistor RS connected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a 230μA TIMER pin pull-up current. The LTC4251B/LTC4251B-1/LTC4251B-2 latch off when CT charges to 4V. If SENSE exceeds VACL (100mV), the analog current limit amplifier pulls GATE down and regulates the MOSFET current at VACL/RS. In the event of a catastrophic short-circuit, SENSE may overshoot 100mV. If SENSE reaches VFCL (200mV), the fast current limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE. Kelvin-sense connections between the sense resistor and the VEE and SENSE pins are strongly recommended, see Figure 6. VEE (Pin 2): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. VIN (Pin 3): Positive Supply Input. Connect this pin to the positive side of the supply through a dropping resistor. A shunt regulator typically clamps VIN at 13V. An internal undervoltage lockout (UVLO) circuit holds GATE low until the VIN pin is greater than VLKO (9.2V), overriding UV/OV. If UV is high, OV is low and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating a GATE ramp up. If VIN drops below approximately 8.2V, GATE pulls low immediately. TIMER (Pin 4): Timer Input. TIMER is used to generate a delay at start-up, and to delay shutdown in the event of an output overload. TIMER starts an initial timing cycle when the following conditions are met: UV is high, OV is low, VIN clears UVLO, TIMER pin is low, GATE is lower than VGATEL and VSENSE – VEE < VCB. A pull-up current of 5.8μA then charges CT, generating a time delay. If CT charges to VTMRH (4V) the timing cycle terminates, TIMER quickly pulls low and GATE is activated. If SENSE exceeds 50mV while GATE is high, a 230μA pull-up current charges CT. If SENSE drops below 50mV before TIMER reaches 4V, a 5.8μA pull-down current slowly discharges CT. In the event that CT eventually integrates up to the 4V VTMRH threshold, TIMER latches high with a 5.8μA pull-up source and GATE quickly pulls low. The LTC4251B/LTC4251B-1/LTC4251B-2 fault latches may be cleared by either pulling TIMER low with an external device, or by pulling UV/OV below VUVLO. UV/OV (Pin 5): Undervoltage/Overvoltage Input. This dual function pin detects undervoltage as well as overvoltage. The high threshold at the UV comparator is set at VUVHI with VUVHST hysteresis. The high threshold at the OV comparator is set at VOVHI with VOVHST hysteresis. If UV/ OV < VUVLO or UV/OV > VOVHI, GATE pulls low. If UV/OV > VUVHI and UV/OV < VOVLO, the LTC4251B/LTC4251B-1/ LTC4251B-2 attempt to start-up. The internal UVLO at VIN always overrides UV/OV. A low at UV resets an internal fault latch. A high at OV pulls GATE low but does not reset the fault latch. A 1nF to 10nF capacitor at UV/OV eliminates transients and switching noise from affecting the UV/OV thresholds and prevents glitches at the GATE pin. GATE (Pin 6): N-Channel MOSFET Gate Drive Output. This pin is pulled high by a 58μA current source. GATE is pulled low by invalid conditions at VIN (UVLO), UV/OV, or the fault latch. GATE is actively servoed to control fault current as measured at SENSE. A compensation capacitor at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, GATE ramp up after an overvoltage event, or restart after a current limit fault. 4251b12f 7 LTC4251B/LTC4251B-1/ LTC4251B-2 BLOCK DIAGRAM VIN 3 VOVHI – VIN OV** 58μA + 6 GATE VEE – 5 + UV/OV* VEE 0.5V UV 230μA + VIN 5.8μA LOGIC 4V + VIN – VUVLO – FCL VIN TIMER – + 200mV 22μA +– VEE 4 – 1V VEE 5.8μA + ACL 5k VOS = 10mV + –+ VEE – VEE VEE + CB 50mV – 2 *UV FOR THE LTC4251B-2 ** THE OV COMPARATOR IS DISABLED FOR LTC4251B-2 1 SENSE +– VEE 4251b12 BD VEE 4251b12f 8 LTC4251B/LTC4251B-1/ LTC4251B-2 OPERATION Note that for simplicity, the following assumptions are made in the text. Firstly, UV/OV also means the UV pin of the LTC4251B-2. Secondly, all overvoltage conditions and references to OV, VOVHI and VOVLO do not apply to the LTC4251B-2 as the OV comparator in this part is disabled. Hot Circuit Insertion LONG –48RTN RIN 10k 500mW When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4251B/ LTC4251B-1/LTC4251B-2 are designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. SHORT DIN† DDZ13B** R1 402k 1% CIN 1μF VIN UV/OV TIMER VEE R2 32.4k 1% CT 150nF LONG –48V A detailed schematic is shown in Figure 2. –48V and –48RTN receive power through the longest connector pins, and are the first to connect when the board is inserted. The GATE pin holds the MOSFET off during this time. UV/ OV determines whether or not the MOSFET should be turned on based upon internal, high accuracy thresholds and an external divider. UV/OV does double duty by also monitoring whether or not the connector is seated. The top of the divider detects –48RTN by way of a short connector pin that is the last to mate during the insertion sequence. SENSE CC 18nF 4 CL 100μF TYP GATE RC 10Ω 3 2 RS 1 20mΩ Initial Start-Up The LTC4251B/LTC4251B-1/LTC4251B-2 reside on a removable circuit board and control the path between the connector and load or power conversion circuitry with an external MOSFET switch (see Figure 1). Both inrush control and short-circuit protection are provided by the MOSFET. + LTC4251B C1 10nF Q1 IRF530S 4251b12 F02 **DIODES, INC. †RECOMMENDED FOR HARSH ENVIRONMENTS Figure 2. –48V, 2.5A Hot Swap Controller Interlock Conditions A start-up sequence commences once five initial “interlock” conditions are met: 1. The input voltage VIN exceeds 9.2V (VLKO) 2. The voltage at UV/OV falls within the range of VUVHI to VOVLO (UV > VUVHI, LTC4251B-2) 3. The (SENSE – VEE) voltage is 50mV, TIMER charges CT during this time and the LTC4251B/LTC4251B-1/LTC4251B-2 will eventually shut down. Low impedance failures on the load side of the LTC4251B/ LTC4251B-1/LTC4251B-2 coupled with 48V or more driving potential can produce current slew rates well in excess of 50A/μs. Under these conditions, overshoot is inevitable. A fast SENSE comparator with a threshold of 200mV detects overshoot and pulls GATE low much harder and hence much faster than can the weaker current limit loop. The 100mV/RS current limit loop then takes over, and servos the current as previously described. As before, TIMER runs and latches the LTC4251B/LTC4251B-1/LTC4251B-2 off when CT reaches 4V. The LTC4251B/LTC4251B-1/LTC4251B-2 circuit breaker latch is reset by either pulling UV/OV momentarily low, or dropping the input voltage VIN below the internal UVLO threshold of 8.2V. Although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus, or the insertion of non-hot swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. The action of TIMER and CT rejects these events allowing the LTC4251B/LTC4251B-1/ LTC4251B-2 to “ride out” temporary overloads and disturbances that would trip a simple current comparator and in some cases, blow a fuse. 4251b12f 10 LTC4251B/LTC4251B-1/ LTC4251B-2 APPLICATIONS INFORMATION SHUNT REGULATOR OV turning off at VOVHI A fast responding shunt regulator clamps the VIN pin to 13V (VZ). Power is derived from –48RTN by an external current limiting resistor, RIN. A 1μF decoupling capacitor, CIN filters supply transients and contributes a short delay at start-up. OV turning on at VOVLO To meet creepage requirements RIN may be split into two or more series connected units, such as two 5.1k or three 3.3k resistors. This introduces a wider total spacing than is possible with a single component while at the same time ballasting the potential across the gap under each resistor. The LTC4251B is fundamentally a low voltage device that operates with –48V as its reference ground. To further protect against arc discharge into its pins, the area in and around the LTC4251B and all associated components should be free of any other planes such as chassis ground, return, or secondary-side power and ground planes. VIN is rated handle 30mA within the thermal limits of the package, and is tested to survive a 100μs, 100mA pulse. To protect VIN against damage from higher amplitude spikes, clamp VIN to VEE with a 13V Zener diode. Star connect VEE and all VEE referred components to the sense resistor Kelvin terminal as illustrated in Figure 2, keeping trace lengths between VIN, CIN, DIN and VEE as short as possible. INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) Internal circuitry monitors VIN for undervoltage. The exact thresholds are defined by VLKO and its hysteresis, VLKH. When VIN rises above 9.2V (VLKO) the chip is enabled; below 8.2V (VLKO-VLKH) it is disabled and GATE is pulled low. The UVLO function at VIN should not be confused with the UV/OV pin. These are completely separate functions. UV/OV COMPARATORS Two hysteretic comparators for detecting under- and overvoltage conditions, with the following thresholds, monitor the dual function UV/OV pin: UV turning on at VUVHI UV turning off at VUVLO The UV and OV trip point ratio for LTC4251B is designed to match the standard telecom operating range of 43V to 75V. The LTC4251B-2 implements a UV threshold of 43V only. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 402k and R2 = 32.4k gives a typical operating range of 43.2V to 74.4V. The under- and overvoltage shutdown thresholds are then 39.2V and 82.5V. 1% divider resistors are recommended to preserve threshold accuracy. The same resistor values can be used for the LTC4251B-2. The R1-R2 divider values shown in the Typical Application set a standing current of slightly more than 100μA, and define an impedance at UV/OV of 30k. In most applications, 30k impedance coupled with 300mV UV hysteresis makes the LTC4251B/LTC4251B-1/LTC4251B-2 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. The UV and OV trip point thresholds for the LTC4251B-1 are designed to encompass the standard telecom operating range of –36V to –72V. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 442k and R2 = 34.8k gives a typical operating range of 33.2V to 81V. The typical under- and overvoltage shutdown thresholds are then 29.6V and 84.5V. 1% divider resistors are recommended to preserve threshold accuracy. The R1-R2 divider values shown in the Typical Application set a standing current of slightly more than 100μA, and define an impedance at UV/OV of 32k. In most applications, 32k impedance coupled with 260mV UV hysteresis makes the LTC4251B-1 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. UV/OV OPERATION A low input to the UV comparator will reset the chip and pull the GATE and TIMER pins low. A low-to-high UV transition will initiate an initial timing sequence if the three remaining interlock conditions are met. 4251b12f 11 LTC4251B/LTC4251B-1/ LTC4251B-2 APPLICATIONS INFORMATION Overvoltage conditions detected by the OV comparator will also pull GATE low, thereby shutting down the load, but it will not reset the circuit breaker latch. Returning the supply voltage to an acceptable range restarts the GATE pin provided all interlock conditions except TIMER are met. TIMER The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor, CT, is used at TIMER to provide timing for the LTC4251B/LTC4251B-1/ LTC4251B-2. Four different charging and discharging modes are available at TIMER: Intermittent overloads may exceed the 50mV threshold at SENSE, but if their duration is sufficiently short TIMER will not reach 4V and the LTC4251B/LTC4251B-1/LTC4251B-2 will not latch off. To handle this situation, the TIMER discharges CT slowly with a 5.8μA pull-down whenever the SENSE voltage is less than 50mV. Therefore any intermittent overload with an aggregate duty cycle of 2.5% or more will eventually trip the circuit breaker and latch off the LTC4251B/LTC4251B-1/LTC4251B-2. Figure 3 shows the circuit breaker response time in seconds normalized to 1μF. The asymmetric charging and discharging of CT is a fair gauge of MOSFET heating. 1. 5.8μA slow charge; initial timing delay NORMALIZED RESPONSE TIME (s/μF) 10 2. 230μA fast charge; circuit breaker delay 3. 5.8μA slow discharge; circuit breaker “cool-off” 4. Low impedance switch; resets capacitor after initial timing delay, in undervoltage lockout, and in overvoltage For initial startup, the 5.8μA pull-up is used. The low impedance switch is turned off and the 5.8μA current source is enabled when the four interlock conditions are met. CT charges to 4V in a time period given by: t= 4V • CT 5.8μA 0.1 0.01 0 20 40 60 80 FAULT DUTY CYCLE, D (%) 100 Figure 3. Circuit Breaker Response Time (1) CIRCUIT BREAKER TIMER OPERATION If the SENSE pin detects more than 50mV across RS, the TIMER pin charges CT with 230μA. If CT charges to 4V, the GATE pin pulls low and the LTC4251B/LTC4251B-1/ LTC4251B-2 latch off. The part remains latched off until either the UV/OV pin is momentarily pulsed low, or VIN dips into UVLO and is then restored. The circuit breaker timeout period is given by 4V • CT 230μA 4 t = CT(μF) 
t
%
o
 4251b12 F03 When CT reaches 4V (VTMRH), the low impedance switch turns on and discharges CT. The GATE output is enabled and the load turns on. t= 1 (2) GATE GATE is pulled low to VEE under any of the following conditions: in UVLO, during the initial timing cycle, in an overvoltage condition, or when the LTC4251B/LTC4251B-1/ LTC4251B-2 are latched off after a short-circuit. When GATE turns on, a 58μA current source charges the MOSFET gate and any associated external capacitance. VIN limits gate drive to no more than 14.5V. Gate-drain capacitance (CGD) feed through at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the MOSFET. A unique circuit pulls GATE low with practically no usable voltage at VIN, and eliminates current spikes at insertion. A large external gate-source capacitor is thus unnecessary for the purpose of compensating CGD. Instead, a smaller value (≥10nF) capacitor CC is adequate. CC also provides compensation for the analog current limit loop. 4251b12f 12 LTC4251B/LTC4251B-1/ LTC4251B-2 APPLICATIONS INFORMATION SENSE The SENSE pin is monitored by the circuit breaker (CB) comparator, the analog current limit (ACL) amplifier, and the fast current limit (FCL) comparator. Each of these three measures the potential of SENSE relative to VEE. If SENSE exceeds 50mV, the CB comparator activates the 230μA TIMER pull-up. At 100mV, the ACL amplifier servos the MOSFET current, and at 200mV the FCL comparator abruptly pulls GATE low in an attempt to bring the MOSFET current under control. If any of these conditions persists long enough for TIMER to charge CT to 4V (see Equation  (2)), the LTC4251B/LTC4251B-1/LTC4251B-2 latch off and pull GATE low. If the SENSE pin encounters a voltage greater than 100mV, the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since GATE overdrives the MOSFET in normal operation, the ACL amplifier needs time to discharge GATE to the threshold of the MOSFET. For a mild overload, the ACL amplifier can control the MOSFET current, but in the event of a severe overload the current may overshoot. At SENSE = 200mV, the FCL comparator takes over, quickly discharging the GATE pin to near VEE potential. FCL then releases, and the ACL amplifier takes over. All the while TIMER is running. The effect of FCL is to add a nonlinear response to the control loop in favor of reducing MOSFET current. Owing to inductive effects in the system, FCL typically overcorrects the current limit loop, and GATE undershoots. A zero in the loop (resistor RC in series with the gate capacitor) helps the ACL amplifier recover. SHORT-CIRCUIT OPERATION Circuit behavior arising from a load-side low impedance short is shown in Figure 4. Initially, the current overshoots the analog current limit level of VSENSE = 100mV (Trace 2) as the GATE pin works to bring VGS under control (Trace 3). The overshoot glitches the backplane in the negative direction, and when the current is reduced to 100mV/RS the backplane responds by glitching in the positive direction. TIMER commences charging CT (Trace 4) while the analog current limit loop maintains the fault current at 100mV/RS, which in this case is 5A (Trace 2). Note that the backplane voltage (Trace 1) sags under load. When CT reaches 4V, GATE turns off, the load current drops to zero and the backplane rings up to over 100V. The positive peak is usually limited by avalanche breakdown in the MOSFET, and can be further limited by adding a transient voltage suppressor across the input from – 48V to –48RTN, such as Diodes Inc. SMAT70A. A low impedance short on one card may influence the behavior of others sharing the same backplane. The initial glitch and backplane sag as seen in Figure 4, Trace 1, can rob charge from output capacitors on adjacent cards. When the faulty card shuts down, current flows in to refresh the capacitors. If LTC4251B, LTC4251B-1 or LTC4251B-2s are used throughout, they respond by limiting the inrush current to a value of 100mV/RS. If CT is sized correctly, the capacitors will recharge long before CT times out. –48RTN 50V/DIV SUPPLY RING OWING TO CURRENT OVERSHOOT SUPPLY RING OWING TO MOSFET TURN-OFF TRACE 1 ONSET OF OUTPUT SHORT-CIRCUIT SENSE 200mV/DIV GATE 10V/DIV TRACE 2 FAST CURRENT LIMIT TRACE 3 ANALOG CURRENT LIMIT TRACE 4 TIMER 5V/DIV LATCH OFF CTIMER RAMP 2ms/DIV 4251b12 F04 Figure 4. Output Short-Circuit Behavior (All Waveforms are Referenced to VEE) MOSFET SELECTION The external MOSFET switch must have adequate safe operating area (SOA) to charge the load capacitance on start-up and handle short-circuit conditions until TIMER latchoff. These considerations take precedence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current, but the opposite cannot be said. Consult the manufacturer’s MOSFET data sheet for safe operating area and effective transient thermal impedance curves. 4251b12f 13 LTC4251B/LTC4251B-1/ LTC4251B-2 APPLICATIONS INFORMATION MOSFET selection is a three-step process. First, RS is calculated, and then the time required to charge the load capacitance is determined. This timing, along with the maximum short-circuit current and maximum input voltage defines an operating point that is checked against the MOSFET’s SOA curve. To begin a design, first specify the required load current and load capacitance, IL and CL. The circuit breaker current trip point (50mV/RS) should be set to accommodate the maximum load current. Note that maximum input current to a DC/DC converter is expected at VSUPPLY (MIN). RS is given by: RS = 40mV IL(MAX) (3) where 40mV represents the guaranteed minimum circuit breaker threshold. During the initial charging process, the LTC4251B/ LTC4251B-1/LTC4251B-2 may operate the MOSFET in current limit, forcing 80mV to 120mV across RS. The minimum inrush current is given by: IINRUSH(MIN) = 80mV RS (4) Maximum short-circuit current limit is calculated using maximum VSENSE, or: 120mV ISHORT-CIRCUIT(MAX) = RS C • V CL • VSUPPLY(MAX) = I IINRUSH(MIN) C •V • R • 230μA CT = L SUPPLY (MAX) S (4V • 80mV) (7) Returning to Equation (2), the TIMER period is calculated and used in conjunction with VSUPPLY(MAX) and ISHORT-CIRCUIT(MAX) to check the SOA curves of a prospective MOSFET. As a numerical design example, consider a 30W load, which requires 1A input current at 36V. If VSUPPLY(MAX) = 72V and CL = 100μF, Equation (3) gives RSENSE = 40mΩ; Equation (7) gives CT = 207nF. To account for errors in RSENSE, CT, TIMER current (230μA) and TIMER threshold (4V), the calculated value should be multiplied by 1.5, giving a nearest standard value of CT = 330nF. If a short-circuit occurs, a current of up to 120mV/40mΩ = 3A will flow in the MOSFET for 5.7ms as dictated by CT = 330nF in Equation (2). The MOSFET must be selected based on this criterion. The IRF530S can handle 100V and 3A for 10ms, and is safe to use in this application. SUMMARY OF DESIGN FLOW To summarize the design flow, consider the application shown in Figure 2, which was designed for 50W: Calculate maximum load current: 50W/36V = 1.4A; allowing 83% converter efficiency, IIN (MAX) = 1.7A. (5) The TIMER capacitor CT must be selected based on the slowest expected charging rate; otherwise TIMER might time out before the load capacitor is fully charged. A value for CT is calculated based on the maximum time it takes the load capacitor to charge. That time is given by: t CL CHARGE = Substituting Equation (4) for IINRUSH(MIN) and equating (6) with (2) gives: (6) Calculate RS: from Equation (3) RS = 20mΩ. Calculate CT: from Equation (7) CT = 150nF (including 1.5X correction factor). Calculate TIMER period: from Equation (2) the short-circuit time-out period is t = 2.6ms. Calculate maximum short-circuit current: from Equation (5) maximum short-circuit current could be as high as 120mV/20mΩ = 6A. Consult MOSFET SOA curves: the IRF530S can handle 6A at 72V for 5ms, so it is safe to use in this application. 4251b12f 14 LTC4251B/LTC4251B-1/ LTC4251B-2 APPLICATIONS INFORMATION FREQUENCY COMPENSATION The LTC4251B/LTC4251B-1/LTC4251B-2 typical frequency compensation network for the analog current limit loop is a series RC (10Ω) and CC connected to VEE. Figure 5 depicts the relationship between the compensation capacitor CC and the MOSFET’s CISS. The line in Figure 5 is used to select a starting value for CC based upon the MOSFET’s CISS specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value of CC versus the starting value are small. Nevertheless, compensation values should be verified by board level short-circuit testing. As seen in Figure 4 previously, at the onset of a shortcircuit event, the input supply voltage can ring dramatically owing to series inductance. If this voltage avalanches the MOSFET, current continues to flow through the MOSFET to the output. The analog current limit loop cannot control this current flow and therefore the loop undershoots. This effect cannot be eliminated by frequency compensation. A zener diode is required to clamp the input supply voltage and prevent MOSFET avalanche. sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. CURRENT FLOW FROM LOAD CURRENT FLOW TO –48V BACKPLANE SENSE RESISTOR TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER W 4251b12 F06 TO SENSE TO VEE Figure 6. Making PCB Connections to the Sense Resistor TIMING WAVEFORMS System Power-Up COMPENSATION CAPACITOR CC (nF) 60 MTY100N10E 50 40 IRF3710 30 20 IRF540 IRF530 IRF740 10 0 0 2000 6000 4000 MOSFET CISS (pF) 8000 4251b12 F05 Figure 5. Recommended Compensation Capacitor CC vs MOSFET CISS SENSE RESISTOR CONSIDERATIONS For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the VEE and SENSE pins are strongly recommended. The drawing in Figure 6 illustrates the correct way of making connections between the LTC4251B/LTC4251B-1/LTC4251B-2 and the Figure 7 details the timing waveforms for a typical power-up sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At time point 1, the supply ramps up, together with UV/OV and VOUT. VIN follows at a slower rate as set by the VIN bypass capacitor. At time point 2, VIN exceeds VLKO and the internal logic checks for VUVHI < UV/OV < VOVLO, TIMER < VTMRL, GATE < VGATEL and SENSE < VCB. When all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8μA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is then quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL and SENSE < VCB must be satisfied before a start-up cycle is allowed to begin. GATE sources 58μA into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current begins flowing into the load capacitor. At time point 5, the SENSE voltage (VSENSE – VEE ) reaches the VCB threshold and activates the TIMER. The TIMER capacitor 4251b12f 15 LTC4251B/LTC4251B-1/ LTC4251B-2 APPLICATIONS INFORMATION is charged by a 230μA current-source pull-up. At time point 6, the analog current limit loop activates. Between time point 6 and time point 7, the GATE voltage is held essentially constant and the sense voltage is regulated at VACL. As the load capacitor nears full charge, its current begins to decline. At point 7, the load current falls and the sense voltage drops below VACL. The analog current limit loop shuts off and the GATE pin ramps further. At time point 8, the sense voltage drops below VCB and TIMER now discharges through a 5.8μA current source pull-down. At time point 9, GATE reaches its maximum voltage as determined by VIN. Live Insertion with Short Pin Control of UV/OV In this example as shown in Figure 8, power is delivered through long connector pins whereas the UV/OV divider makes contact through a short pin. This ensures the power connections are firmly established before the LTC4251B/ LTC4251B-1/LTC4251B-2 are activated. At time point 1, the power pins make contact and VIN ramps through VLKO. At time point 2, the UV/OV divider makes contact and its voltage exceeds VUVHI. In addition, the internal logic checks for VUVHI < UV/OV < VOVHI, TIMER < VTMRL, GATE < VGATEL and SENSE < VCB. When all conditions are met, an initial timing cycle starts and the TIMER capacitor is charged by a 5.8μA current source pull-up. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is then quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL and SENSE < VCB must be satisfied before a start-up cycle is allowed to begin. GATE sources 58μA into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET’s threshold, current begins flowing into the load capacitor. At time point 5, the SENSE voltage (VSENSE – VEE ) reaches the VCB threshold and activates the TIMER. The TIMER capacitor is charged by a 230μA current source pull-up. At time point 6, the analog current limit loop activates. Between time point 6 and time point 7, the GATE voltage is held essentially constant and the sense voltage is regulated at VACL. As the load capacitor nears full charge, its current begins to decline. At time point 7, the load current falls and the sense voltage drops below VACL. The analog current limit loop shuts off and the GATE pin ramps further. At time point 8, the sense voltage drops below VCB and TIMER now discharges through a 5.8μA current source pull-down. At time point 9, GATE reaches its maximum voltage as determined by VIN. Undervoltage Lockout Timing In Figure 9, when UV/OV drops below VUVLO (time point 1), TIMER and GATE pull low. If current has been flowing, the SENSE pin voltage decreases to zero as GATE collapses. When UV/OV recovers and clears VUVHI (time point 2), an initial time cycle begins followed by a start-up cycle. Undervoltage Timing with Overvoltage Glitch In Figure 10, when UV/OV clears VUVHI (time point 1), an initial timing cycle starts. If the system bus voltage overshoots VOVHI as shown at time point 2, TIMER discharges. At time point 3, the supply voltage recovers and drops below the VOVLO threshold. The initial timing cycle restarts followed by a start-up cycle. Overvoltage Timing During normal operation, if UV/OV exceeds VOVHI as shown at time point 1 of Figure 11, the TIMER status is unaffected. Nevertheless, GATE pulls down and disconnects the load. At time point 2, UV/OV recovers and drops below the VOVLO threshold. A gate ramp up cycle ensues. If the overvoltage glitch is long enough to deplete the load capacitor, a full start-up cycle may occur as shown between time points 3 through 6. Timer Behavior In Figure 12a, the TIMER capacitor charges at 230μA if the SENSE pin exceeds VCB. It is discharged with 5.8μA if the SENSE pin is less than VCB. In Figure 12b, when TIMER exceeds VTMRH, TIMER is latched high by the 5.8μA pull-up and GATE pulls down immediately. In Figure 12c, multiple momentary faults cause the TIMER capacitor to integrate until it latches. 4251b12f 16 LTC4251B/LTC4251B-1/ LTC4251B-2 APPLICATIONS INFORMATION VIN CLEARS VLKO, CHECK VUVHI