LTC4301
Supply Independent Hot
Swappable 2-Wire Bus Buffer
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FEATURES
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DESCRIPTIO
The LTC®4301 supply independent, hot swappable, 2-wire
bus buffer allows I/O card insertion into a live backplane
without corruption of the data and clock busses. In addition, the LTC4301 allows the VCC, SDAIN and SCLIN pullup voltage and the SDAOUT and SCLOUT pull-up voltage
to be independent from each other. Control circuitry
prevents the backplane from being connected to the card
until a stop bit or a bus idle is present. When the connection is made, the LTC4301 provides bidirectional buffering, keeping the backplane and card capacitances isolated.
Allows Bus Pull-Up Voltages Above or Below VCC
Bidirectional Buffer* for SDA and SCL Lines
Increases Fanout
Prevents SDA and SCL Corruption During Live Board
Insertion and Removal from Backplane
Isolates Input SDA and SCL Line from Output
10kV Human Body Model ESD Protection
1V Precharge On All SDA and SCL Lines
Supports Clock Stretching, Arbitration and
Synchronization
High Impedance SDA, SCL Pins for VCC = 0V
CS Gates Connection from Input to Output
Compatible with I2CTM, I2C Fast Mode and SMBus
Standards (Up to 400kHz Operation)
Small 8-Pin MSOP and DFN (3mm × 3mm) Packages
During insertion, the SDA and SCL lines are precharged to
1V to minimize bus disturbances. When driven low, the CS
input pin allows the part to connect after a stop bit or bus
idle occurs. Driving CS high breaks the connection between SCLIN and SCLOUT and between SDAIN and
SDAOUT. The READY output pin indicates that the backplane and card sides are connected together.
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APPLICATIO S
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The LTC4301 is offered in 8-pin DFN (3mm × 3mm) and
MSOP packages.
Hot Board Insertion
Servers
Capacitance Buffer/Bus Extender
Desktop Computers
CompactPCITM and ATCA Systems
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 7032051.
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TYPICAL APPLICATIO
3.3V
Input-Output Connection
5V
0.01µF
10k
10k
VCC
10k
LTC4301
STAGGERED CONNECTOR
10k
BACK_SCL
BACK_SDA
SCLIN
SCLOUT
CARD_SCL
SDAIN
INPUT
SIDE
55pF
OUTPUT
SIDE
20pF
SDAOUT
CARD_SDA
5V
1V/DIV
10k
CS
GND
READY
4301 TA01
BACKPLANE
CONNECTOR
4301 TA01b
1µs/DIV
CARD
4301fb
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LTC4301
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
VCC to GND ................................................. –0.3V to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT, CS ........ –0.3V to 7V
READY ........................................................ –0.3V to 6V
Operating Temperature Range
LTC4301C ............................................... 0°C to 70°C
LTC4301I ............................................ – 40°C to 85°C
Storage Temperature Range
MSOP ............................................... – 65°C to 150°C
DFN .................................................. – 65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
ORDER PART
NUMBER
TOP VIEW
CS 1
8
VCC
SCLOUT 2
7
SDAOUT
6
SDAIN
5
READY
9
SCLIN 3
GND 4
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 9)
PCB CONNECTION OPTIONAL
LTC4301CDD
LTC4301IDD
DD PART
MARKING*
LBBY
ORDER PART
NUMBER
TOP VIEW
CS
SCLOUT
SCLIN
GND
8
7
6
5
1
2
3
4
LTC4301CMS8
LTC4301IMS8
VCC
SDAOUT
SDAIN
READY
MS8 PART
MARKING*
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 200°C/W
LTBBW
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
4.5
300
6.2
mA
µA
Power Supply
VCC
Positive Supply Voltage
ICC
Supply Current
●
2.7
VCC = 5.5V, VSDAIN = VSCLIN = 0V
VCC = 5.5V, CS = 5.5V
●
SDA, SCL Floating
●
0.85
1.05
1.25
V
●
60
95
175
µs
0.4
V
2
V
±0.1
±1
µA
1.8
2.0
V
Start-Up Circuitry
VPRE
Precharge Voltage
tIDLE
Bus Idle Time
RDYVOL
READY Output Low Voltage
VTHRCS
Connection Sense Threshold
ICS
CS Input Current
CS from 0V to VCC
VTHR
SDA, SCL Logic Input Threshold Voltage
Rising Edge
VHYS
SDA, SCL Logic Input Threshold Voltage
Hysteresis
(Note 3)
tPLH
IPULLUP = 3mA
●
0.8
1.55
1.4
50
mV
CS Delay On-Off
READY Delay Off-On
10
10
ns
ns
tPHL
CS Delay Off-On
READY Delay On-Off
95
10
µs
ns
IOFF
Ready Off Leakage Current
±0.1
µA
4301fb
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LTC4301
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0
100
175
mV
Input-Output Connection
●
VOS
Input-Output Offset Voltage
10k to VCC on SDA, SCL, VCC = 3.3V,
SDA or SCL = 0.2V (Note 2)
CIN
Digital Input Capacitance SDAIN, SDAOUT,
SCLIN, SCLOUT
(Note 3)
10
pF
ILEAK
Input Leakage Current
SDA, SCL Pins
±5
µA
VOL
Output Low Voltage, Input = 0V
SDA, SCL Pins, ISINK = 3mA, VCC = 2.7V
0.4
V
●
0
Timing Characteristics
fI2C,MAX
I2C Maximum Operating Frequency
(Note 3)
tBUF
Bus Free Time Between Stop and Start
Condition
(Note 3)
1.3
µs
tHD,STA
Hold Time After (Repeated) Start Condition
(Note 3)
100
ns
tSU,STA
Repeated Start Condition Set-Up Time
(Note 3)
0
ns
tSU,STO
Stop Condition Set-Up Time
(Note 3)
0
ns
tHD,DATI
Data Hold Time Input
(Note 3)
0
ns
tSU,DAT
Data Set-Up Time
(Note 3)
100
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
400
600
kHz
Note 2: The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and VCC voltage is shown in the Typical Performance
Characteristics section.
Note 3: Determined by design, not tested in production.
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TYPICAL PERFOR A CE CHARACTERISTICS
Input – Output High to Low
Propagation Delay vs Temperature
ICC vs Temperature
4.9
300
100
4.7
250
80
VCC = 3.3V
4.5
4.3
4.2
TIME (ns)
ICC (mA)
4.6
4.4
VCC = 3.3V
VCC = 2.7V
4.1
60
40
20
4.0
3.9
–80 –60 –40 –20 0 20 40 60
TEMPERATURE (°C)
TA = 25°C
VIN = 0V
VCC = 2.7V
VCC = 5.5V
80 100
4301 G01
VOUT – VIN (mV)
4.8
Connection Circuitry VOUT – VIN
0
–50
VCC = 5.5V
200
150
VCC = 5V
100
VCC = 3.3V
50
CIN = COUT = 100pF
RPULLUPIN = RPULLUPOUT = 10k
–25
0
25
50
TEMPERATURE (°C)
75
100
4301 G02
0
0
10,000
20,000
30,000
RPULLUP (Ω)
40,000
4301 G03
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LTC4301
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CS (Pin 1): The connection sense pin is a 1.4V threshold
digital input pin. For normal operation CS is grounded.
Driving CS above the 1.4V threshold isolates SDAIN from
SDAOUT and SCLIN from SCLOUT and asserts READY
low.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL
on the bus backplane.
GND (Pin 4): Ground. Connect this pin to a ground plane
for best results.
when the start-up sequence described in the Operation
section has not been completed. READY goes high when
CS is low and a start-up is complete.
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the SDA bus on the card.
VCC (Pin 8): Main Input Supply. Place a bypass capacitor
of at least 0.01µF close to VCC for best results.
Exposed Pad (Pin 9): Exposed pad may be left open or
connected to device ground.
READY (Pin 5): The READY pin is an open drain N-channel
MOSFET output which pulls down when CS is high or
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BLOCK DIAGRA
LTC4301 Supply Independent 2-Wire Bus Buffer
PRECHARGE
R1
200k
6
PRECHARGE
R2
CONNECT
200k
VCC 8
CONNECT PRECHARGE
CONNECT
R3
200k
SDAIN
R4
200k
SDAOUT
7
CONNECT
3
SCLOUT
SCLIN
LOGIC
2
PRECHARGE
CONNECT
1.8V
1.8V
1
CONNECT
CS
1.4V
UVLO
READY
5
95µs
DELAY
CONNECT
GND
4
4301 BD
4301fb
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LTC4301
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OPERATIO
Start-Up
When the LTC4301 first receives power on its VCC pin,
either during power-up or live insertion, it starts in an
undervoltage lockout (UVLO) state, ignoring any activity
on the SDA or SCL pins until VCC rises above 2.5V (typical).
This is to ensure that the part does not try to function until
it has enough voltage to do so.
During this time, the 1V precharge circuitry is active and
forces 1V through 200k nominal resistors to the SDA and
SCL pins. Because the I/O card is being plugged into a live
backplane, the voltage on the backplane SDA and SCL
busses may be anywhere between 0V and VCC. Precharging
the SCL and SDA pins to 1V minimizes the worst-case
voltage differential these pins will see at the moment of
connection, therefore minimizing the amount of disturbance caused by the I/O card.
Once the LTC4301 comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the backplane side to indicate
the completion of a data transaction. When either one
occurs, the part also verifies that both the SDAOUT and
SCLOUT voltages are high. When all of these conditions
are met, the input-to-output connection circuitry is activated, joining the SDA and SCL busses on the I/O card with
those on the backplane.
Connection Circuitry
Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low
forced on either pin at any time results in both pin voltages
being low. For proper operation, logic low input voltages
should be no higher than 0.4V with respect to the ground
pin voltage of the LTC4301. SDAIN and SDAOUT enter a
logic high state only when all devices on both SDAIN and
SDAOUT release high. The same is true for SCLIN and
SCLOUT. This important feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the devices
in the system are tied to the LTC4301.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms as
described here.
Input-to-Output Offset Voltage
When a logic low voltage, VLOW1, is driven on any of the
LTC4301’s data or clock pins, the LTC4301 regulates the
voltage on the other side of the device (call it VLOW2) at a
slightly higher voltage, as directed by the following
equation:
VLOW2 = VLOW1 + 75mV + (VCC/R) • 70Ω (typical)
where R is the bus pull-up resistance in ohms. For example, if a device is forcing SDAOUT to 10mV where VCC
= 3.3V and the pull-up resistor R on SDAIN is 10k, then the
voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 =
108mV (typical). See the Typical Performance Characteristics section for curves showing the offset voltage as a
function of VCC and R.
Propagation Delays
During a rising edge, the rise time on each side is determined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between
the two sides. This effect is displayed in Figure 1 for
VCC = 5V and a 10k pull-up resistor on each side (55pF on
one side and 20pF on the other). SDAIN and SCLIN are
pulled-up to 3.3V, and SDAOUT and SCLOUT are pulledup to 5V. Since the output side has less capacitance than
the input, it rises faster and the effective low to high
propagation delay is negative.
INPUT
SIDE
55pF
OUTPUT
SIDE
20pF
1V/DIV
1µs/DIV
4301 F01
Figure 1. Input-Output Connection
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LTC4301
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OPERATIO
There is a finite high to low propagation delay through the
connection circuitry for falling waveforms. Figure 2 shows
the falling edge waveforms for the same pull-up resistors
and equivalent capacitance conditions as used in Figure 1.
An external N-channel MOSFET device pulls down the
voltage on the side with 55pF capacitance; LTC4301 pulls
down the voltage on the opposite side with a delay of 60ns.
This delay is always positive and is a function of supply
voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. The Typical
Performance Characteristics section shows high to low
propagation delay as a function of temperature and voltage for 10k pull-up resistors pulled-up to VCC and 100pF
equivalent capacitance on both sides of the part. Larger
output capacitances translate to longer delays (up to
150ns). Users must quantify the difference in propagation
times for a rising edge versus a falling edge in their
systems and adjust setup and hold times accordingly.
Ready Digital Output
This pin provides a digital flag which is low when either CS
is high or the start-up sequence described earlier in this
section has not been completed. READY goes high when
CS is low and start-up is complete. The pin is driven by an
open-drain pull-down capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor of 10k to VCC to
provide the pull-up.
Connection Sense
When the CS pin is driven above 1.4V with respect to the
LTC4301’s ground, the backplane side is disconnected
from the card side and the READY pin is internally pulled
low. When the pin voltage is low, the part waits for data
transactions on both the backplane and card sides to be
complete (as described in the Start-Up section) before
reconnecting the two sides. At this time the internal
pulldown on READY releases.
OUTPUT
SIDE
20pF
INPUT
SIDE
55pF
1V/DIV
20ns/DIV
4301 F02
Figure 2. Input-Output Connection
High to Low Propagation Delay
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LTC4301
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APPLICATIO S I FOR ATIO
Live Insertion and Capacitance Buffering Application
Figures 3 illustrates applications of the LTC4301 with
different bus pull-up and VCC voltages, demonstrating its
ability to recognize and buffer bus data levels that are
above or below its VCC supply. All of these applications
take advantage of the LTC4301’s Hot SwapTM controlling,
capacitance buffering and precharge features. If the I/O
cards were plugged directly into the backplane without the
LTC4301 buffer, all of the backplane and card capacitances would add directly together, making rise- and falltime requirements difficult to meet. Placing an LTC4301
on the edge of each card, however, isolates the card
capacitance from the backplane. For a given I/O card, the
LTC4301 drives the capacitance of everything on the card
and the backplane must drive only the capacitance of the
LTC4301, which is less than 10pF.
In most applications the LTC4301 will be used with a
staggered connector where VCC and GND will be long pins.
SDA and SCL are medium length pins to ensure that the
VCC and GND pins make contact first. This will allow the
precharge circuitry to be activated on SDA and SCL before
Hot Swap is a trademark of Linear Technology Corporation.
STAGGERED CONNECTOR
5V
3.3V
10k
10k
SDA
SCL
0.01µF
10k
10k
CS
SDAIN
SCLIN
BACKPLANE
CONNECTOR
10k
VCC
SDAOUT
CARD_SDA
LTC4301
SCLOUT
CARD_SCL
GND
READY
CARD
STAGGERED CONNECTOR
3.3V
5V
10k
10k
SDA
SCL
0.01µF
10k
10k
CS
SDAIN
SCLIN
BACKPLANE
CONNECTOR
10k
VCC
SDAOUT
CARD_SDA
LTC4301
SCLOUT
CARD_SCL
GND
READY
CARD
2.5V
STAGGERED CONNECTOR
3.3V
5V
10k
10k
SDA
SCL
0.01µF
10k
10k
CS
SDAIN
SCLIN
10k
VCC
SDAOUT
CARD_SDA
LTC4301
SCLOUT
CARD_SCL
GND
READY
4301 F03
BACKPLANE
CONNECTOR
CARD
Figure 3. Typical Supply Independent Applications
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LTC4301
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APPLICATIO S I FOR ATIO
they make contact. CS is a short pin that is pulled up when
not connected. This is to ensure that the connection
between the backplane and the cards data and clock
busses is not enabled until the transients associated with
live insertion have settled.
Figure 4 shows the LTC4301 in a CompactPCITM configuration. The LTC4301 receives its VCC voltage from one of
the long “early power” pins. Because this power is not
switched, add a 5Ω to 10Ω resistor between VCC of the
LTC4301 and the connector VCC pin. Establishing early
BACKPLANE
BACKPLANE
CONNECTOR
power VCC ensures that the 1V precharge voltage is
present at SDAIN and SCLIN before they make contact.
The CS pin is driven by the CompactPCI’s BD_SEL# pin
using a short pin. This is to ensure that a connection is not
enabled until the transients associated with live insertion
have settled.
Figure 5 shows the LTC4301 in a PCI application where all
of the pins have the same length. In this case, an RC filter
circuit on the I/O card with a product of 10ms provides a
CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.
I/O PERIPHERAL CARD 1
5.1Ω
VCC
R1
10k
BD_SEL
SDA
SCL
R2
10k
0.01µF
STAGGERED CONNECTOR
VCC2
R3
10k
CS
SDAIN
SCLIN
R5
10k
R6
10k
VCC
SDAOUT
CARD_SDA
LTC4301
SCLOUT
CARD_SCL
GND
READY
I/O PERIPHERAL CARD 2
5.1Ω
0.01µF
STAGGERED CONNECTOR
R4
10k
R7
10k
CS
SDAIN
SCLIN
R8
10k
R9
10k
R10
10k
VCC
SDAOUT
CARD2_SDA
LTC4301
SCLOUT
CARD2_SCL
GND
READY
• • •
I/O PERIPHERAL CARD N
STAGGERED CONNECTOR
5.1Ω
0.01µF
R11
10k
CS
SDAIN
SCLIN
R12
10k
R13
10k
R14
10k
VCC
SDAOUT
CARDN_SDA
LTC4301
SCLOUT
CARDN_SCL
GND
READY
4301 F03
Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4301 in a CompactPCI System
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LTC4301
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APPLICATIO S I FOR ATIO
BACKPLANE
BACKPLANE
CONNECTOR
I/O PERIPHERAL CARD 1
VCC
0.01µF
0.1µF
VCC2
R1
10k
R2
10k
R3
100k
CS
SDA
SDAIN
SCL
SCLIN
R4
10k
R5
10k
R6
10k
VCC
SDAOUT
CARD_SDA
LTC4301
SCLOUT
CARD_SCL
GND
READY
I/O PERIPHERAL CARD 2
0.01µF
0.1µF
R7
100k
CS
SDAIN
SCLIN
R8
10k
R9
10k
R10
10k
VCC
SDAOUT
CARD2_SDA
LTC4301
SCLOUT
CARD2_SCL
GND
READY
•
•
•
4301 F05
Figure 5. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4301 in a PCI System
filter to prevent the LTC4301 from becoming activated
until the transients associated with live insertion have
settled. Connect the capacitor between VCC and CS, and
the resistor from CS to GND.
Repeater/Bus Extender Application
Users who wish to connect two 2-wire systems separated
by a distance can do so by connecting two LTC4301s
back-to-back as shown in Figure 6. The I2C specification
allows for 400pF maximum bus capacitance, severely
limiting the length of the bus. The SMBus specification
places no restriction on bus capacitance, but the limited
impedances of devices connected to the bus require
systems to remain small if rise- and fall-time specifications are to be met. Using the LTC4301 allows the capacitance to be isolated into smaller sections, enabling the
system to meet rise- and fall-time requirements. In this
situation, the differential ground voltage between the two
systems may limit the allowed distance, because valid
logic low voltage with respect to the ground at one end of
the system may violate the allowed VOL specification with
respect to the ground at the other end. In addition, the
connection circuitry offset voltages of the back-to-back
LTC4301s add together, directly contributing to the same
problem.
Systems with Supply Voltage Droop
In large 2-wire systems, the VCC voltages seen by devices
at various points in the system can differ by a few hundred
millivolts or more. This situation is well modelled by a series
resistor in the VCC line as shown in Figure 7. For proper
operation, make sure that the VCC(LTC4301) is ≥ 2.7V.
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LTC4301
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APPLICATIO S I FOR ATIO
VCC3
VCC1
VCC4
VCC2
VCC5
0.01µF
R1
10k
R4
10k
0.01µF
R5
10k
LTC4301
R3
R2
5.1k 5.1k
R6
10k
R7
10k
LTC4301
VCC
R8
10k
VCC
CS
SDAOUT
SDAOUT
CS
SDA1
SDAIN
SCLOUT
SCLOUT
SDAIN
SDA2
SCL1
TO OTHER
SYSTEM 1
DEVICES
SCLIN
READY
READY
SCLIN
SCL2
TO OTHER
SYSTEM 2
DEVICES
GND
GND
LONG
DISTANCE
BUS
4301 F07
Figure 6. Repeater/Bus Extender Application
VCC
RDROP
VCC (BUS)
R1
10k
0.01µF
R2
10k
CS
SDA
SDAIN
SCL
SCLIN
R3
10k
R4
10k
R5
10k
VCC
SDAOUT
SDA2
LTC4301
SCLOUT
SCL2
GND
READY
4301 F06
Figure 7. System with VCC Voltage Droop
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LTC4301
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PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
TYP
5
0.38 ± 0.10
8
0.675 ±0.05
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 1203
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
PACKAGE
OUTLINE
4
0.25 ± 0.05
0.75 ±0.05
0.200 REF
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
0.254
(.010)
8
7 6 5
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.52
(.0205)
REF
0° – 6° TYP
GAUGE PLANE
5.23
(.206)
MIN
0.53 ± 0.152
(.021 ± .006)
3.20 – 3.45
(.126 – .136)
DETAIL “A”
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2 3
4
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.127 ± 0.076
(.005 ± .003)
MSOP (MS8) 0204
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
4301fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC4301
U
TYPICAL APPLICATIO
3.3V
5V
0.01µF
10k
10k
VCC
10k
LTC4301
STAGGERED CONNECTOR
10k
BACK_SCL
BACK_SDA
SCLIN
SCLOUT
CARD_SCL
SDAIN
SDAOUT
CARD_SDA
5V
10k
FROM
MICROPROCESSOR
CS
GND
READY
4301 TA01
BACKPLANE
CONNECTOR
CARD
Figure 8. System with Active Connection Control
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1380/LTC1393
Single-Ended 8-Channel/Differential 4-Channel Analog
Mux with SMBus Interface
Low RON: 35Ω Single-Ended/70Ω Differential,
Expandable to 32 Single or 16 Differential Channels
LTC1427-50
Micropower, 10-Bit Current Output DAC
with SMBus Interface
Precision 50µA ± 2.5% Tolerance Over Temperature,
4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale
LTC1623
Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16-Channel Capability
LTC1663
SMBus Interface 10-Bit Rail-to-Rail Micropower DAC
DNL < 0.75LSB Max, 5-Lead SOT-23 Package
LTC1694/LTC1694-1
SMBus Accelerator
Improved SMBus/I2C Rise-Time,
Ensures Data Integrity with Multiple SMBus/I2C Devices
LT1786F
SMBus Controlled CCFL Switching Regulator
1.25A, 200kHz, Floating or Grounded Lamp Configurations
LTC1695
SMBus/I2C Fan Speed Controller in ThinSOTTM
0.75Ω PMOS 180mA Regulator, 6-Bit DAC
LTC1840
Dual I2C Fan Speed Controller
Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0
LTC4300A-1/LTC4300A-2
Hot Swappable 2-Wire Bus Buffer
Isolates Backplane and Card Capacitances
LTC4301L
Hot Swappable 2-Wire Bus Buffer
with Low Voltage Level Translation
Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN
LTC4302-1/LTC4302-2
Addressable 2-Wire Bus Buffer
Address Expansion, GPIO, Software Controlled
ThinSOT is a trademark of Linear Technology Corporation.
4301fb
12
Linear Technology Corporation
LT 0806 REV B • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
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