LTC4304
Hot Swappable 2-Wire
Bus Buffer with Stuck
Bus Recovery
DESCRIPTIO
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FEATURES
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■
■
■
■
■
■
■
■
■
Automatic Disconnect of SDA/SCL Lines when Bus
is Stuck Low for ≥30ms
Fault Flag for Stuck Bus
Recovers Stuck Busses with Automatic Clocking*
Bidirectional Buffer* for SDA and SCL Lines
Increases Fanout
Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
Allows Bus Pullup Voltages Above and Below VCC
±15kV Human Body Model ESD Protection
Isolates Input SDA and SCL Lines from Output
Compatible with I2 CTM, I2 C Fast-Mode and SMBus
Standards (Up to 400kHz Operation)
READY Open Drain Output
1V Precharge on All SDA and SCL Lines
High Impedance SDA, SCL Pins for VCC = 0V
ENABLE Gates Connection from Input to Output
MSOP 10-Pin and DFN (3mm × 3mm) Packages
The LTC®4304 hot swappable 2-wire bus buffer allows I/O
card insertion into a live backplane without corruption of
the data and clock busses. When a connection is made,
the LTC4304 provides bidirectional buffering, keeping the
backplane and card capacitances isolated. If SDAOUT or
SCLOUT is low for ≥30ms (typ), the LTC4304 automatically
breaks the data and clock bus connection and FAULT will
pull low. At this time the LTC4304 automatically generates
up to 16 clock pulses on SCLOUT in an attempt to free the
bus. A connection will be enabled automatically when the
bus becomes free. A logic low on the ACC input enables
the LTC4304’s rise-time accelerators. A logic high on ACC
disables the rise-time accelerators, which allows SDA and
SCL bus pull-up voltages below VCC.
During insertion, the SDA and SCL lines are precharged
to 1V to minimize bus disturbances. When driven high,
ENABLE allows the LTC4304 to connect after a stop bit or
bus idle occurs. Driving ENABLE low breaks the connection
between SDAIN and SDAOUT, SCLIN and SCLOUT. READY
is an open drain output that indicates when the backplane
and card sides are connected together.
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APPLICATIO S
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Hot Board Insertion
Servers
Capacitance Buffer/Bus Extender
RAID Systems
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6356140, 6650174, 7032051.
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TYPICAL APPLICATIO
5V 3.3V
Stuck Bus Resolved with
Automatic Clocking
0.01µF
10k
10k
10k
VCC
10k
LTC4304
SCLIN
SDAOUT
5V/DIV
SCLOUT
BACK_SCL
STUCK LOW > 30ms
RECOVERS
CARD_SCL
SDAIN
5V/DIV
DISCONNECT AT TIMEOUT
AUTOMATIC CLOCKING
SDAIN
SDAOUT
BACK_SDA
CARD_SDA
READY
FAULT
3.3V
ENABLE
SCLOUT
5V/DIV
GND
100k
ACC
FAULT
5V/DIV
4304 TA01
200ms/DIV
BACKPLANE
CONNECTOR
STAGGERED
CONNECTOR
4304 TA01b
CARD
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LTC4304
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ABSOLUTE
AXI U RATI GS (Notes 1, 2)
VCC to GND .................................................. –0.3V to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE,
FAULT, ACC .................................................. –0.3V to 7V
Operating Temperature
LTC4304C ................................................ 0°C to 70°C
LTC4304I .............................................–40°C to 85°C
SDAIN, SCLIN, SDAOUT, SCLOUT,
FAULT READY (Note 3) .........................................30mA
Storage Temperature Range
MSOP ................................................–65°C to 150°C
DFN....................................................–65°C to 125°C
Lead Temperature (Soldering, 10sec)
MSOP ............................................................... 300°C
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W
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
ENABLE
1
10 VCC
SCLOUT
2
9 SDAOUT
SCLIN
3
ACC
4
7 FAULT
GND
5
6 READY
11
TOP VIEW
ENABLE
SCLOUT
SCLIN
ACC
GND
8 SDAIN
VCC
SDAOUT
SDAIN
FAULT
READY
MS10 PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA =200°C/W
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11)
PCB GND CONNECTION OPTIONAL
ORDER PART NUMBER
10
9
8
7
6
1
2
3
4
5
DD PART MARKING*
ORDER PART NUMBER
MS PART MARKING*
LBBD
LBBD
LTC4304CMS
LTC4304IMS
LTBBC
LTBBC
LTC4304CDD
LTC4304IDD
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL
Power Supply
VCC
ICC
Startup Circuitry
VPRE
TIDLE
VOL_READY
VTHR_ENABLE
IENABLE
VTHR
PARAMETER
Positive Supply Voltage
Supply Current
Supply Current, ENABLE = GND
Precharge Voltage
Bus Idle Time
READY Output Low Voltage
CONDITIONS
MIN
●
VCC = 5.5V, VSDAIN = VSDAOUT = 0V (Note 7)
VCC = 5.5V
●
SDA, SCL Floating, VCC = 5.5V
●
●
IPULLUP = 3mA
IPULLUP = 6mA, VCC = 4.7V
ENABLE Threshold
ENABLE Input Current
ENABLE from 0 to VCC
SDA, SCL Logic Input Threshold Voltage Rising Edge
TYP
2.7
6
1.5
5.5
8
V
mA
mA
1
95
1.2
175
0.4
0.4
V
µs
V
V
0.8
1.4
0.1
1.8
2
±1.5
2
V
µA
V
●
●
UNITS
0.8
60
●
●
●
MAX
1.6
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LTC4304
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VHYS
SDA, SCL, Logic Input Threshold Voltage (Note 6)
Hysteresis
50
mV
tPLH
ENABLE Delay On-Off
READY Delay Off-On
VCC = 3.3V
(Note 6)
300
10
ns
ns
tPHL
ENABLE Delay Off-On
READY Delay On-Off
VCC = 3.3V
(Note 6)
●
tPDOFF
ACC Delay, On/Off
VIH
Input High Voltage
Input Low Voltage
VIL
IIN
ACC Input Current
Bus Stuck Low Timeout
tTIMEOUT
Bus Stuck Low Timer
VOLFAULT
FAULT Output Low Voltage
IOFF_FAULT
Input-Output Connection
VOS
Input-Output Offset Voltage
CIN
Digital Input Capacitance
SDAIN, SDAOUT, SCLIN, SCLOUT
Positive Transition on SDA, SCL, VCC = 2.7V,
Slew Rate = 0.8V/µs (Note 5)
(Note 6)
Measured on ACC
Measured on ACC
ACC Shorted to GND or VCC (Note 8)
tSU, STO
tHD, DATI
tSU, DAT
Stop Condition Set-Up Time
Data Hold Time Input
Data Set-Up Time
2
3.5
MAX
175
µs
ns
±10
µA
5.5
mA
0.1VCC
100
ns
V
V
µA
5
●
0.9VCC
●
UNITS
●
–100
SDAOUT, SCLOUT = 0V
IPULLUP = 3mA
VCC = 5.5V
●
25
30
35
0.4
±10
ms
V
µA
10k to VCC on SDA, SCL,
2.7k to VCC on SDA, SCL
VCC = 3.3V, VSDA/SCL = 0.2V (Note 4)
(Note 6)
●
●
40
50
80
100
120
150
mV
mV
10
pF
0.4
±5
0.3
V
µA
V
1.3
kHz
µs
(Note 6)
100
ns
(Note 6)
(Note 6)
(Note 6)
(Note 6)
0
0
0
100
ns
ns
ns
ns
●
●
●
VIL, MAX
Input Logic Low Voltage
ILEAK
Input Leakage Current
VOL
Output Low Voltage, Input = 0V
Timing Characteristics
fI2C, MAX
I2C Maximum Operating Frequency
tBUF
Bus Free Time Between Stop and Start
Condition
tHD, STA
Hold Time After (Repeated)
Start Condition
tSU, STA
Repeated Start Condition Set-Up Time
95
10
●
IOFF_READY
Ready Off Leakage Current
Rise-Time Accelerators
IPULLUPAC
Transient Boosted Pull-Up Current
60
TYP
SDA, SCL, VCC = 5.5V
SDA, SCL Pins, ISINK = 4mA, VCC = 2.7V
(Note 6)
(Note 6)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
Note 3: Pulsed less than 5µs.
Note 4: The connection circuitry always regulates the output to a higher
●
●
0
0.19
400
600
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and VCC voltage is shown in the Typical Performance
Characteristics section.
Note 5: IPULLUPAC varies with temperature and VCC voltage, as shown in
the Typical Performance Characteristics section.
Note 6: Determined by design, not tested in production.
Note 7: ICC test performed with connection circuitry active.
Note 8: When floating, the ACC pin can tolerate ±5µA of leakage.
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LTC4304
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TYPICAL PERFOR A CE CHARACTERISTICS
ICC vs Temperature
Input-Output tPHL vs Temperature
140
6.2
VCC = 5.5V
6.0
TA = 25°C unless otherwise indicated.
120
IPULLUPAC vs Temperature
14
CIN = COUT = 100pF
RPULLUPIN = RPULLUPOUT = 10k
100
10
5.4
80
60
8
VCC = 3.3V
6
40
4
20
2
VCC = 2.7V
5.2
5.0
–50
IPULLUPAC (mA)
tPHL (ns)
ICC (mA)
5.8
5.6
VCC = 5.5V
12
–25
VCC = 2.7V
0
25
50
TEMPERATURE (°C)
75
100
0
–50
–25
0
25
50
TEMPERATURE (°C)
75
0
–50
100
–25
0
25
50
TEMPERATURE (°C)
4303 G02
4303 G01
Connection Circuitry VOUT - VIN
75
100
4303 G03
Input-Output tPHL vs COUT
180
250
CIN = 50pF
160 RPULLUPIN = RPULLUPOUT = 10k
200
140
150
100
tPHL (ns)
VOUT-VIN (mV)
VCC = 5.5V
120
100
80
VCC = 2.7V
60
50
40
0
1000
20
3000
7000
5000
RPULLUP (Ω)
9000
4303 G04
0
500
1000
COUT (pF)
1500
2000
4303 G05
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LTC4304
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PI FU CTIO S
ENABLE (Pin 1): Connection Enable. This is a digital
threshold input pin. For normal operation ENABLE is high.
Driving ENABLE below 0.8V isolates SDAIN from SDAOUT,
SCLIN from SCLOUT, asserts READY low and disables
automatic clocking. A rising edge on ENABLE after a fault
has occurred unconditionally forces a connection between
SDAIN, SDAOUT and SCLIN, SCLOUT.
READY (Pin 6): Connection Status Flag. READY provides
a digital flag which indicates the status of the connection
circuitry described in the “Connection Circuitry” section.
Connect a resistor of 10k to VCC to provide the pull-up.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
FAULT (Pin 7): Bus Stuck Low Fault. FAULT is an open
drain N-channel MOSFET which pulls low to signal a bus
stuck low condition. In normal operation, FAULT is high.
Connect a 10k resistor from this pin to VCC to provide
the pull-up.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL
on the bus backplane.
SDAIN (Pin 8): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
ACC (Pin 4): Rise-Time Accelerator Control. Connect ACC
to VCC to disable all four accelerators. Connect ACC to
GND to enable all four accelerators. Float ACC to enable
the SDAOUT and SCLOUT accelerators only. For applications when VCC is greater than the bus pull-up voltage,
connect ACC to VCC.
SDAOUT (Pin 9): Serial Data Output. Connect this pin to
the SDA bus on the card.
GND (Pin 5): Device Ground. Connect this pin to a ground
plane for best results.
VCC (Pin 10): Supply Voltage Input. Place a bypass capacitor of at least 0.01µF close to VCC for best results.
Exposed Pad (Pin 11, DFN Only): Exposed pad may be
left open or connected to the ground plane.
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LTC4304
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BLOCK DIAGRA
LTC4304 2-Wire Bus Buffer with Stuck Bus Protection
3.5mA
SLEW RATE
DETECTOR
ACC_IN
10 VCC
3.5mA
SLEW RATE
DETECTOR
CONNECT
ACC_OUT
SDAIN
SDAOUT
8
200k
PC_CONNECT
9
200k
PC_CONNECT
PRECHARGE
3.5mA
3.5mA
SLEW RATE
DETECTOR
200k
3
CONNECT
SLEW RATE
DETECTOR
200k
SCLOUT
SCLIN
ACC_IN
2
ACC_IN
4
ACC
CTRL
ACC
ACC_OUT
+
+
AUTOMATIC
CLOCKING
–
–
UVLO
+
LOGIC
PC_CONNECT
–
+
CONNECT
1
ENABLE
7
30ms
TIMER
–
1.8V
FAULT
1.8V
READY
6
+
1.4V
–
UVLO
95µs
DELAY
CONNECT
GND
5
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LTC4304
OPERATION
Start-Up
When the LTC4304 first receives power on its VCC pin,
either during power up or live insertion, it starts in an under
voltage lockout (UVLO) state, ignoring any activity on the
SDA or SCL pins until VCC rises above 2.5V (typical).
During this time, the precharge circuitry is active and
forces 1V through 200K nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged
into a live backplane, the voltage on the backplane SDA
and SCL busses may be anywhere between 0V and VCC.
Precharging the SCL and SDA pins to 1V minimizes the
worst-case voltage differential these pins will see at the
moment of connection, therefore minimizing the amount
of disturbance caused by the I/O card.
Once the LTC4304 comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the input side to indicate the
completion of a data transaction. When either one occurs,
the part also verifies that both the SDAOUT and SCLOUT
voltages are high. When all of these conditions are met,
the input-to-output connection circuitry is activated, joining the SDA and SCL busses on the I/O card with those
on the backplane and READY goes high.
Connection Circuitry
Once the connection circuitry is activated, the functionality
of the SDAIN and SDAOUT pins is identical. A low forced
on either pin at any time results in both pin voltages being low. For proper operation, logic low input voltages
should be no higher than 0.4V with respect to the ground
pin voltage of the LTC4304. SDAIN and SDAOUT enter
a logic high state only when all devices on both SDAIN
and SDAOUT release high. The same is true for SCLIN
and SCLOUT. This important feature ensures that clock
stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the
devices in the system are tied to the LTC4304.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms, as
described here.
Input to Output Offset Voltage
When a logic low voltage, VLOW1, is driven on any of the
LTC4304’s data or clock pins, the LTC4304 regulates the
voltage on the opposite side of the part (call it VLOW2)
to a slightly higher voltage, as directed by the following
equation:
VLOW2 = VLOW1 + 75mV + (VCC/R) • 20Ω (typical)
where R is the bus pull-up resistance in ohms. For example, if a device is forcing SDAOUT to 10mV where VCC
= 3.3V and the pull-up resistor R on SDAIN is 10k, then
the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 20
= 91.6mV(typical). See the Typical Performance Characteristics section for curves showing the offset voltage as
a function of VCC and R.
Bus Stuck Low Timeout
When SDAOUT or SCLOUT is low, an internal timer starts.
The timer is only reset when SDAOUT and SCLOUT are
both high. If they do not go high within 30ms (typical),
FAULT pulls low indicating a bus stuck condition and the
connection between SDAIN and SDAOUT, and SCLIN
and SCLOUT is broken. After a delay of at least 40µs, the
LTC4304 automatically generates up to 16 clock pulses at
8.5kHz (typical) on SCLOUT in an attempt to unstick the
bus. When SDAOUT and SCLOUT go high, FAULT is cleared
and reconnection occurs when the conditions described
in the “Start-Up” section above are satisfied.
When powering up into a bus stuck low condition, the
connection circuitry joining the SDA and SCL busses on
the I/O card with those on the backplane is not activated.
30ms after UVLO, FAULT pulls low indicating a bus stuck
low condition, and automatic clocking takes place as
described above.
Propagation Delays
During a rising edge, the rise-time on each side is determined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
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LTC4304
OPERATION
OUTPUT SIDE
50pF
0.5V/DIV
INPUT SIDE
150pF
0.5V/DIV
200ns/DIV
INPUT SIDE
50pF
0.5V/DIV
OUTPUT SIDE
150pF
0.5V/DIV
4303 F01
20ns/DIV
Figure 1. Input-Output Connection tPLH
same, a difference in rise-time occurs which is directly
proportional to the difference in capacitance between the
two sides. This effect is displayed in Figure 1 for a VCC
= 3.3V and a 10k pull-up resistor on each side (50pF on
one side and 150pF on the other). Since the output side
has less capacitance than the input, it rises faster and the
effective tPLH is negative.
There is a propagation delay, tPHL, through the connection circuitry for falling waveforms. Figure 2 shows the
falling edge waveforms. An external driver pulls down
the voltage on the side with 50pF capacitance; LTC4304
pulls down the voltage on the opposite side with a delay
of 80ns. This delay is always positive and is a function of
supply voltage, temperature and the pull-up resistors and
equivalent bus capacitances on both sides of the bus. The
Typical Performance Characteristics section shows tPHL
as a function of temperature and voltage for 10k pull-up
resistors and 100pF equivalent capacitance on both sides
of the part. Larger output capacitances translate to longer
delays. Users must quantify the difference in propagation
times for a rising edge versus a falling edge in their systems
and adjust setup and hold times accordingly.
4303 F02
Figure 2. Input-Output Connection tPHL
READY Digital Output
The READY pin provides a digital flag which indicates the
status of the connection circuitry described previously in
the “Connection Circuitry” section. READY is high when
the connection circuitry is active, and pulls low when
there is not a valid connection. The pin is driven by an
open drain pull-down capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor of 10k to VCC to
provide the pull-up.
FAULT Digital Output
The FAULT pin provides a digital flag which is low when
SDAOUT and SCLOUT have not both been high within 30ms
(typical). The pin is driven by an open drain pull-down
capable of sinking 3mA while holding 0.4V on the pin.
Connect a resistor of 10k to VCC to provide the pull-up.
ENABLE
When the ENABLE pin is driven below 0.8V with respect
to the LTC4304’s ground, the backplane side is disconnected from the card side, and the READY pin is internally
pulled low. When the pin is driven above 2V, the part
waits for data transactions on both the backplane and
card sides to be complete (as described in the Start-Up
section) before connecting the two sides. At this time the
internal pulldown on READY releases. When ENABLE is
low, automatic clocking is disabled.
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LTC4304
OPERATION
A rising edge on ENABLE after a stuck bus condition has
occurred forces a connection between SDAIN, SDAOUT
and SCLIN, SCLOUT even if bus idle conditions are not
met. At this time the internal 30ms timer is reset but not
disabled.
Rise Time Accelerators
Once connection has been established, rise time accelerator circuits on all four SDA and SCL pins are activated
(assuming accelerators are enabled, see ACC pin description). These allow the use of a large pull-up resistor to
reduce power consumption, or bus capacitance beyond
that specified in I2C, while still meeting system rise time
requirements. During positive bus transitions, the LTC4304
switches in 3.5mA (typical) of current to quickly slew the
SDA and SCL lines once their DC voltages exceed 0.8V.
Choose a pull-up resistor so that the bus will rise on its
own at a rate of at least 0.8V/µs to guarantee activation
of the accelerators. Rise time accelerators turn off when
SDA and SCL lines are approximately 1V below VCC.
Rise time accelerators are automatically disabled during
automatic clocking.
APPLICATIONS INFORMATION
Resistor Pull-Up Selection
The system pull-up resistors must be strong enough
to provide a positive slew rate of 0.8V/µs on the SDA
and SCL pins, in order to activate the rise time accelerators during rising edges. Choose maximum resistor value
RPULL-UP(MAX) using the formula:
RPULLUP(MAX)[kΩ] =
(VBUS(MIN) – 0.8V) • 1250[ns/V]
CBUS [pF]
where VBUSMIN is the minimum operating pull-up supply voltage, and CBUS the total capacitance on respective bus line.
For example, assume VBUS = VCC = 3.3V, and assuming
±10% supply tolerance, VBUSMIN = 2.97V. With CBUS =
100pF, RPULL-UP, MAX = 27.1k. Therefore a smaller pull-up
resistor than 27.1k must be used, so 10k works fine.
Live Insertion and Capacitance Buffering Application
Figures 3 through 6 illustrate applications of the LTC4304
that take advantage of both its Hot SwapTM controlling and
capacitance buffering features. In all of these applications,
note that if the I/O cards were plugged directly into the
backplane without the LTC4304 buffer, all of the backplane
and card capacitances would add directly together, making
rise- and fall-time requirements difficult to meet. Placing a
LTC4304 on the edge of each card, however, isolates the
card capacitance from the backplane. For a given I/O card,
the LTC4304 drives the capacitance on the card side and
the backplane must drive only the digital input capacitance
of the LTC4304, which is less than 10pF.
In most applications the LTC4304 will be used with a
staggered connector where VCC and GND will be long
pins. SDA and SCL are medium length pins to ensure that
the VCC and GND pins make contact first. This will allow
the precharge circuitry to be activated on SDA and SCL
before they make contact. ENABLE is a short pin that is
pulled down when not connected. This is to ensure that the
connection between the backplane and the cards data and
clock busses is not enabled until the transients associated
with live insertion have settled.
Figure 3 shows the LTC4304 in a CompactPCITM configuration. Connect VCC and ENABLE to the output of one of the
CompactPCI power supply Hot Swap circuits. Use a pull-up
resistor to ENABLE for a card side enable/disable. VCC is
monitored by a filtered UVLO circuit. With the VCC voltage
powering up after all the other pins have established connection, the UVLO circuit ensures that the backplane and
the card data and clock busses are not connected until
the transients associated with live insertion have settled.
Owing to their small capacitance, the SDAIN and SCLIN
pins cause minimal disturbance on the backplane busses
when they make contact with the connector.
Hot Swap is a trademark of Linear Technology Corporation.
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LTC4304
APPLICATIONS INFORMATION
BACKPLANE
VCC
R1
10k
BACKPLANE
CONNECTOR
STAGGERED
CONNECTOR
POWER SUPPLY
HOT SWAP
R2
10k
I/O PERIPHERAL CARD 1
R3
10k
BD_SEL
CARD
ENABLE/DISABLE
ENABLE
SDA
SDAIN
SCL
SCLIN
VCC
LTC4304
C1
0.01µF
R4
10k
R5
10k
R6
10k
SDAOUT
CARD1_SDA
SCLOUT
CARD1_SCL
READY
GND
POWER SUPPLY
HOT SWAP
I/O PERIPHERAL CARD 2
R7
10k
CARD
ENABLE/DISABLE
ENABLE
SDAIN
SCLIN
VCC
LTC4304
C3
0.01µF
R8
10k
R9
10k
R10
10k
SDAOUT
CARD2_SDA
SCLOUT
CARD2_SCL
READY
GND
• • •
POWER SUPPLY
HOT SWAP
I/O PERIPHERAL CARD N
C5
0.01µF
R11
10k CARD
R12
10k
R13
10k
R14
10k
ENABLE/DISABLE
ENABLE
SDAIN
SCLIN
VCC
LTC4304
SDAOUT
CARDN_SDA
SCLOUT
CARDN_SCL
READY
GND
4304 F03
Figure 3. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4304 in a CompactPCI System
4304fa
10
LTC4304
APPLICATIONS INFORMATION
Figure 4 shows the LTC4304 in a PCI application where all
of the pins have the same length. In this case, a RC filter
circuit on the I/O card with a product of 10ms provides a
BACKPLANE
filter to prevent the LTC4304 from becoming activated until
the transients associated with live insertion have settled.
Connect the capacitor between ENABLE and GND, and the
resistor from VCC to ENABLE.
BACKPLANE
CONNECTOR
I/O PERIPHERAL CARD 1
VCC
R1
10k
R2
10k
C1
0.01µF
R3
100k
ENABLE
SDA
SDAIN
SCL
SCLIN
C2
0.1µF
VCC
LTC4304
GND
ACC
R4
10k
R5
10k
R6
10k
R11
10k
SDAOUT
CARD1_SDA
SCLOUT
CARD1_SCL
READY
FAULT
I/O PERIPHERAL CARD 2
C3
0.01µF
R7
100k
ENABLE
SDAIN
SCLIN
C4
0.1µF
ACC
VCC
LTC4304
GND
R8
10k
R9
10k
R10
10k
R12
10k
SDAOUT
CARD2_SDA
SCLOUT
CARD2_SCL
READY
FAULT
•
•
•
4304 F04
Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4304 in a PCI System
4304fa
11
LTC4304
APPLICATIONS INFORMATION
Supply Independent Operation
celerators cannot be used. Float ACC in applications where
the pull-up voltage on SDAIN and SCLIN is < VCC and the
pull-up voltage on SDAOUT and SCLOUT is ≥ VCC. Connect
ACC to ground in applications where VCC is ≤ SDA and
SCL pull-up voltages. Connect ACC to VCC for applications
where SDA and SCL pull-up voltages are ≤ VCC.
Figure 5 illustrates applications of the LTC4304 with different bus pull up and VCC voltages, demonstrating its ability
to recognize and buffer bus data levels that are above or
below its VCC supply voltage. In applications where VCC
voltage is greater than bus pull-up voltages, rise-time acBACKPLANE
CONNECTOR
STAGGERED
CONNECTOR
5V
C1
0.01µF
3.3V
R1
10k
R2
10k
ACC
SDA
SDAIN
SCL
SCLIN
5V
ENABLE
VCC
LTC4304
GND
R3
10k
R4
10k
SDAOUT
CARD_SDA
SCLOUT
CARD_SCL
READY
FAULT
R5
10k
BACKPLANE
CONNECTOR
STAGGERED
CONNECTOR
3.3V
C2
0.01µF
5V
R6
10k
R7
10k
ACC
SDA
SDAIN
SCL
SCLIN
3.3V
ENABLE
VCC
LTC4304
GND
R8
10k
R9
10k
SDAOUT
CARD_SDA
SCLOUT
CARD_SCL
READY
FAULT
R10
10k
BACKPLANE
CONNECTOR
STAGGERED
CONNECTOR
2.5V
3.3V
C3
0.01µF
5V
R11
10k
R12
10k
ACC
SDA
SDAIN
SCL
SCLIN
3.3V
ENABLE
R15
10k
VCC
LTC4304
GND
R13
10k
R14
10k
SDAOUT
CARD_SDA
SCLOUT
CARD_SCL
READY
FAULT
4304 F05
Figure 5. Typical Supply Independent Applications
4304fa
12
LTC4304
APPLICATIONS INFORMATION
VCC
SHELF MANAGER
R1
10k
VCC
ShMC
R2
10k
C1
0.01µF
ENABLE
R3
2.7k
ATCA BOARD
C2
0.01µF
R4
2.7k
VCC
SDAIN
SDAOUT
LTC4304
SCLOUT
SCLIN
R6
10k
VCC ENABLE
VCC
SDAOUT
LTC4304
SCLOUT
SCLIN
IPMC
SDAIN
IPM
BUS
(1 OF 2)
R5
10k
4304 F06
Figure 6. Simplified ATCA IPMB Application
4304fa
13
LTC4304
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
6
0.38 0.10
10
0.675 0.05
3.50 0.05
1.65 0.05
2.15 0.05 (2 SIDES)
3.00 0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD10) DFN 1103
5
0.200 REF
0.25 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.25 0.05
0.50 BSC
0.75 0.05
0.50
BSC
2.38 0.05
(2 SIDES)
1
0.00 – 0.05
2.38 0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4304fa
14
LTC4304
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127
(.035 .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 0.102
(.118 .004)
(NOTE 3)
0.50
0.305 0.038
(.0197)
(.0120 .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
10 9 8 7 6
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
DETAIL “A”
0.497 0.076
(.0196 .003)
REF
0 – 6 TYP
GAUGE PLANE
1 2 3 4 5
0.53 0.152
(.021 .006)
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.127 0.076
(.005 .003)
MSOP (MS) 0603
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
4304fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC4304
U
TYPICAL APPLICATIO
5V 3.3V
C1
0.01µF
R1
10k
R4
10k
VCC
R2
10k
R5
10k
LTC4304
SCLIN
SCLOUT
BACK_SCL
CARD_SCL
SDAIN
SDAOUT
BACK_SDA
CARD_SDA
READY
FAULT
FROM
MICROPROCESSOR
ENABLE
R3
10k
BACKPLANE
CONNECTOR
STAGGERED
CONNECTOR
GND
ACC
4304 F07
CARD
Figure 7. System with Active Connection Control
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Hot Swappable 2-Wire Bus Buffer
Hot Swappable 2-Wire Bus Buffer
Supply Independent Hot Swappable 2-Wire Bus Buffer
Hot Swappable 2-Wire Bus Buffer
with Low Voltage Level Translation
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ThinSOT is a trademark of Linear Technology Corporation.
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4304fa
16 Linear Technology Corporation
LT 0806 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
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