LTC4355
Positive High Voltage
Ideal Diode-OR with Input Supply
and Fuse Monitors
Description
Features
n
n
n
n
n
n
n
n
Replaces Power Schottky Diodes
Controls N-Channel MOSFETs
0.3µs Turn-Off Time Limits Peak Fault Current
Wide Operating Voltage Range: 9V to 80V
Smooth Switchover without Oscillation
No Reverse DC Current
Monitors VIN, Fuse, and MOSFET Diode
Available in 14-Lead (4mm × 3mm) DFN,
16-Lead MS and SO Packages
The LTC®4355 is a positive voltage ideal diode-OR controller that drives two external N-channel MOSFETs. Forming
the diode-OR with N-channel MOSFETs instead of Schottky
diodes reduces power consumption, heat dissipation and
PC board area.
With the LTC4355, power sources can easily be ORed
together to increase total system reliability. The LTC4355
can diode-OR two positive supplies or the return paths of
two negative supplies, such as in a –48V system.
In the forward direction the LTC4355 controls the voltage drop across the MOSFET to ensure smooth current
transfer from one path to the other without oscillation. If
a power source fails or is shorted, fast turnoff minimizes
reverse current transients.
Applications
High Availability Systems
AdvancedTCA® (ATCA) Systems
n +48V and –48V Distributed Power Systems
n Telecom Infrastructure
n
n
Power fault detection indicates if the input supplies are
not in regulation, the inline fuses are blown, or the voltages across the MOSFETs are greater than the fault
threshold.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Typical Application
+48V Diode-OR
FDB3632
7A
VIN2 = +48V
FDB3632
22k
340k
340k
IN1
GATE1 IN2
GATE2 OUT
MON1
SET
MON2
12.7k
GND
12.7k
6
TO
LOAD
LTC4355
GND
22k
22k
22k
22k
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
5
POWER DISSIPATION (W)
7A
VIN1 = +48V
Power Dissipation vs Load Current
DIODE (MBR10100)
4
3
POWER
SAVED
2
1
FET (FDB3632)
0
GREEN LEDs
PANASONIC LN1351C
4355 TA01
0
2
4
6
CURRENT (A)
8
10
4355 TA02
4355ff
For more information www.linear.com/LTC4355
1
LTC4355
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltages
IN1, IN2................................................... –1V to 100V
OUT...................................................... –0.3V to 100V
Input Voltages
MON1, MON2, SET................................... –0.3V to 7V
Output Voltages
GATE1 (Note 3).................... VIN1 – 0.2V to VIN1 + 13V
GATE2 (Note 3).................... VIN2 – 0.2V to VIN2 + 13V
PWRFLT1, PWRFLT2, VDSFLT,
FUSEFLT1, FUSEFLT2................................ –0.3V to 8V
Operating Ambient Temperature Range
LTC4355C................................................. 0°C to 70°C
LTC4355I..............................................–40°C to 85°C
LTC4355H...........................................–40°C to 125°C
Storage Temperature Range....................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS, SO Packages.............................................. 300°C
pin configuration
TOP VIEW
TOP VIEW
IN1
1
14 MON1
GATE1
2
13 PWRFLT1
OUT
3
GATE2
4
IN2
5
10 PWRFLT2
VDSFLT
6
9 MON2
GND
7
8 SET
15
12 FUSEFLT1
11 FUSEFLT2
IN1 1
TOP VIEW
1
2
3
4
5
6
7
8
IN1
GATE1
NC
OUT
NC
GATE2
IN2
VDSFLT
16
15
14
13
12
11
10
9
MON1
PWRFLT1
FUSEFLT1
FUSEFLT2
PWRFLT2
MON2
SET
GND
MS PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 120°C/W
DE14 PACKAGE
14-LEAD (4mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 15) PCB GND CONNECTION OPTIONAL
16 MON1
GATE1 2
15 PWRFLT1
NC 3
14 FUSEFLT1
OUT 4
13 FUSEFLT2
NC 5
12 PWRFLT2
GATE2 6
11 MON2
IN2 7
10 SET
NC 8
9
GND
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 80°C/W
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4355CDE#PBF
LTC4355CDE#TRPBF
4355
14-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC4355IDE#PBF
LTC4355IDE#TRPBF
4355
14-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LTC4355CS#PBF
LTC4355CS#TRPBF
LTC4355CS
16-Lead Plastic SO
0°C to 70°C
LTC4355IS#PBF
LTC4355IS#TRPBF
LTC4355IS
16-Lead Plastic SO
–40°C to 85°C
LTC4355CMS#PBF
LTC4355CMS#TRPBF
4355
16-Lead Plastic MSOP
0°C to 70°C
LTC4355IMS#PBF
LTC4355IMS#TRPBF
4355
16-Lead Plastic MSOP
–40°C to 85°C
LTC4355HMS#PBF
LTC4355HMS#TRPBF
4355
16-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4355ff
2
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LTC4355
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. 9V < VOUT < 80V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VOUT
Operating Supply Range
l
IOUT
Supply Current
l
IINx
INx Pin Input Current
GATE High
l
0.5
DVGATEx
External N-Channel Gate Drive
(VGATEx – VINx)
VOUT = 20V to 80V
VOUT = 9V to 20V
l
l
10
4.5
IGATEx(UP)
External N-Channel Gate Pull-Up Current
VGATEx = VINx ,
VINx – VOUT = 100mV
l
IGATEx(DN)
External N-Channel Gate Pull-Down in Fault
Condition
Gate Drive Off, VGATEx = VINx +5V
l
tOFF
Gate Turn-Off Time
–
VINx – VOUT = 55mV |––1V, CGATE = 0
VGATEx – VINx < 1V
VMONx(TH)
MONx Pin Threshold Voltage
VMONx Rising
VMONx(HYST)
MONx Pin Hysteresis Voltage
IMONx(IN)
MONx Pin Input Current
VMONx = 1.23V
l
VINx(TH)
INx Pin Threshold Voltage
VINx Rising
l
VINx(HYST)
INx Pin Hysteresis Voltage
DVSD
Source-Drain Regulation Voltage
(VINx – VOUT )
DVSD(FLT)
Short-Circuit Fault Voltage
(VINx – VOUT) Rising
DVSD(FLT)(HYST)
Short-Circuit Fault Hysteresis Voltage
VFLT
PWRFLTx, FUSEFLTx, VDSFLT Pins
Output Low
IPWRFLTx, IFUSEFLTx, IVDSFLT = 5mA
l
100
200
mV
IFLT
PWRFLTx, FUSEFLTx, VDSFLT Pins
Leakage Current
VPWRFLTx, VFUSEFLTx, VVDSFLT = 5V
l
0
±1
µA
RSET(L)
SET Resistance Range for DVSD(FLT) = 0.25V
l
0
5
kW
RSET(M)
SET Resistance Range for DVSD(FLT) = 0.5V
l
50
150
kW
RSET(H)
SET Resistance Range for DVSD(FLT) = 1.5V
l
1
9
MAX
UNITS
80
V
2
3
mA
0.6
1.2
mA
14
6
18
18
V
V
–14
–20
–26
µA
1
2
l
A
0.3
0.4
µs
l
1.209
1.227
1.245
l
10
30
45
mV
0
±1
µA
3
3.5
4
V
l
25
75
150
mV
VGATEx – VINx = 2.5V
l
10
25
55
mV
SET = 0V
SET = 100kΩ
SET = Hi-Z
l
l
l
0.2
0.4
1.3
0.25
0.5
1.5
0.3
0.6
1.6
V
V
V
30
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
V
mV
MW
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 3: The GATEx pins are internally limited to a minimum of 13V above
INx. Driving these pins beyond the clamp may damage the part.
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3
LTC4355
Typical Performance Characteristics
IOUT vs VOUT
1.0
VOUT = VIN
1.0
0.5
0
–20
VIN = VOUT
0.75
IIN (mA)
IOUT (mA)
1.5
IIN vs VIN
0.5
0.25
0
40
20
60
0
80
VGATE = 2.5V
20
40
0
40
20
VOUT (V)
60
60
–50
80
0
VIN (V)
50
100
4355 G02
4355 G03
Fault Output Low
vs Load Current
DVGATE vs IGATE
Fault Output Low
vs Temperature
0.3
VIN > 18V
150
VSD (mV)
4355 G01
15
IGATE vs DVSD
0
IGATE (µA)
2.0
150
IFLT = 5mA
125
0.2
VFLT (V)
∆VGATE (V)
VIN = 12V
VFLT (mV)
10
VIN = 9V
100
0.1
5
75
0
0
–5
–10
–15
IGATE (µA)
–20
0
–25
0
10
5
400
300
300
100
FET Turn-Off Time
vs Final Overdrive
2000
VIN = 48V
∆VSD = VINITIAL –1V
200
20
20
CGATE (nF)
40
50
4355 G07
0
1000
500
100
10
VIN = 48V
∆VSD = 50mV VFINAL
1500
tPD (ns)
400
tPD (ns)
tOFF (ns)
500
VGATE < VIN + 1V
∆VSD = 50mV –1V
0
4355 G06
FET Turn-Off Time
vs Initial Overdrive
200
100
4355 G05
FET Turn-Off Time
vs GATE Capacitance
0
50
0
TEMPERATURE (°C)
IFLT (mA)
4355 G04
500
50
–50
15
0
0.2
0.6
0.4
VINITIAL (V)
0.8
1.0
4355 G08
0
–1.0
–0.8
–0.4
–0.6
VFINAL (V)
–0.2
0
4355 G09
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LTC4355
Pin Functions
Exposed Pad: Exposed pad may be left open or connected
to GND.
FUSEFLTx: Fuse Fault Outputs. Open-drain output that
pulls to GND when VINx < 3.5V, indicating that the fuse
has blown open. Otherwise, this output is high impedance.
Connect to GND if unused.
GATEx: Gate Drive Outputs. The GATE pins pull high,
enhancing the N-channel MOSFET when the load current creates more than 25mV of voltage drop across
the MOSFET. When the load current is small, the
gates are actively driven to maintain 25mV across the
MOSFET. If the reverse current develops more than
–25mV of voltage drop across a MOSFET, a fast pull-down
circuit quickly connects the GATE pin to the IN pin, turning
off the MOSFET. Limit the capacitance between the GATE
and IN pins to less than 0.1µF.
GND: Device Ground.
INx: Input Voltages and GATE Fast Pull-Down Returns. The
IN pins are the anodes of the ideal diodes and connect to the
sources of the N-channel MOSFETs. The voltages sensed
at these pins are used to control the source-drain voltages
across the MOSFETs and are used by the fault detection
circuits that drive the PWRFLT, FUSEFLT, and VDSFLT pins.
The GATE fast pull-down current is returned through the IN
pins. Connect these pins as close to the MOSFET sources
as possible. Connect to OUT if unused.
MONx: Input Supply Monitors. These pins are used to
sense the input supply voltages. Connect these pins to
external resistive dividers between the input supplies and
GND. If VMONx falls below 1.23V, the PWRFLTx pin pulls
to GND. Connect to GND if unused.
NC: No Connection. Not internally connected. These
pins provide extra distance between high and low voltage pins.
OUT: Drain Voltage Sense and Positive Supply Input. OUT
is the diode-OR output of IN1 and IN2. It connects to the
common drain connection of the N-channel MOSFETs. The
voltage sensed at this pin is used to control the sourcedrain voltages across the MOSFETs and is used by the
fault detection circuits that drive the PWRFLT and VDSFLT
pins. The LTC4355 is powered from the OUT pin.
PWRFLTx: Power Fault Outputs. Open-drain output
that pulls to GND when VMONx falls below 1.23V or
the forward voltage across the MOSFET exceeds
DV SD(FLT). When V MONx is above 1.23V and the
forward voltage across the MOSFET is less than
DVSD(FLT), PWRFLTx is high impedance. Connect to GND
if unused.
SET: DVSD(FLT) Threshold Configuration Input. Tying SET
to GND, to a 100k resistor connected to GND, or leaving
SET open configures the DVSD(FLT) forward voltage fault
threshold to 250mV, 500mV, or 1.5V, respectively. When the
voltage across a MOSFET exceeds DVSD(FLT), the VSDFLT
pin and at least one of the PWRFLT pins pull to GND.
VDSFLT: MOSFET Fault Output. Open-drain output that
pulls to GND when the forward voltage across either
MOSFET exceeds DVSD(FLT). PWRFLT1 or PWRFLT2 also
pulls low to indicate which MOSFET’s forward voltage drop
exceeds DVSD(FLT). Otherwise, this pin is high impedance.
Connect to GND if unused.
4355ff
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5
LTC4355
Block Diagram
IN1
GATE1
OUT
GATE2
17V
IN2
17V
–
+
25mV
–+
∆VSD(FLT)
25mV
+
–
∆VSD(FLT)
+–
∆VSD1(FLT)
FAULT
+
–
+
–
–
+
+
GATE2
AMP
–
GATE1
AMP
∆VSD2(FLT)
FAULT
∆VSD(FLT) =
0.25V, 0.5V OR 1.5V
VDSFLT
–
–
FUSEFLT1
+
FUSEFLT2
FUSE2
FAULT
FUSE1
FAULT
+
–
3.5V
3.5V
+
–
+
PWRFLT1
PWRFLT2
+
–
+
–
MON1
+
–
1.23V
–
MON2
+
MON1
MON2
1.23V
4355 BD
GND
SET
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LTC4355
Operation
High availability systems often employ parallel-connected
power supplies or battery feeds to achieve redundancy
and enhance system reliability. ORing diodes have been
a popular means of connecting these supplies at the
point of load. The disadvantage of this approach is the
forward voltage drop and resulting efficiency loss. This
drop reduces the available supply voltage and dissipates
significant power. Using N-channel MOSFETs to replace
Schottky diodes reduces the power dissipation and
eliminates the need for costly heat sinks or large thermal
layouts in high power applications.
The LTC4355 is a positive voltage diode-OR controller
that drives two external N-channel MOSFETs as pass
transistors to replace ORing diodes. The IN and OUT
pins form the anodes and cathodes of the ideal diodes.
The source pins of the external MOSFETs are connected
to the IN pins. The drains of the MOSFETs are connected
together at the OUT pin, which is the positive supply of
the device. The gates of the external MOSFETs are driven
by the LTC4355 to regulate the voltage drop across the
pass transistors.
At power-up, the initial load current flows through the
body diode of the MOSFET with the higher INx voltage.
The associated GATEx pin immediately ramps up and
turns on the MOSFET. The amplifier tries to regulate the
voltage drop across the source and drain connections to
25mV. If the load current causes more than 25mV of drop,
the MOSFET gate is driven fully on and the voltage drop
is equal to RDS(ON) • ILOAD.
When the power supply voltages are nearly equal, this
regulation technique ensures that the load current is
smoothly shared between the MOSFETs without oscil-
lation. The current flowing through each pass transistor depends on the RDS(ON) of each MOSFET and the
output impedances of the supplies.
In the event of a supply failure, such as if the supply that
is conducting most or all of the current is shorted to GND,
reverse current flows temporarily through the MOSFET that
is on. This current is sourced from any load capacitance
and from the second supply through the body diode of
the other MOSFET. The LTC4355 quickly responds to this
condition, turning off the MOSFET in about 500ns. This
fast turn-off prevents the reverse current from ramping
up to a damaging level.
In the case where the forward voltage drop exceeds the
configurable fault threshold, DVSD(FLT), the VDSFLT pin
pulls low. Using this pin to shunt current away from an
LED or opto-coupler provides an indication that a pass
transistor has either failed or has excessive forward current.
Additionally, in this condition the PWRFLT1 or PWRFLT2
pin pulls low to identify the faulting channel.
The PWRFLT pins also indicate if an input supply is within
regulation. When VMON1 < 1.23V or VMON2 < 1.23V, the
corresponding PWRFLT pin pulls low to indicate that the
input supply is low, turning off an optional LED or optocoupler.
The FUSEFLT pins indicate the status of input fuses. If
the voltage at one of the IN pins is less than 3.5V, the
corresponding FUSEFLT pin pulls low. The IN pins sink
a minimum of 0.5mA to guarantee that the IN pin will
pull low when the input fuse is blown open. Note that the
FUSEFLT pin will activate if the input supply is less than
3.5V even if the fuse is intact.
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7
LTC4355
Applications Information
MOSFET Selection
The LTC4355 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
on-resistance RDS(ON), the maximum drain-source voltage
VDSS, and the threshold voltage.
The gate drive for the MOSFET is guaranteed to be greater
than 4.5V when the supply voltage at VOUT is between
9V and 20V. When the supply voltage at VOUT is greater
than 20V, the gate drive is guaranteed to be greater than
10V. The gate drive is limited to less than 18V. This allows
the use of logic level threshold N-channel MOSFETs and
standard N-channel MOSFETs above 20V. An external
Zener diode can be used to clamp the potential from the
MOSFET’s gate to source if the rated breakdown voltage
is less than 18V. See the Typical Applications section for
an example.
The maximum allowable drain-source voltage, BVDSS,
must be higher than the supply voltages. If an input is
connected to GND, the full supply voltage will appear
across the MOSFET.
If the voltage drop across either MOSFET exceeds the
configurable DVSD(FLT) fault threshold, the VDSFLT
pin and the PWRFLT pin corresponding to the faulting channel pull low. The RDS(ON) should be small
enough to conduct the maximum load current while
not triggering a fault, and to stay within the MOSFET’s power rating at the maximum load current
(I2 • RDS(ON)).
Fault Conditions
The LTC4355 monitors fault conditions and shunts current
away from LEDs or opto-couplers, turning each one off to
indicate a specific fault condition (see Table 1).
When the voltage drop across the pass transistor is
higher than the configurable DVSD(FLT) fault threshold, the
internal pull-down at the VDSFLT pin and the PWRFLT1 or
PWRFLT2 pin corresponding to the faulting channel turns
on. The DVSD(FLT) threshold is configured by the SET pin.
Tying SET to GND, tying SET to a 100k resistor connected
to GND, or floating SET configures DVSD(FLT) to 250mV,
500mV, or 1.5V respectively.
Fault conditions that may cause a high voltage across the
pass transistor include: a MOSFET open on the higher
supply, excessive MOSFET current due to overcurrent
on the load or a shorted MOSFET on the lower supply.
During startup or when a switchover between supplies
occurs, the VDSFLT pin and PWRFLT1 or PWRFLT2 pin
may momentarily indicate that the forward voltage has
exceeded the programmed threshold during the short
interval when the MOSFET gate ramps up and the body
diode conducts.
The PWRFLT pins are additionally used to indicate if either
input supply is below its normal regulation range. If the
voltage at the MON1 or MON2 pin is less than VMON(TH),
typically 1.23V, the corresponding PWRFLT1 or PWRFLT2
pin will pull low. A resistive divider connected to the input
supply drives the MON pin for the corresponding supply,
configuring the PWRFLT threshold for that supply. Be sure
to account for the tolerance of the MON pin threshold,
the resistor tolerances, and the regulation range of the
supply being monitored. Also, ensure that the voltage on
the MON pin will not exceed 7V.
The FUSEFLT pins are used to indicate the status of the
input fuses. If one of the IN pins falls below VINx(TH), typically 3.5V, the FUSEFLT pin corresponding to that supply
will pull low. The IN pins each sink a minimum of 0.5mA,
enough to pull the pin low after an input fuse blows open.
If there is a possibility that the MOSFET leakage current
can be greater than 0.5mA, a resistor can be connected
between the IN pin and GND to sink more current. Note
that if the input supply voltage is less than VINx(TH) the
FUSEFLT pin will pull low.
Table 1. Fault Table
DVSD1
< DVSD(FLT)
VIN1
> 3.5V
VMON1
> 1.23V
VDSFLT*
FUSEFLT1
PWRFLT1
True
True
True
Hi-Z
Hi-Z
Hi-Z
True
True
False
Hi-Z
Hi-Z
Pull-Down
True
False
True
Hi-Z
Pull-Down
Hi-Z
True
False
False
Hi-Z
Pull-Down
Pull-Down
False
True
True
Pull-Down
Hi-Z
Pull-Down
False
True
False
Pull-Down
Hi-Z
Pull-Down
False
False
True
Pull-Down
Pull-Down
Pull-Down
False
False
False
Pull-Down
Pull-Down
Pull-Down
*DVSD2 < DVSD(FLT)
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LTC4355
Applications Information
System Power Supply Failure
High slew rates coupled with parasitic inductances in series with the input and output paths may cause potentially
destructive transients to appear at the IN and OUT pins of
the LTC4355 during reverse recovery. A zero impedance
short-circuit directly across an input that is supplying
current is especially troublesome because it permits the
highest possible reverse current to build up during the
delay phase. When the MOSFET finally commutates the
reverse current the LTC4355 IN pin experiences a negative voltage spike, while the OUT pin spikes in the positive
direction.
The LTC4355 automatically supplies load current from the
system input supply with the higher voltage. If this supply
shorts to ground, reverse current begins to flow through
the pass transistor temporarily and the transistor begins
to turn off. When this reverse current creates –25mV of
voltage drop across the drain and source pins of the pass
transistor, a fast pull-down circuit engages to drive the
gate low faster.
The remaining system power supply delivers the load current through the body diode of its pass transistor until the
channel turns on. The LTC4355 ramps the gate up with
20µA, turning on the N-channel MOSFET to reduce the
voltage drop across it.
To prevent damage to the LTC4355 under conditions of
input short-circuit, protect the IN pins and OUT pin as
shown in Figure 1. The IN pins are protected by clamping
to the GND pin in the negative direction. Protect the OUT
pin with a clamp, such as with a TVS or TransZorb, or with
a local bypass capacitor of at least 10µF. In low voltage
applications the MOSFET’s drain-source breakdown may
be sufficient to protect the OUT pin, provided BVDSS +
VIN < 100V.
Input Short-Circuit Faults
The dynamic behavior of an active, ideal diode entering
reverse bias is most accurately characterized by a delay
followed by a period of reverse recovery. During the delay
phase some reverse current is built up, limited by parasitic resistances and inductances. During the reverse recovery phase, energy stored in the parasitic inductances
is transferred to other elements in the circuit. Current
slew rates during reverse recovery may reach 100A/µs
or higher.
VIN1
INPUT PARASITIC
INDUCTANCE
+
–
DIN1
SBR1U150SA
REVERSE RECOVERY CURRENT
M1
FDS3672
COUT
OR
10µF
REVERSE
RECOVERY
CURRENT
INPUT
SHORT
VIN2
Parasitic inductance between the load bypass or the
second supply and the LTC4355 allows a zero impedance
input short to collapse the voltage at the OUT pin, which
increases the total turn-off time (tOFF). For applications
up to 30V, bypass the OUT pin with 39µF; above 30V use
at least 100µF. One capacitor serves to guard against OUT
collapse and also protect OUT from voltage spikes.
INPUT PARASITIC
INDUCTANCE
–
+
OUTPUT PARASITIC
INDUCTANCE
+
–
DCLAMP
SMAT70A
VOUT
CLOAD
M2
FDS3672
DIN2
SBR1U150SA
IN1 GATE1 IN2
GATE2 OUT
LTC4355
GND
4355 F01
Figure 1. Reverse Recovery Produces Inductive Spikes at the IN and OUT Pins.
The Polarity of Step Recovery Spikes Is Shown Across Parasitic Inductances
4355ff
For more information www.linear.com/LTC4355
9
LTC4355
Applications Information
Loop Stability
Next, select the resistive dividers that guarantee the
PWRFLT pins will not assert when the input supplies are
above 36V. The maximum VMONx(TH) is 1.245V and the
maximum IMONx(IN) is 1µA. Choose a 1% tolerance resistor
R1 = 12.7k. Then,
The servo loop is compensated by the parasitic capacitance of the power N-channel MOSFET. No further
compensation components are normally required. In
the case when a MOSFET with less than 1000pF gate
capacitance is chosen, a 1000pF compensation capacitor
connected across the gate and source pins might be
required.
IR2 =
Design Example
VMONx(TH)
+I
R1(MIN) MONx (TH)(MAX)
1.245V
=
+ 1µA = 100µA
12.7kΩ(−1%)
The following design example demonstrates the calculations
involved for selecting components in a 36V to 72V system
with 5A maximum load current (see Figure 2).
Use IR2 to choose R2.
First, choose the N-channel MOSFET. The 100V, FDS3672
in the SO-8 package with RDS(ON) = 22mW(max) offers
a good solution. The maximum voltage drop across it is:
The LED D1, a Panasonic Green LN1351C, requires at least
1mA of current to fully turn on. Therefore, R5 is set to 33k
to accommodate the lowest input supply voltage of 36V.
The maximum power dissipation in the MOSFET is a mere:
P = 5A • 110mV = 0.55W
VIN1 = +48V
M1
FDS3672
F2
7A
VIN2 = +48V
R2
340k
R4
340k
R5
33k
IN1
SET
MON2
R3
12.7k
TO
LOAD
M2
FDS3672
GATE1 IN2
GATE2 OUT
MON1
R1
12.7k
36V − 1.245V
= 348kΩ
100µA
Adjust R2 down by 1% to 344k to account for its tolerance.
The next lower standard resistor value is R2 = 340k.
DV = 5A • 22mΩ = 110mV
F1
7A
R2 =
LTC4355
GND
R6
33k
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
GREEN LEDs
PANASONIC LN1351C
R7
33k
D1
R8
33k
D3
D2
GND
R9
33k
D5
D4
4355 F02
Figure 2. 36V to 72V/5A Design Example
4355ff
10
For more information www.linear.com/LTC4355
LTC4355
Applications Information
Layout Considerations
The following advice should be considered when laying
out a printed circuit board for the LTC4355.
Keep the traces to the MOSFETs wide and short. The PCB
traces associated with the power path through the MOSFETs should have low resistance (see Figure 3).
S
D
D
S
D
D
D
D
D
D
FET
S
G
FET
S
S
S
IN1
LTC4355
GATE1
OUT
GATE2
IN2
For the DFN package, pin spacing may be a concern at
voltages greater than 30V. Check creepage and clearance
guidelines to determine if this is an issue. Use no-clean
solder to minimize PCB contamination.
G
4355 F03
The inputs to the servo amplifiers, IN1, IN2, and OUT
should be connected as closely as possible to the
MOSFETs’ terminals for good accuracy.
Figure 3. Layout Considerations
4355ff
For more information www.linear.com/LTC4355
11
LTC4355
typical applications
–36V to –72V/10A with Positive Supply and Negative Supply Diode-ORing
15A
RTNA
IRF3710
15A
RTNB
IRF3710
33k
340k
340k
IN1
GATE1 IN2
MON2
12.7k
GND
12.7k
33k
33k
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
LTC4355
SET
33k
GATE2 OUT
MON1
33k
GREEN LEDs
PANASONIC LN1351C
LOAD
12k
33k
VCC
LTC4354
DA
VA = –48V
VB = –48V
10A
10A
DB
2k
GA
FAULT
GB
VSS
1µF
2k
RED LED
PANASONIC
LN1251CLA
IRF3710
IRF3710
4355 F04
4355ff
12
For more information www.linear.com/LTC4355
LTC4355
typical applications
–48V/5A with Positive Supply and Negative Supply Diode-ORing with Reverse Input Protection
RTNA
RTNB
10A
FDS3672
10A
FDS3672
IN1
GATE1 IN2 GATE2 OUT
= BAS21
LTC4355
GND
SMBT70A
LOAD
12k
VCC
1µF
LTC4354
DA
VA = –48V
VB = –48V
7A
DB
2k
GA
GB
VSS
2k
FDS3672
7A
FDS3672
4355 F05
NOTE: MAXIMUM VOLTAGE BETWEEN ANY TWO INPUTS = 80VDC
+24V Diode-OR With Reverse Input Protection
FDS3672
VIN1 = +24V
FDS3672
VIN2 = +24V
LOAD
= BAS21
IN1
GATE1 IN2
GATE2 OUT
LTC4355
SMBT70A
GND
GND
4355 TA05
4355ff
For more information www.linear.com/LTC4355
13
LTC4355
typical applications
Single 12V/15A Ideal Diode with Parallel Drivers
F1
15A
VIN = 12V
M1
HAT2165H
TO LOAD
R1
86.6k
R3
10k
IN1
IN2
VDSFLT
FUSEFLT1
PWRFLT1
FUSEFLT2
PWRFLT2
LTC4355
SET
MON2
R5
10k
GATE1 GATE2 OUT
MON1
R2
12.7k
R4
10k
GND
D1
D2
GND
GREEN LEDs
D3 PANASONIC
LN1351C
4355 TA03
Single 36V to 72V/30A Ideal Diode Using Parallel MOSFETs
F1
30A
VIN = +48V
M1
IRFS4710
TO
LOAD
M2
IRFS4710
R3
33k
R1
340k
IN1
SET
R2
12.7k
MON2
R4
33k
IN2 GATE1 GATE2 OUT
MON1
LTC4355
GND
R5
33k
VDSFLT
FUSEFLT1
PWRFLT1
FUSEFLT2
PWRFLT2
D1
D3
GREEN LEDs
PANASONIC
LN1351C
D2
GND
4355 TA04
4355ff
14
For more information www.linear.com/LTC4355
LTC4355
TYPICAL Applications
AdvancedTCA with High Side and Low Side Ideal Diode-OR
and Hot SwapTM Controller with I2C Current and Voltage Monitor
LONG
10A
LONG
10A
FDS3672
VRTN_A
–48VRTN(OUT)
FDS3672
VRTN_B
91Ω
SMBT70A
22nF
100V
IN1 GATE1 IN2 GATE2 OUT
MON1
SET
MON2
D
ENABLE_B
ENABLE_A
SHORT
100k
SHORT
100k
1M
1M
LTC4355
GND
1.1k
D
1.1k
FMMT5401
D 100k
1.1k
1.1k
FMMT5401
D 100k
1µF
137k
10k
107k
VCC
LTC4354
100nF
2k
2k
MEDIUM LONG
100nF
100nF
100k
10.2k
100nF
2.49k
PG
SCL
SDAI
SDAO
ALERT
PGIO
PGI
ADIN
LTC4261
TMR VEE
SENSE
GATE DRAIN RAMP
330nF
330nF
33nF
47nF
FDS3672
MEDIUM SHORT
–48V_B
HZS5C1
7A
–48V_A
1µF
GB VSS VSS
DA DB GA
VIN
UVH
UVL
ADIN2
OV
ON
INTVCC
FLTIN
EN
ADR1
ADR0 SS
10Ω
1M
1k
10nF
100V
7A
FDS3672
8mΩ
D: 1N4148WS
IRF1310NS
–48VOUT
4355 TA06
4355ff
For more information www.linear.com/LTC4355
15
LTC4355
TYPICAL Applications
36V to 72V/10A with Positive Supply and Negative Supply Diode-ORing,
Combined Fault Outputs, and Zener Clamps on MOSFET Gates
10A
VA = 48V
IRLR3110ZPbF
12V ZENER
CMZ4699
10A
VB = 48V
IRLR3110ZPbF
33k
12V ZENER
CMZ4699
340k
340k
IN1
GATE1 IN2
GATE2 OUT
MON1
LTC4355
SET
MON2
12.7k
VDSFLT
FUSEFLT1
FUSEFLT2
PWRFLT1
PWRFLT2
GND
GREEN LED
PANASONIC
LN1351C
12.7k
LOAD
12k
VCC
100k
LTC4354
DA
GNDA
GNDB
15A
15A
DB
2k
GA
2N2222
FAULT
GB
VSS
1µF
2k
IRLR3110ZPbF
IRLR3110ZPbF
4355 TA07
4355ff
16
For more information www.linear.com/LTC4355
LTC4355
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
0.70 ±0.05
3.30 ±0.05
3.60 ±0.05
2.20 ±0.05
1.70 ± 0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ±0.10
(2 SIDES)
R = 0.05
TYP
3.00 ±0.10
(2 SIDES)
R = 0.115
TYP
8
0.40 ± 0.10
14
3.30 ±0.10
1.70 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.75 ±0.05
(DE14) DFN 0806 REV B
7
1
0.25 ± 0.05
0.50 BSC
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4355ff
For more information www.linear.com/LTC4355
17
LTC4355
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev A)
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.889 ±0.127
(.035 ±.005)
5.10
(.201)
MIN
16151413121110 9
3.20 – 3.45
(.126 – .136)
0.254
(.010)
DETAIL “A”
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
0° – 6° TYP
0.280 ±0.076
(.011 ±.003)
REF
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
0.50
(.0197)
BSC
0.305 ±0.038
(.0120 ±.0015)
TYP
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
RECOMMENDED SOLDER PAD LAYOUT
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.17 – 0.27
(.007 – .011)
TYP
1234567 8
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
0.50
(.0197)
BSC
MSOP (MS16) 0213 REV A
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
.386 – .394
(9.804 – 10.008)
NOTE 3
.045 ±.005
.050 BSC
16
N
14
13
12
11
10
9
N
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
1
.030 ±.005
TYP
15
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
1
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
2
3
4
5
.053 – .069
(1.346 – 1.752)
NOTE:
1. DIMENSIONS IN
.014 – .019
(0.355 – 0.483)
TYP
7
8
.004 – .010
(0.101 – 0.254)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
6
.050
(1.270)
BSC
S16 REV G 0212
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
4355ff
18
For more information www.linear.com/LTC4355
LTC4355
Revision History
(Revision history begins at Rev E)
REV
DATE
DESCRIPTION
PAGE NUMBER
E
2/10
Updated Features section and removed patent
1
Revised tOFF conditions
3
Revised NC pin description
Revised Typical Application drawings
F
8/13
5
13, 15, 16
Corrected part number LTC4352 in Related Parts
20
Added H-grade (LTC4355H) information
2
Changed θJA: MS package from 125°C/W to 120°C/W, S package from 75°C/W to 80°C/W
2
Swapped ampere ratings between the two sets of fuses
12
4355ff
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC4355
19
LTC4355
Typical Application
200W AdvancedTCA Ideal Diode-OR
10A
RTNA
FDS3672
10A
RTNB
FDS3672
IN1
GATE1 IN2
GATE2 OUT
LTC4355
GND
LOAD
12k
VCC
1µF
LTC4354
DA
7A
VA = –48V
DB
2k
GA
VSS
2k
7A
VB = –48V
GB
FDS3672
FDS3672
4355 TA08
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC1921
Dual –48V Supply and Fuse Monitor
UV/OV Monitor, –10V to –80V Operation, MSOP Package
LT4250
–48V Hot Swap Controller
Active Current Limiting, Supplies From –20V to –80V
LTC4251/LTC4251-1/
LTC4251-2
–48V Hot Swap Controllers in SOT-23
Fast Active Current Limiting, Supplies From –15V
LTC4252-1/LTC4252-2/
LTC4252-A1/LTC4252-A2
–48V Hot Swap Controllers in MS8/MS10
Fast Active Current Limiting, Supplies From –15V, Drain Accelerated
Response
LTC4253
–48V Hot Swap Controller with Sequencer
Fast Active Current Limiting, Supplies From –15V, Drain Accelerated
Response, Sequenced Power Good Outputs
LT4256-1
Positive 48V Hot Swap Controller with
Open-Circuit Detect
Foldback Current Limiting, Open-Circuit and Overcurrent Fault Output,
Up to 80V Supply
LTC4260
Positive High Voltage Hot Swap Controller
With I2C and ADC, Supplies from 8.5V to 80V
LTC4261
Negative High Voltage Hot Swap Controller
With I2C and 10-Bit ADC, Adjustable Inrush and Overcurrent Limits
LTC4352
Ideal Diode Controller with Monitor
Controls N-Channel MOSFET, 0V to 18V Operation
LTC4354
Negative Voltage Diode-OR Controller
and Monitor
Controls Two N-Channel MOSFETs, 1µs Turn-Off, –80V Operation
LTC4357
Positive High Voltage Ideal Diode Controller
Controls Single N-Channel MOSFET, 0.5µs Turn-Off, 80V Operation
LTC4358
5A Ideal Diode
Integrated N-Channel MOSFET, 0.5µs Turn-Off, 9V to 26.5V
LTC4359
Ideal Diode Controller with Reverse Input
Protection
4V to 80V Operation, –40V Input Protection, 150µA IQ
4355ff
20 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC4355
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC4355
LT 0813 REV F • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2007
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