LTC4362IDCB-2#TRPBF

LTC4362-1/LTC4362-2 1.2A Overvoltage/Overcurrent Protector FEATURES DESCRIPTION 2.5V to 5.5V Operation nn Overvoltage Protection Up to 28V nn Internal 40mΩ N-Channel MOSFET and 31mΩ R SENSE nn Avalanche Rated MOSFET Requires No Input Capacitor or TVS for Most Applications nn 2.1V), a start-up delay cycle begins. Any overvoltage condition causes the delay cycle to continue until a safe voltage is present. When the delay cycle completes, an internal high-side switch driver slowly ramps up the MOSFET gate, powering up the output at a controlled rate and limiting the inrush current to the output capacitor. Rev. B For more information www.analog.com LTC4362-1/LTC4362-2 OPERATION If the voltage at the IN pin exceeds 5.8V (VIN(OV)), the internal N-channel MOSFET is turned off quickly to protect the load. The incoming power supply must remain below 5.7V (VOUT(OV) – ΔVOV) for the duration of the start-up delay to restart the OUT ramp-up. An internal sense resistor is used to implement an overcurrent protection with a 1.5A current trip threshold and a 10µs glitch filter. After an overcurrent, the LTC4362-1 latches off while the LTC4362-2 restarts following a 130ms delay. The LTC4362 has a CMOS compatible ON input. When driven low, the part is enabled. When driven high, the internal N-channel MOSFET is turned off and the supply current of the LTC4362 drops to 1.5μA. The PWRGD pull-down releases during this low current sleep mode, UVLO, overvoltage, overcurrent or thermal shutdown and the subsequent 130ms start-up delay. After the start-up delay, the internal MOSFET gate starts its 3V/ms ramp-up. It trips an internal gate high threshold to trigger a 65ms delay. When that completes, PWRGD pulls low. The output pull-down device is capable of sinking up to 3mA allowing it to drive an optional LED. The LTC4362 has a GATEP pin that drives an optional external P-channel MOSFET to provide protection against negative voltages at IN. APPLICATIONS INFORMATION The typical LTC4362 application protects 2.5V to 5.5V systems in portable devices from power supply overvoltage. The basic application circuit is shown in Figure 1. Device operation and external component selection is discussed in detail in the following sections. VIN 5V IN OUT LTC4362 5V VIO VOUT 5V COUT 0.5A 10µF R1 1k ON PWRGD GND D1 LN1351CTR 436212 F01 Figure 1. Protection from Overvoltage and Overcurrent Start-Up When VIN is less than the undervoltage lockout level of 2.1V, the internal N-channel MOSFET is held off and the PWRGD pull-down is high impedance. When VIN rises above 2.1V and ON is held low, a 130ms delay cycle starts. Any undervoltage or overvoltage event at IN (VIN < 2.1V or VIN > 5.7V) restarts the delay cycle. This delay allows the MOSFET to isolate the output from any input transients that occur at start-up. When the delay cycle completes, the MOSFET is turned on and OUT starts its slow ramp-up. OUT Control An internal charge pump enhances the internal N-channel MOSFET with the OUT ramp-rate limited to 3V/ms. This results in an inrush current into the load capacitor COUT of: IINRUSH = COUT • dVOUT dt = COUT • 3 [mA /µF ] Overvoltage When power is first applied, VIN must remain below 5.7V (VIN(OV) – ΔVOV) for more than 130ms before the output is turned on. If VIN then rises above 5.8V (VIN(OV)), the overvoltage comparator turns off the internal MOSFET within 1µs. After an overvoltage condition, the MOSFET is held off until VIN once again remains below 5.7V for 130ms. Overcurrent The overcurrent comparator protects the internal MOSFET from excessive current. It trips when IOUT > 1.5A for 10µs. When the overcurrent comparator trips, the internal MOSFET is turned off quickly and the PWRGD pull-down releases. The LTC4362-2 automatically tries to apply power again after a 130ms start-up delay. The LTC4362-1 has an internal latch that maintains this off state until it is reset. To reset this latch, cycle IN below 2.1V (VIN(UVL)) Rev. B For more information www.analog.com 7 LTC4362-1/LTC4362-2 APPLICATIONS INFORMATION or ON above 1.5V (VON(TH)) for more than 500µs. After reset, the LTC4362-1 goes through the start-up cycle. In applications not requiring the overcurrent protection, tie SENSE and the exposed pad to the IN pin. PWRGD Output PWRGD is an active low output with a MOSFET pull-down to ground and a 500k resistive pull-up to OUT. The PWRGD pin pull-down releases during the low current sleep mode (invoked by ON high), UVLO, overvoltage, overcurrent or thermal shutdown and the subsequent 130ms startup delay. After the start-up delay, the internal MOSFET gate starts its 3V/ms ramp-up and control of the PWRGD pull-down passes on to the internal gate high comparator. When the internal gate is higher than the gate high threshold for more than 65ms, PWRGD asserts low. When the internal gate goes lower than the gate high threshold, the PWRGD pull-down releases. The PWRGD pull-down device is capable of sinking up to 3mA of current allowing it to drive an optional LED. To interface PWRGD to another I/O rail, connect a resistor from PWRGD to that I/O rail with a resistance low enough to override the internal 500k pull-up to OUT. Figure 2 details PWRGD behavior for a LTC4362-2 with 1k pull-up to 5V at PWRGD. START-UP FROM UVLO OV RESTART FROM OV ON Input ON is a CMOS compatible, active low enable input. It has a default 5µA pull-down to ground. Connect this pin to ground or leave open to enable normal device operation. If it is driven high while the MOSFET is turned on, the MOSFET is turned off gradually with an internal 40µA gate pull-down, minimizing input voltage transients. The LTC4362 then goes into a low current sleep mode, drawing only 1.5µA at IN. When ON goes back low, the part restarts with a 130ms delay cycle. GATEP Control GATEP has a 2M resistive pull-down to ground and a 5.8V Zener clamp in series with a 200k resistor to IN. It controls the gate of an optional external P-channel MOSFET to provide negative voltage protection. The 2M pull-down turns on the external P-channel MOSFET once VIN is more than the P-channel MOSFET gate threshold voltage. The IN to GATEP Zener protects the external P-channel MOSFET from gate overvoltage by clamping its VGS to 5.8V when VIN goes high. ON OC RESTART FROM OC RESTART FROM ON OC THRESHOLD ICABLE VIN(OV) VIN(OV) – ∆VOV VIN(UVL) IN OUT INTERNAL GATE HIGH MOSFET THRESHOLD GATE GATE HIGH THRESHOLD GATE HIGH THRESHOLD GATE HIGH THRESHOLD GATE HIGH THRESHOLD ON PWRGD 130ms 65ms 130ms 65ms Figure 2. PWRGD Behavior 8 130ms 65ms 10µs (NOT TO SCALE) 130ms 65ms 436212 F02 Rev. B For more information www.analog.com LTC4362-1/LTC4362-2 APPLICATIONS INFORMATION WALL ADAPTOR AC/DC RIN + LIN MOBILE DEVICE IN ICABLE VIN 10V/DIV COUT CABLE LOAD ICABLE 20A/DIV 436212 F03a 5µs/DIV 436212 F03b RIN = 150mΩ, LIN = 0.7µH LOAD = 10Ω, COUT = 10µF Figure 3. 20V Hot-Plug Into a 10µF Capacitor WALL ADAPTOR AC/DC RIN + LIN ICABLE IN IN OUT LT4362 CABLE OUT MOBILE DEVICE COUT LOAD VIN 10V/DIV GND 436212 F04a VOUT 1V/DIV ICABLE 1A/DIV 5µs/DIV 436212 F04b RIN = 150mΩ, LIN = 0.7µH LOAD = 10Ω, COUT = 10µF Figure 4. 20V Hot-Plug Into the LTC4362 Thermal Shutdown The internal N-channel MOSFET is protected by a thermal shutdown circuit. If its temperature reaches 150°C, it will shut off immediately and the PWRGD pull-down releases. It will turn on again after its temperature drops below 140°C. Input Transients Figure 3 shows a typical setup when an AC wall adaptor charges a mobile device. The inductor LIN represents the lumped equivalent inductance of the cable and the EMI filter found in some wall adaptors. RIN is the lumped equivalent resistance of the cable, adaptor output capacitor ESR and the connector contact resistance. LIN and RIN form an LC tank circuit with any capacitance at IN. If the wall adaptor is powered-up first, plugging the wall adaptor output to IN does the equivalent of applying a voltage step to this LC circuit. The resultant voltage overshoot at IN can rise to twice the DC output voltage of the wall adaptor (or more if ceramic capacitors with large voltage coefficients are used) as shown in Figure 3. Figure 4 shows the 20V adaptor output applied to the LTC4362. Due to the low capacitance at the IN pin, the plug-in transient has been brought down to a manageable level. Input transients also occur when the current through the cable inductance changes abruptly. This can happen when the LTC4362 turns off its internal N-channel MOSFET quickly in an overvoltage or overcurrent event. Rev. B For more information www.analog.com 9 LTC4362-1/LTC4362-2 APPLICATIONS INFORMATION Figure 5 shows an input transient after an overcurrent. The current in LIN will cause VIN to overshoot and avalanche the internal N-channel MOSFET to COUT. TURN-OFF VIN 10V/DIV VOUT 5V/DIV wall adaptor is mistakenly hot-plugged into the 5V device with the USB input already live. As shown in Figure 7, a large current can build up in LIN to charge up COUT. When the internal MOSFET shuts off, this current is dumped into COUT, causing a large 40V transient. The LTC4362 limits this to a 1V rise in the output voltage. ICABLE 10A/DIV OVERCURRENT ICABLE 2A/DIV VOUT 2V/DIV 436212 F05 2µs/DIV FIGURE 4 CIRCUIT RIN = 150mΩ, LIN = 0.7µH LOAD = 10Ω, COUT = 10µF VIN 10V/DIV 1µs/DIV Figure 5. Input Transient After Overcurrent Typically, IN will be clamped to a voltage of VOUT + 1.3•(30V BVDSS of Internal MOSFET) = 45V. The single, nonrepetitive, pulse of energy (EAS) absorbed by the MOSFET during this avalanche breakdown with a peak current IAS is approximated by the formula: E AS = 1 2 • LIN • IAS 2 For LIN = 0.7µH and IAS = 3A, then EAS = 3.15µJ. This is within the IAS and EAS capabilities of the internal MOSFET. So in most instances, the LTC4362 can ride through such transients without a bypass capacitor, transient voltage suppressor or other external components at IN. Figure 6 shows a particularly bad situation which can occur in a mobile device with dual power inputs. A 20V RIN 20V WALL ADAPTOR + – ICABLE Figure 7. Overvoltage Protection Waveforms When 20V Plugged into 5V System If the voltage rise at VOUT due to the discharge of the energy in LIN into COUT is not acceptable or the avalanche capability of the MOSFET is exceeded, an additional external clamp Z1 such as the SMAJ24A can be placed between IN and GND. Figure 8 shows the resulting waveform. ICABLE 10A/DIV VOUT 2V/DIV VIN 10V/DIV IN + – RIN = 150mΩ, LIN = 2µH LOAD = 10Ω COUT = 10µF (16V, SIZE 1210) LIN B160 5V USB 436212 F07 IN OUT LT4362 OUT 1µs/DIV RIN = 150mΩ, LIN = 0.7µH LOAD = 10Ω COUT = 10µF (16V, SIZE 1210) COUT LOAD GND 436212 F06 436212 F08 Figure 8. Overvoltage Protection Waveforms When 20V Plugged into 5V System with External IN Clamp Figure 6. Setup for Testing 20V Plugged into 5V System 10 Rev. B For more information www.analog.com LTC4362-1/LTC4362-2 APPLICATIONS INFORMATION Layout Considerations COUT is the decoupling capacitor of the protected circuit and its value is largely determined by the circuit requirements. Using a larger COUT works with LIN to slow down the dV/dt at OUT, allowing time for the LTC4362 to shut off its MOSFET before VOUT overshoots to a dangerous voltage. A larger COUT also helps to lower the ∆VOUT due to the discharge of energy in LIN if the MOSFET BVDSS is used as an input clamp. Figure 9 shows an example PCB layout for the LTC4362 with an external P-channel MOSFET for negative voltage protection. Keep the traces to the internal N-channel MOSFET wide and short. The PCB traces associated with the power path through the internal N-channel MOSFET should have low resistance. SUPPLY 6 5 4 1 Si1471DH 8 LTC4362 2 7 9 3 6 5 4 1 2 OUT 3 GND 436212 F08 Figure 9. Layout for External P-Channel MOSFET Configuration VIN 5V IN OUT LTC4362 SENSE ON COUT VOUT 5V 3A PWRGD GND 436212 F10 Figure 10. 5V Overvoltage Protection with Overcurrent Disabled Rev. B For more information www.analog.com 11 LTC4362-1/LTC4362-2 PACKAGE DESCRIPTION DCB Package 8-Lead Plastic DFN (2mm × 3mm) (Reference LTC DWG # 05-08-1718 Rev A) 0.70 ±0.05 1.35 ±0.05 3.50 ±0.05 1.65 ±0.05 2.10 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.45 BSC 1.35 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 2.00 ±0.10 (2 SIDES) R = 0.05 TYP R = 0.115 TYP 5 0.40 ±0.10 8 1.35 ±0.10 1.65 ±0.10 3.00 ±0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.25 × 45° CHAMFER PIN 1 BAR TOP MARK (SEE NOTE 6) (DCB8) DFN 0106 REV A 4 0.200 REF 1 0.23 ±0.05 0.45 BSC 0.75 ±0.05 1.35 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 12 Rev. B For more information www.analog.com LTC4362-1/LTC4362-2 REVISION HISTORY REV DATE DESCRIPTION A 1/11 Revised the Features section. 1 Revised conditions for VGATEP(CLP), tPWRGD(LH) and tPWRGD(HL) in the Electrical Characteristics section. 3 Revised Overcurrent in the Applications Information section. 7 Added VIN(OVL) specification, changed ∆VOV maximum limit. 3 Updated Typical Performance Characteristics. 5 Added Figure 10. 11 B 12/18 PAGE NUMBER Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 13 LTC4362-1/LTC4362-2 TYPICAL APPLICATION 5V System Protected from ±24V Power Supplies and Overcurrent VIN 5V M1 Si1471DH IN Z1 OPTIONAL OUT 5V VIO GATEP Z1: SMAJ24A COUT 10µF LTC4362 VOUT 5V 0.5A R1 1k D1 LN1351CTR PWRGD ON GND 436212 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2935 Ultralow Power Supervisor with Eight Pin-Selectable Thresholds 500nA Quiescent Current, 2mm × 2mm 8-Lead DFN and TSOT-23 Packages LT®3008 20mA, 45V, 3µA IQ Micropower LDO 280mV Dropout Voltage, Low IQ: 3µA, VIN = 2.0V to 45V, VOUT = 0.6V to 39.5V; ThinSOT™ and 2mm × 2mm DFN-6 Packages LT3009 20mA, 3µA IQ Micropower LDO 280mV Dropout Voltage, Low IQ: 3µA, VIN = 1.6V to 20V, VOUT = 0.6V to 19.5V; ThinSOT and SC-70 Packages LTC3576/ LTC3576-1 Switching USB Power Manager with USB OTG + Triple Step-Down DC/DCs Complete Multifunction PMIC: Bidirectional Switching Power Manager + 3 Bucks + LDO LTC4090/ LTC4090-5 High Voltage USB Power Manager with Ideal Diode Controller and High Efficiency Li-Ion Battery Charger High Efficiency 1.2A Charger from 6V to 38V (60V Max) Input Charges Single Cell Li-Ion Batteries Directly from a USB Port LTC4098 USB-Compatible Switchmode Power Manager with OVP High VIN: 38V Operating, 60V Transient; 66V OVP. 1.5A Max Charge Current from Wall, 600mA Charge Current from USB LTC4210-3 Single Channel, Low Voltage Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6 LTC4213 No RSENSE Electronic Circuit Breaker Controls Load Voltages from 0V to 6V. 3 Selectable Circuit Breaker Thresholds. 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