LTC4366MPDDB-2#TRMPBF

LTC4366 High Voltage Surge Stopper FEATURES DESCRIPTION Rugged Floating Topology nn Wide Operating Voltage Range: 9V to >500V nn Adjustable Output Clamp Voltage nn Controls N-Channel MOSFET nn Adjustable Protection Timer nn Internal 9-Second Cool-Down Timer nn Shutdown I < 14µA Q nn 8-Lead TSOT and 3mm × 2mm DFN Packages The LTC®4366 surge stopper protects loads from high voltage transients. By controlling the gate of an external N-channel MOSFET, the LTC4366 regulates the output during an overvoltage transient. The load may remain operational while the overvoltage is dropped across the MOSFET. Placing a resistor in the return line isolates the LTC4366 and allows it to float up with the supply; therefore, the upper limit on the output voltage depends only on the availability of high valued resistors and MOSFET ratings. nn APPLICATIONS Industrial, Automotive and Avionic Surge Protection High Voltage DC Distribution nn 28V Vehicle Systems nn nn An adjustable overvoltage timer prevents MOSFET damage during the surge while an additional 9-second timer provides for MOSFET cool down. A shutdown pin reduces the quiescent current to less than 14µA during shutdown. After a fault the LTC4366-1 latches off while the LTC4366‑2 will auto-retry. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents pending. TYPICAL APPLICATION Overvoltage Protected 1.5A, 28V Supply IXTK90N25L2 VIN 28V VOUT 1.5A 2nF 10Ω 0.47µF 324k VDD GATE SD LTC4366-2 TIMER VSS Overvoltage Protector Regulates Output at 43V During Transient OUT VIN 100V/DIV 28V 12.4k FB BASE 250V INPUT SURGE 422k VOUT 20V/DIV 43V CLAMP 28V 1µF 436612 TA01a 100ms/DIV 46.4k 436612 TA01b 436612fe For more information www.linear.com/LTC4366 1 LTC4366 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) All voltages relative to VSS, unless otherwise noted. Supply Voltage (VDD) ................................. –0.3V to 10V Supply Voltage (OUT) .................................. –0.3V to 5V Input Voltages FB............................................... –0.3V to OUT + 0.3V TIMER.................................................... –0.3V to 3.5V SD........................................................... –0.3V to 10V Output Voltages BASE..........................................................–1.5V to 4V OUT – BASE .......................................... –0.3V to 5.5V GATE (Note 3)......................................... –0.3V to 15V GATE – OUT (Note 3).............................. –0.3V to 10V Currents IVDD....................................................................10mA IOUT ....................................................................10mA BASE.................................................. –300µA to 10µA SD........................................................–10mA to 10µA Operating Ambient Temperature Range (Note 4) LTC4366C................................................. 0°C to 70°C LTC4366I..............................................–40°C to 85°C LTC4366H........................................... –40°C to 125°C LTC4366MP........................................ –55°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) TSOT-23 Package Only..................................... 300°C PIN CONFIGURATION TOP VIEW TOP VIEW VDD 1 SD 2 TIMER 3 VSS 4 8 GATE 7 OUT 6 FB 5 BASE TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 195°C/W 2 VSS 1 8 BASE TIMER 2 7 FB 6 OUT 5 GATE SD 3 VDD 4 9 DDB PACKAGE 8-LEAD (3mm × 2mm) PLASTIC DFN TJMAX = 150°C, θJA = 75°C/W IF VSS IS SOLDERED TO PCB, θJA = 135°C/W IF VSS IS NOT SOLDERED TO PCB EXPOSED PAD (PIN 9), PCB VSS CONNECTION OPTIONAL 436612fe For more information www.linear.com/LTC4366 LTC4366 ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4366CTS8-1#TRMPBF LTC4366CTS8-1#TRPBF LTFMC 8-Lead Plastic TSOT-23 0°C to 70°C LTC4366ITS8-1#TRMPBF LTC4366ITS8-1#TRPBF LTFMC 8-Lead Plastic TSOT-23 –40°C to 85°C LTC4366HTS8-1#TRMPBF LTC4366HTS8-1#TRPBF LTFMC 8-Lead Plastic TSOT-23 –40°C to 125°C LTC4366CDDB-1#TRMPBF LTC4366CDDB-1#TRPBF LFMD 8-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C LTC4366IDDB-1#TRMPBF LTC4366IDDB-1#TRPBF LFMD 8-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C LTC4366HDDB-1#TRMPBF LTC4366HDDB-1#TRPBF LFMD 8-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC4366CTS8-2#TRMPBF LTC4366CTS8-2#TRPBF LTFMF 8-Lead Plastic TSOT-23 0°C to 70°C LTC4366ITS8-2#TRMPBF LTC4366ITS8-2#TRPBF LTFMF 8-Lead Plastic TSOT-23 –40°C to 85°C LTC4366HTS8-2#TRMPBF LTC4366HTS8-2#TRPBF LTFMF 8-Lead Plastic TSOT-23 –40°C to 125°C LTC4366CDDB-2#TRMPBF LTC4366CDDB-2#TRPBF LFMG 8-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C LTC4366IDDB-2#TRMPBF LTC4366IDDB-2#TRPBF LFMG 8-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C LTC4366HDDB-2#TRMPBF LTC4366HDDB-2#TRPBF LFMG 8-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC4366MPTS8-1#TRMPBF LTC4366MPTS8-1#TRPBF LTFMC 8-Lead Plastic TSOT-23 –55°C to 125°C LTC4366MPTS8-2#TRMPBF LTC4366MPTS8-2#TRPBF LTFMF 8-Lead Plastic TSOT-23 –55°C to 125°C LTC4366MPDDB-1#TRMPBF LTC4366MPDDB-1#TRPBF LFMD 8-Lead (3mm × 2mm) Plastic DFN –55°C to 125°C LTC4366MPDDB-2#TRMPBF LTC4366MPDDB-2#TRPBF LFMG 8-Lead (3mm × 2mm) Plastic DFN –55°C to 125°C TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 436612fe For more information www.linear.com/LTC4366 3 LTC4366 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. All voltages relative to VSS, unless otherwise noted. SYMBOL PARAMETER CONDITIONS VZ(VDD) VDD Shunt Regulator Voltage I = 1mA ∆VZ(VDD) VDD Shunt Regulator Load Regulation I = 1mA to 5mA VDD VDD Supply Voltage (Note 3) MIN TYP MAX UNITS 11.5 12 12.5 V 30 30 90 130 mV mV VDD Regulator l LTC4366C/I/H LTC4366MP l l l 4.5 VZ(VDD) V IVDD(STLO) VDD Pin Current – Start-Up, Gate Low GATE = 0V, VDD = 7V, OUT = 0V l 15 23 µA IVDD(STHI) VDD Pin Current – Start-Up, Gate High GATE Open, VDD = 7V, OUT = 0V l 9 13 µA IVDD(SD) VDD Pin Current – Shutdown VDD = 7V, OUT = 0V l 5 8 µA OUT Shunt Regulator Voltage I = 1mA, BASE = 0V l 5.7 6.0 V ∆VZ(OUT) OUT Shunt Regulator Load Regulation I = 1mA to 5mA l 70 mV OUT OUT Supply Voltage (Note 3) VUVLO1 OUT Undervoltage Lockout 1 ∆VUVH1 OUT Undervoltage Lockout 1 Hysteresis VUVLO2 OUT Undervoltage Lockout 2 ∆VUVH2 OUT Regulator VZ(OUT) 5.0 30 l 3.0 l l 2.42 2.42 l l OUT Undervoltage Lockout 2 Hysteresis l IOUT(AMP) OUT Pin Current – Regulation Amplifier On l IOUT(CP) OUT Pin Current – Charge Pump On l IOUT(SD) OUT Pin Current – Shutdown l Rising LTC4366C/I/H LTC4366MP Rising VZ(OUT) V 2.55 2.55 2.75 2.80 V V 0.2 0.28 0.4 V 4.5 4.75 4.9 V 0.3 0.4 0.5 V 37 54 µA 150 220 µA 3 6 µA 6.2 6.6 V 125 200 mV BASE, VSS VZ(BASE) BASE Shunt Regulator Voltage (OUT – BASE) I = –10µA, OUT = 4.5V l ∆VZ(BASE) BASE Shunt Regulator Load Regulation I = –10µA to –80µA, OUT = 4.5V l OUT = 4.5V, BASE = –0.5V l 5.5 IBASE BASE Pin Leakage Current –0.1 –0.8 –5.5 µA IVSS(AMP) VSS Pin Current – Regulation Amplifier On l –30 –45 –72 µA IVSS(CP) VSS Pin Current – Charge Pump On l –108 –160 –230 µA IVSS(SD) VSS Pin Current – Shutdown l –7 –12 µA GATE Drive ∆VGATE External N-Channel Gate Drive (GATE – OUT) OUT = 4.9V, I = 0, –1µA IGATE(ST) GATE Pin Current – Start-Up GATE = OUT = 0V IGATE(CP) GATE Pin Current – Charge Pump On IGATE(FD) IGATE(FLT) 4 l 11.2 12 12.5 V l l –4.5 –3.2 –7.5 –7.5 –11 –11 µA µA GATE = 5V, OUT = 4.9V l –14 –20 –28 µA GATE Pin Current – Fast Discharge GATE = 10V, OUT = 4.9V l 122 200 300 mA GATE Pin Current – Fault GATE = 10V, OUT = 4.9V l 0.3 0.7 1.2 mA LTC4366C/I/H LTC4366MP 436612fe For more information www.linear.com/LTC4366 LTC4366 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. All voltages relative to VSS, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1.193 1.23 1.267 V FB, SD, TIMER VFB(REG) 3% FB pin Regulation Threshold (OUT – FB) IFB FB Pin Leakage Current OUT – FB = 1.2V l 0 ±1 µA VSD(TH) SD Pin Threshold Voltage (VDD – SD) Falling l 1.0 1.5 2.3 V VSD(HYST) SD Pin Hysteresis LTC4366C/I/H LTC4366MP l l 147 129 280 280 530 530 mV mV ISD SD Pin Input Pull-Up Current VDD – SD = 0.7V LTC4366C/I/H LTC4366MP l l –0.7 –0.5 –1.6 –1.6 –3.5 –3.5 µA µA VTIMER(H) TIMER Pin Threshold TIMER Rising, VDD = 7V, OUT = VZ(OUT) l 2.6 2.8 3.1 V ITIMER(UP) TIMER Pin Pull-Up Current TIMER = 1V LTC4366C/I/H LTC4366MP l l –5.1 –4 –9 –9 –13 –13 µA µA ITIMER(DN) TIMER Pin Pull-Down Current TIMER = 1V LTC4366C/I/H LTC4366MP l l 0.9 0.7 1.8 1.8 2.8 2.8 µA µA l 15 20 25 % 420 700 1200 µs l ITIMER(RATIO) TIMER Pin Current Ratio ITIMER(DN)/ITIMER(UP) AC Characteristics tDLY – SD SD Low to Gate Low Filter Time Step VDD – SD from 0V to 3V l tDLY – FAST FB Low to Gate Low Delay Time Step OUT – FB from 0V to 1.3V l 60 150 300 ns tD(COOL) Cool-Down Timer (Internal) VDD = VZ(VDD) l l 5.9 5.9 9 9 16 19 Seconds Seconds Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive. LTC4366C/I/H LTC4366MP Note 3: Limits on the maximum rating is defined as whichever limit occurs first. An internal clamp limits the GATE pin to a maximum of 12V above source. Driving this pin to voltages beyond the clamp may damage the device. Note 4: TJ is calculated from the ambient temperature, TA, and power dissipation, PD, according to the formula: TJ = TA + (PD • θJA) 436612fe For more information www.linear.com/LTC4366 5 LTC4366 TYPICAL PERFORMANCE CHARACTERISTICS 13.0 VDD Shunt Regulator vs VDD Current VDD Shunt Regulator vs Temperature VDD Start-Up Current vs Temperature (Gate High) 13.0 15 12.5 12 IVDD(STHI) (µA) VZ(VDD) (V) VZ(VDD) (V) 12.5 12.0 12.0 6 11.5 11.5 5 0 10 IVDD (mA) 15 20 9 11.0 –50 –25 0 25 50 75 TEMPERATURE (°C) 436612 G01 100 3 –50 125 –25 0 25 50 75 TEMPERATURE (°C) 436612 G02 OUT Shunt Regulator vs OUT Current 125 436612 G03 OUT Shunt Regulator vs Temperature 5.9 100 VSS Current (Regulation AMP On) vs Temperature 7 75 6 50 IVSS(AMP) (µA) VZ(OUT) (V) VZ(OUT) (V) 5.8 5.7 5 25 5.6 5.5 0 5 10 IOUT (mA) 15 4 –50 20 0 25 50 75 TEMPERATURE (°C) 436612 G04 100 16 –40 12 –30 IGATE(CP) (µA) ∆VGATE (V) 8 –100 100 125 436612 G11 6 0 100 125 –20 –10 4 0 25 50 75 TEMPERATURE (°C) 0 25 50 75 TEMPERATURE (°C) Gate Current (Charge Pump On) vs Temperature –200 –25 –25 436612 G10 Gate Drive vs Gate Pull-Up Current –300 0 –50 0 –50 125 436612 G05 VSS Current (Charge Pump On) vs Temperature IVSS(CP) (µA) –25 0 –10 –20 IGATE (µA) –30 436612 G12 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 436612 G14 436612fe For more information www.linear.com/LTC4366 LTC4366 TYPICAL PERFORMANCE CHARACTERISTICS Base Shunt Regulator vs Base Current Gate Start-Up Current vs Temperature –12 Timer Pull-Up Current vs Temperature 7.0 –12 –10 ITIMER(UP) (µA) 6.5 VZ(BASE) (V) IGATE(ST) (µA) –10 –8 6.0 –6 –8 –6 –4 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 5.5 125 0 –100 436612 G15 –200 –300 IBASE (µA) –400 –4 –50 –500 100 125 436612 G18 Cool-Down Time vs Temperature 1.24 –3 0 25 50 75 TEMPERATURE (°C) 436612 G16 FB Regulation Threshold vs Temperature SD Pull-Up Current vs Temperature –25 16 14 1.23 tD(COOL) (s) ISD (µA) VFB(REG) (V) –2 12 10 1.22 –1 8 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 436612 G21 1.21 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 436612 G22 6 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 436612 G23 436612fe For more information www.linear.com/LTC4366 7 LTC4366 PIN FUNCTIONS BASE: Base Driver Output for External PNP Shunt Regulator. This pin is connected to the anode of an internal 6.2V Zener with the cathode tied to OUT. In cases where lower Zener (Z3) clamp current is desired but a large VSS resistor is prohibited, connect an external PNP base to this pin (PNP collector is grounded, emitter is tied to VSS). Tie this pin to VSS if unused. Exposed Pad: The exposed pad may be left open or connected to VSS. FB: Overvoltage Regulation Amplifier Feedback Input. Connect this pin to an external resistive divider from OUT to ground. The overvoltage regulation amplifier controls the gate of the external N-channel MOSFET to regulate the FB pin voltage at 1.23V below OUT. The overvoltage amplifier will activate a 200mA pull-down on the GATE pin during a fast overvoltage event. GATE: Gate Drive for External N-Channel MOSFET. During start-up an internal 7.5µA current source charges the gate of the external N-channel MOSFET from the VDD pin. Once the OUT voltage is above VSS by 4.75V, the charge pump will finish charging the GATE to 12V above OUT. During a fast overvoltage event, a 200mA pull-down current source between GATE and OUT is activated, followed by regulation of the GATE pin voltage by the overvoltage regulation amplifier. OUT: Charge Pump and Overvoltage Regulation Amplifier Supply Voltage. Supply input for floating circuitry powered from the MOSFET source. Once the OUT voltage is 4.75V (UVLO2) above VSS, the charge pump will turn on and draw power from this pin. When OUT exceeds 2.55V (UVLO1) it is used as a power supply and reference input for overvoltage regulation amplifier. This pin is clamped at 5.7V and requires a 0.22µF or greater bypass to the VSS pin. 8 SD: Shutdown Comparator Input. Tie to VDD if unused. Connect pin to a limited current pull down created by adding a resistor in series with an open-drain or open-collector pull-down transistor. Activating the external pull down overcomes the internal 1.6µA pull-up current source and allows the SD pin to cross the shutdown threshold. This threshold is defined as 1.5V below VDD with a 280mV hysteresis. To prevent false triggers this pin must stay below the threshold for 700µs to activate the shutdown state. The shutdown state lowers the total quiescent current (IVDD plus IOUT) below 20µA. This quiescent current does not include shunt current in the VDD, OUT and BASE regulators. After a fault on the LTC4366, putting the part in shutdown will clear the fault and allow operation to resume. Clearing the fault during the 9-second cool-down period will shorten the timeout for the LTC4366-2 (autoretry) version. TIMER: Timer Input. Leave this pin open for a 1µs overvoltage regulation period before fault off. Connect a capacitor between this pin and VSS to set a 311ms/µF duration for overvoltage regulation before the switch is turned off. The LTC4366-2 version will restart after a nine second cool-down period. VDD: Start-Up Supply. Supply input for 7.5µA start-up current source that charges the gate of the external N-channel MOSFET. Also provides supply for timer and logic circuits active when the external MOSFET is off. This pin is clamped at 12V above VSS. Do not bypass this pin with a capacitor. VSS: Device Return and Substrate. The capacitors on the TIMER and OUT pins should be returned to this pin. 436612fe For more information www.linear.com/LTC4366 LTC4366 SIMPLIFIED DIAGRAM Start Run Regulate RIN 7.5µA 1.23V 20µA CP Z1 12V Z3 5.7V + – – + Z3 5.7V RFB1 RFB2 RSS RSS RSS 436612 SD FUNCTIONAL DIAGRAM M1 VIN VOUT RG RIN CG VDD Z4 12V GATE 7.5µA OUT Z1 12V LOGIC SUPPLY D1 20µA VCC OUT CHARGE PUMP f = 2MHz UVLO2 4.75V UVLO1 2.55V VDD VCC 1.6µA + – SHUTDOWN 1.5V COMPARATOR + – SD 1.23V – + LOGIC AND TIMER VCC + – C1 FB RFB1 RFB2 OVERVOLTAGE AMPLIFIER 9µA TIMER COMPARATOR TIMER CT 1.8µA + – + – 2.8V OUT Z2 6.2V Z3 5.7V BASE VSS 436612 FD RSS 436612fe For more information www.linear.com/LTC4366 9 LTC4366 OPERATION The Simplified Diagram shows three states of operation: the start, run and regulate mode. Previous surge stopper parts are powered off the input supply, therefore the surge voltage is limited to the breakdown voltage of the input pins of the part. As demonstrated in run and regulate modes, the majority of this part is powered off the output, so the MOSFET isolates the surge from the power pins of the part. This allows surge voltages up to the breakdown of the external MOSFET. Once the OUT to VSS voltage exceeds the 2.55V UVLO1 threshold, the overvoltage amplifier is enabled. Next, the UVLO2 threshold of 4.75V is crossed and the charge pump turns on. The charge pump charges the GATE pin with 20µA to its final value 12V above OUT (clamped by Z4). This allows the capacitor between OUT and VSS to charge until clamped by Z3 to 5.7V. In this run mode the MOSFET is configured as a low resistance pass transistor with little voltage drop and power dissipation in the MOSFET. In the start mode a 15µA trickle current flows through RIN, half is used to charge the gate with the other half used as bias current. As the GATE pin charges, the external MOSFET brings up the OUT pin. This leads to the run mode where the output is high enough to become a supply voltage for the charge pump. The charge pump is then used to fully charge the gate 12V above the source. The powered up LTC4366 is now ready to protect the load against an overvoltage transient. The overvoltage regulation amplifier monitors the load voltage between OUT and ground by sensing the voltage on the FB pin with respect to the OUT pin (drop across RFB1). In an overvoltage condition the OUT rises until the amplifier drives the M1 gate to regulate and limit the output voltage. This is the regulate mode. With the output voltage equal to the input voltage, it is necessary to protect the load from an input supply overvoltage. In the regulate mode, the overvoltage regulation amplifier is referenced to the output through a 1.23V reference. If the voltage drop across the upper feedback resistor, RFB1, exceeds 1.23V the regulation amplifier pulls the gate down to regulate the RFB1 voltage back to 1.23V. Therefore, the output voltage is clamped by setting the proper ratio between RFB1 and RFB2. For example, if the output voltage is regulated at 100V then the voltage drop across the RFB2 is 98.77V. If the Zener Z3 is 5.7V then the voltage drop across RSS is 94.3V. Therefore, when the output is at a high voltage, the majority of the voltage is dropped across the two resistors RFB2 and RSS. This demonstrates how the LTC4366 floats up with the supply. The adjustable 3-terminal regulators, such as the LT®1085 and LM117, are also based on this idea. During regulation the excess voltage is dropped across the MOSFET. To prevent overheating the MOSFET, the LTC4366 limits the overvoltage regulation time using the TIMER pin. The TIMER pin is charged with 9µA until the pin exceeds 2.8V. At that point an overvoltage fault is set, the MOSFET is turned off, and the part enters a cool-down period of 9 seconds. The logic and timer block are active during cool down while the GATE pin is pulled to OUT. The latched-off version, LTC4366-1, will remain in fault until the SD pin is toggled low and then high. Once the fault is cleared, the GATE is permitted to turn the MOSFET on again. The auto-retry version, LTC4366-2, waits 9 seconds then clears the fault and restarts. The Functional Diagram shows the actual circuits. An external RIN resistor on the VDD pin powers up the 12V shunt regulator which then powers up logic supply, VCC. After verifying that the shutdown input is not active, the GATE pin is charged with a 7.5µA current from VDD. This is the start mode. 10 436612fe For more information www.linear.com/LTC4366 LTC4366 APPLICATIONS INFORMATION The typical LTC4366 application is a protected system that distributes power to loads safe from overvoltage transients. External component selection is discussed in the following sections. Dual Shunt Regulators The LTC4366 uses two shunt regulators coupled with the external voltage dropping resistors, RSS and RIN, to generate internal supply rails at the VDD and OUT pins. These shunt-regulated rails allow overvoltage protection from unlimited high voltage transients irrespective of the voltage rating of the LTC4366’s internal circuitry. At the beginning of start-up, during shutdown, or after an overvoltage fault, the GATE pin is clamped to the OUT pin thereby shutting off the MOSFET. This allows the VSS and OUT pins to be pulled to ground by output load and RSS. Under this condition the VDD pin is clamped with a 12V shunt regulator to VSS. The full supply voltage minus 12V is then impressed on the RIN resistor which sets the shunt current. The shunt current can be as high as 10mA which is several orders of magnitude higher than the typical 9µA VDD pin quiescent current. In normal operation the OUT voltage is equal to the input supply. With C1 fully charged IC1 is zero at this point. Under this condition the voltage between the OUT and VSS pins are clamped with a 5.7V shunt regulator. The input supply M1 FQA62N25C VIN 28V (18V DC TO 250V DC) RIN 324k R1 470k SD R2 100k VDD SD Q1 MMBT3904 C1 0.47µF GATE LTC4366-2 TIMER VSS Turn-On Sequence The voltage between the VDD and VSS pins is shunt regulated to 12V after ramping up the input supply. Next, the internally generated supply, VCC, produces a 30µs poweron-reset pulse which clears the fault latch and initializes internal latches. Next, the shutdown comparator determines if the SD pin is externally pulled low, thereby requesting a low bias current shutdown state. Otherwise the external MOSFET, M1, is allowed to turn on. Turning on the 7.5µA GATE pull-up current source from the VDD pin begins what can be described as a “bootstrapped” method for powering up the MOSFET gate. Once the GATE reaches the VDD pin voltage (minus a Schottky diode), the 7.5µA source loses voltage headroom and stops charging the GATE (middle of waveforms in Figure 2.). The bootstrap method relies on charging C1 to a sufficient voltage after GATE stops increasing. The voltage on C1 is then used as a supply for a charge pump that charges the gate to its final value 12V above OUT. C1 will discharge if the charge pump current exceeds the C1 charging current. If the voltage drops below 4.35V, the charge pump will pause allowing C1 to recharge. VOUT 1.5A (43V CLAMP) CG 10nF RG 10Ω voltage minus 5.7V is impressed on RSS. The RSS current is divided into three areas: the 5.7V shunt current, bias current between OUT and VSS and finally the RIN current. The 5.7V shunt current can be as high as 10mA which greatly exceeds the typical OUT (160µA) bias current. OUT FB BASE RFB1 12.4k RFB2 422k VGATE 10V/DIV CHARGE PUMP PAUSE VOUT 10V/DIV C1 RECHARGING CT 8.2nF RSS 46.4k 436612 F01 VC1 5V/DIV CHARGE PUMP STARTS C1 CHARGING 20ms/DIV Figure 1. Typical Application 436612 TA01b Figure 2. Turn-On Waveforms 436612fe For more information www.linear.com/LTC4366 11 LTC4366 APPLICATIONS INFORMATION Starting up with a supply voltage insufficient to charge C1 with large load current may result in overheating the MOSFET and subsequent damage. While the gate and output are ramping the drop across the MOSFET is the input supply minus the output. If the supply is lower than necessary to charge C1, then the output fails to ramp higher than the supply minus the threshold of the MOSFET. This 3V to 5V MOSFET drop with high load current will result in power dissipation without any protection or timeout limit. Overvoltage Fault The LTC4366 prevents an overvoltage on the input supply from reaching the load. Normally, the pass transistor is fully on, powering the load with very little voltage drop. As the input voltage increases the OUT voltage increases until it reaches the regulation point (VREG). From that point any further voltage increase is dropped across the MOSFET. Note the MOSFET is still on so the LTC4366 allows uninterrupted operation during a short overvoltage event. The VREG point is configured with the two FB resistors, RFB1 and RFB2. The regulation amplifier compares the FB pin to a threshold 1.23V below the OUT pin. During regulation the drop across RFB1 is 1.23V, while the remainder of the VREG voltage is dropped across RFB2. When the output is at the regulation point a timer is started to prevent excessive power dissipation in the MOSFET. Normally the TIMER pin is held low with a 1.8µA pulldown current. During regulation the TIMER pin charges with 9µA. If the regulation point is held long enough for the TIMER pin to reach 2.8V then an overvoltage fault is latched. The equation for setting the timer capacitor is: CT = 3.2 • t [nF / ms] 12 Depending on which version, the part will cool down and self start (LTC4366-2), or remain latched off until the SD pin activates a shutdown followed by a start-up command (LTC4366-1). The cool-down time is typically nine seconds which provides a very low pulsed power duty cycle. Starting up with an input supply overvoltage and full load current does increase the power dissipation in the MOSFET well beyond the case for an overvoltage surge. During the gate and output ramp up, the partial supply voltage (at full current) is dropped across the MOSFET. After start-up the normal overvoltage surge (with timeout) occurs before the shutting off the MOSFET. The Design Example section only considers the normal overvoltage surge for safe operating area (SOA) calculations for the MOSFET. Start-up into overvoltage will require additional SOA considerations. Shutdown The LTC4366 has a low current ( 0.22µF). In this example we choose CG to be 10nF which limits the inrush current to be 660mA for a 330µF CLOAD. VSS(MATCH) = threshold, 2.75V: If we desire a larger value of C1 then a lower size of RSS is required. A lower value for RSS is 48.7k, which calls out an RIN value of 309k and a max C1 value of 0.27µF. The next lower value of 46.4k with RVIN of 324k, results in the worst-case maximum C1 value of 0.49µF. A larger C1 increases circuit immunity to transients in exchange for slightly higher current. Therefore, a selection of components that allow a 0.47µF C1 is recommended. The lowered RSS value of 46.4k now considers the tolerances of all the components that set the C1 ramp rate to guarantee it charges to the 2.55V UVLO1 threshold before the OUT voltage exceeds the overvoltage threshold. Step 6: Determine RFB1, RFB2 The feedback resistors, RFB1 and RFB2, are chosen to regulate the overvoltage at 43V. One way to quickly choose these resistors is to assign 100µA or 1.2V across a 12.4k RFB1. RFB2 would need to drop the remainder of the regulated voltage. Dividing this remainder by 100µA yields the value for RFB2. In this example RFB2 drops 41.8V. When divided by 100µA it results in a 422k value. Step 7: Determine CT, R1 During an overvoltage the power dissipated in the MOSFET is dependent on the load current and the difference between the supply and regulated voltages. It is necessary to keep the device power in a safe range. In the power MOSFET data sheets there is a maximum safe operating curve displaying current versus drain to source voltage for a fixed pulsed time. Other pulsed time data from DC to 10µs are plotted on the one graph. The different lines of operation generally follow a constant power squared 436612fe For more information www.linear.com/LTC4366 LTC4366 APPLICATIONS INFORMATION times time or P2t. Knowing the power we then adjust the time using the timer capacitor to limit the P2t during overvoltage. In this example the MOSFET data sheet has a 6400W2s P2t for a 10ms single pulse. In order to limit the SD pin current (10mA max) a collector resistor, R1, in series with Q1 is required. The maximum value for this resistor is around 5M. This requirement occurs when the pull-down is required to sink 1.6µA from SD and VDD is clamped at 12V. High valued resistors are susceptible to leakage currents so we chose a 470k resistor for R1. Resistor R2 provides ESD protection for Q1’s base. In this application 250V minus 43V is applied across the MOSFET at 3A. If the power is applied for less than 16.5ms then MOSFET P2t limit is not exceeded: The gate resistor RG limits the parasitic trace capacitance on M1’s gate node that could lead to parasitic MOSFET self-oscillation. The recommended value for RG is 10Ω. P = (250V – 43V) • 3A = 621W P2t = (621W)2 • 16.5ms = 6363W2s Prior to the moment when the output is regulated at 43V, the output is ramping from 28V to 43V. This ramp time is based on the 20µA gate current charging the 10nF capacitor. Using the equation for ramp time: ∆t = High Voltage Application In Figure 7 the circuit accepts 110V AC (rectified to 160V) and protects the load from accidental connection to 220V AC by limiting the output to less than 200V. The circuit has a 100V to 800V VIN operating range where the FET breakdown voltage limits the maximum input voltage. The C1 is set to 0.47µF to provide a bypass for the charge pump that is large enough to provide good noise immunity from outside voltage transients. The timer capacitor is sized to give a 1ms overvoltage regulation time that keeps the P2t below the 640W2s specified for this MOSFET. CG • ∆V 10nF • 15V = = 7.5ms IG 20µA To be safe we set the overvoltage time to 10ms. We set the regulation time to be 2.5ms (the remainder of the 10ms overvoltage time minus the ramp time). In this example it is assumed the 250V overvoltage is a constant DC voltage for 10ms. This duration exceeds Mil-Std-1275 which specifies a 70µs surge to 250V that decays in 1.6ms. Using the following equation (based on charging with 9µA) to set the CT: CT = IT • ∆t 2.5ms = 9µA • ≈ 8.2nF ∆V 2.8V M1 IXTH12N100L VIN 160V (RECTIFIED 110V AC) 100V TO 800V VOUT 0.5A (200V CLAMP) CG 2nF RG 10Ω RIN 4.64M R1 470k SD R2 100k Q1 BF722 VDD C1 0.47µF GATE LTC4366-2 SD TIMER VSS OUT FB BASE RFB1 12.4k RFB2 2M CT 3.3nF DANGER! Lethal Voltages Present RSS 412k 436612 F07 Figure 7. Rectified 110V AC Supply Protected from 220V AC 436612fe For more information www.linear.com/LTC4366 19 LTC4366 APPLICATIONS INFORMATION 28V Vehicle Application The circuit in Figure 8 adds reverse voltage protection to the standard 28V application shown in Figure 6. There are three modes to this circuit: pass FET On when the input is 18V to 41V, clamping the output to 43V when more than 43V appears at the input and finally reverse voltage protection when up to –250V DC is present at the input. The reverse voltage protection consists of the circuitry inside the dotted box in Figure 8. When a positive voltage is first applied to the input, D3 and the forward biased base-collector junction of Q2 allow the gate of M2 to follow the input voltage minus a two diode drop. During this condition the body diode of M2 is used to transmit power to the LTC4366. Once the LTC4366 is powered up it fully enhances the gate of M1 and M2 (via D1). The M1 and M2 pass FETs then provide a low impedance path to the load. In an overvoltage condition, D1 blocks excessive positive voltage from the input supply passing to the GATE pin of the LTC4366. D4 eliminates current flow through R6 when the input is positive while D3 prevents emitter base breakdown of Q2 when the input is powering up. VIN 18V TO 41V (±250V DC) REVERSE VOLTAGE PROTECTION During negative input voltages Q2 turns on when current from R6 (via D4) develops a forward diode drop on R5. Q2 then holds the gate of M2 at the input voltage which turns M2 off. This blocks negative input voltages from reaching M1 and the load. D2 prevents damage to the LTC4366’s GATE pin by clamping it at ground when the M2’s gate is negative. Low Voltage Application The circuit on the last page (Surge Protected Automotive Supply) starts up with minimum input voltage of 9V. In order to successfully start up at 9V and clamp the output voltage at 18V for input voltages up to 100V the value of RSS has to be small (1.91k). The FET used in this case has a 3V threshold to ease the start-up requirements. The timer capacitor is sized to give a 2.5ms overvoltage regulation time that keeps the P2t below the 420W2s specified for this MOSFET. M2 FDB33N25 M1 FQA62N25C Q2 MMBT3904 D3 BAV3004W D4 BAV3004W R5 470k R4 270k D1 BAV3004W CG 10nF RG 10Ω RIN 324k VOUT 1.5A (43V CLAMP) C1 0.47µF D2 BAV3004W R1 470k R6 270k SD R2 100k Q1 MMBT3904 VDD GATE SD LTC4366-2 TIMER VSS OUT FB BASE RFB1 12.4k RFB2 422k CT 8.2nF RSS 46.4k 436612 F08 Figure 8. 28V Vehicle Application with Reverse Voltage Protection 20 436612fe For more information www.linear.com/LTC4366 LTC4366 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 0.40 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 – 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) 1.95 BSC TS8 TSOT-23 0710 REV A NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 436612fe For more information www.linear.com/LTC4366 21 LTC4366 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DDB Package 8-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1702 Rev B) 0.61 ±0.05 (2 SIDES) 0.70 ±0.05 2.55 ±0.05 1.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.20 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (2 SIDES) R = 0.115 TYP 5 R = 0.05 TYP 0.40 ±0.10 8 2.00 ±0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 0.56 ±0.05 (2 SIDES) 0.200 REF 0.75 ±0.05 0 – 0.05 4 0.25 ±0.05 1 PIN 1 R = 0.20 OR 0.25 × 45° CHAMFER (DDB8) DFN 0905 REV B 0.50 BSC 2.15 ±0.05 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 22 436612fe For more information www.linear.com/LTC4366 LTC4366 REVISION HISTORY REV DATE DESCRIPTION A 1/12 Added Patents Pending statement PAGE NUMBER 1 Revised Figure 4 in Applications Information section 11 B 2/12 Removed reference to overcurrent faults under MOSFET Selection 13 Fixed orientation of M2 in Figure 8 18 C 8/12 Updated Shutdown current from