LTC5587
6 GHz RMS Power Detector
with Digital Output
FEATURES
DESCRIPTION
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The LTC®5587 is a 10MHz to 6GHz, low power monolithic
precision RMS power detector with an integrated 12-bit
serial analog-to-digital converter (ADC). The RMS detector uses a proprietary technique to accurately measure the
RF power of modulated signals with crest-factor as high
as 12dB. For an input frequency of 2.14GHz the detection
range is from –34dBm to 6dBm. The serial digital output
of the detector is a 12-bit word value that is directly proportional to the RF signal power measured in dBm. The
LTC5587 is suitable for precision power measurement
for a wide variety of RF standards, including LTE, WiMAX,
W-CDMA, TD-SCDMA, CDMA, CDMA2000, EDGE, GSM,
etc. The DC output of the detector is connected in series
with an on-chip 300Ω resistor to the analog output pin
(VOUT). This enables further filtering of the output modulation ripple using an off-chip capacitor before analog-todigital conversion. The ADC features include no data latency,
no missing codes, and a sampling rate of up to 500ksps. A
dedicated external reference pin (VREF) can be tied to VDD
or other suitable low-impedance voltage reference to set the
ADC full-scale input voltage range. The ADC also features
an automatic power down after each conversion making
the LTC5587 ideal for low-power applications.
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Frequency Range: 10MHz to 6GHz
Accurate Power Measurement of High Crest Factor
(Up to 12dB) Waveforms
40dB Log Linear Dynamic Range
Exceptional Accuracy Over Temperature
Single-Ended RF Input
0.014dB/Bit (12-Bit) ADC Resolution (VREF = 1.8V)
ADC Sample Rate Up to 500ksps
SPI/MICROWIRE Serial I/O
Compatible with 1V to 3.6V Digital Logic
Fast Response Time: 1μs Rise, 8μs Fall
Low Power: 3mA at 3.3V and 500ksps
Small 3mm × 3mm 12-pin DFN Package
APPLICATIONS
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LTE, WiMAX, W-CDMA, TD-SCDMA, CDMA,
CDMA2000, EDGE, GSM
Pico-Cells, Femto-Cells RF Power Control
Wireless Repeaters
CATV/DVB Transmitters
MIMO Wireless Access Points
Portable RMS Power Measurement
Antenna Monitor
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
BLOCK DIAGRAM
Linearity Error vs RF Input Power
2140MHz Modulated Waveforms
3
4
EXPOSED
PAD
150kHz LPF
7
RF
RMS
DETECTOR
VOUT
OUTPUT
BUFFER
3
11
VDD
300Ω
S/H
12-BIT ADC
OVDD
THREE-STATE
SERIAL OUTPUT
PORT
SDO
SCK
BIAS
6
CSQ
9
EN
TIMING
LOGIC
8
VCC
5
GND
10
TA = 25°C
2
CONV
1
2
12
VREF
5587 BD
LINEARITY ERROR (dB)
13
1
0
–1
–2
CW
WCDMA, UL
WCDMA DL 1C
WCDMA DL 4C
LTE DL 1C
LTE DL 4C
–3
–35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
5
10
5587 G12
5587f
1
LTC5587
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VDD, VCC Voltage, (Note 12) ........................................4V
OVDD Supply Voltage ......................Min(VDD + 0.3V, 4V)
Maximum Input Signal Power (Average) .............15dBm
Maximum Input Signal Power (Peak)...................25dBm
DC Voltage at RF .......................................... –0.3V to 2V
VOUT Voltage ................................... –0.3V to VDD + 0.3V
EN Voltage ...................................... –0.3V to VDD + 0.3V
SDO, SCK, CONV Voltage ................ –0.3V to VDD + 0.3V
VREF Voltage.................................... –0.3V to VDD + 0.3V
Power Dissipation ...............................................100mW
Maximum Junction Temperature, TJMAX ............... 150°C
Operating Temperature Range (Note 2)....–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
TOP VIEW
SDO
1
SCK
2
OVDD
3
VOUT
4
GND
5
CSQ
6
12 CONV
11 VDD
13
GND
10 VREF
9 EN
8 VCC
7 RF
DFN PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 76°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
Caution: This part is sensitive to electrostatic discharge. It
is very important that proper ESD precautions be observed
when handling the LTC5587.
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC5587IDD#PBF
LTC5587IDD#TRPBF
LFRH
12-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V, fSMPL =
fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. Test circuit is shown in Figure 1.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RF Input
Input Frequency Range (Note 4)
Input Impedance
10 to 6000
MHz
205||1.6
Ω||pF
–34 to 6
dBm
fRF = 450MHz
RF Input Power Range
Externally Matched to 50Ω Source
Linear Dynamic Range, CW (Note 3)
±1dB Linearity Error
40
dB
Linear Dynamic Range, CDMA (Note 3)
±1dB Linearity Error; CDMA 4-Carrier
40
dB
73
LSB/dB
–42
dBm
±1
dB
Output Slope
Logarithmic Intercept (Note 5)
Output Variation vs Temperature
Normalized to Output at 25°C; PIN = –34dBm to 6dBm
5587f
2
LTC5587
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V, fSMPL =
fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. Test circuit is shown in Figure 1.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Variation vs Temperature
Normalized to Output at 25°C; PIN = –27dBm to –10dBm
±0.5
dB
Deviation from CW Response;
PIN = –34dBm to 0dBm
TETRA π/4 DQPSK
CDMA 4-Carrier 64-Channel Fwd 1.23Mcps
±0.1
±0.5
dB
dB
2nd Order Harmonic Distortion
At RF Input; CW Input; PIN = 0dBm
–57
dBc
3rd Order Harmonic Distortion
At RF Input; CW Input; PIN = 0dBm
–52
dBc
–34 to 6
dBm
fRF = 880MHz
RF Input Power Range
CW Input: Externally Matched to 50Ω Source
Linear Dynamic Range, CW (Note 3)
±1dB Linearity Error
40
dB
Linear Dynamic Range, EDGE (Note 3)
±1dB Linearity Error; EDGE 3π/8-Shifted 8PSK
40
dB
Output Slope
73
LSB/dB
Logarithmic Intercept (Note 5)
–42
dBm
Output Variation vs Temperature
Output Variation vs Temperature
Deviation from CW Response;
PIN = –34dBm to 6dBm
Normalized to Output at 25°C; PIN = –34dBm to 6dBm
Normalized to Output at 25°C; PIN = –27dBm to –10dBm
±1
dB
±0.5
dB
EDGE 3π/8 Shifted 8PSK
±0.1
dB
fRF = 2140MHz
RF Input Power Range
CW Input: Externally Matched to 50Ω Source
Linear Dynamic Range, CW (Note 3)
±1dB Linearity Error
43
dB
Linear Dynamic Range, WCDMA (Note 3)
±1dB Linearity Error; 4-Carrier WCDMA
37
dB
Output Slope
73
LSB/dB
Logarithmic Intercept (Note 5)
–42
dBm
Output Variation vs Temperature
Normalized to Output at 25°C; PIN = –34dBm to 6dBm
Output Variation vs Temperature
Normalized to Output at 25°C; PIN = –27dBm to –10dBm
WCDMA 1-Carrier Uplink
WCDMA 64-Channel 4-Carrier Downlink
Deviation from CW Response;
PIN = –34dBm to –4dBm
–34 to 6
dBm
±1
dB
±0.5
dB
±0.1
±0.5
dB
dB
fRF = 2600MHz
RF Input Power Range
CW Input: Externally Matched to 50Ω Source
Linear Dynamic Range, CW (Note 3)
±1dB Linearity Error
Output Slope
Logarithmic Intercept (Note 5)
–34 to 6
dBm
40
dB
73
LSB/dB
–42
dBm
±1
dB
Output Variation vs Temperature
Normalized to Output at 25°C; PIN = –34dBm to 6dBm
Normalized to Output at 25°C; PIN = –27dBm to –10dBm
±0.5
dB
Deviation from CW Response;
PIN = –34dBm to 2dBm
WiMax OFDMA Preamble
WiMax OFDM Burst
±0.1
±0.5
dB
dB
Output Variation vs Temperature
fRF = 3500MHz
RF Input Power Range
CW Input: Externally Matched to 50Ω Source
Linear Dynamic Range, CW (Note 3)
±1dB Linearity Error
–30 to 6
dBm
36
dB
Output Slope
73
LSB/dB
Logarithmic Intercept (Note 5)
–40
dBm
5587f
3
LTC5587
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V, fSMPL =
fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. Test circuit is shown in Figure 1.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Variation vs Temperature
Normalized to Output at 25°C; PIN = –30dBm to 6dBm
±1
dB
Output Variation vs Temperature
Normalized to Output at 25°C; PIN = –27dBm to –10dBm
WiMax OFDMA Preamble
WiMax OFDM Burst
±0.5
dB
±0.1
±0.5
dB
dB
Output DC Voltage at VOUT
No Signal Applied to RF Input
180
mV
Output Impedance
Internal Series Resistor Allows for Off-Chip Filter Cap
300
Ω
5/5
mA
Deviation from CW Response;
PIN = –34dBm to –4dBm
Detector Analog Output
Output Current Sourcing/Sinking
Rise Time (1000pF on VOUT)
0.2V to 1.6V, 10% to 90%, fRF = 2140MHz
1
μsec
Fall Time (1000pF on VOUT)
1.6V to 0.2V, 10% to 90%, fRF = 2140MHz
8
μsec
Power Supply Rejection Ratio (Note 6)
For CW RF Input Over Operating Input Power Range
49
dB
Integrated Output Voltage Noise
1 to 6.5 kHz Integration BW, PIN = 0dBm CW
150
μVRMS
Peak-to-Peak ADC Output Noise
CFILT = 1000pF, PIN = 0dBm CW
11
LSB
ADC Resolution
ADC Resolution
(No Missing Codes)
l
Differential Linearity Error
EN = 0V, Voltage on VOUT = 0V to 1.8V, VREF = 1.8V
l
Measurement Resolution
1LSB = VREF/(4096 • 32mV/dB), VREF = 1.8V
12
Bits
±0.25
±1
0.014
LSB
dB/Bit
ADC Digital Timing
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
fSAMPL(MAX)
Maximum Sampling Frequency
(Notes 8, 9)
l
fSCK
Shift Clock Frequency
(Notes 8, 9)
l
tSCK
Shift Clock Period
l
tTHROUGHPUT
Minimum Throughput Time, tACQ + tCONV
l
tACQ
Acquisition Time
l
0.5
μs
tCONV
Conversion Time
l
1.5
μs
t1
Minimum Positive CONV Pulse Width
(Note 8)
l
1.5
μs
t2
SCK↑ Setup Time After CONV↓
(Note 8)
l
16
ns
500
UNITS
kHz
50
20
MHz
ns
2
μs
t3
SDO Enabled Time After CONV↓
(Notes 8, 9)
l
16
ns
t4
SDO Data Valid Access Time After SCK↓
(Notes 8, 9, 10)
l
8
ns
t5
SCK Low Time
(Note 7)
l
40%
tSCK
t6
SCK High Time
(Note 7)
l
40%
tSCK
t7
SDO Data Valid Hold Time After SCK↓
(Notes 8, 9, 10)
l
4
t8
SDO Into Hi-Z State Time After CONV↑
(Notes 8, 9)
ns
6
ns
ADC Digital Inputs and Outputs
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
SCK, CONV Logic High Input
l
VIL
SCK, CONV Logic Low Input
l
IIH
Logic High Input Current
SCK, CONV = VDD
l
IIL
Logic Low Input Current
SCK, CONV = 0V
l
TYP
MAX
2
–2.5
UNITS
V
0.8
V
2.5
μA
μA
5587f
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LTC5587
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V, fSMPL =
fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. Test circuit is shown in Figure 1.
SYMBOL
PARAMETER
CIN
SCK, CONV Input Capacitance
CONDITIONS
MIN
TYP
MAX
VOH
SDO Logic High Output
ISOURCE = 200μA
l
VOL
SDO Logic Low Output
ISINK = 200μA
l
0.2
V
IOZ
Hi-Z Output Leakage
CONV = VDD
l
±3
μA
COZ
Hi-Z Output Capacitance
CONV = VDD
4
pF
ISOURCE
SDO Source Current
SDO Connected to GND = 0V
–10
mA
ISINK
SDO Sink Current
SDO Connected to VDD
10
mA
2
UNITS
pF
VDD – 0.2
V
Detector Enable (EN) Low = Off, High = On
PARAMETER
CONDITIONS
MIN
EN Input High Voltage (On)
l
EN Input Low Voltage (Off)
l
TYP
MAX
2
UNITS
V
0.3
V
Enable Pin Input Current
EN = 3.3V
25
μA
Turn ON Time; CW RF Input
VOUT within 10% of Final Value; PIN = 0dBm
1
μs
Turn OFF Time; CW RF Input
VOUT < 0.18V; PIN = 0dBm
8
μs
Power Supply
OVDD Supply Voltage
l
1
3.3
VDD
V
VDD Supply Voltage
l
2.7
3.3
3.6
V
VREF Reference Voltage
l
1.4
VDD + 0.05
V
Should Be Equal to VDD
l
2.7
3.3
3.6
V
Total Supply Current
No RF Input Signal, ADC Operational at 500ksps
No RF Input Signal, ADC Sleep-Mode
l
l
3
1.4
4
2.5
mA
mA
Shutdown Current
EN = 0.3V, CONV = 3.3V, ADC Sleep-Mode
0.2
10
μA
VCC Supply Voltage
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. The maximum RF input power rating is guaranteed
by design and engineering characterization, but not production tested.
Note 2: The LTC5587 is guaranteed to be functional over the operating
temperature range from –40°C to 85°C.
Note 3: The linearity error is calculated by the difference between the
incremental slope of the output and the average output slope from –20dBm
to 0dBm. The dynamic range is defined as the range over which the
linearity error is within ±1dB.
Note 4: An external capacitor at the CSQ pin should be used for input
frequencies below 250MHz. Without this capacitor, lower frequency
operation results in excessive RF ripple in the output voltage.
Note 5: Logarithmic intercept is an extrapolated input power level from
the best fitted log-linear straight line, where the converted output code is
0LSB.
Note 6: PSRR determined as the dB value of the change in converted
output voltage over the change in VCC supply voltage at a given CW input
power level.
Note 7: Guaranteed by design not subject to test.
Note 8: Guaranteed by characterization. All input signals are specified with
tR = tF = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 9: All timing specifications given are with a 10pF capacitance load.
With a capacitance load greater than this value, a digital buffer or latch
must be used.
Note 10: The time required for the output to cross the VIH or VIL voltage.
Note 11: When pins VOUT and VREF are taken below GND or above VDD,
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below GND or above VDD without latchup.
Note 12: The VDD supply voltage can be the same as VCC and the pins can
share a common bypass capacitor of 2.2μF.
5587f
5
LTC5587
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V,
fSMPL = fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. VOUT = ADC Output (LSB) • 1.8/4096. Test circuit is shown in Figure 1.
Output Voltage vs Frequency
1.2
1.0
2
0.8
0.6
0.4
1
0
10MHz
450MHz
880MHz
2.14GHz
2.6GHz
3.5GHz
5.8GHz
–1
–2
0.2
0
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
5
–3
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
10
Output Voltage and Linearity
Error at 450MHz
2.5
25°C
85°C
– 40°C
1.5
1.4
1.0
1.2
0.5
1.0
0
0.8
–0.5
0.6
–1.0
0.4
–1.5
0.2
–2.0
0
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
5
2
2
1
0
85°C
2.5
–40°C
1.2
0.5
1.0
0
0.8
–0.5
0.6
–1.0
0.4
–1.5
0.2
–2.0
–2.5
5
10
5587 G07
VARIATION (dB)
1.0
–1
TA = 25°C
CW
TETRA
CDMA 4C
–1
–2
5
–3
–35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
10
2
2
85°C
–40°C
–1
–2
–3
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
10
Linearity Error vs RF Input Power
880MHz Modulated Waveforms
3
0
5
5587 G06
3
1
6
0
2.0
1.5
5
1
Output Voltage Temperature
Variation from 25°C at 880MHz
1.4
0
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
2
3
4
FREQUENCY (GHz)
5587 G05
LINEARITY ERROR (dB)
VOUT (V)
1.6
1
Linearity Error vs RF Input Power
450MHz Modulated Waveforms
3
–3
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
10
25°C
85°C
– 40°C
0
5587 G03
3
Output Voltage and Linearity
Error at 880MHz
1.8
–30
10
–2
–2.5
5
L1= 3.3nH,C1=1.8pF
L1= 1.5nH,C1=1.8pF
L1= 0, C1=1.5pF
L1= 0, C1=0.7pF
L1= 0, C1=0
–25
5587 G04
2.0
–20
2.0
LINEARITY ERROR (dB)
VOUT (V)
1.6
–15
Output Voltage Temperature
Variation from 25°C at 450MHz
VARIATION (dB)
1.8
–10
5587 G02
5587 G01
2.0
TA = 25°C
–5
RETURN LOSS (dB)
VOUT (V)
1.4
10MHz
450MHz
880MHz
2.14GHz
2.6GHz
3.5GHz
5.8GHz
TA = 25°C
LINEARITY ERROR(dB)
1.6
TA = 25°C
RF Input Return Loss vs Frequency
0
LINEARITY ERROR(dB)
1.8
Linearity Error vs Frequency
3
LINEARITY ERROR (dB)
2.0
TA = 25°C
CW
EDGE
1
0
–1
–2
5
10
5587 G08
–3
–35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
5
10
5587 G09
5587f
6
LTC5587
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V,
fSMPL = fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. VOUT = ADC Output (LSB) • 1.8/4096. Test circuit is shown in Figure 1.
Output Voltage and Linearity
Error at 2140MHz
3
2
2
1.0
1.2
0.5
1.0
0
0.8
–0.5
0.6
–1.0
0.4
–1.5
0.2
–2.0
85°C
0
–40°C
–1
–2
–2.5
5
1
–3
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
10
2.5
25°C
85°C
– 40°C
0.5
1.0
0
0.8
–0.5
3
2
2
0.6
–1.0
0.4
–1.5
0.2
–2.0
0
85°C
–40°C
–1
–2.5
–3
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
5587 G13
2.5
25°C
85°C
– 40°C
1.5
1.4
1.0
1.2
0.5
1.0
0
0.8
–0.5
0.6
–1.0
0.4
–1.5
0.2
–2.0
0
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
–2.5
5
10
5587 G16
CW
WiMax OFDM PREAMBLE
WiMax OFDM BURST
WiMax OFDMA PREAMBLE
–3
–35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
10
3
2
2
0
85°C
–40°C
–1
–2
–3
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
10
5587 G17
TA = 25°C
1
0
–1
–2
5
10
Linearity Error vs RF Input Power
3.5GHz Modulated Waveforms
3
1
5
5587 G15
2.0
LINEARITY ERROR (dB)
VOUT (V)
1.6
–1
Output Voltage Temperature
Variation from 25°C at 3500MHz
VARIATION (dB)
1.8
0
5587 G14
Output Voltage and Linearity
Error at 3500MHz
2.0
5
TA = 25°C
1
–2
–2
10
10
Linearity Error vs RF Input Power
2.6GHz Modulated Waveforms
3
1
5
5587 G12
LINEARITY ERROR (dB)
1.0
1.2
VARIATION (dB)
1.5
5
CW
WCDMA, UL
WCDMA DL 1C
WCDMA DL 4C
LTE DL 1C
LTE DL 4C
–3
–35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
10
2.0
1.4
0
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
–1
Output Voltage Temperature
Variation from 25°C at 2600 MHz
LINEARITY ERROR (dB)
VOUT (V)
1.6
0
5587 G11
Output Voltage and Linearity
Error at 2600MHz
1.8
5
TA = 25°C
1
–2
5587 G10
2.0
LINEARITY ERROR (dB)
1.5
1.4
0
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
3
2.0
LINEARITY ERROR (dB)
VOUT (V)
1.6
2.5
25°C
85°C
– 40°C
Linearity Error vs RF Input Power
2140MHz Modulated Waveforms
LINEARITY ERROR (dB)
1.8
VARIATION (dB)
2.0
Output Voltage Temperature
Variation from 25°C at 2140MHz
CW
WiMax OFDMA PREAMBLE
WiMax OFDM BURST
–3
–35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
5
10
5587 G18
5587f
7
LTC5587
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V,
fSMPL = fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. VOUT = ADC Output (LSB) • 1.8/4096. Test circuit is shown in Figure 1.
Output Voltage and Linearity
Error at 5800MHz
3
2
2
0.5
1.0
0
0.8
–0.5
0.6
–1.0
0.4
–1.5
0.2
–2.0
LINEARITY ERROR (dB)
1.0
1
85°C
0
–40°C
–1
–2
–2.5
5
30
28
26
5
fSMPL = 500kHz
4
30
20
3
2
1
10
28
29
30
31
32
SLOPE (mV/dB)
33
85°C
25°C
–40°C
0
2.7 2.8 2.9
0
6
34
3 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
5587 G24
Logarithmic Intercept vs
Frequency
5587 G25
Logarithmic Intercept Distribution
vs Temperature
50
PERCENTAGE DISTRIBUTION (%)
TA = 25°C
–35
–40
–45
Total Supply Current vs RF Input
Power and Sample Rate
16
TA = –40°C
TA = 25°C
TA = 85°C
40
10
Supply Current vs Supply Voltage
TA = –40°C
TA = 25°C
TA = 85°C
40
5
5587 G21
5
5587 G23
LOGARITHMIC INTERCEPT (dBm)
–3
–35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
10
SUPPLY CURRENT (mA)
PERCENTAGE DISTRIBUTION (%)
SLOPE (mV/dB)
32
–30
–1
Slope Distribution vs
Temperature
50
2
3
4
FREQUENCY (GHz)
0
5587 G20
TA = 25°C
1
1
CW
WiMax OFDM BURST
–3
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
10
Slope vs Frequency
0
TA = 25°C
–2
5587 G19
34
LINEARITY ERROR (dB)
1.5
1.2
5
3
2.0
1.4
0
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
Linearity Error vs RF Input Power
5.8GHz Modulated Wavefroms
TA = 25°C
14
TOTAL SUPPLY CURRENT (mA)
1.6
VOUT (V)
2.5
25°C
85°C
– 40°C
1.8
VARIATION (dB)
2.0
Output Voltage Temperature
Variation from 25°C at 5800MHz
30
20
10
500kHz
12 100kHz
200kHz
10
8
6
4
2
0
–50
0
1
2
3
4
FREQUENCY (GHz)
5
6
5587 G26
–48
–47 –46 –45 –44 –43 –42
LOGARITHMIC INTERCEPT (dBm)
–41
5587 G27
0
–30 –25 –20 –15 –10 –5 0
5
RF INPUT POWER (dBm)
10
15
5587 G28
5587f
8
LTC5587
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = VDD = OVDD = 3.3V, VREF = 1.8V, EN = 3.3V,
fSMPL = fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise noted. VOUT = ADC Output (LSB) • 1.8/4096. Test circuit is shown in Figure 1.
Output Voltage and Linearity
Error vs VCC at 2140MHz
2.5
1.6
1.5
1.4
1.0
1.2
0.5
1.0
0
0.8
–0.5
0.6
–1.0
0.4
–1.5
0.2
0
–40 –35 –30 –25 –20 –15 –10 –5 0
RF INPUT POWER (dBm)
2.7V
3.6V
5
5000
EN
PULSE
OFF
4000
5
TA = 25°C
EN PULSE ON
PIN = 10dBm
3000
PIN = –10dBm
2000
PIN = –20dBm
–15
PIN = –30dBm
–2.0
0
–2.5
10
0
–20
10 20 30 40 50 60 70 80 90 100
TIME (μsec)
5587 G33
Output Transient Response with
RF Pulse and EN Pulse
PIN = –10dBm
–10
PIN = –20dBm
1000
–15
ADC OUTPUT (LSB)
–5
PIN = 0dBm
2000
4000
0
RF PULSE ENABLE (V)
ADC OUTPUT (LSB)
RF PULSE ON
PIN = 10dBm
3000
5000
5
TA = 25°C
RFAND EN
PULSE
OFF RF AND EN PULSE ON
0
0
PIN = 10dBm
3000
–5
PIN = 0dBm
PIN = –10dBm
2000
–10
PIN = –20dBm
1000
–15
PIN = –30dBm
PIN = –30dBm
0
5
TA = 25°C
RF PULSE AND ENABLE (V)
4000
–10
1000
Output Transient Response
RF
PULSE
OFF
–5
PIN = 0dBm
5587 G29
5000
0
ENABLE (V)
2.0
ADC OUTPUT (LSB)
TA = 25°C
1.8
LINEARITY ERROR (dB)
VOUT (V)
2.0
Output Transient Response with
CW RF and EN Pulse
–20
10 20 30 40 50 60 70 80 90 100
TIME (μsec)
5587 G32
0
0
–20
10 20 30 40 50 60 70 80 90 100
TIME (μsec)
5587 G31
5587f
9
LTC5587
PIN FUNCTIONS
SDO (Pin 1): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB first. The data stream consists of 12 bits
of conversion data followed by trailing zeros.
VCC (Pin 8): Detector Power Supply Voltage, 2.7V to 3.6V.
Can be connected to the VDD voltage supply. VCC should
be bypassed with a 1μF ceramic capacitor. If VCC and VDD
are tied together, then bypass with 2.2μF.
SCK (Pin 2): Shift Clock Input. The SCK serial clock synchronizes the serial data transfer. SDO data transitions
on the falling edge of SCK.
EN (Pin 9): Detector Enable. A logic low or no-connect
on the enable pin shuts down the detector. A logic high
enables the detector. An internal 500k pull-down resistor
ensures the detector is off when the pin is left floating.
OVDD (Pin 3): ADC Output Driver Supply Voltage, 1.0V
to 3.6V. OVDD should be bypassed with a 1μF ceramic
capacitor. OVDD can be driven separately from VDD and
OVDD can be higher than VDD.
VREF (Pin 10): ADC Reference Input Voltage. VREF defines
the input span of the ADC, 0V to VREF. The VREF range
is 1.4V to VDD. Bypass to ground with a 1μF ceramic
capacitor.
VOUT (Pin 4): Detector Analog Voltage Output. An internal
series 300Ω resistor at the detector output allows for
simple R-C filtering with a capacitor placed on this pin to
GND. A 1000pF capacitor is recommended for a corner
frequency of 500kHz.
VDD (Pin 11): ADC Power Supply Voltage, 2.7V to 3.6V.
VDD should be bypassed with a 1μF ceramic capacitor.
CONV (Pin 12): Convert Input. This active high signal starts
a conversion on the rising edge. The ADC automatically
powers down after conversion. A logic low on this input
enables the SDO pin, allowing the data to be shifted out.
CSQ (Pin 6): Optional low-frequency range extension
capacitor for frequencies below 250MHz. Connect 0.01μF
from this pin to ground for 10MHz operation.
GND (Pin 5, Exposed Pad Pin 13): Ground. For highfrequency operation, backside ground connection should
have a low-inductance connection to the pcb ground using
many through-hole vias. See layout information.
RF (Pin 7): RF Input Voltage. Should be externally
DC-blocked. A capacitor of 1000pF is recommended. This
pin has an internal 205Ω termination.
BLOCK DIAGRAM
13
4
EXPOSED
PAD
150kHz LPF
7
RF
RMS
DETECTOR
11
VOUT
OUTPUT
BUFFER
3
VDD
300Ω
S/H
12-BIT ADC
OVDD
THREE-STATE
SERIAL OUTPUT
PORT
SDO
SCK
BIAS
6
CSQ
9
EN
TIMING
LOGIC
8
VCC
5
GND
10
CONV
1
2
12
VREF
5587 BD
5587f
10
LTC5587
TIMING DIAGRAMS
SDO Into Hi-Z State After CONV Rising Edge
t8
CONV
1.6V
Hi-Z
SDO
5587 TD01
SDO Data Valid Hold Time After SCK Falling Edge
t7
SCK
SDO
1.6V
VIH
VIL
5587 TD02
SDO Data Valid Access Time After SCK Falling Edge
t4
SCK
1.6V
VIH
SDO
VIL
5587 TD03
5587f
11
LTC5587
TEST CIRCUIT
OVDD
VDD
VREF
VCC
0.018˝
C5 1μF
SLK
RF
GND
0.062˝
CONV
SDO
EF = 4.4
1
2
SDO
CONV
SLK
VDD
C7
1μF
11
LTC5587
10
OVDD
VREF
4
9
VOUT
EN
5
8
VCC
GND
6
7
RF
CSQ
GND
13
C3
0.01μF
DC
GND
0.018˝
C8
1μF
12
3
VOUT
REF DES
C4
1000pF
VALUE
SIZE
PART NUMBER
1μF
0402
AVX 0402ZG105ZAT2A
C3
0.01μF
0402
AVX 04023C103KAT2A
C2, C4
1000pF
0402
68Ω
0402
C5, C6, C7, C8
R1
EN
C6 1μF
L1
1.5nH
RF
C2
1000pF
R1
68Ω
FREQUENCY
RANGE
C1
1.8pF
5587 F01
RFIN MATCH
L1
C1
0.04 to 1.8GHz
3.3nH
1.8pF
AVX 04025C102KAT2A
1.75 to 2.2GHz
1.5nH
1.8pF
CRCW040268R1FKED
2.4 to 2.9GHz
0
1.5pF
2.8 to 3.8GHz
0
0.7pF
4.5 to 6.0GHz
0
0
Figure 1. Evaluation Circuit Schematic
Figure 2. Evaluation Circuit Board
5587f
12
LTC5587
APPLICATIONS INFORMATION
Operation
The LTC5587 combines a proprietary high-speed power
detector with an internal 150kHz lowpass averaging filter
and a true 12-bit successive approximation ADC with a
serial output interface. It can accurately measure the RMS
power of high crest-factor modulated RF signals. The
output voltage of the RF power detector is converted to
a 12-bit digital word that is directly proportional to the
average RF input power in dBm. The part can be operated from a single supply or dedicated supplies, allowing
the user to select a specific voltage range for the ADC
conversion in addition to interfacing with 1.8V, 2.5V, or
3V digital systems.
Evaluation
Figure 1 shows the simplified evaluation circuit schematic,
and Figure 2 shows the associated board artwork. To ensure proper operation, good grounding practice should be
followed in the board layout, with liberal placement of vias
under the exposed pad of the package and around signal
and digital lines. The evaluation board shown in Figure 2
contains additional support circuitry not shown in Figure 1
that includes an optional 3.3V regulator for the VDD, OVDD,
and VCC supplies and an optional 1.8V regulator for the VREF
reference. This onboard reference provides good accuracy
(less than ±5mV) over temperature, contributing less than
±0.1dB error to the ADC output. To evaluate the digital
output, the QuickEval PC-based software can be used with
the DC590B USB controller interface board. This board
contains a generic USB to serial peripheral interface (SPI)
controller. A 14-pin ribbon cable connects the evaluation
board to the DC590B board. The DC590B allows the evaluation at approximately a 200Hz sample rate (fSMPL). (See
http://cds.linear.com/docs/Reference%20Design/dc590B.
pdf). For higher sample rates the digital I/O pins can be
accessed directly on the board. Contact LTC Applications
for more information on higher sample rate evaluation.
RF Input Matching
The input resistance is about 205Ω. Input capacitance
is 1.6pF. The impedance vs frequency of the RF input is
detailed in the following table.
Table 1. RF Input Impedance
S11
FREQUENCY
(MHz)
INPUT
IMPEDANCE (Ω)
MAG
ANGLE (°)
10
203.3-j1.4
0.605
–0.7
50
201.8-j7.0
0.605
–3.7
100
197.2-j13.7
0.606
–7.3
200
161.9-j25.8
0.608
–14.6
400
142.5-j43.6
0.614
–28.9
500
125.3-j48.5
0.619
–35.8
800
88.0-j60.4
0.636
–55.6
900
79.2-j62.6
0.643
–61.8
1000
71.8-j64.3
0.650
–67.7
1500
46.6-j68.8
0.685
–94.3
2000
31.1-j69.2
0.715
–116
2100
29.9-j69.0
0.721
–119.9
2500
22.4-j66.8
0.739
–134.1
3000
15.3-j60.7
0.756
–149.6
3500
9.9-j47.3
0.768
–163.2
4000
6.6-j16.9
0.779
–175.5
5000
9.8-j51.7
0.787
162.1
6000
18.5-j69.4
0.792
141.4
A shunt 68Ω resistor can be used to provide a broadband
match at low frequencies up to 1GHz and from 4.5GHz to
6GHz. As shown in Figure 3, a nominal broadband input
match can be achieved up to 1.8GHz by using an LC matching circuit consisting of a series 3.3nH inductor (L1) and
a shunt 1.8pF capacitor (C1). This match will maintain a
return loss of about 10dB across the band. For matching
at higher frequencies, L1 and C1 values are listed in the
table of Figure 1. The input reflection coefficient referenced
to the RF input pin with no external components is shown
on the smith chart in Figure 4. Alternatively, it is possible
to match using an impedance transformation network by
omitting R1 and transforming the 205Ω input to 50Ω. This
narrow band matching will improve sensitivity up to about
6dB max, and the dynamic range remains the same. For
example: by omitting R1 and setting L1 = 1.8nH and C1 =
3pF, a 2:1 VSWR match can be obtained from 1.95GHz to
2.36GHz with a sensitivity improvement of 5dB.
5587f
13
LTC5587
APPLICATIONS INFORMATION
The RF input DC-blocking capacitor (C2) and CSQ bias
decoupling capacitor (C3), can be adjusted for low-frequency operation. For input frequencies down to 10MHz,
0.01μF is needed at CSQ. For frequencies above 250MHz,
the on-chip 20pF decoupling capacitor is sufficient and
CSQ may be eliminated as desired. The DC-blocking capacitor can be as large as 2200pF for 10MHz operation
or 100pF for 2GHz operation. A DC-blocking capacitor
larger than 2200pF results in an undesirable RF pulse
response on the falling edge due to the rectifier action of
the diode limiter/ESD protection at the RF pin. Therefore,
the recommended value for C2 for general applications
is conservatively set at 1000pF.
Filter Capacitor
The interface of the VOUT pin of the LTC5587 is shown in
Figure 5. It includes a push-pull output stage with a series
300Ω resistor. The detector output stage is capable of
sourcing and sinking 5mA of current. The VOUT pin can be
shorted to GND or VCC (or VDD whichever is lower) without
damage, but going beyond the VCC + 0.5V or VDD + 0.5V
and alternatively going beyond GND – 0.5V may result in
damage as the internal ESD protection diodes will start
to conduct excessive current.
VCC
LTC5587
40μA
VCC
C3
0.01μF
6
RFIN
(MATCHED)
CSQ
300Ω
INPUT
20pF
C2
1000pF
L1
LTC5587
CFILT
RF
R1
68Ω
C1
VOUT
FILTERED
4
VDD
205Ω
7
VOUT
12-BIT ADC
S/H
5587 F05
5587 F03
Figure 5. Simplified Schematic of the Detector Analog Output
Figure 3. Simplified Schematic of the RF Input Interface
6GHz
The residual ripple due to RF modulation can be reduced
by adding an external capacitor, CFILT (C4 on evaluation
circuit schematic) to the VOUT pin to form a simple RC
lowpass filter. The internal 300Ω resistor in series with
the output pin enables filtering of the output signal with
just the addition of CFILT. The filter –3dB corner frequency,
fC, can be calculated with the following equation:
fC(–3dB) = 1/(2 • π • 300 • CFILT)
4GHz
10MHz
3GHz
500MHz
900MHz
1.8GHz
5587 F04
with fC in Hz and CFILT in F. Since the bandwidth of the
detected signal is effectively limited by the internal 150kHz
filter, a choice of CFILT = 1000pF sets the ADC –3dB input
bandwidth at 530kHz and does not affect the residual
modulation ripple much. CFILT has a small effect on ADC
sampling accuracy. For example, when the sample rate of
the ADC is changed from 25ksps to 500ksps, the output
value changes less than 0.2dB with any choice of CFILT.
Figure 4. Input Reflection Coefficient
5587f
14
LTC5587
APPLICATIONS INFORMATION
Figure 6 shows the effect of the external filter capacitor on
the residual ripple level for a 4-carrier WCDMA downlink
signal at 2.14GHz with –10dBm. Adding a 0.047μF capacitor to the output decreases the peak-to-peak output ripple
from 150LSB to about 60LSB.
3200
2500
3100
2000
3000
1500
2900
1000
2800
500
2700
0
2600
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TIME (msec)
0
OUTPUT RIPPLE PEAK-TO-PEAK (dB)
3000
9
RIPPLE
RISE
FALL
8
1000
TA = 25°C
7
100
6
5
4
3
10
2
RISE TIME AND FALL TIME (μs)
3500
3400
NO CAP
0.047μF 3300
TA = 25°C
ADC OUTPUT (LSB)
ADC OUTPUT (LSB)
4000
Figure 8 shows how the peak-to-peak ripple decreases with
increasing external filter capacitance value. Also shown is
how the RF pulse response will have longer rise and fall
times with the addition of this lowpass filter cap.
1
1
0
0.001
0.01
0.1
1
EXTERNAL CAPACITOR (μF)
5587 F08
5587 F06
Figure 7 shows the transient response for a 2.6GHz WiMax
signal with preamble and burst ripple reduced by a factor of three using a 0.047μF external filter capacitor. The
average power in the preamble section is –10dBm, while
the burst section has 3dB lower average power. With the
capacitor, the ripple in the preamble section is about 0.5dB
peak to peak. The modulation used was OFDM (WiMax
802.16-2004) MMDS band 1.5MHz BW, with 256 size FFT
and 1 burst at QPSK ¾.
3500
TA = 25°C
ADC OUTPUT (LSB)
3000
NO CAP
0.047μF
2500
Figure 8. Residual Ripple, Output Transient Times for RF Pulse
with WCDMA 4-Carrier Modulation vs External Filter Capacitor C4
Figure 9 shows the rise time and fall time is a strong
function of the RF input power when the filter capacitor
is not present.
9
TA = 25°C
8
RISE TIME AND FALL TIME (μs)
Figure 6. Residual Ripple, Output Transient Response for RF
Pulse with WCDMA 4-Carrier Modulation
FALL TIME
7
6
5
4
3
2
2000
1
1500
0
–30
RISE TIME
–25
–20
–15
–10
–5
0
5
INPUT POWER (dBm)
1000
5587 F09
500
0
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
TIME (msec)
2
Figure 9. RF Pulse Response Rise Time and Fall Time vs RF
Input Power
5587 F07
Figure 7. Residual Ripple for 2.6GHz WiMax OFDM 802.16-2004
5587f
15
LTC5587
APPLICATIONS INFORMATION
For a given RF modulation type, WCDMA for example,
the internal 150kHz filter provides nominal filtering of the
residual ripple level. Additional external filtering happens
in the log-domain, which introduces a systematic log-error in relation to the signal’s crest factor as shown in the
following equation in dB1:
The output voltage noise density and integrated noise are
shown respectively in Figures 11 and 12 for various input
power levels. The noise is a strong function of input level
and there is roughly a 10dB improvement in the output
noise level for an input level of 0dBm versus no input.
Error|dB = 10 • log10(r + (1-r)10 –CF/10) – CF • (r-1)
Figure 10 shows the output AC modulation ripple as a
function of modulation difference frequency for a 2-tone
input signal at 2140MHz with –10dBm input power. The
resulting deviation in the output voltage of the detector
shows the effect of the internal 150kHz filter.
0
TA = 25°C
25
–0.5
20
–1.0
15
–1.5
10
–2.0
5
–2.5
0
0.001
DEVIATION OF OUTPUT VOLTAGE (dB)
OUTPUT AC RIPPLE (dB)
30
–3.0
0.01
TA = 25°C
NOISE VOLTAGE (μVRMS / Hz)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.1
0dBm
–10dBm
–20dBm
–30dBm
NO RF INPUT
1
100
10
FREQUENCY (kHz)
1000
5587 F11
Figure 11. Output Voltage Noise Density
2.0
1.8
INTEGRATED NOISE (mVRMS)
Where CF is the crest factor and r is the duty cycle of the
measurement (or number of measurements made at the
peak envelope divided by the total number of periodic
measurements in the measurement period). It is important
to note that the CF refers to the 150kHz low-pass filtered
envelope of the signal. The error will depend on the statistics and bandwidth of the modulation signal in relation to
the internal 150kHz filter. For example: simulations have
shown for the case of WCDMA that it is possible to set
the external filter capacitor corner frequency at 15kHz and
only introduce an error less than 0.1dB.
4.0
TA = 25°C
1.6
1.4
1.2
0dBm
–10dBm
–20dBm
–30dBm
NO RF INPUT
1.0
0.8
0.6
0.4
0.2
0
0.1
1
100
10
FREQUENCY (kHz)
1000
5587 F12
Figure 12. Integrated Output Voltage Noise
0.1
10
1
2-TONE FREQUENCY SEPARATION (MHz)
5587 F10
Figure 10. Output DC Voltage Deviation and Residual Ripple vs
2-Tone Separation Frequency
1. Steve Murray, “Beware of Spectrum Analyzer Power Averaging Techniques,” Microwaves
& RF, Dec. 2006.
5587f
16
LTC5587
APPLICATIONS INFORMATION
The total noise at the ADC output is dominated by the
output noise of the detector, and the sampling noise
is insignificant. The peak-to-peak output noise is also
almost independent of the sample rate. Figure 13 shows
the peak-to-peak noise at the ADC output as a function
of the RF input level for a CW RF input. Increasing CFILT
from 1000pF to 0.01μF gives roughly 2x to 3x lower noise
over input power.
0.6
TA = 25°C
fSMPL = 500ksps 0.525
40
30
0.45
25
0.375
20
0.3
CFILT = 1000pF
15
0.225
10
0.15
CFILT = 0.01μF
0.075
5
0
–40
ADC OUTPUT NOISE (dBP-P)
ADC OUTPUT NOISE (P-P LSB)
35
0
10
0
–30
–20
–10
RF INPUT POWER (dBm)
5587 F13
Figure 13. Peak-to-Peak Noise at ADC Output vs RF Input Power
Data Transfer
A rising CONV edge starts a conversion and disables SDO.
After the conversion, the ADC automatically goes into
sleep mode, drawing only leakage current. CONV going
low enables SDO and clocks out the MSB bit, B11. SCK
then synchronizes the data transfer with each bit being
transmitted on the falling SCK edge and can be captured
on the rising SCK edge. After completing the data transfer,
if further SCK clocks are applied with CONV low, SDO will
output zeros indefinitely (see Figure 14). For example,
16-clocks at SCK will produce the 12-bit data and four
trailing zeros on SDO.
Sleep Mode
The LTC5587 ADC enters sleep mode to save power after
each conversion if CONV remains high. In sleep mode, all
bias currents are shut down and only leakage currents
remain (about 0.1μA). The sample-and-hold is in hold
mode while the ADC is in sleep mode. The ADC returns
to sample mode after the falling edge of CONV during
power-up.
Exiting Sleep Mode and Power-Up Time
Serial Interface
The LTC5587 communicates with microcontrollers, DSPs
and other external circuitry via a 3-wire interface. Figure 14
shows the operating sequence of the serial interface.
By taking CONV low, the ADC powers up and acquires an
input signal completely after the acquisition time (tACQ).
After t ACQ, the ADC is ready to perform a conversion again
by a rising edge on CONV.
BY TAKING CONV LOW, THE DEVICE POWERS UP
AND ACQUIRES AN INPUT ACCURATELY AFTER tACQ
CONV
tCONV
SCK
SDO
SLEEP MODE
RECOMMENDED HIGH OR LOW
Hi-Z STATE
t2
t6
1
t3
B11
2
3
4
t4
B10
B9
10
11
12
t7
B3
B2
t8
B1
B0*
5587 F14
(MSB)
t1
9
t5
tACQ
tTHROUGHPUT
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
Figure 14. LTC5587 Serial Interface Timing Diagram
5587f
17
LTC5587
APPLICATIONS INFORMATION
Conversion Range
Detector Enable Pin
The VREF pin defines the full-scale range of the ADC. The
reference voltage can range from VDD down to 1.4V. If
the difference between the input voltage on the VOUT pin
and GND exceeds VREF, the output code will stay fixed at
all ones, and if this difference goes below 0V, the output
code will stay fixed at all zeros. Figure 15 shows the ideal
input/output characteristics for the ADC. The code transitions occur midway between successive integer LSB
values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, …, FS – 1.5LSB).
The output code is straight binary with 1LSB = VREF/4096.
Using the onboard 1.8V reference on the evaluation board,
the conversion range can be easily calculated between LSB
and dBm. For an analog output slope of 32mV/dB, we can
calculate the total 40dB range is equivalent to 2912.7LSB’s
at the ADC output:
A simplified schematic of the EN pin is shown in Figure 16.
To enable the LTC5587 detector it is necessary to put
greater than 2V on this pin. To disable or turn off the
detector, this voltage should be below 0.3V. At an enable
voltage of 3.3V the pin draws roughly 20μA. If the EN pin
is not connected, the detector circuitry is disabled through
an internal 500k pull-down resistor.
It is important that the voltage applied to the EN pin
should never exceed VCC by more than 0.5V. Otherwise,
the supply current may be sourced through the upper ESD
protection diode connected at the EN pin.
40dB = (40dB • 4096LSB • 32mV/dB)/1.8V = 2912.7LSB
LTC5587
VCC
111...111
UNIPOLAR OUTPUT CODE
111...110
9
EN
300k
300k
500k
000...001
000...000
0
5587 F16
1LSB
INPUT VOLTAGE (V)
FS – 1LSB
5587 F15
Figure 15. ADC Transfer Characteristics
Figure 16. Enable Pin Simplified Schematic
5587f
18
LTC5587
PACKAGE DESCRIPTION
DD Package
12-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1725 Rev A)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
2.38 ±0.05
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.45 BSC
2.25 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ±0.10
(4 SIDES)
R = 0.115
TYP
7
0.40 ± 0.10
12
2.38 ±0.10
1.65 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
6
0.200 REF
1
0.23 ± 0.05
0.45 BSC
0.75 ±0.05
2.25 REF
(DD12) DFN 0106 REV A
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
5587f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC5587
TYPICAL APPLICATION
10MHz to 6GHz Infrastructure Power
Amplifier Level Control
RF COUPLER
RFIN
RFOUT
POWER AMP
3.3VDC
CMATCH
50Ω
DIGITAL
POWER
CONTROL
1
2
1μF
1000pF
0.01μF
SDO
CONV
SCK
VDD
12
1μF
11
LTC5587
10
OVDD
VREF
4
9
VOUT
EN
5
8
VCC
GND
6
7
RF
CSQ
GND
13
3
LMATCH
1μF
1000pF
68Ω
5587 TA01a
RELATED PARTS
PART NUMBER DESCRIPTION
RF Power Detectors
LTC5505
RF Power Detectors with >40dB Dynamic Range
LTC5507
100kHz to 1000MHz RF Power Detector
LTC5508
300MHz to 7GHz RF Power Detector
LTC5509
300MHz to 3GHz RF Power Detector
LTC5530
300MHz to 7GHz Precision RF Power Detector
LTC5531
300MHz to 7GHz Precision RF Power Detector
LTC5532
300MHz to 7GHz Precision RF Power Detector
LT5534
50MHz to 3GHz Log RF Power Detector with 60dB
Dynamic Range
LTC5536
Precision 600MHz to 7GHz RF Power Detector with
Fast Comparator Output
LT5537
Wide Dynamic Range Log RF/IF Detector
LT5538
75dB Dynamic Range 3.8GHz Log RF Power
Detector
LTC5582
60dB Dynamic Range RMS Detector
LT5581
6GHz RMS Power Detector, 40dB Dynamic Range
Infrastructure
LT5568
700MHz to 1050MHz High Linearity Direct
Quadrature Modulator
LT5572
1.5GHz to 2.5GHz High Linearity Direct Quadrature
Modulator
LT5579
1.5GHz to 3.8GHz High Linearity Upconverting
Mixer
LTC5598
5MHz to 1600MHz High Linearity Direct Quadrature
Modulator
LTC5588-1
200MHz to 6GHz Very High Linearity Direct
Quadrature Modulator
COMMENTS
300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply
100kHz to 1GHz, Temperature Compensated, 2.7V to 6V Supply
44dB Dynamic Range, Temperature Compensated, SC70 Package
36dB Dynamic Range, Low Power Consumption, SC70 Package
Precision VOUT Offset Control, Shutdown, Adjustable Gain
Precision VOUT Offset Control, Shutdown, Adjustable Offset
Precision VOUT Offset Control, Adjustable Gain and Offset
±1dB Output Variation over Temperature, 38ns Response Time, Log Linear
Response
25ns Response Time, Comparator Reference Input, Latch Enable Input,
–26dBm to +12dBm Input Range
Low Frequency to 1GHz, 83dB Log Linear Dynamic Range
±0.8dB Accuracy Over Temperature
40MHz to 10GHz, ±0.5dB Accuracy Over Temperature
±1dB Accuracy Over Temperature, Log Linear Response, 1.4mA at 3.3V
22.9dBm OIP3 at 850MHz, –160.3dBm/Hz Noise Floor, 50Ω, 0.5VDC Baseband
Interface, 3-Ch CDMA2000 ACPR = –71.4dBc at 850MHz
21.6dBm OIP3 at 2GHz, –158.6dBm/Hz Noise Floor, High-Ohmic 0.5VDC Baseband
Interface, 4-Ch W-CDMA ACPR = –67.7dBc at 2.14GHz
27.3dBm OIP3 at 2.14GHz, 9.9dB NF, 2.6dB Conversion Gain, –35dBm LO Leakage
27.7dBm OIP3 at 140MHz, –161.2dBm/Hz Noise Floor, 0.5VDC Baseband Interface,
–55dBm LO Leakage and 50.4dBc Image Rejection at 140MHz
30dBm OIP3 at 2.14GHz, Optimizable to 35dBm, –160.5dBm/Hz Output Noise Floor,
0.5VDC Baseband Interface
5587f
20 Linear Technology Corporation
LT 0810 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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