LTC5800-IPR
SmartMesh IP Network Manager
2.4GHz 802.15.4e Wireless Manager
Network Features
Description
Complete Radio Transceiver, Embedded Processor,
and Networking Software for Forming a Self-Healing
Mesh Network
n SmartMesh® Networks Incorporate:
n Time Synchronized Network-Wide Scheduling
n Per-Transmission Frequency-Hopping
n Redundant Spatially Diverse Topologies
n Network-Wide Reliability and Power Optimization
n NIST Certified Security
n SmartMesh Networks Deliver:
n >99.999% Network Reliability Achieved in the
Most Challenging RF Environments
n Sub 50µA Routing Nodes
n Compliant to 6LoWPAN Internet Protocol (IP) and
IEEE 802.15.4e Standards
SmartMesh IP™ wireless sensor networks are self managing, low power internet protocol (IP) networks built from
wireless nodes called motes. The LTC®5800-IPR is the IP
Manager-on-Chip™ in the Eterna®* family of IEEE 802.15.4e
system-on-chip (SoC) solutions, featuring a highly integrated, low power radio design by Dust Networks® as well
as an ARM Cortex-M3 32-bit microprocessor running
Dust’s embedded SmartMesh IP networking software.
n
LTC5800-IPR Features
Provides Network Management Functions and
Security Capabilities
n Manages Networks of Up to 100 nodes
n Sub 1mA Average Current Consumption Enables
Battery-Powered Network Management
n PCB Module Versions Available (LTP™5901/2-IPR)
with RF Modular Certifications
n 72-Lead 10mm × 10mm QFN Package
n
Based on the IETF 6LoWPAN and IEEE-802.15.4e standards, the LTC5800-IPR SoC runs SmartMesh IP network
management software to monitor and manage network
performance and provide a data ingress/egress point via
a UART interface. The SmartMesh IP software provided
with the LTC5800-IPR is fully tested and validated, and is
readily configured via a software Application Programming
Interface. With Dust’s time-synchronized SmartMesh IP
networks, all motes in the network may route, source or
terminate data, while providing many years of batterypowered operation.
SmartMesh IP motes deliver a highly flexible network
with proven reliability and low power performance in an
easy-to-integrate platform.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Dust, Dust Networks, SmartMesh and
Eterna are registered trademarks and LTP, the Dust Networks logo SmartMesh IP and Manageron-Chip are trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217,
7791419, 7881239, 7898322, 8222965.
* Eterna is Dust Networks’ low power radio SoC architecture.
Typical Application
20MHz
LTC5800-IPM
ANTENNA
20MHz
LTC5800-IPR
ANTENNA
IN+
LTC2379-18 SPI
SENSOR
µCONTROLLER
UART
UART
IN–
HOST
APPLICATION
32kHz
32kHz
5800IPR TA01
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LTC5800-IPR
Table of Contents
Network Features........................................... 1
LTC5800-IPR Features..................................... 1
Typical Application ......................................... 1
Description.................................................. 1
SmartMesh Network Overview............................ 3
Absolute Maximum Ratings............................... 4
Order Information........................................... 4
Recommended Operating Conditions.................... 4
Pin Configuration........................................... 4
DC Characteristics.......................................... 5
Radio Specifications....................................... 5
Radio Receiver Characteristics........................... 6
Radio Transmitter Characteristics........................ 6
Digital I/O Characteristics................................. 7
Temperature Sensor Characteristics..................... 7
System Characteristics.................................... 7
UART AC Characteristics................................... 8
TIMEn AC Characteristics................................. 9
RADIO_INHIBIT AC Characteristics...................... 9
Flash AC Characteristics.................................. 10
Flash SPI Slave AC Characteristics..................... 10
External Bus AC Characteristics......................... 11
Typical Performance Characteristics................... 13
Pin Functions............................................... 18
2
Operation................................................... 23
Power Supply...........................................................23
Supply Monitoring And Reset.................................. 24
Precision Timing...................................................... 24
Application Time Synchronization........................... 24
Time References...................................................... 24
Radio.......................................................................25
UARTS.....................................................................25
CLI UART................................................................. 27
Autonomous Mac.................................................... 27
Security................................................................... 27
Temperature Sensor................................................ 28
Radio Inhibit............................................................ 28
Flash Programming................................................. 28
Flash Data Retention................................................ 28
Networking..............................................................29
State Diagram..........................................................30
Applications Information................................. 32
Regulatory And Standards Compliance................... 32
Soldering Information.............................................. 32
Related Documentation................................... 33
Package Description...................................... 34
Revision History........................................... 35
Typical Application........................................ 36
Related Parts............................................... 36
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SmartMesh Network Overview
A SmartMesh network consists of a self-forming multi-hop,
mesh of nodes, known as motes, which collect and relay
data, and a network manager that monitors and manages
network performance and security, and exchanges data
with a host application.
SmartMesh networks communicate using a time slotted
channel hopping (TSCH) link layer, pioneered by Dust
Networks. In a TSCH network, all motes in the network
are synchronized to within less than a millisecond. Time
in the network is organized into time slots, which enable
collision-free packet exchange and per-transmission
channel-hopping. In a SmartMesh network, every device
has one or more parents (e.g., mote 3 has motes 1 and 2
as parents) that provide redundant paths to overcome
communications interruption due to interference, physical
obstruction or multi-path fading. If a packet transmission
fails on one path, the next retransmission may try on a
different path and different RF channel.
The network manager uses health reports to continually
optimize the network to maintain >99.999% data reliability
even in the most challenging RF environments.
The use of TSCH allows SmartMesh devices to sleep inbetween scheduled communications and draw very little
power in this state. Motes are only active in time slots
where they are scheduled to transmit or receive, typically
resulting in a duty cycle of 85°C or Temperature < –40°C
4
MIN
2.1
TYP
MAX
UNITS
3.76
V
250
mV
10
90
% RH
–8
–2
8
2
°C/Min
°C/Min
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DC Characteristics
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. VSUPPLY = 3.6V unless otherwise noted.
OPERATION/STATE
CONDITIONS
MIN
TYP
MAX
UNITS
Power-On Reset
During Power-On Reset, Maximum 750µs + VSUPPLY Rise Time
from 1V to 1.9V
12
mA
Doze
RAM On, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All
Data and State Retained, 32.768kHz Reference Active
1.2
µA
Deep Sleep
RAM On, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All
Data and State Retained, 32.768kHz Reference Inactive
0.8
µA
In-Circuit Programming
RESETn and FLASH_P_ENn Asserted, IPCS_SCK at 8MHz
20
mA
Peak Operating Current
8dBm
0dBm
System Operating at 14.7MHz, Radio Transmitting, During Flash
Write. Maximum Duration 4.33ms
30
26
mA
mA
Active
ARM Cortex M3, RAM and Flash Operating, Radio and All Other
Peripherals Off. Clock Frequency of CPU and Peripherals Set to
7.3728MHz, VCORE = 1.2V
1.3
mA
Flash Write
Single Bank Flash Write
3.7
mA
Flash Erase
Single Bank Page or Mass Erase
2.5
mA
Radio Tx
+0dBm (LTC5800I)
+0dBm (LTC5800H)
+8dBm (LTC5800I)
+8dBm (LTC5800H)
Current With Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
5.4
5.6
9.7
9.9
mA
mA
mA
mA
Radio Rx
LTC5800I
LTC5800H
Current With Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
4.5
4.7
mA
mA
Radio Specifications
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
2.4000
MAX
2.4835
UNITS
GHz
Frequency Band
l
Number of Channels
l
Channel Separation
l
5
MHz
l
2405 + 5 •(k – 11)
MHz
l
250
kbps
Channel Center Frequency
Where k = 11 to 25, as Defined by IEEE.802.15.4
Modulation
IEEE 802.15.4 Direct Sequence Spread Spectrum (DSSS)
Raw Data Rate
Antenna Pin ESD Protection
HBM Per JEDEC JESD22-A114F
Range (Note 4)
Indoor
Outdoor
Free Space
25°C, 50% RH, 2dBi Omni-Directional Antenna, Antenna 2m
Above Ground
15
±1000
V
100
300
1200
m
m
m
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LTC5800-IPR
Radio Receiver Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
Receiver Sensitivity
Packet Error Rate (PER) = 1% (Note 5)
–93
MAX
UNITS
dBm
Receiver Sensitivity
PER = 50%
–95
dBm
Saturation
Maximum Input Level the Receiver Will Properly Receive Packets
0
dBm
Adjacent Channel Rejection (High Side)
Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz
Above the Desired Signal, PER = 1% (Note 5)
22
dBc
Adjacent Channel Rejection (Low Side)
Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz
Below the Desired Signal, PER = 1% (Note 5)
19
dBc
Alternate Channel Rejection (High Side)
Desired Signal at –82dBm, Alternate Modulated Channel 10MHz
Above the Desired Signal, PER = 1% (Note 5)
40
dBc
Alternate Channel Rejection (Low Side)
Desired Signal at –82dBm, Alternate Modulated Channel 10MHz
Below the Desired Signal, PER = 1% (Note 5)
36
dBc
Second Alternate Channel Rejection
Desired Signal at –82dBm, Second Alternate Modulated Channel
Either 15MHz Above or Below, PER = 1% (Note 5)
42
dBc
Co-Channel Rejection
Desired Signal at –82dBm, Undesired Signal is an 802.15.4
Modulated Signal at the Same Frequency, PER = 1%
–6
dBc
LO Feed Through
–55
dBm
Frequency Error Tolerance (Note 6)
±50
ppm
Symbol Error Tolerance
Received Signal Strength Indicator (RSSI)
Input Range
±50
ppm
–90 to –10
dBm
RSSI Accuracy
±6
dB
RSSI Resolution
1
dB
Radio Transmitter Characteristics
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VSUPPLY = 3.6V unless otherwise noted.
PARAMETER
CONDITIONS
Output Power
High Calibrated Setting
Low Calibrated Setting
Delivered to a 50Ω load
Spurious Emissions
Conducted Measurement with a 50Ω Single-Ended Load,
8dBm Output Power. All Measurements Made with Max Hold.
RF Implementation Per Eterna Reference Design
30MHz to 1000 MHz
1GHz to 12.75GHz
2.4GHz ISM Upper Band Edge (Peak)
2.4GHz ISM Upper Band Edge (Average)
2.4GHz ISM Lower Band Edge
Harmonic Emissions
2nd Harmonic
3rd Harmonic
6
MIN
TYP
MAX
UNITS
8
0
dBm
dBm
RBW = 120kHz, VBW = 100Hz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 3MHz
RBW = 1MHz, VBW = 10Hz
RBW = 100kHz, VBW = 100kHz
105°C
can be approximated by calculating the dimensionless
acceleration factor using the following equation.
Flash Programming
TUSE = is the specified temperature retention in °C
This product is provided without software programmed into
the device. OEMs will need to program software images
during development and manufacturing. Eterna’s software
images are loaded via the in-circuit programming control
system (IPCS) SPI interface. Sequencing of RESETn and
FLASH_P_ENn, as described in the Flash SPI Slave A/C
Characteristics table, places Eterna in a state emulating a
serial flash to support in-circuit programming. Hardware
and software for supporting development and production programming of devices is described in the Eterna
Serial Programmer Guide. The serial protocol, SPI, and
timing parameters are described in the Flash SPI Slave
A/C Characteristics table.
28
AF = e
⎡ ⎛ Ea ⎞ ⎛
⎞⎤
1
1
–
⎢ ⎜⎝ ⎟⎠ • ⎜
⎟⎠ ⎥
T
T
+273
+273
k
⎝ USE
STRESS
⎣
⎦
where:
AF = acceleration factor
Ea = activation energy = 0.6eV
k = 8.625 • 10–5eV/°K
TSTRESS = actual storage temperature in °C
Example: Calculate the effect on retention when storing
at a temperature of 125°C.
TSTRESS = 125°C
TUSE = 85°C
AF = 7.1
So the overall retention of the flash would be degraded
by a factor of 7.1, reducing data retention from 20 years
at 85°C to 2.8 years at 125°C.
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LTC5800-IPR
Operation
Networking
The LTC5800-IPR network manager provides the ingress/
egress point at the wired to wireless mesh network
boundary via the API UART interface. The complexity of
the mesh network management is handled entirely within
the embedded software, which also provides dynamic
network optimization, deterministic power management,
intelligent routing, and configurable bandwidth allocation
while achieving carrier class data reliability and low power
operation.
Dynamic Network Optimization
Dynamic network optimization allows Eterna to address the
changing RF requirements in harsh environments resulting in a network that is continuously self-monitoring and
self-adjusting. The manager performs dynamic network
optimization based upon periodic reports on network health
and link quality that it receives from the network motes.
The manager uses this information to provide performance
statistics to the application layer and proactively solve
connectivity problems in the network. Dynamic network
optimization not only maintains network health, but also
allows Eterna to deliver deterministic power management.
One of the key advantages of SmartMesh networking solutions is the network manager is aware of and tracking
the success or failure of every packet transaction, so not
only can the network be optimized, but the solution can
be rigorously tested to produce a system solution with
better than 99.999% reliability.
Deterministic Power Management
Deterministic power management balances traffic in the
network by diverting traffic around heavily loaded motes
(for example, motes with high reporting rates). In doing so, it reduces power consumption for these motes
and balances power consumption across the network.
Deterministic power management provides predictable
maintenance schedules to prevent down time and lower
the cost of network ownership. When combined with field
devices using Eterna’s industry-leading low power radio
technology, deterministic power management enables
over a decade of battery life for network motes.
Intelligent Routing
Intelligent routing provides each packet with an optimal
path through the network. The shortest distance between
two points is a straight line, but in RF the quickest path is
not always the one with the fewest hops. Intelligent routing
finds optimal paths by considering the link quality (one
path may lose more packets than another) and the retry
schedule, in addition to the number of hops. The result
is reduced network power consumption, elimination of
in-network collisions, and unmatched network scalability
and reliability.
Configurable Bandwidth Allocation
SmartMesh networks provide configurations that enable
users to make bandwidth and latency versus power tradeoffs both network wide and on a per device basis. This
flexibility enables solutions that tailored to the application
requirements, such as request/response, fast file transfer, and alerting. Relevant configuration parameters are
described in the SmartMesh IP User’s Guide. The Design
trade-offs between network performance and current
consumption are supported via the SmartMesh Power
and Performance Estimator.
IP Manager Options
The IP Manager can operate with or without external
SRAM, as described in the Eterna Integration Guide. When
used without external SRAM, the IP manager is limited to
managing networks of 32 motes or fewer and is limited to
a maximum packet throughput of 24 packets per second.
With external SRAM, the IP Manager supports managing
networks of up to 100 motes and the packet throughput
of the IP Manager increases from 24 packets per second
without SRAM to 36 packets per second with SRAM.
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LTC5800-IPR
Operation
State Diagram
Serial Flash Emulation
In order to provide capabilities and flexibility in addition
to ultra low power, Eterna operates in various states, as
shown in Figure 15, and described in this section. State
transitions shown in red are not recommended.
When both RESETn and FLASH_P_ENn are asserted,
Eterna disables normal operation and enters a mode to
emulate the operation of a serial flash. In this mode, its
flash can be programmed.
Fuse Table
Operation
Eterna’s Fuse Table is a 2kB page in flash that contains
two data structures. One structure supports hardware
configuration immediately following power-on reset or
the assertion of RESETn. The second structure supports
configuration of software board support parameters. Fuse
Tables are generated via the Fuse Table application described in the Board Specific Configuration Guide. Hardware
configuration of I/O immediately following power-on reset
provides a method to minimize leakage due to floating nets
prior to software configuration. I/O leakage can contribute
hundreds of microamperes of leakage per input, potentially
stressing current limited supplies. Examples of software
board support parameters include setting of UART modes,
clock sources and trim values. Fuse Tables are loaded into
flash using the same software and in-circuit programmer
used to load software images as described in the Eterna
Serial Programmer Guide.
Once Eterna has completed start-up Eterna transitions to
the Operational group of states (active/CPU active, active/
CPU inactive, and Doze). There, Eterna cycles between the
various states, automatically selecting the lowest possible power state while fulfilling the demands of network
operation.
In the Active State, Eterna’s relaxation oscillator is running
and peripherals are enabled as needed. The ARM Cortex-M3
cycles between CPU-active and CPU-inactive (referred to
in the ARM Cortex-M3 literature as “Sleep Now” mode).
Eterna’s extensive use of DMA and intelligent peripherals
that independently move Eterna between Active state and
Doze state minimizes the time the CPU is active, significantly reducing Eterna’s energy consumption.
Doze State
Start-Up
Start-up occurs as a result of either crossing the power-on
reset threshold or asserting RESETn. After the completion of power-on reset or the falling edge of an internally
synchronized RESETn, Eterna loads its Fuse Table which,
as described in the previous section, includes configuring
I/O direction. In this state, Eterna checks the state of the
FLASH_P_ENn and RESETn pins and enters the serial
flash emulation mode if both signals are asserted. If the
FLASH_P_ENn pin is not asserted but RESETn is asserted,
Eterna automatically reduces its energy consumption to
a minimum until RESETn is released. Once RESETn is
de-asserted, Eterna goes through a boot sequence, and
then enters the Active state.
30
Active State
The Doze state consumes orders of magnitude less current than the Active state and is entered when all of the
peripherals and the CPU are inactive. In the Doze state
Eterna’s full state is retained, timing is maintained, and
Eterna is configured to detect, wake, and rapidly respond
to activity on I/Os (such as UART signals and the TIMEn
pin). In the Doze state the 32.768kHz oscillator and associated timers are active.
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Operation
POWER-ON
RESET
VSUPPLY > PoR
RESETn LOW AND
FLASH_P_ENn LOW
LOAD FUSE
SETTINGS
RESETn LOW AND
FLASH_P_ENn HIGH
SET RESETn HIGH AND
FLASH_P_ENn HIGH
FOR 125µs, THEN
SET RESETn LOW
SERIAL FLASH
EMULATION
RESETn HIGH
AND
FLASH_P_ENn
HIGH
RESET
DEASSERT
RESETn
BOOT
START-UP
ASSERT RESETn
DOZE
ASSERT RESETn
CPU AND
PERIPHERALS
INACTIVE
HW OR PMU EVENT
OPERATION
ASSERT RESETn
CPU
ACTIVE
ACTIVE
CPU
INACTIVE
DEEP SLEEP
LOW POWER SLEEP
COMMAND
INACTIVE
5800IPR F15
Figure 15. Eterna State Diagram
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LTC5800-IPR
Applications Information
Regulatory And Standards Compliance
The RoHS-compliant design features include:
Radio Certification
n
RoHS-compliant solder for solder joints
Eterna is suitable for systems targeting compliance with
worldwide radio frequency regulations: ETSI EN 300 328
and EN 300 440 class 2 (Europe), FCC CFR47 Part 15
(US), and ARIB STD-T66 (Japan). Application Programming Interfaces (APIs) supporting regulatory testing are
provided on both the API and CLI UART interfaces. The
Eterna Certification User Guide provides:
n
RoHS-compliant base metal alloys
n
RoHS-compliant precious metal plating
Reference information required for certification
n
Test plans for common regulatory test cases
n
Example CLI API calls
n
Sample manual language and example label
n
Compliance to Restriction of Hazardous Substances
(RoHS)
Restriction of Hazardous Substances (RoHS) is a directive
that places maximum concentration limits on the use of
cadmium (Cd), lead (Pb), hexavalent chromium (Cr+6),
mercury (Hg), Polybrominated Biphenyl (PBB), and Polybrominated Diphenyl Ethers (PBDE). Linear Technology is
committed to meeting the requirements of the European
Community directive 2002/95/EC.
RoHS-compliant cable assemblies and connector
choices
n
Lead-free QFN package
n
Halogen-free mold compound
n
RoHS-compliant and 245 °C re-flow compatible
n
Note: Customers may elect to use certain types of leadfree solder alloys in accordance with the European Community directive 2002/95/EC. Depending on the type of
solder paste chosen, a corresponding process change to
optimize reflow temperatures may be required.
Soldering Information
Eterna is suitable for both eutectic PbSn and RoHS-6 reflow.
The maximum reflow soldering temperature is 260 ºC. A
more detailed description of layout recommendations, assembly procedures and design considerations is included
in the Eterna Integration Guide.
This product has been specifically designed to utilize
RoHS-compliant materials and to eliminate or reduce the
use of restricted materials to comply with 2002/95/EC.
32
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LTC5800-IPR
Related Documentation
TITLE
LOCATION
DESCRIPTION
SmartMesh IP User’s Guide
http://www.linear.com/docs/41880
Theory of operation for SmartMesh IP networks and motes
SmartMesh IP Manager API Guide
http://www.linear.com/docs/41883
Definitions of the applications interface commands available over the
API UART
SmartMesh IP Manager CLI Guide
http://www.linear.com/docs/41882
Definitions of the command line interface commands available over
the CLI UART
Eterna Integration Guide
http://www.linear.com/docs/41874
Recommended practices for designing with the LTC5800
Eterna Serial Programmer Guide
http://www.linear.com/docs/41876
User’s guide for the Eterna serial programmer used for in circuit
programming of the LTC5800
Board Specific Configuration Guide
http://www.linear.com/docs/41875
User’s guide for the Eterna Board Specific Configuration application,
used to configure the board specific parameters
Eterna Certification User Guide
http://www.linear.com/docs/42918
The essential documentation necessary to complete radio
certifications, including examples for common test cases
SmartMesh IP Tools Guide
http://www.linear.com/docs/42453
The user’s guide for all IP related tools, and specifically the definition
for the on-chip application protocol (OAP)
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LTC5800-IPR
Package Description
Please refer to http://www.linear.com/product/LTC5800#packaging for the most recent package drawings.
WR Package
72-Lead QFN (10mm × 10mm)
(Reference LTC DWG # 05-08-1930 Rev A)
0°–14° (×4)
0.65 REF
10.50 ±0.05
6.00 ±0.15
MAX
1.0mm
0.02
8.90 ±0.05
8.50 REF
(4 SIDES)
0.20
REF
6.00 ±0.15
0.50
DETAIL A
0.25 ±0.05
0.50 BSC
0.8 ±0.05
0.60 MAX
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.10 M C A B
0.0.5 M C
0.15 C
10.00 BSC
B
9.75 BSC
B
0.60
MAX
b
0.25 ±0.05
DETAIL B
0.5 ±0.1
6.00 ±0.15
55
72
54
1
PIN 1
10.00 9.75
BSC BSC
6.00 ±0.15
37
0.15 C
18
36
R0.300
TYP
C
0.50 BSC
19
DETAIL B
WR72 0213 REV A
DETAIL A
0.10 C
SEATING PLANE
LTCXXXXXX
0.10 C
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220
2. DIMENSION “b” APPLIES TO METALIZED TERMINAL AND IS MEASURED BETWEEN
0.15mm AND 0.30mm FROM THE TERMINAL TIP. IF THE TERMINAL HAS OPTIONAL
RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION B SHOULD NOT BE
MEASURED IN THAT RADIUS AREA
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. DRAWING NOT TO SCALE
COMPONENT
PIN “A1”
TRAY PIN 1
BEVEL
34
PACKAGE IN TRAY LOADING ORIENTATION
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LTC5800-IPR
Revision History
REV
DATE
DESCRIPTION
A
12/15
Updated Order Part Number and Manager Options
PAGE NUMBER
Added H-Grade Ordering Information and Product Specifications
4, 29
4, 5, 26
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However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTC5800-IPR
tion that the interconnection
of its
circuits as described
herein will not infringe on existing patent rights.
35
LTC5800-IPR
Typical Application
Power over Ethernet Network Manager
SMSC 8710A
(10/100 PHY)
TXP
TXM
RXP
RXM
ATMEL SAM4E
LTC5800-IPR
3.3nH
ANTENNA
MII
MII
TXP
TXM
1pF 1pF
TIMEn
UART
100pF
RJ45
1
TX+
TX–
2
RX+
3
6
4
5
7
8
RX–
14
1
12
3
13
10
2
5
11
4
9
6
COILCRAFT
ETHI-230LD
SPARE+
LTC4265
PoE PD
SMAJ58A
INTERFACE
TVS
CONTROLLER
0.1µF
100V
SPARE–
LT8300
ISOLATED
FLYBACK
CONVERTER
3.3V
5800IPR TA02
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36 Linear Technology Corporation
COMMENTS
Includes Modular Radio Certification in the United States, Canada, Europe,
Japan, South Korea, Taiwan, India, Japan, Australia and New Zealand
Includes Modular Radio Certification in the United States, Canada, Europe,
South Korea, Japan, Taiwan, India, Australia and New Zealand
Includes Modular Radio Certification in the United States, Canada, Europe,
Japan, South Korea, Taiwan, India, Australia and New Zealand
Includes Modular Radio Certification in the United States, Canada, Europe,
South Korea, Japan, Taiwan, India, Australia and New Zealand
Includes Modular Radio Certification in the United States, Canada, Europe,
Japan, South Korea, Taiwan, India, Australia and New Zealand
Includes Modular Radio Certification in the United States, Canada, Europe,
South Korea, Japan, Taiwan, India, Australia and New Zealand
Ultralow Power Mote, 72-Lead 10mm × 10mm QFN
Includes Modular Radio Certification in the United States, Canada, Europe,
Japan, South Korea, Taiwan, India, Australia and New Zealand
Includes Modular Radio Certification in the United States, Canada,
Europe,South Korea, Japan, Taiwan, India, Australia and New Zealand
2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC
860nA IQ in Sleep, 2.7V to 20V Input, VOUT: 1.2V to 5.0V, Enable and Standby
Pins
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC5800-IPR
●
●
(408) 432-1900 FAX: (408) 434-0507
www.linear.com/LTC5800-IPR
5800iprfa
LT 1215 REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2014
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