LTC6268-10/LTC6269-10
4GHz Ultra-Low Bias
Current FET Input Op Amp
FEATURES
DESCRIPTION
Gain Bandwidth Product: 4GHz
nn Low Input Bias Current:
nn ±3fA Typ. Room Temperature
nn 4pA Max at 125°C
nn Current Noise (100kHz): 7fA/√Hz
nn Voltage Noise (1MHz): 4.0nV/√Hz
nn Extremely Low C 0.45pF
IN
nn Rail-to-Rail Output
nn A ≥10
V
nn Slew Rate: +1500V/µs, –1000V/µs
nn Supply Range: 3.1V to 5.25V
nn Quiescent Current: 16.5mA
nn Operating Temp Range: –40°C to 125°C
nn Single in 8-Lead SO-8, 6-Lead TSOT-23 Packages
nn Dual in 8-Lead MS8, 3mm × 3mm 10-Lead
DFN 10 Packages
The LTC®6268-10/LTC6269-10 is a single/dual 4GHz FETinput operational amplifier with extremely low input bias
current and low input capacitance. It also features low
input-referred current noise and voltage noise making it an
ideal choice for high speed transimpedance amplifiers, and
high-impedance sensor amplifiers. It is a decompensated
op amp that is gain-of-10 stable.
nn
APPLICATIONS
It operates on 3.1V to 5.25V supply and consumes 16.5mA
per amplifier. A shutdown feature can be used to lower
power consumption when the amplifier is not in use.
The LTC6268-10 single op amp is available in 8-lead SOIC
and 6-lead SOT-23 packages. The SOIC package includes
two unconnected pins which can be used to create an input
pin guard ring to protect against board leakage currents.
The LTC6269-10 dual op amp is available in 8-lead MSOP
with exposed pad and 3mm × 3mm 10-lead DFN packages.
They are fully specified over the –40°C to 85°C and the
–40°C to 125°C temperature ranges.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Transimpedance Amplifiers
nn ADC Drivers
nn Photomultiplier Tube Post-Amplifier
nn Low I
BIAS Circuits
nn
TYPICAL APPLICATION
20kΩ TIA Frequency Response
20kΩ Gain 210MHz Transimpedance Amplifier
90
87
2.5V
81
2.5V
PD
–
IPD
84
PARASITIC
FEEDBACK C
LTC6268-10
+
VOUT = –IPD • 20k
BW = 210MHz
GAIN (dBΩ)
20kΩ
78
75
72
69
66
–2.5V
63
626810 TA01
PD = OSI OPTOELECTRONICS, FCI-125G-006
60
10k
100k
1M
10M
FREQUENCY (Hz)
100M
1G
626810 TA01b
626810f
For more information www.linear.com/LTC6268-10
1
LTC6268-10/LTC6269-10
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage V+ to V–............................................5.5V
Input Voltage ................................V– – 0.2V to V+ + 0.2V
Input Current (+IN, –IN) (Note 2)............................ ±1mA
Input Current (SHDN)............................................. ±1mA
Output Current (IOUT ) (Note 8, 9)..........................135mA
Output Short-Circuit Duration (Note 3).... Thermally Limited
Operating Temperature Range
LTC6268-10I/LTC6269-10I....................–40°C to 85°C
LTC6268-10H/LTC6269-10H............... –40°C to 125°C
Specified Temperature Range (Note 4)
LTC6268-10I/LTC6269-10I....................–40°C to 85°C
LTC6268-10H/LTC6269-10H............... –40°C to 125°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature S8, S6 and
MS8E (Soldering, 10 sec).................................. 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
NC 1
8
SHDN
–IN 2
7
V+
+IN 3
6
OUT
NC 4
5
V–
6 V+
OUT 1
V– 2
5 SHDN
+IN 3
4 –IN
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 120°C/W (NOTE 5)
TJMAX = 150°C, θJA = 192°C/W (NOTE 5)
TOP VIEW
TOP VIEW
OUTA
–INA
+INA
V–
1
2
3
4
9
V–
8
7
6
5
V+
OUTB
–INB
+INB
OUTA
1
–INA
2
+INA
3
V–
4
SDA
5
MS8E PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 40°C/W (NOTE 5)
EXPOSED PAD (PIN 9) IS V–, IT IS RECOMMENDED TO SOLDER TO PCB
10 V+
11
V–
9 OUTB
8 –INB
7 +INB
6 SDB
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W (NOTE 5)
EXPOSED PAD (PIN 11) IS V–, IT IS RECOMMENDED TO SOLDER TO PCB
2
626810f
For more information www.linear.com/LTC6268-10
LTC6268-10/LTC6269-10
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6268IS6-10#TRMPBF
LTC6268IS6-10#TRPBF
LTGQT
6-Lead Plastic TSOT-23
–40°C to 85°C
LTC6268HS6-10#TRMPBF
LTC6268HS6-10#TRPBF
LTGQT
6-Lead Plastic TSOT-23
–40°C to 125°C
LTC6268IS8-10#PBF
LTC6268IS8-10#TRPBF
626810
8-Lead Plastic SOIC
–40°C to 85°C
LTC6268HS8-10#PBF
LTC6268HS8-10#TRPBF
626810
8-Lead Plastic SOIC
–40°C to 125°C
LTC6269IMS8E-10#PBF
LTC6269IMS8E-10#TRPBF
LTGRM
8-Lead Plastic MSOP
–40°C to 85°C
LTC6269HMS8E-10#PBF
LTC6269HMS8E-10#TRPBF
LTGRM
8-Lead Plastic MSOP
–40°C to 125°C
LTC6269IDD-10#PBF
LTC6269IDD-10#TRPBF
LGRK
10-Lead Plastic DD
–40°C to 85°C
LTC6269HDD-10#PBF
LTC6269HDD-10#TRPBF
LGRK
10-Lead Plastic DD
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
5.0V
ELECTRICAL CHARACTERISTICS
The l denotes specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VSUPPLY = 5.0V (V+ = 5V, V– = 0V, VCM = mid-supply), RL = 1kΩ, VSHDN
is unconnected.
SYMBOL PARAMETER
VOS
Input Offset Voltage
CONDITIONS
MIN
TYP
MAX
VCM = 2.75V
0.2
l
–0.7
–3
0.7
3
mV
mV
–1.0
–4.5
0.2
l
1.0
4.5
mV
mV
VCM = 4.0V
TC VOS
Input Offset Voltage Drift
VCM = 2.75V
IB
Input Bias Current
(Notes 6, 8)
VCM = 2.75V
LTC6268I-10/LTC6269I-10
LTC6268H-10/LTC6269H-10
–20
–900
–4
±3
l
l
20
900
4
fA
fA
pA
VCM = 4.0V
LTC6268I-10/LTC6269I-10
LTC6268H-10/LTC6269H-10
–20
–900
–4
±3
l
l
20
900
4
fA
fA
pA
VCM = 2.75V
LTC6268I-10/LTC6269I-10
LTC6268H-10/LTC6269H-10
–40
–450
–2
±6
l
l
40
450
2
fA
fA
pA
IOS
en
Input Offset Current (Notes 6, 8)
Input Voltage Noise Density, VCM = 2.75V
f = 1MHz
Input Voltage Noise Density, VCM = 4.0V
Input Referred Noise Voltage
Input Current Noise Density, VCM = 2.75V
Input Current Noise Density, VCM = 4.0V
RIN
Input Resistance
CIN
Input Capacitance
Differential (DC to 200MHz)
CMRR
Common Mode Rejection Ratio
VCM = 0.5V to 3.2V (PNP Side)
in
4
UNITS
4.0
nV/√Hz
f = 1MHz
4.0
nV/√Hz
f = 0.1Hz to 10Hz
12.6
μVP-P
f = 100kHz
7
fA/√Hz
f = 100kHz
7
fA/√Hz
Differential
>1000
GΩ
Common Mode
>1000
GΩ
0.1
pF
Common Mode (DC to 100MHz)
VCM = –0.1V to 4.5V
IVR
Input Voltage Range
μV/°C
Guaranteed by CMRR
0.45
pF
85
l
72
68
dB
dB
64
52
82
l
dB
dB
l
–0.1
4.5
V
626810f
For more information www.linear.com/LTC6268-10
3
LTC6268-10/LTC6269-10
5.0V
ELECTRICAL CHARACTERISTICS
The l denotes specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VSUPPLY = 5.0V (V+ = 5V, V– = 0V, VCM = mid-supply), RL = 1kΩ, VSHDN
is unconnected.
SYMBOL PARAMETER
CONDITIONS
PSRR
VCM = 1.0V, VSUPPLY Ranges from 3.1V to 5.25V
Power Supply Rejection Ratio
Supply Voltage Range
AV
Open Loop Voltage Gain
VOUT = 0.5V to 4.5V
MIN
TYP
95
l
78
75
l
3.1
125
40
250
l
V/mV
V/mV
10
2
21
l
V/mV
V/mV
RLOAD = 10k
RLOAD = 100
VOL
Output Swing Low (Input Overdrive 30mV)
Measured from V–
ISINK = 10mA
Output Swing High (Input Overdrive 30mV)
Measured from V+
ISOURCE = 10mA
140
200
mV
mV
130
200
260
mV
mV
70
140
200
mV
mV
160
270
370
mV
mV
l
ISOURCE = 25mA
l
ISC
IS
Output Short Circuit Current (Note 9)
60
40
90
l
15
9
16.5
l
18
25
mA
mA
0.39
0.85
1.5
mA
mA
2
2
12
12
µA
µA
0.75
V
Supply Current Per Amplifier
Supply Current in Shutdown
(Per Amplifier)
dB
dB
80
l
VOH
UNITS
5.25
l
ISINK = 25mA
MAX
l
ISHDN
Shutdown Pin Current
VSHDN = 0.75V
VSHDN =1.50V
l
l
VIL
SHDN Input Low Voltage
Disable
l
l
–12
–12
mA
mA
VIH
SHDN Input High Voltage
Enable. If SHDN is Unconnected, Amp is Enabled
tON
Turn On Time, Delay from SHDN Toggle to
Output Reaching 90% of Target
SHDN Toggle from 0V to 2V
360
ns
tOFF
Turn Off Time, Delay from SHDN Toggle to
Output High Z
SHDN Toggle from 2V to 0V
183
ns
GBW
Gain-Bandwidth Product (Note 8)
f = 10MHz
l
3500
4000
MHz
SR+
Slew Rate+
AV = 11 (RF = 1000, RG = 100)
VOUT = 0.5V to 4.5V, Measured 20% to 80%,
RLOAD = 500Ω
1100
600
1500
l
V/µs
V/µs
AV = 11 (RF = 1000, RG = 100)
VOUT = 4.5V to 0.5V, Measured 80% to 20%,
l
900
500
SR–
Slew Rate–
FPBW
Full Power Bandwidth (Note 7)
4VP-P
HD
Harmonic Distortion(HD2/HD3)
AV = 10, 10MHz. 2VP-P, VCM = 2.25V, RL = 1k,
RF = 450Ω, RG = 50Ω
ILEAK
Output Leakage Current in Shutdown
VSHDN = 0V, VOUT = 0V
VSHDN = 0V, VOUT = 5V
4
1.5
V
1000
V/µs
V/µs
73
MHz
–91/–96
dB
400
400
nA
nA
626810f
For more information www.linear.com/LTC6268-10
LTC6268-10/LTC6269-10
3.3V ELECTRICAL CHARACTERISTICS
The l denotes specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VSUPPLY = 3.3V (V+ = 3.3V, V– = 0V, VCM = mid-supply), RL = 1kΩ,
VSHDN is unconnected.
SYMBOL PARAMETER
VOS
Input Offset Voltage
CONDITIONS
MIN
TYP
MAX
VCM = 1.0V
0.2
l
–0.7
–3
0.7
3
mV
mV
–1.0
–4.5
0.2
l
1.0
4.5
mV
mV
±3
l
l
–20
–900
–4
20
900
4
fA
fA
pA
VCM = 2.3V
–20
l
LTC6268I-10/LTC6269I-10
–900
l
–4
LTC6268H-10/LTC6269H-10
±3
20
900
4
fA
fA
pA
VCM = 1.0V
–40
l
LTC6268I-10/LTC6269I-10
–450
l
–2
LTC6268H-10/LTC6269H-10
±6
40
450
2
fA
fA
pA
VCM = 2.3V
TC VOS
Input Offset Voltage Drift
VCM = 1.0V
IB
Input Bias Current (Notes 6, 8)
VCM = 1.0V
LTC6268I-10/LTC6269I-10
LTC6268H-10/LTC6269H-10
IOS
Input Offset Current (Notes 6, 8)
en
Input Voltage Noise Density, VCM =1.0V f = 1MHz
in
4
nV/√Hz
Input Voltage Noise Density, VCM = 2.3V f = 1MHz
4.0
nV/√Hz
Input Referred Noise Voltage
13.5
μVP-P
Input Current Noise Density, VCM = 1.0V f = 100kHz
7
fA/√Hz
Input Current Noise Density, VCM = 2.3V f = 100kHz
7
fA/√Hz
f = 0.1Hz to 10Hz
Input Resistance
Differential
Common Mode
CIN
Input Capacitance
Differential (DC to 200MHz)
Common Mode (DC to 100MHz)
CMRR
Common Mode Rejection Ratio
VCM = 0.5V to 1.2V (PNP Side)
VCM = –0.1V to 2.8V (Full Range)
IVR
Input Voltage Range
Guaranteed by CMRR
AV
Open Loop Voltage Gain
VOUT = 0.5V to 2.8V
Output Swing Low
(Input Overdrive 30mV).
Measured from V–
>1000
>1000
GΩ
GΩ
0.1
0.45
pF
pF
63
60
90
l
dB
dB
60
50
77
l
dB
dB
l
–0.1
200
l
80
40
V/mV
V/mV
10
2
18
l
V/mV
V/mV
RLOAD = 10k
RLOAD = 100
ISINK = 10mA
2.8
ISINK = 25mA
Output Swing High
(Input Overdrive 30mV).
Measured from V+
ISOURCE = 10mA
140
200
mV
mV
140
200
260
mV
mV
80
140
200
mV
mV
170
270
370
mV
mV
l
ISOURCE = 25mA
l
ISC
IS
Output Short Circuit Current (Note 9)
50
35
80
l
14.5
9
16
l
Supply Current per Amplifier
V
80
l
l
VOH
µV/C
4.0
RIN
VOL
UNITS
mA
mA
17.5
25
mA
mA
626810f
For more information www.linear.com/LTC6268-10
5
LTC6268-10/LTC6269-10
3.3V ELECTRICAL CHARACTERISTICS
The l denotes specifications that apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VSUPPLY = 3.3V (V+ = 3.3V, V– = 0V, VCM = mid-supply) RL = 1kΩ, VSHDN
is unconnected.
SYMBOL PARAMETER
CONDITIONS
MIN
Supply Current in Shutdown
(Per Amplifier)
TYP
MAX
0.23
0.6
1.2
mA
mA
2
2
12
12
µA
µA
0.75
V
l
ISHDN
Shutdown Pin Current
VSHDN = 0.75V
VSHDN = 1.5V
l
l
VIL
SHDN Input Low Voltage
Disable
l
Enable. If SHDN is Unconnected, Amp Is Enabled
l
–12
–12
UNITS
VIH
SHDN Input High Voltage
tON
Turn On Time, Delay from SHDN Toggle SHDN Toggle from 0V to 2V
to Output Reaching 90% of Target
750
ns
tOFF
Turn Off Time, Delay from SHDN Toggle SHDN Toggle from 2V to 0V
to Output High Z
201
ns
GBW
Gain-Bandwidth Product (Note 8)
f = 10MHz
l
3500
4000
MHz
SR+
Slew Rate+
AV = 11 (RF = 1000, RG = 100),
VOUT = 1V to 2.3V, Measured 20% to 80%,
RLOAD = 500Ω
800
600
1500
l
V/µs
V/µs
AV = 11 (RF = 1000, RG = 100),
VOUT = 1V to 2.3V, Measured 80% to 20%,
RLOAD = 500Ω
600
400
1000
l
V/µs
V/µs
105
MHz
SR–
Slew Rate–
FPBW
Full Power Bandwidth (Note 7)
2.3VP-P
HD
Harmonic Distortion(HD2/HD3)
A = 10, 10MHz. 2VP-P, VCM = 1.65V, RL = 1k,
RF = 450Ω, RG = 50Ω
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs are protected by two series connected ESD protection
diodes to each power supply. The input current should be limited to less
than 1mA. The input voltage should not exceed 200mV beyond the power
supply.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 4: The LTC6268-10I/LTC6269-10I is guaranteed to meet specified
performance from –40°C to 85°C. The LTC6268-10H/LTC6269-10H is
guaranteed to meet specified performance from –40°C to 125°C.
6
1.5
V
–67/–78
dB
Note 5: Thermal resistance varies with the amount of PC board metal
connected to the package. The specified values are for short traces
connected to the leads.
Note 6: The input bias current is the average of the currents into the
positive and negative input pins. Typical measurement is for S8 package.
Note 7: Full Power Bandwidth is determined from distortion performance
in a gain-of-10 configuration with HD2/HD3 < –40dB (1%) as the criteria
for a valid output.
Note 8: This parameter is specified by design and/or characterization and
is not tested in production.
Note 9: The LTC6268-10/LTC6269-10 is capable of producing peak
output currents in excess of 135mA. Current density limitations within
the IC require the continuous current supplied by the output (sourcing or
sinking) over the operating lifetime of the part be limited to under 135mA
(Absolute Maximum).
626810f
For more information www.linear.com/LTC6268-10
LTC6268-10/LTC6269-10
TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset Voltage Distribution
250
VS = ±2.5V
VCM = 0.25V
2.0
VS = ±2.5V
VCM = 1.5V
VS = ±2.5V
1.5 VCM = 0.25V
200
200
150
100
1.0
0.5
150
VOS (mV)
NUMBER OF UNITS
250
Input Offset Voltage
vs Temperature
Input Offset Voltage Distribution
NUMBER OF UNITS
300
TA = 25°C, unless otherwise noted.
100
–0.5
–1.0
50
50
0
–1.5
0
–0.4 –0.3 –0.2 –01 0 0.1 0.2 0.3 0.4 0.5 0.6
VOS (mV)
0
–0.4 –0.3 –0.2 –01 0 0.1 0.2 0.3 0.4 0.5 0.6
VOS (mV)
626810 G01
626810 G02
Input Offset
Drift Distribution
Input Offset Voltage
vs Common Mode Voltage
VS = ±2.25V
VCM = 0.25V
1
H–GRADE
I–GRADE
0.8
15
VOS (mV)
NUMBER OF UNITS
20
10
5
0
–15
–10
626810 G03
–5
0
5
DISTRIBUTION (µV/°C)
10
1
VS = ±2.5V
VS = 3.1V to 5.25V
0.8 VCM = 1V
0.6
0.6
0.4
0.4
0.2
0.2
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1
–2.5
15
Input Offset Voltage
vs Supply Voltage
VOS (mV)
25
–2.0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
–1.25
0
1.25
–1
2.5
VCM (V)
626810 G04
3
3.5
4
4.5
VS (V)
5
626810 G06
626810 G05
Input Offset Voltage
vs Output Current
1.40
PSRR vs Frequency
100
VS = ±2.5V
1.20
0.80
VCM = 1.5V
PSRR (dB)
VOS (mV)
1.00
0.60
CMRR vs Frequency
100
+PSRR
–PSRR
80
80
60
60
CMRR (dB)
1.60
5.5
40
40
0.40
0.20
0.00
VCM = 0.25V
–0.20
–100 –80 –60 40 –20 0 20 40 60 80 100
OUTPUT CURRENT (mA)
20
VS = ±2.5V, VCM = 0.25V
0
0.01
0.1
1
10
FREQUENCY (MHz)
20
100
1000
626810 G08
Vs = ±2.5V, VCM = 0.25V
0
0.01
0.1
1
10
FREQUENCY (MHz)
100
1000
626810 G09
626810 G07
626810f
For more information www.linear.com/LTC6268-10
7
LTC6268-10/LTC6269-10
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bias Current vs Common
Mode Voltage
Input Bias Current vs Supply
Voltage
8.0
–1
6.0
–2
4.0
100
+IN
2.0
0
0.0
–2.0
–IN
–100
–4.0
–6.0
–200
INPUT BIAS CURRENT (fA)
INPUT BIAS CURRENT (fA)
200
0
–10.0
5.0
1.0
2.0
3.0
4.0
COMMON MODE VOLTAGE (V)
VS = ±2.5V
1400 VCM = 0.25V
+IN
1200
–IN
–3
–4
+IN
–5
–6
200
0
120
80
TA = 125°C
TA = 25°C
TA = –55°C
10.0
15.0
20.0
LOAD CURRENT (mA)
25.0
–40
–120
–160
2
0.1
FREQUENCY(MHz)
1
626810 G16
8
100
SINKING
50
TA = 125°C
TA = 25°C
TA = –55°C
0
–50
SOURCING
–100
–240
–150
VS = ±2.5V
VCM = 0.25V
–280
0.0
5.0
10.0
15.0
20.0
LOAD CURRENT (mA)
25.0
–200
3.0
3.5
4.0
4.5
VS (V)
5.0
5.5
626810 G15
626810 G14
10
0.1Hz to 10Hz Input
Referred Voltage Noise
20
VS = ±2.5V
VCM = 0.25V
VS = ±2.5V
AV = 11
VCM = –0.25V
16
8
12
VOLTAGE NOISE (µV)
4
0
0.01
150
Wide Band Input Referred
Voltage Noise
6
125
200
–200
VOLTAGE NOISE DENSITY (nV/√Hz)
VOLTAGE NOISE DENSITY (nV/√Hz)
8
65
85
105
TEMPERATURE (°C)
Output Short Circuit Current
vs Supply Voltage
–80
Input Referred Voltage Noise
Density
VS = ±2.5V
VCM = 0.25V
45
626810 G12
TA = 125°C
TA = 25°C
TA = –55°C
626810 G13
10
–200
25
5.5
ISC (mA)
OUTPUT SATURATION VOLTAGE (mV)
OUTPUT SATURATION VOLTAGE (mV)
0
160
5.0
400
Output Saturation Voltage
vs Load Current (Output High)
VS = ±2.5V
VCM = 0.25V
0
0.0
600
626810 G11
Output Saturation Voltage
vs Load Current (Output Low)
40
800
–IN
–8
626810 G10
200
1000
–7
–9 VS = 3.2V TO 5.25V
VCM = 1.0V
–10
3.5
4.0
4.5
5.0
3.0
SUPPLY VOLTAGE (V)
–8.0
–300
0.0
Input Bias Current vs Temperature
1600
CURRENT (fA)
VS = 5V
10.0
INPUT BIAS CURRENT (fA)
300
TA = 25°C, unless otherwise noted.
6
4
2
8
4
0
–4
–8
–12
–16
0
0
100
200
300
FREQUENCY (MHz)
400
500
626810 G17
–20
0
1
2
3
4 5 6
TIME (s)
7
8
9
10
626810 G18
626810f
For more information www.linear.com/LTC6268-10
LTC6268-10/LTC6269-10
TYPICAL PERFORMANCE CHARACTERISTICS
Input Referred
Current Noise
0.1Hz to 10Hz Input
Referred Voltage Noise
8
0
–4
–8
–12
–16
–20
0
1
2
3
4 5 6
TIME (s)
7
8
9
10
VS = ±2.5V
VCM = 0.25V
12
9
6
3
0
0
50
100
150
FREQUENCY(MHz)
Output Impedance
vs Frequency
10
1
0.1
–45
20.0
–90
0.1
100
1
10
FREQUENCY(MHz)
–60
626810 G21
100
HD2
0
–100
HD3
–200
–140
0.1
1000
Small Signal Step Response
–80
–100
1
FREQUENCY (MHz)
626810 G22
–135
100
200
–120
0.1
1
10
FREQUENCY(MHz)
40.0
0
0.01
200
VS = ±2.5V
VOUT = 2VP–P
RL = 1kΩ
RF = 450Ω
RG = 50Ω
AV = 10V
VCM = –0.25V
–40
DISTORTION (dB)
OUTPUT IMPEDANCE (Ω)
–20
AV = 10V
AV = 100V
0.01
0
Harmonic
Distortion vs Frequency
1000
0.01
0.001
60.0
626810 G20
626810 G19
100
45
GAIN
PHASE
10
VS = ±2.5V
VCM = 0.25V
0
40
AV = 10V/V, 20mV STEP
RL = 1kΩ
80
120
160
626810 G24
Small Signal Step Response
Small Signal Step Response
200
TIME (ns)
626810 G23
Large Signal Step Response
200
200
PHASE
4
Gain/Phase vs Frequency
80.0
VOUT (mV)
12
CURRENT NOISE DENSITY (ρA/√Hz)
VS = ±2.5V
AV = 11
VCM = 1.5V
16
VOLTAGE NOISE (µV)
15
GAIN (dB)
20
TA = 25°C, unless otherwise noted.
2.0
1.5
100
0
0.5
0
–100
–100
–200
1.0
VOUT (V)
VOUT (mV)
VOUT (mV)
100
VS = ±2.5V
VCM = 0.25V
0
40
AV = 10V/V, 20mV STEP
RL = 1kΩ, CL = 2.7pF
80
120
TIME (ns)
160
200
626810 G25
–200
0.0
–0.5
–1.0
VS = ±2.5V
VCM = 1.25V
0
40
–1.5
AV = 10V/V, 20mV STEP
RL = 1kΩ, CL = 2.7pF
80
120
TIME (ns)
160
200
626810 G26
–2.0
VS = ±2.5V
VCM = 0.25V
–0
40
AV = 10V/V, 200mV STEP
RL = 1kΩ
80
120
TIME (ns)
160
200
626810 G27
626810f
For more information www.linear.com/LTC6268-10
9
LTC6268-10/LTC6269-10
TYPICAL PERFORMANCE CHARACTERISTICS
1.5
1.0
1.0
0.5
0.5
0.0
–0.5
30
VCM = 1V
27 AV = 1
24
SUPPLY CURRENT (mA)
1.5
VOUT (V)
VOUT (V)
2.0
0.0
–0.5
–1.0
–1.0
–2.0
Supply Current vs Supply Voltage
Large Signal Step Response
Large Signal Step Response
2.0
–1.5
TA = 25°C, unless otherwise noted.
VS = ±2.5V
VCM = 0.25V
–0
40
80
120
TIME (ns)
160
200
–2.0
18
15
12
9
6
–1.5
AV = 10V/V, 200mV STEP
RL = 1kΩ, CL = 2.7pF
21
VS = ±2.5V
VCM = 1.25V
–0
40
AV = 10V/V, 200mV STEP
RL = 1kΩ, CL = 2.7pF
80
120
TIME (ns)
160
3
0
3.0
200
TA = 125°C
TA = 25°C
TA = –55°C
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
626810 G29
626810 G28
626810 G30
Supply Current vs Shutdown
Voltage
Supply Current vs Shutdown
Voltage
25
VS = 5V
VCM = 2.75V
AV = 1
20
TA = 125°C
TA = 25°C
TA = –55°C
15
20
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
25
10
10
5
5
0
0.0
15
VS = 3.1V
VCM = 1V
AV = 1
TA = 125°C
TA = 25°C
TA = –55°C
0.5
1.0
1.5
SHUT DOWN VOLTAGE (V)
2.0
0
0.0
0.5
1.0
1.5
SHUT DOWN VOLTAGE (V)
2.0
626810 G32
626810 G31
PIN FUNCTIONS
–IN: Inverting Input of the Amplifier. The voltage range of
this pin is from V– to V+ –0.5V.
+IN: Non-Inverting Input. The voltage range of this pin is
from V– to V+ –0.5V.
V+: Positive Power Supply. Total supply (V+ – V–) voltage
is from 3.1V to 5.25V. Split supplies are possible as long
as the total voltage between V+ and V– is between 3.1V
and 5.25V. A bypass capacitor of 0.1µF should be used
between V+ to ground as close to the pin as possible.
V–:
Negative Power Supply. Normally tied to ground, it
can also be tied to a voltage other than ground as long
10
as the voltage difference between V+ and V– is between
3.1V and 5.25V. If it is not connected to ground, bypass
it to ground with a capacitor of 0.1µF as close to the pin
as possible.
SHDN, SDA, SDB: Active Low op amp shutdown, threshold
is 0.75V above the negative supply, V–. If left unconnected,
the amplifier is enabled.
OUT: Amplifier Output.
NC: Not connected. May be used to create a guard ring
around the input to guard against board leakage currents.
See Applications Information section for more details.
626810f
For more information www.linear.com/LTC6268-10
LTC6268-10/LTC6269-10
SIMPLIFIED SCHEMATIC
LTC6268-10 Simplified Schematic Diagram
V+
C0
I0
D2
COMPLEMENTARY
INPUT STAGE
Q1
INPUT REPLICA
+IN
Q9
D4
Q4
CASCODE STAGE
Q3
D0
CMOS INPUT
BUFFER
–IN
Q5
Q6
BUFFER
OUT
D1
Q7
D6
Q8
INPUT REPLICA
Q2
D5
D3
SHDN
REFERENCE
GENERATION
D7
V–
626810 BD
(ONE POLARITY SHOWN IN INPUT PINS)
626810f
For more information www.linear.com/LTC6268-10
11
LTC6268-10/LTC6269-10
OPERATION
The LTC6268-10/LTC6269-10 input signal range is specified from the negative supply to 0.5V below the positive
power supply, while the output can swing from rail-to-rail.
The schematic above depicts a simplified schematic of
the amplifier.
The input pins drive a CMOS buffer stage. The CMOS buffer
stage creates replicas of the input voltages to boot strap
the protection diodes. In turn, the buffer stage drives a
complementary input stage consisting of two differential
amplifiers, active over different ranges of input common
mode voltage. The main differential amplifier is active with
input common mode voltages from the negative power
supply to approximately 1.55V below the positive supply,
with the second amplifier active over the remaining range
to 0.5V below the positive supply rail. The buffer and
output bias stage uses a special compensation technique
ensuring stability of the op amp. The common emitter
topology of output transistors Q1/Q2 enables the output
to swing from rail-to-rail.
APPLICATIONS INFORMATION
Noise
To minimize the LTC6268-10’s noise over a broad range
of applications, careful consideration has been placed on
input referred voltage noise (eN), input referred current
noise (iN) and input capacitance CIN.
For a transimpedance amplifier (TIA) application such as
shown in Figure 1, all three of these op amp parameters,
plus the value of feedback resistance RF, contribute to noise
behavior in different ways, and external components and
traces will add to CIN. It is important to understand the
impact of each parameter independently. Input referred
CF
RF
IN
–
CIN
OUT
626810 F01
+
voltage noise (eN) consists of flicker noise (or 1/f noise),
which dominates at lower frequencies, and thermal noise
which dominates at higher frequencies. For LTC6268‑10,
the 1/f corner, or transition between 1/f and thermal noise,
is at 40kHz. The iN and RF contributions to input referred
noise current at the minus input are relatively straight
forward, while the eN contribution is amplified by the noise
gain. Because there is no gain resistor, the noise gain is
calculated using feedback resistor(RF) in conjunction
with impedance of CIN as (1 + 2π RF • CIN • Freq), which
increases with frequency. All of the contributions will be
limited by the closed loop bandwidth. The equivalent input
current noise is shown in Figure 2 and Figure 3, where eN
represents contribution from input referred voltage noise
(eN), iN represents contribution from input referred current
noise (iN), and RF represents contribution from feedback
resistor (RF). TIA gain (RF) and capacitance at input (CIN)
are also shown on each figure. Comparing Figure 2 and
Figure 3, iN dominates at higher frequencies. At lower
frequencies, the RF contribution dominates. Since average wide band eN is 4.0nV/√Hz (see typical performance
characteristics), RF contribution will become a lesser factor
at lower frequencies if RF is less than 860Ω as indicated
by the following equation:
eN /RF
4kT /RF
1
GND
Figure 1. Simplified TIA Schematic
12
626810f
For more information www.linear.com/LTC6268-10
LTC6268-10/LTC6269-10
APPLICATIONS INFORMATION
10
100
RF = 20kΩ,
CIN = 1pF,
CF = 60fF
CURRENT NOISE DENSITY pA/√Hz)
CURRENT NOISE DENSITY pA/√Hz)
100
1
0.1
TOTAL
eN
iN
RN
0.01
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
100
10
RF = 499kΩ,
CIN = 1pF,
CF = 13fF
1
0.1
0.001
0.01
1000
TOTAL
eN
iN
RN
0.01
0.1
1
10
FREQUENCY (MHz)
Figure 2
Figure 3
Optimizing the Bandwidth for TIA Application
The capacitance at the inverting input node can cause
amplifier stability problems if left unchecked. When the
feedback around the op amp is resistive (RF), a pole will
be created with RF ||CIN. This pole can create excessive
phase shift and possibly oscillation. Referring to Figure 1,
the response at the output is:
RF
2
1+ 2 s + S
2
Where RF is the DC gain of the TIA, ω is the natural frequency of the closed loop, which can be expressed as:
=
2 GBW
RF (CIN +CF )
GBW
2 RF (CIN )
ζ is the damping factor of the loop, which can be expressed as:
=
1
2
1
2 GBW •RF (CIN +CF )
CIN +CF
•
+ RF CF + 1+ A
O
2 GBW
RF (CIN +CF )
Where CIN is the total capacitance at the inverting input
node of the op amp, GBW is the gain bandwidth of the
op amp, and AO is the DC open loop gain of the op amp.
The small capacitor CF in parallel with RF can introduce
enough damping to stabilize the loop. By assuming CIN
>> CF, the following condition needs to be met for CF,
Hence the maximum achievable bandwidth of TIA is:
fTIA (Hz) =
1000
6268-10 F03
626810 F02
100
CF >
CIN
•GBW •RF
Since LTC6268-10 is a decompensated op amp with gainof-10 stable, it requires that CIN/CF ≥ 10. Table 1 shows
the minimum and maximum CF for RF of 20k and 402k
and CIN of 1pF and 5pF.
Table 1. Min/Max CF
RF
20kΩ
402kΩ
CIN = 1pF
60fF/100fF
13fF/100fF
CIN = 5pF
140fF/500fF
31fF/500fF
626810f
For more information www.linear.com/LTC6268-10
13
LTC6268-10/LTC6269-10
APPLICATIONS INFORMATION
Achieving Higher Bandwidth with Higher Gain TIAs
Good layout practices are essential to achieving best
results from a TIA circuit. The following two examples
show drastically different results from an LTC6268-10 in
a 402k TIA. (See Figure 4.) The first example is with an
0805 resistor in a basic circuit layout. In a simple layout,
without expending a lot of effort to reduce feedback capacitance, the rise time achieved is about 87ns (Figure 5),
implying a bandwidth of 4MHz (BW = 0.35/tr). In this case,
the bandwidth of the TIA is limited not by the GBW of
the LTC6268-10, but rather by the fact that the feedback
capacitance is reducing the actual feedback impedance
(the TIA gain itself) of the TIA. Basically, it’s a resistor
bandwidth limitation. The impedance of the 402kΩ is being
reduced by its own parasitic capacitance at high frequency.
From the 4MHz bandwidth and the 402k low frequency
gain, we can estimate the total feedback capacitance as
C = 1/(2π • 4MHz • 402kΩ) = 0.1pF. That’s fairly low, but
it can be reduced further.
With some extra layout techniques to reduce feedback
capacitance, the bandwidth can be increased. Note that
PARASITIC
FEEDBACK C
–
K
PD
CASE
A
OUTPUT
(500MV/DIV)
+2.5
LTC6268-10
VOUT
+
–2.5
Figure 7 shows the dramatic increase in bandwidth simply
by careful attention to low capacitance methods around
the feedback resistance. Bandwidth and rise time went
from 4MHz (87ns) to 34MHz (10.3ns), a factor of 8. The
ground trace used for LTC6268-10 was much wider than
that used in the case of the LTC6268 (see LTC6268 data
sheet), extending under the entire resistor dielectric. Assuming all the bandwidth limit is due to feedback capacitance (which isn't fair), we can calculate an upper limit of
Cf = 1/(2π • 402kΩ • 34MHz) = 11.6fF.
LASER DRIVE
(2mA/DIV)
402k
IPD
we are increasing the effective “bandwidth” of the 402k
resistance. A very powerful method to reduce feedback
capacitance is to shield the E field paths that give rise to
the capacitance. In this particular case, the method is to
place a ground trace between the resistor pads. Such a
ground trace shields the output field from getting to the
summing node end of the resistor and effectively shunts
the field to ground instead. The trace increases the output
load capacitance very slightly. See Figure 6 for a pictorial
representation.
20ns/DIV
626810 F05
Figure 5. Time Domain Response of 402kΩ TIA without
Extra Effort to Reduce Feedback Capacitance. Rise Time
Is 87ns and BW Is 4MHz
–2.5
626810 F04
PD: OSI FCI-125G-006
Figure 4. LTC6268-10 and Low Capacitance Photodiode
in a 402kΩ TIA
14
626810f
For more information www.linear.com/LTC6268-10
LTC6268-10/LTC6269-10
APPLICATIONS INFORMATION
CERAMIC R SUBSTRATE
E
RESISTIVE
ELEMENT
ENDCAP
IPD
K
G
A
FR4
K
LTC6268-10
VOUT
G
A
E FIELD ⇒ C
–2.5
E
RESISTIVE
ELEMENT
ENDCAP
IPD
–
+
CERAMIC R SUBSTRATE
–
FR4
LTC6268-10
+
–2.5
EXTRA GND
TRACE UNDER
RESISTOR
VOUT
TAKE E FIELD TO GND,
MUCH LOWER C
626810 F06
Figure 6. A Normal Layout at Left and a Field-Shunting Layout at Right. Simply Adding a Ground Trace Under the Feedback Resistor
Does Much to Shunt Field Away from the Feedback Side and Dumps It to Ground. Note That the Dielectric Constant of Fr4 and
Ceramic Is Typically 4, so Most of the Capacitance Is in the Solids and Not Through the Air. Feedback C is Reduced from 100fF at Left
to 11.6fF at Right
Maintaining Ultralow Input Bias Current
Leakage currents into high impedance signal nodes can
easily degrade measurement accuracy of fA signals. High
temperature applications are especially susceptible to these
issues. For humid environments, surface coating may be
necessary to provide a moisture barrier.
There are several factors to consider in a low input bias
current circuit. At the femtoamp level, leakage sources can
come from unexpected sources including adjacent signals
on the PCB, both on the same layer and from internal
layers, any form of contamination on the board from the
assembly process or the environment, other components
on the signal path and even the plastic of the device package. Care taken in the design of the system can mitigate
these sources and achieve excellent performance.
LASER DRIVE
(2mA/DIV)
OUTPUT
(500MV/DIV)
20ns/DIV
626810 F07
Figure 7. LTC6268-10 in a 402kΩ TIA with Extra
Layout Effort to Reduce Feedback Capacitance Achieves
10.3ns Total System Rise Time, or 34MHz Total System
Bandwidth
The choice of device package should be considered because
although each has the same die internally, the pin spacing
and adjacent signals influence the input bias current. The
LTC6268-10/LTC6269-10 is available in SOIC, MSOP,
DFN and SOT-23 packages. Of these, the SOIC has been
designed as the best choice for low input bias current. It
has the largest lead spacing which increases the impedance of the package plastic and the pinout is such that the
two input pins are isolated on the far side of the package
from the other signals. The gull-wing leads on this package also allow for better cleaning of the PCB and reduced
contamination-induced leakage. The other packages have
advantages in size and pin count but do so by reducing
the input isolation. Leadless packages such as the DFN
offer the minimum size but have the smallest pin spacing
and may trap contaminants under the package.
The material used in the construction of the PCB can
sometimes influence the leakage characteristics of the
design. Exotic materials such as Teflon can be used to
improve leakage performance in specific cases but they
are generally not necessary if some basic rules are applied
in the design of conventional FR4 PCBs. It is important to
keep the high impedance signal path as short as possible
on the board. A node with high impedance is susceptible
to picking up any stray signals in the system so keeping it
as short as possible reduces this effect. In some cases, it
may be necessary to have a metallic shield over this portion of the circuit. However, metallic shielding increases
capacitance. Another technique for avoiding leakage paths
is to cut slots in the PCB. High impedance circuits are also
626810f
For more information www.linear.com/LTC6268-10
15
LTC6268-10/LTC6269-10
APPLICATIONS INFORMATION
susceptible to electrostatic as well as electromagnetic effects. The static charge carried by a person walking by the
circuit can induce an interference on the order of 100’s of
femtoamps. A metallic shield can reduce this effect as well.
The layout of a high impedance input node is very important.
Other signals should be routed well away from this signal
path and there should be no internal power planes under
it. The best defense from coupling signals is distance and
this includes vertically as well as on the surface. In cases
where the space is limited, slotting the board around the
high impedance input nodes can provide additional isolation and reduce the effect of contamination. In electrically
noisy environments the use of driven guard rings around
these nodes can be effective (see Figure 8). Adding any
additional components such as filters to the high impedance input node can increase leakage. The leakage current
of a ceramic capacitor is orders of magnitude larger than
the bias current of this device. Any filtering will need to
be done after this first stage in the signal chain.
RF§
SD
NC
VBIAS
–IN
‡ V–IN
LEAKAGE
CURRENT
LTC6268-10
S8
V+
OUT
+IN
NC
V–
NO SOLDER
MASK OVER
GUARD RING
LOW IMPEDANCE ‡ NO LEAKAGE CURRENT. V–IN = VGRD
NODE ABSORBS § AVOID DISSIPATING SIGNIFICANT AMOUNTS OF POWER IN THIS RESISTOR.
LEAKAGE CURRENT
IT WILL GENERATE THERMAL GRADIENTS WITH RESPECT TO THE INPUT PINS
AND LEAD TO THERMOCOUPLE-INDUCED ERROR.
(a)
GUARD RING
VBIAS
RF
HIGH-Z SENSOR
VIN
–+
V+
RIN
–
LEAKAGE
CURRENT
LTC6268-10
VOUT
+
V–
LEAKAGE CURRENT IS ABSORBED BY GROUND INSTEAD OF
CAUSING A MEASUREMENT ERROR.
626810 F8
(b)
Figure 8. Example Layout of Inverting Amplifier
(or Transimpedance) with Leakage Guard Ring
Driving Capacitive Load
The layout of the output node is also very important since
LTC6268-10/LTC6269-10 is very sensitive to capacitive
loading due to the very high gain-bandwidth-product. Appreciable ringing will be observed when capacitive loading
is more than 5pF.
Low Input Offset Voltage
The LTC6268-10 has a maximum offset voltage of ±2.5mV
(PNP region) over temperature. The low offset voltage is
essential for precision applications. There are 2 different input stages that are used depending on the input
common mode voltage. To increase the versatility of the
LTC6268-10, the offset voltages are trimmed for both
regions of operation.
16
GUARD RING
HIGH-Z
SENSOR
(RIN)
Rail-to-Rail Output
The LTC6268-10 has a rail-to-rail output stage that has
excellent output drive capability. It is capable of delivering over ±40mA of output drive current over temperature.
Furthermore, the output can reach within 200mV of either
rail while driving ±10mA. Attention must be paid to keep
the junction temperature of the IC below 150°C.
Input Protection
To prevent breakdown of internal devices in the input stage,
the two op amp inputs should NOT be separated by more
than 2.0V. To help protect the input stage, internal circuitry
will engage automatically if the inputs are separated by
>2.0V and input currents will begin to flow. In all cases,
care should be taken so that these currents remain less
than 1mA. Additionally, if only one input is driven, internal circuitry will prevent any breakdown condition under
626810f
For more information www.linear.com/LTC6268-10
LTC6268-10/LTC6269-10
APPLICATIONS INFORMATION
transient conditions. The worst-case differential input
voltage usually occurs when the +input is driven and the
output is accidentally shorted to ground while in a unity
gain configuration.
ESD
ESD Protection devices can be seen in the simplified schematic. The +IN and –IN pins use a sophisticated method
of ESD protection that incorporates a total of 4 reversebiased diodes connected as 2 series diodes to each rail.
To maintain extremely low input bias currents, the center
node of each of these series diode chains is driven by a
buffered copy of the input voltage. This maintains the two
diodes connected directly to the input pins at low reverse
bias, minimizing leakage current of these ESD diodes to
the input pins.
Shutdown
The LTC6268-10S6, LTC6268-10S8, and LTC6268-10DD
have SHDN pins that can shut down the amplifier to less
than 1.2mA supply current per amplifier. The SHDN pin
voltage needs to be within 0.75V of V– for the amplifier
to shut down. During shutdown, the output will be in a
high output resistance state, so the LTC6268-10 is suitable for multiplexer applications. The internal circuitry is
kept in a low current active state for fast recovery. When
left floating, the SHDN pin is internally pulled up to the
positive supply and the amplifier is enabled.
The remaining pins have traditional ESD protection, using
reverse-biased ESD diodes connected to each power supply
rail. Care should be taken to make sure that the voltages
on these pins do not exceed the supply voltages by more
than 100mV or these diodes will begin to conduct large
amounts of current.
626810f
For more information www.linear.com/LTC6268-10
17
LTC6268-10/LTC6269-10
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
0.62
MAX
2.90 BSC
(NOTE 4)
0.95
REF
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
18
0.01 – 0.10
1.00 MAX
DATUM ‘A’
1.90 BSC
S6 TSOT-23 0302
626810f
For more information www.linear.com/LTC6268-10
LTC6268-10/LTC6269-10
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
8
.245
MIN
.160 ±.005
.010 – .020
× 45°
(0.254 – 0.508)
NOTE:
1. DIMENSIONS IN
5
.150 – .157
(3.810 – 3.988)
NOTE 3
1
RECOMMENDED SOLDER PAD LAYOUT
2
.053 – .069
(1.346 – 1.752)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
6
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
.008 – .010
(0.203 – 0.254)
7
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
3
4
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
SO8 REV G 0212
626810f
For more information www.linear.com/LTC6268-10
19
LTC6268-10/LTC6269-10
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev K)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074)
1
1.88 ±0.102
(.074 ±.004)
0.29
REF
1.68
(.066)
0.889 ±0.127
(.035 ±.005)
0.05 REF
5.10
(.201)
MIN
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
1.68 ±0.102 3.20 – 3.45
(.066 ±.004) (.126 – .136)
8
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.65
(.0256)
BSC
0.42 ±0.038
(.0165 ±.0015)
TYP
8
7 6 5
0.52
(.0205)
REF
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1
2 3
4
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS8E) 0213 REV K
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
20
626810f
For more information www.linear.com/LTC6268-10
LTC6268-10/LTC6269-10
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
R = 0.125
TYP
6
0.40 ±0.10
10
1.65 ±0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.75 ±0.05
0.00 – 0.05
5
1
(DD) DFN REV C 0310
0.25 ±0.05
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
626810f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility
is assumed
for its use.
Linear Technology Corporation makes no representaFor more
information
www.linear.com/LTC6268-10
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
21
LTC6268-10/LTC6269-10
TYPICAL APPLICATION
100kΩ Gain 90MHz Transimpedance Amplifier
100kΩ TIA Frequency Response
109
100kΩ
2.5V
103
100
–
LTC6268-10
+
VOUT = –IPD • 100k
BW = 90MHz
GAIN (dBΩ)
2.5V
PD
IPD
106
PARASITIC
FEEDBACK C
97
94
91
88
–2.5V
85
626810 TA02
PD = OSI OPTOELECTRONICS, FCI-125G-006
OUTPUT NOISE = 20mVP-P MEASURED ON A 100MHz BW
82
79
1M
10M
FREQUENCY(Hz)
100M
626810 TA3
RELATED PARTS
PART NUMBER
Op Amps
LTC6268/LTC6269
LTC6244
LTC6240/LTC6241/
LTC6242
LTC6252/LTC6253/
LTC6254
LTC6246/LTC6247/
LTC6248
LT1818
LT6236
LT6411
SAR ADC
LTC2376-18/
LTC2377-18/
LTC2378-18/
LTC2379-18
DESCRIPTION
COMMENTS
500MHz Ultra-Low Bias Current FET Input Op Amp
Dual 50MHz, Low Noise, Rail-to-Rail, CMOS Op Amp
18MHz, Low Noise, Rail-to-Rail Output, CMOS Op Amp
Unity Gain Stable, Ultra Low Input Bias Current (3fA), 500MHz GBW
Unity Gain Stable, 1pA Input Bias Current, 100μV Max Offset.
18MHz GBW, 0.2pA Input Current, 125μV Max Offset.
720MHz, 3.5mA Power Efficient Rail-to-Rail I/O Op Amp
720MHz GBW, Unity Gain Stable, Low Noise
180MHz, 1mA Power Efficient Rail-to-Rail I/O Op Amps
180MHz GBW, Unity Gain Stable, Low Noise
400MHz, 2500V/µs, 9mA Single Operational Amplifier
Unity Gain Stable, 6nV/√Hz Unity Gain Stable
215MHz, Rail-to-Rail Output, 1.1nV/√Hz, 3.5mA Op Amp Family 350μV Max Offset Voltage, 3V to 12.6V Supply
650MHz Differential ADC Driver/Dual Selectable Amplifier
SR 3300V/µs, 6ns 0.1% Settling.
18-Bit, 250ksps to 1.6Msps, Low Power SAR ADC, 102dB SNR
22 Linear Technology Corporation
18mW at 1.6Msps, 3.4μW at 250sps, –126dB THD.
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC6268-10
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC6268-10
626810f
LT 0415 • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2015
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