LTC6360
Very Low Noise Single-Ended
SAR ADC Driver
with True Zero Output
Description
Features
The LTC®6360 is a very low noise, high precision, high
speed amplifier suitable for driving SAR ADCs. The
LTC6360 features a total output noise of 2.3nV/√Hz
combined with 150ns settling time to 16-bit levels (AV = 1).
Output Swings to True Zero on Single Supply
2.3nV/√Hz Noise Density
Fast Settling Time: 150ns, 16-Bit, 4V Step
110dB SNR in 3MHz Bandwidth
Low Distortion, HD2 = –103dBc and HD3 = –109dBc
for 4VP-P Output at 40kHz
n Low Offset Voltage: 250µV Max
n Low Power Shutdown: 350µA Max
n 3mm × 3mm 8-Pin DFN and 8-lead MSOP Packages
n
n
n
n
n
While powered from a single 5V supply, the amplifier output can swing to 0V while maintaining high linearity. This
is made possible with the inclusion of a very low noise
on-chip charge pump that generates a negative voltage
to bias the output stage of the amplifier, increasing the
allowable negative voltage swing.
Applications
The LTC6360 is available in a compact 3mm × 3mm,
8-pin leadless DFN package and an 8-pin MSOP package
with exposed pad and operates over a –40°C to 125°C
temperature range.
16-Bit and 18-Bit SAR ADC Driver
High Speed Buffer Amplifiers
n Low Noise Signal Processing
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
Harmonic Distortion vs
Output Amplitude
ADC Driver
–60
0.1µF
1µF
5V
+
–
–80
+IN
SHDN
+
LTC6360
–
CPI
DISTORTION (dBc)
VIN
0V TO 4V
fIN = 20kHz
VOUT = 0V TO VP-P
–70
CPO
CHARGE
PUMP
GND
–90
–100
–110
HD2
–120
–IN
OUT
VCC
VDD
5V
–130
5V
10Ω
0.1µF
RADC
–140
10µF
HD3
0
1
2
3
VOUT (VP-P)
4
5
6360 TA01b
ADC
330pF
6360 TA01a
6360f
1
LTC6360
Absolute Maximum Ratings
(Note 1)
Total Supply Voltage
(VCC/VDD – GND)..................................................5.5V
Input Current (Note 2)........................................... ±10mA
Output Short Circuit Duration (Note 3)............. Indefinite
Operating Ambient Temperature Range
(Note 4)................................................... –40°C to 125°C
Specified Temperature Range (Note 5)..... –40°C to 125°C
Maximum Junction Temperature........................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) MS8E Only....... 300°C
Pin Configuration
TOP VIEW
–IN
1
OUT
2
VCC
3
VDD
4
TOP VIEW
8 +IN
9
GND
–IN
OUT
VCC
VDD
7 SHDN
6 CPI
5 CPO
1
2
3
4
9
GND
8
7
6
5
+IN
SHDN
CPI
CPO
MS8E PACKAGE
8-LEAD PLASTIC MSOP WITH EXPOSED PAD
DD-8 PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN 9) PCB CONNECTION TO GND
TJMAX = 150°C, θJA = 43°C/W
EXPOSED PAD (PIN 9) PCB CONNECTION TO GND
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6360CDD#PBF
LTC6360CDD#TRPBF
LFQT
8-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC6360IDD#PBF
LTC6360IDD#TRPBF
LFQT
8-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6360HDD#PBF
LTC6360HDD#TRPBF
LFQT
8-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC6360CMS8E#PBF
LTC6360CMS8E#TRPBF
LTFQS
8-Lead Plastic MSOP
0°C to 70°C
LTC6360IMS8E#PBF
LTC6360IMS8E#TRPBF
LTFQS
8-Lead Plastic MSOP
–40°C to 85°C
LTC6360HMS8E#PBF
LTC6360HMS8E#TRPBF
LTFQS
8-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
6360f
2
LTC6360
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless noted otherwise, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V. See
Figure 1 for circuit configuration.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage (MS8E)
V+IN = 0V
MIN
TYP
MAX
UNITS
30
250
600
µV
µV
30
250
600
µV
µV
40
300
700
µV
µV
90
400
900
µV
µV
90
400
900
µV
µV
170
600
1200
µV
µV
l
V+IN = 2V
l
V+IN = 4.25V
l
VOS
Input Offset Voltage (DD8)
V+IN = 0V
l
V+IN = 2V
l
V+IN = 4.25V
l
VOS/∆T
Offset Voltage Drift
IB
Input Bias Current (at +IN, –IN)
l
V+IN = 0V
–30
–39
–17
µA
µA
–28
–36
–15
l
µA
µA
–26
–31
–13.5
l
µA
µA
V+IN = 4.25V
Input Offset Current (at +IN, –IN)
V+IN = 0V
V+IN = 2V
V+IN = 4.25V
en
Input Voltage Noise Density
f = 1MHz
in
Input Current Noise Density
f = 1MHz
SNR
Signal to Noise Ratio
VOUT = 4VP-P, 3MHz Noise Bandwidth
VCMR
Input Common Mode Voltage Range
Guaranteed by CMRR
RIN
Input Resistance
Differential Mode
Common Mode
CIN
Input Capacitance
+IN, –IN
AVOL
Large Signal Voltage Gain
VOUT = 0V to 4.5V
CMRR
Common Mode Rejection Ratio
µV/°C
l
V+IN = 2V
IOS
1.3
0.1
0.1
0.1
l
l
l
1.0
1.0
1.0
2.3
nV/√Hz
3
pA/√Hz
110
l
µA
µA
µA
0
dB
4.25
V
8
940
kΩ
kΩ
2
pF
235
200
1000
l
V/mV
V/mV
V+IN = V–IN = 0V to 3V
l
83
114
dB
V+IN = V–IN = 0V to 4.25V (MS8E)
l
78
111
dB
V+IN = V–IN = 0V to 4.25V (DD8)
l
75
96
dB
99
dB
PSRR
Power Supply Rejection Ratio
(∆VS/∆VOS)
VCC = 4.75V to 5.25V
VS
Supply Voltage
VCC = VDD
INL
DC Linearity (Note 6)
V+IN = 0V to 4.25V
VOH
Output Voltage High
No Load
Sourcing 1mA
l
l
VOL
Output Voltage Low
No Load
Sinking 1mA
l
l
ISC
Output Short Circuit Current
Sourcing, Output Shorted to GND,
V+IN – V–IN = 200mV
18
16
45
l
mA
mA
Sinking, Output Shorted to VCC,
V+IN – V–IN = –200mV
4.1
3.2
5.8
l
mA
mA
l
4.75
4.80
4.75
5
5.25
V
40
µV
4.91
4.89
V
V
–0.48
–0.47
–0.20
–0.15
V
V
6360f
3
LTC6360
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless noted otherwise, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V. See
Figure 1 for circuit configuration.
SYMBOL
PARAMETER
CONDITIONS
VL
SHDN Pin Input Voltage, Logic Low
l
MIN
VH
SHDN Pin Input Voltage, Logic High
l
ISHDNH
SHDN Pin Current, Logic High
VSHDN = 5V
l
ISHDNL
SHDN Pin Current, Logic Low
VSHDN = 0V
l
ICC
VCC Supply Current
VSHDN = 2.0V
TYP
0.8
2.0
100
–15
VDD Supply Current
VSHDN = 2.0V
–9.5
Total Supply Current ICC + IDD
VSHDN = 2.0V
V
nA
µA
6.6
8
9
mA
mA
7.0
9.5
10
mA
mA
13.6
17.5
19
mA
mA
110
200
µA
l
ITOT
UNITS
V
l
IDD
MAX
l
ICC(SHDN)
VCC Supply Current in Shutdown
VSHDN = 0.8V
l
IDD(SHDN)
VDD Supply Current in Shutdown
VSHDN = 0.8V
l
80
150
µA
ITOT (SHDN)
Total Supply Current ICC + IDD in
Shutdown
VSHDN = 0.8V
l
190
350
µA
GBW
Gain-Bandwidth Product
Noninverting, f = 1MHz
BW
Closed Loop –3dB Bandwidth
VOUT = 50mVP-P, AV = 1
FPBW
Full Power Bandwidth (Note 7)
SR
Slew Rate
HD2/HD3
Harmonic Distortion
HD2/HD3
1
GHz
250
MHz
VOUT = 0V to 4V
2.7
MHz
AV = –1
Rising
Falling
135
95
V/µs
V/µs
VOUT = 0V to 2V
fIN = 10kHz
fIN = 40kHz
fIN = 1MHz
–121/–130
–121/–123
–96/–116
dBc
dBc
dBc
Harmonic Distortion
VOUT = 0V to 4V
fIN = 10kHz
fIN = 40kHz
fIN = 1MHz
–101/–110
–103/–109
–87/–105
dBc
dBc
dBc
tS
Settling Time
4V Step
0.25%
0.025%
0.0015% (±1LSB, 16-Bit, Falling Edge)
45
110
150
ns
ns
ns
150
tOVDR
Overdrive Recovery Time
V+IN to GND and VCC
30
ns
tON
Turn-On Time
VSHDN = 0V to 5V
1
µs
tOFF
Turn-Off Time
VSHDN = 5V to 0V
0.3
µs
VCPO
CPO Output Voltage
VCPORIPPLE
CPO Ripple Voltage
No External CPO/CPI Capacitors, 100MHz
Measurement Bandwidth
1.5
mVRMS
VOUTRIPPLE
Output Ripple Voltage
No External CPO/CPI Capacitors, 50MHz
Measurement Bandwidth
11.5
µVRMS
fRIPPLE
Ripple Frequency
l
l
ICPO(MAX)
Maximum Continuous CPO Output
Current
VCPO ≤ –0.4V (Note 8)
RCPO
CPO DC Output Impedance
ICPO = 0 to 3.5mA (Note 8)
l
–0.8
–0.6
9.5
9.25
10
3.5
4.5
30
–0.3
10.5
10.75
V
MHz
MHz
mA
65
Ω
6360f
4
LTC6360
Electrical Characteristics
meet specified performance from –40°C to 125°C, but are not tested or
QA sampled at these temperatures. The LTC6360I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6360H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 6: DC linearity is calculated by measuring the output vs input voltage
and calculating the maximum deviation from the least squares best fit line
at 100mV increments.
Note 7: FPBW is determined from distortion performance with HD2, HD3
< –70dBc as the criteria for a valid output. FPBW is limited by the charge
pump current sinking capability. See text for details.
Note 8: ICPO(MAX) and RCPO are measured with CPO disconnected from
CPI and CPI driven by external –0.7V source.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Inputs are protected by back-to-back diodes and diodes to each
supply. If the inputs are taken beyond the supplies or the differential input
voltage exceeds 0.7V, the input current must be limited to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 4: The LTC6360C/LTC6360I/LTC6360H are guaranteed functional over
the temperature range –40°C to 125°C.
Note 5: The LTC6360C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6360C is designed, characterized and expected to
Typical
Performance Characteristics A = 25°C, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V,
T
see Figure 1 for circuit configuration.
VOS Distribution, MS8E (PNP Stage)
80
70
NUMBER OF UNITS
NUMBER OF UNITS
440 TYPICAL UNITS
70 V+IN = 2V
50
40
30
80
440 TYPICAL UNITS
V+IN = 4V
440 TYPICAL UNITS
70 V+IN = 2V TO 4V
60
NUMBER OF UNITS
80
60
∆VOS Distribution, MS8E
(PNP to NPN Stage)
VOS Distribution, MS8E (NPN Stage)
50
40
30
50
40
30
20
20
20
10
10
10
0
50 100 150 200
–200 –150 –100 –50 0
INPUT OFFSET VOLTAGE (µV)
0
50 100 150 200
–200 –150 –100 –50 0
INPUT OFFSET VOLTAGE (µV)
6360 G01
0
50 100 150 200
–200 –150 –100 –50 0
CHANGE IN INPUT OFFSET VOLTAGE (µV)
6360 G02
Offset Voltage vs Input Common
Mode Voltage
500
300
6360 G03
Input Bias Current vs Input
Common Mode Voltage
VOS vs Temperature
20
15
400
100
0
–100
TA = –40°C
TA = 25°C
TA = 125°C
–200
–300
–0.5
10
300
INPUT BIAS CURRENT (µA)
200
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
60
200
V+IN = 2V
100
0
–100
–200
V+IN = 4V
–300
4.5
6360 G04
–500
–50
0
–5
–10
–15
–20
–25
TA = 125°C
TA = 25°C
TA = –40°C
–30
–400
1.5
2.5
0.5
3.5
INPUT COMMON MODE VOLTAGE (V)
5
–35
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6360 G05
–40
–1
1
2
3
0
4
INPUT COMMON MODE VOLTAGE (V)
5
6360 G06
6360f
5
LTC6360
T
Typical
Performance Characteristics A = 25°C, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V,
see Figure 1 for circuit configuration.
Total Supply Current vs
Temperature
Input Bias Current vs Temperature
–6
16
Total Supply Current in Shutdown
vs Temperature
300
VSHDN = 5V
VSHDN = 0V
V+IN = 4V
–10
–12
–14
V+IN = 2V
–16
15
SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)
INPUT BIAS CURRENT (µA)
–8
14
13
250
200
150
–18
–20
–50
0
–25
25
50
75
TEMPERATURE (°C)
100
12
–50
125
–25
0
25
50
75
TEMPERATURE (°C)
100
Total Supply Currents vs Supply
Voltage
10
8
6
14
10
8
6
4
2
2
0
0
2
1
3
0
5
4
4
12
4
SUPPLY VOLTAGE (V)
VOUT
2
TA = 125°C
TA = 25°C
TA = –40°C
0
1
2
3
4
0
VCPO
–1
5
5µs/DIV
6360 G11
Output Settling Time vs
Output Step
0.1Hz to 10Hz Voltage Noise
100
120
2000
10
100
1000
SETTLING TIME (ns)
VOLTAGE NOISE (nV)
1500
500
0
–500
TO 1mV
80
60
40
TO 10mV
–1000
20
–1500
10
100
1k
6360 G12
SHDN PIN VOLTAGE (V)
Input Voltage Noise vs Frequency
VOLTAGE NOISE (nV/√Hz)
3
1
6360 G10
1
125
VSHDN
5
VOLTAGE (V)
12
100
6
16
14
25
50
75
TEMPERATURE (°C)
Turn-On and Turn-Off Transient
Response
18
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
16
0
6360 G09
Total Supply Currents vs
SHDN Voltage
TA = 125°C
TA = 25°C
TA = –40°C
18
–25
6360 G08
6360 G07
20
100
–50
125
10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
6360 G13
–2000
TIME (1s/DIV)
6360 G14
0
–4
–3
–2
–1
0
1
2
OUTPUT STEP (V)
3
4
6360 G15
6360f
6
LTC6360
T
Typical
Performance Characteristics A = 25°C, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V,
see Figure 1 for circuit configuration.
Output Low Voltage vs
Load Current
Output High Voltage vs
Load Current
–0.2
–0.3
–0.4
TA = 125°C
TA = 25°C
TA = –40°C
–0.6
0
2
1
3
4
LOAD CURRENT (mA)
5
100
4
10
3
2
1
0
6
TA = 125°C
TA = 25°C
TA = –40°C
0
20
10
30
40
LOAD CURRENT (mA)
20
6
10
5
SINKING, OUTPUT SHORTED TO VCC
–20
SOURCING, OUTPUT SHORTED TO GROUND
2
–50
–1
100
VOUT
1
0
25
50
0
75
TEMPERATURE (°C)
0.01
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
100
1000
6360 G18
120
AV = 5
SEE TABLE 1 FOR CIRCUIT
COMPONENT VALUES
3
–40
–25
0.1
Common Mode Rejection Ratio
vs Frequency
4
–10
–60
–50
1
Output Overdrive Recovery
VIN, VOUT (V)
SHORT CIRCUIT CURRENT (mA)
Output Short Circuit Current vs
Temperature
–30
60
AV = 1
6360 G17
6360 G16
0
50
COMMON MODE REJECTION RATIO (dB)
–0.5
Output Impedance vs Frequency
5
OUTPUT IMPEDANCE (Ω)
–0.1
OUTPUT HIGH VOLTAGE (V)
OUTPUT LOW VOLTAGE (V)
0
VIN x 5
–2
125
500ns/DIV
100
80
60
40
20
0
0.1
6360 G20
1
1000
10
100
FREQUENCY (MHz)
6360 G21
6360 G19
25
10
GAIN MAGNITUDE (dB)
15
AV = 5
AV = 2
5
0
–5
0.1
AV = 1
1
10
100
FREQUENCY (MHz)
1000
6360 G22
PHASE
100
0
–2
–4
–6
SEE TABLE 1 FOR CIRCUIT
COMPONENTS VALUES
135
120
2
AV = 10
180
–8
0.1
TA = 125°C
TA = 25°C
TA = –40°C
1
10
100
FREQUENCY (MHz)
1000
6360 G23
90
80
45
60
0
GAIN
40
–45
PHASE (DEG)
GAIN (dB)
20
140
4
AV = 20
GAIN (dB)
30
Open Loop Gain and Phase vs
Frequency
Frequency Response vs
Temperature
Frequency Response vs Gain
20
–90
0
–135
–20
10
100
1k
10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
–180
6360 G23a
6360f
7
LTC6360
T
Typical
Performance Characteristics A = 25°C, VCC = VDD = 5V, V+IN = 2V, VSHDN = 5V,
see Figure 1 for circuit configuration.
Small Signal Step Response
Large Signal Step Response
2.10
Slew Rate vs Filter Capacitor
5
1000
RFILT = 10Ω
OUTPUT VOLTAGE (V)
2.00
1.95
3
SLEW RATE (V/µs)
OUTPUT VOLTAGE (V)
4
2.05
2
1
100
RISING
FALLING
10
0
1.90
200ns/DIV
–1
6360 G24
200ns/DIV
1
100
6360 G25
1000
FILTER CAPACITOR (pF)
10000
6360 G26
Harmonic Distortion vs Output
Amplitude
Slew Rate vs Temperature
160
–60
RFILT = 10Ω
CFILT = 330pF
RISING
140
Harmonic Distortion vs Frequency
–60
fIN = 20kHz
VOUT = 0V TO VP-P
–70
–80
FALLING
100
80
–90
–100
–110
HD2
–120
60
40
–50
–130
25
50
0
75
TEMPERATURE (°C)
–25
100
–140
125
DISTORTION (dBc)
DISTORTION (dBc)
SLEW RATE (V/µs)
–80
120
1
2
3
VOUT (VP-P)
4
5
CPO RIPPLE FREQUENCY (MHz)
CPO VOLTAGE (V)
0.2
0
–0.2
–0.4
TA = 125°C
TA = 25°C
TA = –40°C
2
3
HD3
1
10
FREQUENCY (kHz)
5
6
4
CPO LOAD CURRENT (mA)
100
6360 G29
10.4
0.4
1
–140
0.1
10.5
CPO PIN DISCONNECTED FROM CPI PIN
0.8 CPI PIN CONNECTED TO EXTERNAL
SOURCE
0.6
0
HD2
CPO Ripple Frequency vs
Temperature
1.0
–1.0
–110
6360 G28
CPO Voltage vs CPO Load Current
–0.8
–100
–130
HD3
0
–90
–120
6360 G27
–0.6
VOUT = 0V TO 2V
–70
7
10.3
10.2
10.1
10.0
9.9
9.8
9.7
9.6
8
6360 G30
9.5
–50
–25
0
25
75
50
TEMPERATURE (°C)
100
125
6360 G31
6360f
8
LTC6360
Pin Functions
–IN (Pin 1): Inverting Amplifier Input.
CPI (Pin 6): Input for Amplifier Negative Rail. Normally
connected to CPO.
OUT (Pin 2): Output of Amplifier.
VCC (Pin 3): Analog Power Supply. Normally connected
to a 5V supply.
VDD (Pin 4): Digital Power Supply. Normally connected
to VCC.
CPO (Pin 5): Output of Charge Pump. This pin is internally
biased at –0.6V below GND.
SHDN (Pin 7): Shutdown Pin. If tied high or left floating,
the part is enabled. If tied low, the part is disabled and
draws less than 350µA of supply current.
+IN (Pin 8): Noninverting Amplifier Input. Provides a high
impedance input.
GND (Exposed Pad Pin 9): Ground Pin. Normally connected to ground.
Block Diagram
+
–
VIN
1µF
8
7
+IN
GND
6
SHDN
VCC
0.1µF
GND
5
CPI
VCC
GND
CPO
VCC
VCC SHDN
CHARGE
PUMP
–
GND
GND CPI
VCC
9
GND
GND
VCC
–IN
1
VDD
VDD SHDN
+
GND
GND
2
VDD
VCC
OUT
3
4
6360 BD
5V
RFILT
10Ω
0.1µF
10µF
CFILT
330pF
6360f
9
LTC6360
TEST CIRCUIT
VSHDN
+
–
VIN
+IN
0.1µF
+
–
SHDN
CPI
1µF
CPO
LTC6360
+
CHARGE
PUMP
–
–IN
OUT
VCC
GND
VDD
6360 F01
V+
RFILT
10Ω
CFILT
330pF
0.1µF
10µF
VOUT
Figure 1. Test Circuit
6360f
10
LTC6360
Operation
The LTC6360 is a low noise amplifier suitable for driving
single-ended high performance successive approximation
register (SAR) ADCs. The LTC6360 uses a single amplifier with negative charge pump topology as shown in the
Block Diagram.
The output can swing from –0.48V to 4.91V. The amplifier is designed to drive a series 10Ω resistor and 330pF
capacitor filter network to ground, although larger load
capacitances can be driven.
An on-chip low noise charge pump generates a small
negative voltage (typically –0.6V) at the CPO pin. This
negative voltage is normally connected to the amplifier’s
output stage via the CPI pin, allowing the output to swing
to true zero on a single 5V supply. Compared to typical
rail-to-rail output amplifiers that can only swing to within
a few hundred millivolts of ground, the LTC6360 provides
improved linearity and increased functionality for applications that benefit from a true zero output swing.
a single 5V rail. This provides a simple interface for 5V
ADCs with a 4.096V full-scale range.
Noninverting gain (shown in Figure 3) and inverting gain
(shown in Figure 4) configurations are also possible. For
best DC precision, RS should be made equal to the parallel combination of RF and RG. RS can be bypassed with a
capacitor to reduce its noise contribution.
0.1µF
CS
RS
+
–
VIN
+IN
5V
SHDN
CPI
CPO
LTC6360
+
CHARGE
PUMP
–
–IN
RG
VCC
OUT
GND
VDD
6360 F03
RF
5V
CF
The LTC6360 features a low noise amplifier that can
support a signal-to-noise ratio of 110dB over a 3MHz
noise bandwidth.
0.1µF
10µF
RFILT
VOUT
CFILT
Basic Connections
Shown in Figure 2 is a typical application for the LTC6360
as a unity gain driver. The amplifier’s two inputs (+IN and
–IN) can accommodate a voltage range of 0V to 4.25V on
Figure 3. Noninverting Gain Configuration.
0.1µF
RS
4V
VIN
VIN
0V TO 4V
1µF
5V
1µF
0.1µF
0V
+
–
1µF
5V
+IN
SHDN
CPI
CPO
LTC6360
+IN
SHDN
CPI
+
CPO
LTC6360
+
CHARGE
PUMP
–
–IN
OUT
CHARGE
PUMP
–
VCC
–IN
GND
RG
VDD
6360 F02
5V
0.1µF
10Ω
10µF
+
–
VIN
OUT
VCC
GND
VDD
6360 F04
RF
5V
CF
0.1µF
10µF
RFILT
VOUT
VOUT
CFILT
4V
330pF
0V
Figure 4. Inverting Gain Configuration
Figure 2. Unity Gain Driver.
6360f
11
LTC6360
Applications Information
Amplifier Characteristics
Figure 5 shows a simplified schematic of the LTC6360’s
amplifier. The input stage has NPN and PNP differential
pairs operating in parallel. This topology allows the inputs
to swing all the way from the negative rail to within 0.75V
of the positive supply rail. The PNP differential pair is
the primary input differential pair and is active when the
common mode voltage is less than 1.5V from the positive
rail. When the common mode voltage exceeds VCC – 1.5V,
the NPN pair is activated and the PNP is deactivated. The
input stage transconductance, gm, is maintained nearly
constant during the handover from PNP pair to NPN pair.
Additionally, a precision two-point trim algorithm is used
to maintain near constant offset voltage over the entire
input common mode range.
Input bias current flows out of the +IN and –IN inputs. The
magnitude of this current is regulated via an input current
compensation circuit which eliminates the discontinuity
and polarity reversal of input bias current that would oth-
erwise occur when transitioning from one input pair to the
other. Typical total change in input bias current over the
entire input common mode range is approximately 3.5µA.
Amplifier Feedback Components
When feedback resistors are used to set gain, care should
be taken to ensure that the pole formed by the feedback
resistors and the total capacitance at the inverting input,
–IN, does not degrade stability. For instance, to set the
LTC6360 in a gain of +2, RF and RG of Figure 3 could be
set to 2k. If the total capacitance at –IN (LTC6360 plus
PC board) were 2pF, a new pole would be formed in the
loop response at 80MHz, which could lead to instability or
ringing in the step response. A capacitor connected across
the feedback resistor and having the same value as the
total –IN parasitic capacitance will eliminate any ringing
or oscillation. Special care should be taken during layout,
including using the shortest possible trace lengths and
removing the ground plane under the –IN pin, to minimize
the parasitic capacitance.
VCC
INPUT
CURRENT
COMPENSATION
VCC
DESD1
DESD2
VCC
INPUT PAIR
CONTROL
+IN
D1
–IN
DESD3
D2
DESD5
DIFFERENTIAL
DRIVE
GENERATOR
OUT
DESD6
DESD4
VCC
6360 F05
CPI
Figure 5. Amplifier Simplified Schematic
6360f
12
LTC6360
Applications Information
Input Protection
Back-to-back diodes (D1 and D2 in Figure 5) are included
between +IN and –IN to protect the input devices. The
inputs do not have internal resistors in series with the
input transistors, a technique often used to protect the
input transistors from excessive current flow during an
overdrive condition. Adding series input resistors would
significantly degrade the low noise performance. Therefore,
if the voltage across the amplifier’s inputs is allowed to
exceed ±0.7V, steady state current conducted through the
protection diodes should be externally limited to ±10mA.
The input diodes are rugged enough to handle transient
currents due to amplifier slew rate overdrive or momentary
clipping without protection resistors.
Driving the input signal sufficiently beyond the specified
input common mode voltage range will cause the input
transistors to saturate. When saturation occurs, the amplifier loses a stage of phase inversion and the output will
begin to invert. Diode D1 or D2 (Figure 5) forward biases
and holds the output within a diode drop of the input signal.
To avoid this inversion, limit the input drive to within the
specified input common mode range.
ESD
The LTC6360 has ESD protection diodes on all inputs
and outputs. The diodes are reverse biased during normal operation. If the input pins are driven beyond either
supply, large currents will flow through these diodes. If
the current is transient and limited to 10mA or less, no
damage to the device will occur.
On-Chip Charge Pump
A low noise on-chip charge pump generates a small negative voltage that is used to bias the output stage of the
amplifier, enabling output swing below 0V. The charge
pump output voltage is typically –0.6V. Several design
techniques have been used to lower the ripple present
at OUT due to the switching action of the charge pump.
The charge pump output is made available via the CPO
pin, and the amplifier’s charge pump input at the CPI pin.
This allows additional external filtering via a capacitor
connected from CPI to GND.
The charge pump operates at a nominal frequency of
10MHz. The output voltage at CPO will have small frequency
components at multiples of 5MHz. These components
are further reduced by the PSRR of the amplifier’s output stage. The amplitude of the fundamental component
at the OUT pin is typically 1µVRMS with a 0.1µF bypass
capacitor at CPI.
Conventionally, a two chip solution is chosen to provide
output swing to true zero on a single supply: one amplifier and an inverting charge pump to provide a negative
rail. Compared to a two chip solution, the LTC6360 offers
several advantages: a more compact layout with lower
part count, lower output ripple, less EMI and lower power.
Figure 6 shows the ripple voltage spectrum at the output,
VOUT, with a 0.1µF external CPI bypass capacitor.
10
VOUT (µVRMS)
Input bias current induced DC voltage offsets can be
minimized by matching the parallel impedance of RF and
RG to the source impedance, RS. For example, in the
typical application when the amplifier is configured as a
unity gain buffer, choosing RF equal to RS will minimize
the offset. Since nonzero values of RF will contribute to the
total output noise, RF may be bypassed with a capacitor
to reduce the noise bandwidth.
INPUT GROUNDED
0.1µF CPI BYPASS CAPACITOR
1
0.1
0
20
40
60
FREQUENCY (MHz)
80
100
6360 F06
Figure 6. Output Ripple Voltage
6360f
13
LTC6360
Applications Information
The charge pump is capable of sinking up to 4.5mA of
DC current with a typical DC output impedance of 30Ω. If
more current is demanded of the charge pump, the voltage at CPO will collapse towards 0V. A diode connected
from CPO to GND limits the CPO node from being pulled
above ground by more than one diode drop.
Transient currents are absorbed by the filter capacitors
from CPO/CPI to GND. Care should be taken in selecting
the filter capacitors such that there is minimum ripple
voltage and droop during peak transient current demand.
Using multiple small surface mount capacitors is advised, with each capacitor covering a portion of the total
frequency range.
Slew Rate and Full Power Bandwidth
Additional consideration needs to be paid to the current
demanded of the charge pump. When driving a capacitive load, the LTC6360 will exhibit a clipped distortion
characteristic at a lower frequency than where slew rate
limited distortion would occur. In contrast to a traditional
amplifier, where the full power bandwidth is determined
from the amplifier’s slew rate, when driving capacitive
loads, the full power bandwidth of the LTC6360 will be
limited by the charge pump sinking capability.
The average current sunk by the charge pump when driving
a capacitive load can be approximated as:
ICP(AVG) = 2VP • CFILT • f + 1mA
(1)
where VP and f are the amplitude and frequency of the
driven signal respectively.
The maximum frequency that the charge pump can support
while maintaining the CPO pin below –0.4V is:
fFPBW = (ICP(MAX) – 1mA)/(2VP • CFILT) (2)
where ICP(MAX) is given in the specification table. Full-scale
signals beyond this frequency will cause the charge pump
to collapse towards 0V, limiting the output amplitude and
causing distortion.
Output Compensation
The LTC6360 is internally compensated to be gain of 5
stable. Lower gains require an external RC network at
the output to provide compensation. The amplifier has
been decompensated to provide the highest possible
gain-bandwidth with a typical RC load of 10Ω in series
with 330pF. The extra gain-bandwidth obtained serves to
reduce distortion over a wider bandwidth. Since an external
RC filter network is desired in most ADC applications, the
decompensation is transparent in these cases and actually
serves to improve distortion performance.
The RC network at the output contributes a pole-zero pair
that reduces the loop gain above the pole frequency. The
simplified circuit model at high frequencies is shown in
Figure 7. At high frequencies, the open-loop output impedance of the amplifier can be represented by an equivalent
resistor, ro, of 45Ω.
The pole frequency is:
fP = 1/(2π(RFILT + ro)CFILT) (3)
The zero frequency is:
fZ = 1/(2πRFILTCFILT)
(4)
which is also the –3dB bandwidth of the filter formed by
RFILT and CFILT. The zero-pole ratio is given by:
fZ /fP = 1 + ro/RFILT
TO FEEDBACK
NETWORK
VO
+
ro
–
(5)
OUT
RFILT
CFILT
6360 F07
AMPLIFIER
fZ = 1/[2πRFILTCFILT]
fρ = 1/[2π(RFILT + ro)CFILT]
Figure 7. Pole-Zero Introduced by RC Network at Output
6360f
14
LTC6360
Applications Information
The amount that the loop gain and subsequent bandwidth
will be reduced is equal to this zero-pole ratio. For example,
for 20dB of loop gain reduction (one decade bandwidth
reduction), RFILT should be made equal to 5Ω.
Figure 8 shows the open loop gain without compensation
and with a 10Ω/330pF RC compensation network. The
pole-zero can be seen to reduce the open loop gain above
10MHz, stabilizing the amplifier for unity gain applications.
140
120
PHASE
GAIN
80
45
60
0
40
–45
20
10Ω/330pF
COMPENSATED
0
–20
10
100
1k
–135
10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
Figure 8. Open Loop Gain and Phase with and without
Output Compensation
The following is a guideline for designing the RC filter to
ensure stability with a circuit gain less than five:
1. In order to sufficiently reduce the gain prior to the
unity loop gain crossover point, fC, the zero-pole ratio
should be greater than 5/NG, where NG is the circuit
noise gain. For example, based on Equation 5, a unity
gain configuration allows a maximum RFILT value of
11.25Ω.
2. The zero should be located below to the unity gain
crossover frequency, fC. Once the RC network is introduced, fC will occur at a lower frequency given by:
(6)
where fC(AMP) is the unity gain-bandwidth of the amplifier
without the RC network. Thus, the following condition
should be met:
fZ < fC(AMP)/(fZ / fP • NG)
where fC(AMP) is approximately 1GHz.
Note that for large zero-pole ratios, additional margin
may be needed. In this case, setting fZ equal to fC yields
a phase margin of at best 45°. In practice, the amplifier’s higher order poles will further reduce the phase
margin below 45°. Therefore, fZ should be made lower
than fC in order to ensure adequate phase margin. Phase
margin in the case of large pole-zero ratios case can
be estimated as tan –1(fC/fZ).
The layout of the filter RC network is critical to the stability
of the part and care should be taken to minimize parasitic
inductance in this path.
–180
6360 F08
fC = fC(AMP)/(fZ / fP • NG)
(8)
3. Select RFILT and CFILT to yield the desired filter bandwidth
while meeting the two constraints listed above.
–90
UNCOMPENSATED
CFILT > (fZ / fP • NG)/(2πRFILTfC(AMP))
Likewise for small zero-pole ratios, the pole will not
have contributed a full 90° of lagging phase prior to the
zero contributing leading phase. The requirement for
fZ being lower than fC can be relaxed in these cases.
PHASE (DEG)
GAIN (dB)
100
180
UNCOMPENSATED
10Ω/330pF
135
COMPENSATED
90
This sets a lower limit on CL of:
(7)
Table 1 lists suggested RC filter values for some common
circuit gains. Note that longer filter time constants can be
implemented by increasing the CFILT value beyond what is
shown in Table 1 without degrading stability. For large CFILT
values, it may be necessary to use multiple high quality
surface mount capacitors to reduce ESR and maintain a
high self resonant frequency.
Table 1. Component Values for Various Circuit Gains
Noise Gain (NG)
RF
CF
RG
RFILT
CFILT
1
0
DNI
DNI
10
330pF
2
2k
2pF
2k
25
150pF
5
2k
0.2pF
500
DNI
DNI
10
2k
DNI
222
DNI
DNI
20
2k
DNI
181
DNI
DNI
DNI – Do Not Install
Interfacing the LTC6360 to A/D Converters
When driving an ADC, a single-pole RC filter between
the output of the LTC6360 and the input of the ADC can
improve system performance. The sampling process
of ADCs creates a charge transient at the ADC input
6360f
15
LTC6360
Applications Information
caused by the switching of the ADC sampling capacitor.
This momentarily disturbs the output of the amplifier as
charge is transferred between amplifier and ADC. The
amplifier must recover and settle from this load transient
before the acquisition period ends. An RC network at
the output of the LTC6360 helps decouple the sampling
transient of the ADC from the amplifier, reducing the
demands on the amplifier’s output stage (see Figure 9).
The resistor at the input of the ADC minimizes the sampling
transients that discharge the RC filter capacitor.
0.1µF
1µF
+
–
+IN
SHDN
+
LTC6360
CPI
–
–IN
OUT
10Ω
The SHDN pin is 5V TTL or 3.6V CMOS level compatible.
If the SHDN pin (Pin 7) is pulled low, below 0.8V, the
LTC6360 will power down. If the pin is left open or pulled
high, above 2.0V, the part will enter normal active operation. The turn-on time between the shutdown and active
states is typically 1μs, and turn-off time is typically 0.3µs.
CPO
CHARGE
PUMP
GND
VDD
VCC
5V
0.1µF
10µF
5V
RADC
High quality resistors and capacitors should be used for
the RC filter network since these components stabilize
the internal amplifier and can also contribute their own
distortion. For lowest distortion, choose capacitors with
a high quality dielectric, such as a C0G multilayer ceramic
capacitor. Metal film surface mount resistors are more
linear than carbon types.
SHDN
5V
VIN
0V TO 4V
eleven RC time constants of a first order filter. Note also
that too small a resistor will not properly dampen the load
transient of the sampling process, prolonging the time
required for settling.
ADC
330pF
In shutdown, the output pin (OUT) appears as an open
collector with a nonlinear capacitor to ground and steering diodes to VCC and ground. Because of the nonlinear
capacitance, the output will still have the ability to sink and
source small amounts of transient current if exposed to
significant voltage transients. The input protection diodes
between +IN and –IN can still conduct if voltage transients
at the input exceed 700mV.
6360 F09
Figure 9. Driving an ADC
The filter capacitor serves to provide the bulk of the charge
during the sampling process, while the filter resistor
dampens and attenuates any charge injected by the ADC.
The RC filter has the additional benefit of band limiting
broadband output noise.
The selection of the RC time constant depends on the application; but generally, longer time constants will improve
SNR at the expense of longer settling time. Excessive
settling time can introduce gain errors and distortion
if the filter components are not perfectly linear. 16-bit
applications typically require a minimum settling time of
Noise Considerations
The LTC6360 has a low noise density en of 2.3nV/√Hz.
This is equivalent to the voltage noise of a 320Ω resistor
at the +IN input. For source resistors larger than 320Ω,
voltage noise due to the source resistance will start to
dominate. The current noise density is 3pA/√Hz, thus
source resistors larger than about 770Ω will interact with
the input current noise and result in output noise that is
amplifier current noise dominant.
Note that the parallel combination of gain setting resistors RF and RG behaves like the source resistance, RS, in
noise calculations.
6360f
16
LTC6360
Applications Information
Lower value gain and feedback resistors, RG and RF, will
result in lower output noise at the expense of increased
distortion due to increased loading of the amplifier.
External loading should not be less than 2kΩ to avoid degrading distortion performance. When using RS equal to
RF||RG, wideband noise can be substantially reduced by
bypassing with a small capacitor across RF.
Using a single pole passive RC filter network at the output
of the LTC6360 reduces the output noise bandwidth and
thereby increases the signal to noise ratio of the system.
For example, in a typical system with an output signal of 4VP-P, an RC output filter with RFILT = 10Ω and
CFILT = 330pF will reduce the total integrated noise from
57µV (250MHz –3dB bandwidth at OUT) to 27µV (48MHz
–3dB bandwidth) and improve the SNR from 90dB to 97dB.
Keep in mind that long RC time constants in the output
filter can increase the settling time at the inputs of the
ADC. Incomplete settling can cause gain errors or increase
apparent crosstalk in multiplexed systems.
Board Layout and Bypass Capacitors/DC1639A
Demoboard
It is recommended that a high quality X5R or X7R, 0.1μF
bypass capacitor be placed directly between the VCC and
the GND pin; the GND pin (exposed pad) should be tied
directly to a low impedance ground plane with minimal
routing. The CPI pin can be filtered with several high quality X5R or X7R capacitors returned to GND with minimal
trace routing. Small geometry (e.g., 0603) surface mount
ceramic capacitors have a much higher self resonant
frequency than do leaded capacitors, and perform best
with the LTC6360.
Stray parasitic capacitance at the –IN pin should be kept
to a minimum to prevent degraded stability response resulting in excessive ringing or oscillations. Traces at –IN
should be kept as short as possible, and any ground plane
should be stripped from under the pin and trace.
The RC filter network at the output serves both as a filter
and compensation network. Parasitic trace inductance
in this path will tend to destabilize the amplifier. The RC
filter network at the output should return directly to a
low impedance ground plane and trace routing should be
minimized in this path. A high quality COG/NPO surface
mount capacitor should be used to optimize distortion
performance and reduce destabilizing series resistance and
inductance. When large filter capacitor values are required,
multiple surface mount capacitors may be necessary with
the smallest-valued capacitor placed closest to the output.
The DC1639A demoboard has been designed for the evaluation of the LTC6360 following the above layout practices.
Its schematic and layout are shown in Figures 10 and 11.
6360f
17
LTC6360
Applications Information
VCC
R11
30.1k
EXT
VCM
E1
R12
20k
J1
SMA
+IN
C1
1µF
C2
OPT
0805
JP1
SHDN
1
E2
2
ENABLE
DISABLE
R13*
OPT
R3* 0Ω
R1
0Ω
V+
R2
49.9
0805
C3
OPT
C5
1µF
C4
0.1µF
3
R14
0Ω
8
+IN
7
6
SHDN CPI
LTC6360CMS8E
5
CPO
GND 9
*SEE TABLE BELOW FOR ALTERNATE VALUES
DC MODE (SHOWN)
R3 = 0Ω
INSTALL
NOT INSTALL
R13 = OPEN
OUT
2
INSTALL
R3 = 1µF
R7
INSTALL
R13 = 10k
0Ω
J2
SMA
–IN
GND GND
E4
E5
–IN
1
AC MODE
C7
OPT
R4
OPT
R6
OPT
C6
OPT
0805
R5
OPT
0805
VCC
3
VDD
4
R15
0Ω
C13
0.1µF
C8
OPT
NPO
C9
0.01µF
VCC
R8**
10Ω
R10
OPT
R9
C15**
330pF
NPO
0805
C11
10µF
0805
C12
10µF
0805
E3 +
V
4.75V TO 5.25V
C14
10µF
0805
NOTE: UNLESS OTHERWISE SPECIFIED ALL
RESISTORS: Ω, 0603, 1%, 1/10W
J3
SMA
**R8 AND C15 ARE NEEDED FOR STABILITY
OUT
0Ω
V+
C10
0.1µF
C16
OPT
NPO
0805
6360 F08
Figure 10. DC1639A Demoboard Schematic
6360f
18
LTC6360
Applications Information
6360 F11
Figure 11. DC1639A Demoboard Layout
6360f
19
LTC6360
Applications Information
Interfacing to High Voltage Signals
Using the amplifier in the inverting configuration, with a
fixed input common mode voltage, allows the input signal
to traverse a swing beyond the LTC6360 supply rails.
A practical application for the inverting gain configuration
is translating a high voltage signal to a range suitable for
a low voltage SAR ADC. For a clean interface, two conditions must be met:
1. The gain is selected so that full-scale signals at HVIN
are translated at the output of the LTC6360 to the appropriate full-scale range for the ADC.
Applying the above constraints to the design equations
gives values for RF/RG and V1:
RF / RG =
[ VOUT(MAX) – VOUT(MIN)]
[HVIN(MAX) – HVIN(MIN)]
(9)
V1 = [VFS/2 + RF/RG • HVNOM]/(1 + RF/RG) (10)
Applying these formulas to the case where ±10V input
signal is to be translated to a 0V to 4V full-scale range
yields the values shown in Figure 12.
5V
C4
0.1µF
2. VOUT = VFS/2 when HVIN is centered at HVNOM, where
VFS is the ADC full-scale input voltage and HVNOM is
the average level of the input voltage.
C1
50fF (PARASITIC)
R5
2k
R1
J1 NXP
BF862
0.1µF
0.1µF
1.67k
+
–
V1
1.67V
+IN
–
1µF
5V
SFH213
PHOTODIODE
CPI
CPO
LTC6360
+
–IN
HVIN
1µF
CHARGE
PUMP
–
10k
OUT
VCC
0V
–10V
10k
VDD
CPI
6360 F12
5V
0.1µF
+
C6
0.1µF
R3
10M
C5
0.1µF
CPO
5V
+
R6
1k CPO CPI
U3
CPI
10µF
LTC2054
6360 F13
Figure 13. Low Noise, True Zero 1MΩ DC Precise Photodiode
Transimpedance Amplifier
4V
10Ω
VOUT
330pF
10µF
U1
LTC6360
–
GND
2k
10pF
10V
R2
1k
IPD
SHDN
5V
1M
2V
0V
Figure 12. Interfacing a ±10V Input Signal to a 5V ADC
6360f
20
LTC6360
Applications Information
Low Noise, True Zero 1MΩ Photodiode
Transimpedance Amplifier
Figure 13 shows the LTC6360 applied as a transimpedance amplifier. The LTC6360 charge pump drives the
anode of the photodiode. The BF862 ultra low noise JFET
(J1) acts as a source follower, buffering the input of the
LTC6360 and making it suitable for the high impedance
feedback element R1. The BF862 has a minimum IDSS of
10mA and a pinchoff voltage between –0.3V and –1.2V.
The LTC2054 chopper stabilized op amp acts to servo
the DC voltage at the JFET gate to 0V, which allows the
output of the LTC6360 to swing to 0V when there is no
photo diode current.
Amplifier output noise density is dominated by the
130nV/√Hz of the feedback resistor at low frequency, rising
to 320nV/√Hz at 1MHz. Note that because the JFET has a
gm of approximately 1/100Ω, its attenuation looking into
R2 is only about 10%. The closed loop bandwidth using
a SFH213 photodiode was measured at approximately
3.2MHz.
6360f
21
LTC6360
Package Description
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
0.70 ±0.05
3.5 ±0.05
1.65 ±0.05
2.10 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.00 ±0.10
(4 SIDES)
R = 0.125
TYP
5
0.40 ± 0.10
8
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
4
0.25 ± 0.05
1
(DD8) DFN 0509 REV C
0.50 BSC
2.38 ±0.10
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
6360f
22
LTC6360
Package Description
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev I)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074)
1
1.88 ± 0.102
(.074 ± .004)
0.29
REF
1.68
(.066)
0.889 ± 0.127
(.035 ± .005)
0.05 REF
5.23
(.206)
MIN
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
1.68 ± 0.102 3.20 – 3.45
(.066 ± .004) (.126 – .136)
8
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
TYP
8
7 6 5
0.52
(.0205)
REF
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
1
2 3
4
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS8E) 0910 REV I
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
6360f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC6360
Typical Application
Precision Ultralow Noise True Zero Photodiode Amplifier
1M 1%
5V
40fF
(PARASITIC)
100
1µF
806
NXP
BF862
IPD
–
0.1µF
OSRAM
PHOTODIODE
SFH213
OR EQUIVALENT
5V
+
LTC6360
CPO CPI
CPO
CPI
1µF
0.1µF
133
10µF
0.1µF
10k
100k
10M
CPI
10M
5V
–
LTC2054
0.1µF
GAIN = 1MΩ
–3dB BW = 4MHz
OUTPUT NOISE = 710µVRMS ON A 4MHz BANDWIDTH
OUTPUT OFFSET = 50µV TYPICAL EXCLUDING
PHOTODIODE DARK CURRENT
+
6360 TA02
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PART NUMBER
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6360f
24 Linear Technology Corporation
LT 0711 • PRINTED IN USA
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