LTC6803-1/LTC6803-3
Multicell Battery Stack
Monitor
FEATURES
DESCRIPTION
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The LTC®6803 is a 2nd generation, complete battery
monitoring IC that includes a 12-bit ADC, a precision
voltage reference, a high voltage input multiplexer and
a serial interface. Each LTC6803 can measure up to 12
series-connected battery cells or supercapacitors. Using a
unique level shifting serial interface, multiple LTC6803-1/
LTC6803-3 devices can be connected in series, without
opto-couplers or isolators, allowing for monitoring of every
cell in a long string of series-connected batteries. Each cell
input has an associated MOSFET switch for discharging
overcharged cells. The LTC6803-1 connects the bottom
of the stack to V– internally. It is pin compatible with the
LTC6802‑1, providing a drop-in upgrade. The LTC6803-3
separates the bottom of the stack from V–, improving
cell 1 measurement accuracy.
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Measures Up to 12 Battery Cells in Series
Stackable Architecture
Supports Multiple Battery Chemistries
and Supercapacitors
Serial Interface Daisy Chains to Adjacent Devices
0.25% Maximum Total Measurement Error
Engineered for ISO26262 Compliant Systems
13ms to Measure All Cells in a System
Passive Cell Balancing:
– Integrated Cell Balancing MOSFETs
– Ability to Drive External Balancing MOSFETs
Onboard Temperature Sensor and Thermistor Inputs
1MHz Serial Interface with Packet Error Checking
Safe with Random Connection of Cells
Built-In Self Tests
Delta-Sigma Converter With Built-In Noise Filter
Open-Wire Connection Fault Detection
12µA Standby Mode Supply Current
High EMI Immunity
44-Lead SSOP Package
APPLICATIONS
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Electric and Hybrid Electric Vehicles
High Power Portable Equipment
Backup Battery Systems
Electric Bicycles, Motorcycles, Scooters
The LTC6803 provides a standby mode to reduce supply
current to 12µA. Furthermore, the LTC6803 can be powered
from an isolated supply, providing a technique to reduce
battery stack current draw to zero.
For applications requiring individually addressable serial
communications, see the LTC6803-2/LTC6803-4.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
V+
LTC6803-3
DIE TEMP
+
MUX
12-CELL
BATTERY
1mA
100µA
REGISTERS
AND
CONTROL
+
Supply Current vs Modes of Operation
SERIAL DATA
TO LTC6803-3
ABOVE
50V
12-BIT
∆Σ ADC
ISOLATED
DC/DC
CONVERTER
+
VOLTAGE
REFERENCE
NEXT 12-CELL
PACK BELOW
V–
100k NTC
EXTERNAL
TEMP
12V
SUPPLY CURRENT
NEXT 12-CELL
PACK ABOVE
10µA
1µA
100nA
10nA
SERIAL DATA
TO LTC6803-3
BELOW
1nA
100k
680313 TA01a
HW
SHUTDOWN
STANDBY
MEASURE
680313 TA01b
680313fa
1
LTC6803-1/LTC6803-3
ABSOLUTE MAXIMUM RATINGS (Note 1)
Total Supply Voltage (V+ to V–)..................................75V
Input Voltage (Relative to V–)
C0............................................................. –0.3V to 8V
C12......................................................... –0.3V to 75V
Cn (Note 5).......................... –0.3V to Min (8 • n, 75V)
Sn (Note 5).......................... –0.3V to Min (8 • n, 75V)
CSBO, SCKO, SDOI................................ – 0.3V to 75V
All Other Pins............................................ –0.3V to 7V
Voltage Between Inputs
Cn to Cn – 1.............................................. –0.3V to 8V
Sn to Cn – 1.............................................. –0.3V to 8V
C12 to C8................................................ –0.3V to 25V
C8 to C4.................................................. –0.3V to 25V
C4 to C0.................................................. –0.3V to 25V
Operating Temperature Range
LTC6803I..............................................–40°C to 85°C
LTC6803H........................................... –40°C to 125°C
Specified Temperature Range
LTC6803I..............................................–40°C to 85°C
LTC6803H........................................... –40°C to 125°C
Junction Temperature............................................ 150°C
Storage Temperature Range................... –65°C to 150°C
Note: n = 1 to 12
PIN CONFIGURATION
LTC6803-1
LTC6803-3
TOP VIEW
TOP VIEW
CSBO
1
44 CSBI
CSBO
1
44 CSBI
SDOI
2
43 SDO
SDOI
2
43 SDO
SCKO
3
42 SDI
SCKO
3
42 SDI
V+
4
41 SCKI
V+
4
41 SCKI
C12
5
40 VMODE
C12
5
40 VMODE
S12
6
39 GPIO2
S12
6
39 GPIO2
C11
7
38 GPIO1
C11
7
38 GPIO1
S11
8
37 WDTB
S11
8
37 WDTB
C10
9
36 NC
C10
9
36 TOS
S10 10
35 TOS
S10 10
35 VREG
C9 11
34 VREG
C9 11
34 VREF
S9 12
33 VREF
S9 12
33 VTEMP2
C8 13
32 VTEMP2
C8 13
32 VTEMP1
S8 14
31 VTEMP1
S8 14
31 NC
C7 15
30 NC
C7 15
30 V–
S7 16
29
V–
S7 16
29 C0
C6 17
28 S1
C6 17
28 S1
S6 18
27 C1
S6 18
27 C1
C5 19
26 S2
C5 19
26 S2
S5 20
25 C2
S5 20
25 C2
C4 21
24 S3
C4 21
24 S3
S4 22
23 C3
S4 22
23 C3
G PACKAGE
44-LEAD PLASTIC SSOP
G PACKAGE
44-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 70°C/W
TJMAX = 150°C, θJA = 70°C/W
680313fa
2
LTC6803-1/LTC6803-3
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFICED TEMPERATURE RANGE
LTC6803IG-1#PBF
LTC6803IG-1#TRPBF
LTC6803G-1
44-Lead Plastic SSOP
–40°C to 85°C
LTC6803IG-3#PBF
LTC6803IG-3#TRPBF
LTC6803G-3
44-Lead Plastic SSOP
–40°C to 85°C
LTC6803HG-1#PBF
LTC6803HG-1#TRPBF
LTC6803G-1
44-Lead Plastic SSOP
–40°C to 125°C
LTC6803HG-3#PBF
LTC6803HG-3#TRPBF
LTC6803G-3
44-Lead Plastic SSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
+
–
temperature range, otherwise specifications are at TA = 25°C. V = 43.2V, V = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Specifications
VS
Supply Voltage, V+ Relative to V–
VERR Specification Met
Timing Specification Met
l
l
VLSB
Measurement Resolution
Quantization of the ADC
l
ADC Offset
(Note 2)
l
–0.5
0.5
mV
ADC Gain Error
(Note 2)
l
–0.12
–0.22
0.12
0.22
%
%
VERR
Total Measurement Error
(Note4)
VCELL = –0.3V
VCELL = 2.3V
VCELL = 2.3V
VCELL = 3.6V
VCELL = 3.6V, LTC6803IG
VCELL = 3.6V, LTC6803HG
VCELL = 4.2V
VCELL = 4.2V, LTC6803IG
VCELL = 4.2V, LTC6803HG
VCELL = 5V
2.3V < VTEMP < 4.2V, LTC6803IG
2.3V < VTEMP < 4.2V, LTC6803HG
VCELL
Cell Voltage Range
Full-Scale Voltage Range
VCM
Common Mode Voltage Range
Measured Relative to V–
Range of Inputs Cn < 0.25% Gain Error,
n = 2 to 11, LTC6803IG
VREF
10
4
1.5
l
l
–2.8
–5.1
–4.3
–7.9
–9
–5
–9.2
–10
l
l
–9.2
–10
l
l
l
55
55
±2.5
±3
V
V
mV/Bit
2.8
5.1
4.3
7.9
9
5
9.2
10
9.2
10
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
–0.3
5
V
l
1.8
5•n
V
Range of Inputs C0, C1 < 0.25% Gain Error,
LTC6803IG
l
0
5
V
Range of Inputs Cn < 0.5% Gain Error,
n = 2 to 11, LTC6803HG
l
1.8
5•n
V
Range of Inputs C0, C1 < 0.5% Gain Error,
LTC6803HG
l
0
5
V
l
3.020
3.015
Die Temperature Measurement Error
Error in Measurement of 125°C
Reference Pin Voltage
RLOAD = 100k to V–
Reference Voltage Temperature
Coefficient
5
3.065
3.065
8
°C
3.110
3.115
V
V
ppm/°C
Reference Voltage Thermal Hysteresis 25°C to 85°C and 25°C to –40°C
100
ppm
Reference Voltage Long-Term Drift
60
ppm/√kHr
680313fa
3
LTC6803-1/LTC6803-3
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
+
–
temperature range, otherwise specifications are at TA = 25°C. V = 43.2V, V = 0V, unless otherwise noted.
SYMBOL
PARAMETER
VREF2
2nd Reference Voltage
VREG
Regulator Pin Voltage
CONDITIONS
10V < V+ < 50V, No Load
ILOAD = 4mA
Regulator Pin Short-Circuit Limit
IB
IS
IQS
ICS
ISD
IOW
Input Bias Current
Supply Current, Measure Mode
(Note 7)
Supply Current, Standby
Supply Current, Serial I/O
MIN
TYP
MAX
UNITS
l
2.25
2.1
2.5
2.5
2.75
2.9
V
V
l
l
4.5
4.5
5.0
5.0
5.5
V
V
l
8
In/Out of Pins C1 Through C12
When Measuring Cell
When Not Measuring Cell
Current Into the V+ Pin When Measuring
Continuous Measuring (CDC = 2)
Continuous Measuring (CDC = 2)
Measure Every 130ms (CDC = 5)
Measure Every 500ms (CDC = 6)
Measure Every 2 Seconds (CDC = 7)
Current Into V+ Pin When In Standby, All Serial
Port Pin at Logic “1”
LTC6803IG
LTC6803HG
Current Into V+ Pin During Serial
Communications, All Serial Port Pins at Logic “0”.
VMODE = “0”, This Current is Added to IS or IQS
LTC6803IG
LTC6803HG
Supply Current, Hardware Shutdown
Current Out of V–, VC12 = 43.2V, V+ Floating
(Note 8)
Discharge Switch-On Resistance
VCELL > 3V (Note 3)
Current Used for Open-Wire Detection
–10
l
l
l
l
l
l
l
l
mA
1
10
µA
nA
620
600
190
140
55
780
780
250
175
70
1000
1150
360
250
105
µA
µA
µA
µA
µA
8
12
16.5
µA
6
6
12
12
18
19
µA
µA
3.1
3.9
4.3
mA
3
3
3.9
3.9
4.5
4.9
mA
mA
0.001
1
µA
20
Ω
110
140
µA
l
l
10
l
70
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
145
°C
5
°C
Voltage Mode Timing Specifications
tCYCLE
Measurement Cycling
t1
Time Required to Measure 12 Cells
Time Required to Measure 10 Cells
Time Required to Measure 3 Temperatures
Time Required to Measure 1 Cell or Temperature
l
l
l
l
11
9
2.8
1.0
13
11
3.4
1.2
15
13
4.1
1.4
ms
ms
ms
ms
SDI Valid to SCKI Rising Setup
l
10
ns
t2
SDI Valid to SCKI Rising Hold
l
250
ns
t3
SCKI Low
l
400
ns
t4
SCKI High
l
400
ns
t5
CSBI Pulse Width
l
400
ns
t6
CSBI Falling to SCKI Rising
l
100
ns
t7
CSBI Falling to SDO Valid
l
100
ns
t8
SCKI Falling to SDO Valid
l
250
Clock Frequency
l
1
Watchdog Timer Timeout Period
l
1
ns
MHz
2.5
Seconds
Timing Specifications
tPD1
CSBI to CSBO
CCSBO = 150pF
l
600
ns
tPD2
SCKI to SCKO
CSCKO = 150pF
l
300
ns
tPD3
SDI to SDOI Write Delay
CSDOI = 150pF
l
300
ns
tPD4
SDI to SDOI Read Delay
CSDO = 150pF
l
300
ns
680313fa
4
LTC6803-1/LTC6803-3
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
+
–
temperature range, otherwise specifications are at TA = 25°C. V = 43.2V, V = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage Mode Digital I/O
VIH
Digital Input Voltage High
Pins SCKI, SDI and CSBI
l
VIL
Digital Input Voltage Low
Pins SCKI, SDI and CSBI
l
0.8
VOL
Digital Output Voltage Low
Pin SDO, Sinking 500µA
l
0.3
V
IIN
Digital Input Current
VMODE, TOS, SCKI, SDI, CSBI
l
10
µA
10
µA
2
V
V
Current Mode Digital I/O
IIH1
Digital Input Current High
Pins CSBI, SCKI, SDI (Write, Pin Sourcing)
l
3
IIL1
Digital Input Current Low
CSBI, SCKI, SDI (Write, Pin Sourcing)
l
1000
µA
IIH2
Digital Input Current High
SDOI (Read, Pin Sinking)
l
1000
µA
IIL2
Digital Input Current Low
SDOI (Read, Pin Sinking)
l
IOH1
Digital Output Current High
CSBO, SCKO, SDOI (Write, Pin Sinking)
l
10
µA
3
10
µA
IOL1
Digital Output Current Low
CSBO, SCKO, SDOI(Write, Pin Sinking)
l
1000
1300
1600
µA
IOH2
Digital Output Current High
SDI (Read, Pin Sourcing)
l
1000
1300
1600
µA
IOL2
Digital Output Current Low
SDI (Read, Pin Sourcing)
l
3
10
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The ADC specifications are guaranteed by the Total Measurement
Error (VERR) specification.
Note 3: Due to the contact resistance of the production tester, this
specification is tested to relaxed limits. The 20Ω limit is guaranteed by
design.
Note 4: VCELL refers to the voltage applied across Cn to Cn – 1 for
n = 1 to 12. VTEMP refers to the voltage applied from VTEMP1 or VTEMP2
to V–.
Note 5: These absolute maximum ratings apply provided that the voltage
between inputs do not exceed the absolute maximum ratings.
Note 6: Supply current is tested during continuous measuring. The supply
current during periodic measuring (130ms, 500ms, 2s) is guaranteed by
design.
Note 7: The CDC = 5, 6 and 7 supply currents are not measured. They are
guaranteed by the CDC = 2 supply current measurement.
Note 8: Limit is determined by high speed automated test capability.
TYPICAL PERFORMANCE CHARACTERISTICS
Cell Measurement Error
vs Cell Input Voltage
0
1.5
0
–1.5
–3.0
–4.5
0
–5
–10
C = 0µF
C = 0.1µF
C = 1µF
C = 3.3µF
CELL 1, 13ms CELL MEASUREMENT
REPETITION
VCELL = 3.3V
–15
–20
–25
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CELL INPUT VOLTAGE (V)
680313 G01
CELL VOLTAGE ERROR (mV)
3.0
Cell Measurement Error
vs Input RC Values
5
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
CELL VOLTAGE ERROR (mV)
TOTAL UNADJUSTED ERROR (mV)
4.5
Cell Measurement Error
vs Input RC Values
–30
0
1
2
3
7 8
4 5 6
INPUT RESISTANCE (kΩ)
9
10
680313 G02
CELLS 2 TO 12, 13ms CELL
MEASUREMENT REPETITION
VCELL = 3.3V
–5
–10
–15
–20
C = 0µF
C = 0.1µF
C = 1µF
C = 3.3µF
–25
–30
0
1
2
3
7 8
4 5 6
INPUT RESISTANCE (kΩ)
9
10
680313 G03
680313fa
5
LTC6803-1/LTC6803-3
TYPICAL PERFORMANCE CHARACTERISTICS
Cell Voltage Measurement Error
vs Common Mode Voltage
Cell 12 Measurement Error vs V+
1
0
–2
–4
–6
–8
VCELL = 3.6V
TA = 25°C
CELL2 ERROR vs VC1
CELL3 ERROR vs VC2
CELLn ERROR VS VCn–1,
n = 4 TO 12
–10
–12
–14
0.1
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
V+ – VC12 (V)
0
1
2
4
3
COMMON MODE VOLTAGE (V)
0.25
–0.50
–1.25
–2.00
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
2.50
CELL MEASUREMENT ERROR (mV)
VCELL = 0.8V
V+ = 9.6V
4 SAMPLES
1.75
1.00
0.25
–0.50
–1.25
–2.00
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
Measurement Gain Error
Hysteresis
0.1
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
VIN CELL6 (V)
Cell 3 to Cell 12 Voltage
Measurement Error vs Temperature
1.75
1.00
0.25
–0.50
–1.25
20
TA = 85°C TO 25°C
18
680313 G09
Cell Measurement Common Mode
Rejection
0
TA = –45°C TO 25°C
VCM(IN) = 5VP-P
72dB REJECTION
–10 CORRESPONDS TO
LESS THAN 1 BIT
–20 AT ADC OUTPUT
16
NUMBER OF UNITS
15
10
14
12
10
8
6
680313 G10
–40
–60
2
0
–250 –200 –150 –100 –50 0 50 100 150 200
CHANGE IN GAIN ERROR (ppm)
–30
–50
4
5
VCELL = 0.8V
V+ = 9.6V
4 SAMPLES
–2.00
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
Measurement Gain Error
Hysteresis
20
NUMBER OF UNITS
1
680313 G08
680313 G07
25
CELL6
10
680313 G06
REJECTION (dB)
CELL MEASUREMENT ERROR (mV)
1.00
100
Cell 2 Voltage Measurement Error
vs Temperature
Cell 1 Voltage Measurement Error
vs Temperature
VCELL = 0.8V
V+ = 9.6V
4 SAMPLES
5
ALL OTHER CELLS = 3V
680313 G05
680313 G04
1.75
CELL VOLTAGE MEASUREMENT ERROR (mV)
10
1000
2
CELL MEASUREMENT ERROR (mV)
TA = 25°C
VCELL = 3.3V
CELL MEASUREMENT ERROR (mV)
CELL 12 MEASUREMENT ERROR (mV)
100
Cell Measurement Error
vs Cell Voltage
0
–250 –200 –150 –100 –50 0 50 100 150 200
CHANGE IN GAIN ERROR (ppm)
680313 G11
–70
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
680313 G12
680313fa
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LTC6803-1/LTC6803-3
TYPICAL PERFORMANCE CHARACTERISTICS
ADC Normal Mode Rejection
vs Frequency
ADC INL
0
2.0
–10
1.5
0.8
0.6
1.0
–30
–40
–50
0.4
0.5
DNL (BITS)
INL (BITS)
–20
0
–0.5
–60
–1.5
–70
–2.0
10
100
1k
10k
FREQUENCY (Hz)
100k
–0.8
1
0
2
3
INPUT (V)
4
0
40
850
CDC = 2
CONTINUOUS CONVERSION
25
20
15
C12
10
10
8
6
4
C6
5
125°C
85°C
25°C
–40°C
2
C1
0
20 40 60 80 100 120
TEMPERATURE (°C)
10
0
20
40
30
SUPPLY VOLTAGE (V)
4.5
10 SAMPLES
10
5
0
–5
–10
0
25
60
700
125°C
85°C
25°C
–40°C
650
600
0
10
20
40
30
SUPPLY VOLTAGE (V)
50
75
100
TEMPERATURE (°C)
50
60
680313 G18
External Temperature
Measurement Total Unadjusted
Error vs Input
Internal Die Temperature
Measurement Error Using an
8mV/°K Scale Factor
15
50
750
680313 G17
680313 G16
TOTAL UNADJUSTED ERROR (mV)
0
800
12
SUPPLY CURRENT (µA)
30
5
4
Supply Current vs Supply Voltage
During Continuous Conversions
16
35
3
2
INPUT (V)
1
680313 G15
14
E = (AMBIENT TEMP-INTERNAL
DIE TEMP READING) (°C)
CELL INPUT BIAS CURRENT (nA)
–1.0
5
Standby Supply Current
vs Supply Voltage
CELL INPUT = 3.6V
0
–40 –20
–0.2
680313 G14
Cell Input Bias Current During
Standby and Hardware Shutdown
50
0
–0.6
680313 G13
45
0.2
–0.4
–1.0
SUPPLY CURRENT (µA)
REJECTION (dB)
ADC DNL
1.0
125
150
680313 G19
3.0
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
1.5
0
–1.5
–3.0
–4.5
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE INPUT VOLTAGE (V)
680313 G20
680313fa
7
LTC6803-1/LTC6803-3
TYPICAL PERFORMANCE CHARACTERISTICS
VREF Output Voltage
vs Temperature
VREF Load Regulation
VREF Line Regulation
3.09
3.070
3.068
3.074
3.072
3.08
3.070
3.062
3.07
TA = 85°C
TA = 25°C
3.06
3.060
3.05
3.056
–50
–25
25
75
0
50
TEMPERATURE (°C)
100
125
3.04
0
3.060
1000
10
100
SOURCING CURRENT (µA)
5.5
V+ = 43.2V
50
CDC = 2
CONTINUOUS CONVERSIONS
VREG (V)
4.2
0
2
4
6
8
SUPPLY CURRENT (mA)
10
12
4.0
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
0
10
20
30
40
SUPPLY VOLTAGE (V)
50
Die Temperature Increase vs
Discharge Current in Internal FET
6 CELLS
DISCHARGING
1 CELL
DISCHARGING
10
20
15
10
5
0
60
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CELL VOLTAGE (V)
680313 G26
13.10
13.05
13.00
12.95
12.90
12.85
5
0
CONVERSION TIME (ms)
INCREASE IN DIE TEMPERATURE (°C)
15
25
13.15
35
20
30
Cell Conversion Time
ALL 12 CELLS AT 3.6V
45 VS = 43.2V
TA = 25°C
40
25
35
13.20
50
12 CELLS
DISCHARGING
40
680313 G25
680313 G24
30
60
TA = 105°C
TA = 85°C
TA = 25°C
TA = –45°C
45
4.5
TA = 125°C
TA = 85°C
TA = 25°C
TA = –40°C
50
Internal Discharge Resistance
vs Cell Voltage
5.0
4.8
20
30
40
SUPPLY VOLTAGE (V)
680313 G23
VREG Line Regulation
5.0
4.4
10
0
680313 G22
VREG Load Regulation
4.6
TA = –40°C
3.062
680313 G21
5.2
TA = 85°C
3.066
DISCHARGE RESISTANCE (Ω)
5 REPRESENTATIVE UNITS
TA = 25°C
3.068
3.064
TA = –40°C
3.058
VREG (V)
VREF (V)
3.064
VREF (V)
VREF (V)
3.066
4.0
NO EXTERNAL LOAD ON VREF, CDC = 2
(CONTINUOUS CELL CONVERSIONS)
0
10 20 30 40 50 60 70 80
DISCHARGE CURRENT PER CELL (mA)
680313 G27
12.80
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100 120
680313 G28
680313fa
8
LTC6803-1/LTC6803-3
PIN FUNCTIONS
To ensure pin compatibility with the LTC6802-1, the
LTC6803-1 is configured such that the bottom cell input
(C0) is connected internally to the negative supply voltage
(V–). The LTC6803-3 offers a unique pinout with an input
for the bottom cell (C0). This simple functional difference
offers the possibility for enhanced cell 1 measurement
accuracy, enhanced SPI noise tolerance and simplified
wiring. More information is provided in the applications
section entitled Advantages of Kelvin Connections for C0.
CSBO (Pin 1): Chip Select Output (Active Low). CSBO is
a buffered version of the chip select input, CSBI. CSBO
drives the next IC in the daisy chain. See Serial Port in the
Applications Information section.
SDOI (Pin 2): Serial Data I/O Pin. SDOI transfers data to
and from the next IC in the daisy chain. See Serial Port in
the Applications Information section.
SCKO (Pin 3): Serial Clock Output. SCKO is a buffered version of SCKI. SCKO drives the next IC in the daisy chain.
See Serial Port in the Applications Information section.
V+ (Pin 4): Positive Power Supply. Pin 4 can be tied to the
most positive potential in the battery stack or an isolated
power supply. V+ must be greater than the most positive
potential in the battery stack under normal operation. With
an isolated power supply, LTC6803 can be turned off by
simply shutting down V+.
C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins
5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27): C1 through
C12 are the inputs for monitoring battery cell voltages. The
negative terminal of the bottom cell is tied to pin V– for
LTC6803-1, pin C0 for LTC6803-3 . The next lowest potential
is tied to C1 and so forth. See the figures in the Applications Information section for more details on connecting
batteries to the LTC6803-1 and LTC6803-3. The LTC6803
can monitor a series connection of up to 12 cells. Each
cell in a series connection must have a common mode
voltage that is greater than or equal to the cells below it.
100mV negative voltages are permitted.
S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins
6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28): S1 though
S12 pins are used to balance battery cells. If one cell in a
series becomes overcharged, an S output can be used to
discharge the cell. Each S output has an internal N-channel
MOSFET for discharging. See the Block Diagram. The
NMOS has a maximum on resistance of 20Ω. An external
resistor should be connected in series with the NMOS to
dissipate heat outside of the LTC6803 package. When
using the internal MOSFETs to discharge cells, the die
temperature should be monitored. See Power Dissipation
and Thermal Shutdown in the Applications Information
section. The S pins also feature an internal pull-up PMOS.
This allows the S pins to be used to drive the gates of
external MOSFETs for higher discharge capability.
C0 (Pin 29 on LTC6803-3): Negative Terminal of the Bottom Battery Cell. C0 and V– form Kelvin connections to
eliminate effect of voltage drop at the V– trace.
V– (Pin 29 on LTC6803-1/ Pin 30 on LTC6803-3): Connect
V– to the most negative potential in the series of cells.
NC (Pin 30 on LTC6803-1/Pin 31 on LTC6803-3 ): This pin
is not used and is internally connected to V– through 10Ω.
It can be left unconnected or connected to V– on the PCB.
VTEMP1, VTEMP2 (Pins 31, 32 on LTC6803-1/ Pins 32, 33
on LTC6803-3 ): Temperature Sensor Inputs. The ADC
measures the voltage on VTEMPn with respect to V– and
stores the result in the TMP registers. The ADC measurements are relative to the VREF pin voltage. Therefore a
simple thermistor and resistor combination connected
to the VREF pin can be used to monitor temperature. The
VTEMP inputs can also be general purpose ADC inputs.
Any voltage from 0V to 5.125V referenced to V– can be
measured.
VREF (Pin 33 on LTC6803-1/ Pin 34 on LTC6803-3 ): 3.065V
Voltage Reference Output. This pin should be bypassed
with a 1µF capacitor. The VREF pin can drive a 100k resistive load connected to V–. Larger loads should be buffered
with an LT6003 op amp, or similar device.
680313fa
9
LTC6803-1/LTC6803-3
PIN FUNCTIONS
VREG (Pin 34 on LTC6803-1/ Pin 35 on LTC6803-3 ): Linear
Voltage Regulator Output. This pin should be bypassed
with a 1µF capacitor. The VREG pin is capable of supplying up to 4mA to an external load. The VREG pin does not
sink current.
TOS (Pin 35 on LTC6803-1/Pin 36 on LTC6803-3): Top
of Stack Input. Tie TOS to VREG when the LTC6803-1 or
LTC6803-3 is the top device in a daisy chain. Tie TOS to
V– otherwise. When TOS is tied to VREG, the LTC6803-1
or LTC6803-3 ignores the SDOI input and SCKO, CSBO
are turned off. When TOS is tied to V–, the LTC6803-1
or LTC6803-3 expects data to be passed to and from the
SDOI pin.
NC (Pin 36 on LTC6803-1 ): No Connection.
WDTB (Pin 37): Watchdog Timer Output (Active Low). If
there is no valid command received for 1 to 2.5 seconds, the
WDTB output is asserted. The WDTB pin is an open-drain
NMOS output. When asserted it pulls the output down to
V– and resets the configuration register to its default state.
GPIO1, GPIO2 (Pins 38, 39): General Purpose Input/
Output. By writing a “0” to a GPIO configuration register
bit, the open-drain output is activated and the pin is pulled
to V–. By writing logic “1” to the configuration register bit,
the corresponding GPIO pin is high impedance. An external
resistor is required to pull the pin up to VREG. By reading
the configuration register locations GPIO1 and GPIO2, the
state of the pins can be determined. For example, if a “0”
is written to register bit GPIO1, a “0” is always read back
because the output N-channel MOSFET pulls Pin 38 to V–.
If a “1” is written to register bit GPIO1, the pin becomes
high impedance. Either a “1” or a “0” is read back, depending on the voltage present at Pin 38. The GPIOs makes it
possible to turn on/off circuitry around the LTC6803, or
read logic values from a circuit around the LTC6803. The
GPIO pins should be connected to V– if not used.
VMODE (Pin 40): Voltage Mode Input. When VMODE is tied
to VREG, the SCKI, SDI, SDO and CSBI pins are configured
as voltage inputs and outputs. This means these pins
accept standard TTL logic levels. Connect VMODE to VREG
when the LTC6803-1 or LTC6803-3 is the bottom device in
a daisy chain. When VMODE is connected to V–, the SCKI,
SDI and CSBI pins are configured as current inputs and
outputs, and SDO is unused. Connect VMODE to V– when
the LTC6803-1 or LTC6803-3 is being driven by another
LTC6803-1 or LTC6803-3 in a daisy chain.
SCKI (Pin 41): Serial Clock Input. The SCKI pin interfaces
to any logic gate (TTL levels) if VMODE is tied to VREG. SCKI
must be driven by the SCKO pin of another LTC6803-1 or
LTC6803-3 if VMODE is tied to V–. See Serial Port in the
Applications Information Section.
SDI (Pin 42): Serial Data Input. The SDI pin interfaces to
any logic gate (TTL levels) if VMODE is tied to VREG. SDI
must be driven by the SDOI pin of another LTC6803-1 or
LTC6803-3 if VMODE is tied to V–. See Serial Port in the
Applications Information section.
SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS
open-drain output if VMODE is tied to VREG. A pull-up resistor is needed on SDO. SDO is not used if VMODE is tied to
V–. See Serial Port in the Applications Information section.
CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI
pin interfaces to any logic gate (TTL levels) if VMODE is tied
to VREG. CSBI must be driven by the CSBO pin of another
LTC6803-1 or LTC6803-3 if VMODE is tied to V–. See Serial
Port in the Applications Information section.
680313fa
10
LTC6803-1/LTC6803-3
BLOCK DIAGRAMS
4
LTC6803-1
2ND REFERENCE
REGULATOR
VREF2
5
6
7
V+
VREG
S12
WATCHDOG
TIMER
WDTB
25
26
27
SCKO
S3
CSBO
∆Σ A/D
CONVERTER
MUX
C2
12
RESULTS
REGISTER
AND
COMMUNICATIONS
S2
29
30
C1
VMODE
S1
GPIO2
V–
CONTROL
10Ω
NC
EXTERNAL
TEMP
DIE
TEMP
31
VTEMP2
32
32
26
27
4
29
30
43
42
41
40
39
38
35
V+
REGULATOR
VREG
35
C12
S12
WATCHDOG
TIMER
WDTB
37
C11
SCKO
S3
CSBO
∆Σ A/D
CONVERTER
MUX
C2
12
RESULTS
REGISTER
AND
COMMUNICATIONS
S2
CSBI
SDO
SDI
SCKI
C1
REFERENCE
28
1
44
68031 BD
SDOI
25
2
VREF
VREF2
24
3
NC 36
2ND REFERENCE
7
GPIO1
TOS
LTC6803-3
6
SDO
SCKI
VTEMP1
5
CSBI
SDI
REFERENCE
28
37
C11
SDOI
24
34
C12
VMODE
S1
GPIO2
C0
CONTROL
V–
10Ω
NC
31
EXTERNAL
TEMP
DIE
TEMP
VTEMP1
32
VTEMP2
33
GPIO1
TOS
3
2
1
44
43
42
41
40
39
38
36
VREF
34
68033 BD
680313fa
11
LTC6803-1/LTC6803-3
TIMING DIAGRAM
Timing Diagram of the Serial Interface
t1
t4
t2
t6
t3
t7
SCKI
D3
SDI
D2
D1
D0
D7···D4
D3
t5
CSBI
t8
SDO
D4
D3
D2
PREVIOUS
COMMAND
D1
D0
D7···D4
CURRENT
COMMAND
D3
680313 TD
OPERATION
THEORY OF OPERATION
The LTC6803 is a data acquisition IC capable of measuring the voltage of 12 series connected battery cells.
An input multiplexer connects the batteries to a 12-bit
delta-sigma analog-to-digital converter (ADC). An internal
8ppm/°C voltage reference combined with the ADC give
the LTC6803 its outstanding measurement accuracy. The
inherent benefits of the delta-sigma ADC versus other types
of ADCs (e.g., successive approximation) are explained
in Advantages of Delta-Sigma ADCs in the Applications
Information section.
Communication between the LTC6803 and a host processor
is handled by an SPI compatible serial interface. As shown
in Figure 1, the LTC6803-1s or LTC6803-3s can pass data
up and down a stack of devices using simple diodes for
isolation. This operation is described in Serial Port in the
Applications Information section.
The LTC6803 also contains circuitry to balance cell voltages.
Internal MOSFETs can be used to discharge cells. These
internal MOSFETs can also be used to control external
balancing circuits. Figure 1 illustrates cell balancing by
internal discharge. Figure 12 shows the S pin controlling
an external balancing circuit. It is important to note that
the LTC6803 makes no decisions about turning on/off
the internal MOSFETs. This is completely controlled by
the host processor. The host processor writes values to
a configuration register inside the LTC6803 to control the
switches. The watchdog timer inside the LTC6803 will turn
off the discharge switches if communication with the host
processor is interrupted.
The LTC6803 has three modes of operation: hardware
shutdown, standby and measure. Hardware shutdown is
a true zero power mode. Standby mode is a power saving
state where all circuits except the serial interface are turned
off. In measure mode, the LTC6803 is used to measure
cell voltages and store the results in memory. Measure
mode will also monitor each cell voltage for overvoltage
(OV) and undervoltage (UV) conditions.
HARDWARE SHUTDOWN MODE
The V+ pin can be disconnected from the C pins and the
battery pack. If the V+ supply pin is 0V, the LTC6803 will
typically draw less than 1nA from the battery cells. All
circuits inside the IC are off. It is not possible to communicate with the IC when V+ = 0V. See the Applications
Information section for hardware shutdown circuits.
STANDBY MODE
The LTC6803 defaults (powers up) to standby mode.
Standby mode is the lowest supply current state with
a supply connected. Standby current is typically 12µA
680313fa
12
LTC6803-1/LTC6803-3
OPERATION
BATTERY
POSITIVE
350V
+
+
+
+
+
+
+
+
+
LTC6803-3
IC #8
CSBI
CSBO
SDO
SDOI
SDI
SCKO
SCKI
V+
VMODE
C12
S12
GPIO2
C11
GPIO1
S11
WDTB
C10
TOS
S10
VREG
C9
VREF
S9
VTEMP2
C8
VTEMP1
S8
NC
C7
V–
S7
C0
C6
S1
S6
C1
C5
S2
S5
C2
C4
S3
S4
C3
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
LTC6803-3
IC #2
CSBI
CSBO
SDO
SDOI
SDI
SCKO
+
SCKI
V
VMODE
C12
S12
GPIO2
C11
GPIO1
S11
WDTB
C10
TOS
S10
VREG
C9
VREF
S9
VTEMP2
C8
VTEMP1
S8
NC
C7
V–
S7
C0
C6
S1
S6
C1
C5
S2
S5
C2
C4
S3
S4
C3
+
+
+
BATTERIES #25 TO #84
AND
LTC6803-3 ICs #3 TO #7
+
V2 –
OE2
LTC6803-3
IC #1
CSBI
CSBO
SDO
SDOI
SDI
SCKO
SCKI
V+
VMODE
C12
S12
GPIO2
C11
GPIO1
S11
WDTB
C10
TOS
S10
VREG
C9
VREF
S9
VTEMP2
C8
VTEMP1
S8
NC
C7
V–
S7
C0
C6
S1
S6
C1
C5
S2
S5
C2
C4
S3
S4
C3
V2 +
3V
V1–
OE1
MPU
CS
MISO
MISI
CLK
V1–
V2 –
V1+
DIGITAL
ISOLATOR
MODULE
IO
3V
+
+
+
680313 F01
Figure 1. 96-Cell Battery Stack, Daisy-Chain Interface. This is a Simplified Schematic Showing the Basic Multi-IC Architecture
680313fa
13
LTC6803-1/LTC6803-3
OPERATION
when V+ = 44V. All circuits are turned off except the serial
interface and the voltage regulator. For the lowest possible
standby current consumption all SPI logic inputs should
be set to logic 1 level. The LTC6803 can be programmed
for standby mode by setting the comparator duty cycle
configuration bits, CDC[2:0], to 0. If the part is put into
standby mode while ADC measurements are in progress,
the measurements will be interrupted and the cell voltage
registers will be in an indeterminate state. To exit standby
mode, the CDC bits must be written to a value other than 0.
MEASURE MODE
The LTC6803 is in measure mode when the CDC bits are
programmed with a value from 1 to 7. When CDC = 1 the
LTC6803 is on and waiting for a start ADC conversion
command. When CDC is 2 through 7 the IC monitors each
cell voltage and produces an interrupt signal on the SDO
pin indicating all cell voltages are within the UV and OV
limits. The value of the CDC bits determines how often
the cells are monitored, and how much average supply
current is consumed.
There are two methods for indicating the UV/OV interrupt status: toggle polling (using a 1kHz output signal)
and level polling (using a high or low output signal). The
polling methods are described in the Serial Port section.
The UV/OV limits are set by the VUV and VOV values in the
configuration registers. When a cell voltage exceeds the
UV/OV limits a bit is set in the flag register. The UV and
OV flag status for each cell can be determined using the
Read Flag Register Group.
An ADC measurement can be requested at any time when
the IC is in measure mode. To initiate cell voltage measurements while in measure mode, a Start A/D Conversion is
sent. After the command has been sent, the LTC6803 will
indicate the A/D converter status via toggle polling or level
polling (as described in the Serial Port section). During
cell voltage measurement commands, the UV and OV flags
(within the flag register group) are also updated. When
the measurements are complete, the part will continue
monitoring UV and OV conditions at the rate designated
by the CDC bits. Note that there is a 5µs window during
each UV/OV comparison cycle where an ADC measurement request may be missed. This is an unlikely event.
For example, the comparison cycle is 2 seconds when
CDC = 7. Use the CLEAR command to detect missing
ADC commands.
Operating with Less than 12 Cells
If fewer than 12 cells are connected to the LTC6803, the
unused input channels must be masked. The MCxI bits in
the configuration registers are used to mask channels. In
addition, the LTC6803 can be configured to automatically
bypass the measurements of the top 2 cells, reducing power
consumption and measurement time. If the CELL10 bit is
high, the inputs for cell 11 and cell 12 are masked and only
the bottom 10 cell voltages will be measured. By default,
the CELL10 bit is low, enabling measurement of all 12 cell
voltages. Additional information regarding operation with
less than 12 cells is provided in the applications section.
ADC RANGE AND OUTPUT FORMAT
The ADC outputs a 12-bit code with an offset of 0x200
(512 decimal). The input voltage can be calculated as:
VIN = (DOUT – 512) • VLSB; VLSB = 1.5mV
where DOUT is a decimal integer.
For example, a 0V input will have an output reading
of 0x200. An ADC reading of 0x000 means the input
was –0.768V. The absolute ADC measurement range is
–0.768V to 5.376V. The resolution is VLSB = 1.5mV = (5.376
+ 0.768)/212. The useful range is –0.3V to 5V. This range
allows monitoring super capacitors, which could have small
negative voltage. Inputs below –0.3V exceed the absolute
maximum rating of the C pins. If all inputs are negative
then the ADC range is reduced to –0.1V. Inputs above 5V
will have noisy ADC readings (see Typical Performance
Characteristics curves).
ADC MEASUREMENTS DURING CELL BALANCING
The primary cell voltage ADC measurement commands
(STCVAD and STOWAD) automatically turn off a cell’s
discharge switch while its voltage is being measured. The
discharge switches for the cell above and the cell below will
also be turned off during the measurement. For example,
discharge switches S4, S5 and S6 will be off while cell 5
is being measured. The UV/OV comparison conversions in
680313fa
14
LTC6803-1/LTC6803-3
OPERATION
CDC modes 2 through 7 also cause a momentary turn-off
of the discharge switch. For example, switches S4, S5 and
S6 will be off while cell 5 is checked for a UV/OV condition.
In some systems it may be desirable to allow discharging to
continue during cell voltage measurements. The cell voltage
ADC conversion commands STCVDC and STOWDC allow
the discharge switches to remain on during cell voltage
measurements. This feature allows the system to perform
a self test to verify the discharge functionality.
ADC REGISTER CLEAR COMMAND
The clear command can be used to clear the cell voltage
registers and temperature registers. The clear command
will set all registers to 0xFFF. This command is used to
make sure conversions are being made. When cell voltages are stable, ADC results could stay the same. If a start
ADC conversion command is sent to the LTC6803 but the
PEC fails to match then the command is ignored and the
voltage register contents also will not change. Sending a
clear command then reading back register contents is a
way to make sure LTC6803 is accepting commands and
performing new measurements. The clear command takes
1ms to execute.
ADC CONVERTER SELF TEST
Two self-test commands can be used to verify the functionality of the digital portions of the ADC. The self tests
also verify the cell voltage registers and temperature
monitoring registers. During these self tests a test signal
is applied to the ADC. If the circuitry is working properly all
cell voltage and temperature registers will contain 0x555
or 0xAAA. The time required for the self-test function is
the same as required to measure all cell voltages or all
temperature sensors.
MULTIPLEXER AND REFERENCE SELF TEST
The LTC6803 uses a multiplexer to measure the 12 battery cell inputs, as well as the temperature signals. A
diagnostic command is used to validate the function of
the multiplexer, the temperature sensor, and the precision
reference circuit. Diagnostic registers will be updated after
each diagnostic test. The muxfail bit of the registers will
be 1 if the multiplexer self test fails.
A constant voltage generated by the 2nd reference circuit
will be measured by the ADC and the results written to the
diagnostic register. The voltage reading should be 2.5V
±16%. Readings outside this range indicate a failure of the
temperature sensor circuit, the precision reference circuit,
or the analog portion of the ADC. The DAGN command
executes in 16.4ms, which is the sum of the 12-cell tCYCLE
and 3 temperature tCYCLE. The diagnostic read command
can be used to read the registers.
USING THE GENERAL PURPOSE INPUTS/OUTPUTS
(GPIO1, GPIO2)
The LTC6803 has two general purpose digital input/output
pins. By writing a GPIO configuration register bit to a logic
low, the open-drain output can be activated. The GPIOs
give the user the ability to turn on/off circuitry around
the LTC6803. One example might be a circuit to verify the
operation of the system.
When a GPIO configuration bit is written to a logic high,
the corresponding GPIO pin may be used as an input.
The read back value of that bit will be the logic level that
appears at the GPIO pin.
WATCHDOG TIMER CIRCUIT
The LTC6803 includes a watchdog timer circuit. The
watchdog timer is on for all modes except CDC = 0. The
watchdog timer times out if no valid command is received
for 1 to 2.5 seconds. When the watchdog timer circuit
times out, the WDTB open-drain output is asserted low
and the configuration register bits are reset to their default
(power-up) state. In the power-up state, CDC is 0, the S
outputs are off and the IC is in the low power standby
mode. The WDTB pin remains low until a valid command
is received. The watchdog timer provides a means to turn
off cell discharging should communications to the MPU
be interrupted. There is no need for the watchdog timer
at CDC = 0 since discharging is off. The open-drain WDTB
output can be wire ORd with other external open-drain
signals. Pulling the WDTB signal low will not initiate a
680313fa
15
LTC6803-1/LTC6803-3
OPERATION
watchdog event, but the CNFGO bit 7 will reflect the state
of this signal. Therefore, the WDTB pin can be used to
monitor external digital events if desired.
SERIAL PORT
Overview
The LTC6803 has an SPI bus compatible serial port. Several
devices can be daisy chained in series. There are two sets
of serial port pins, designated as low side and high side.
The low side and high side ports enable devices to be
daisy chained even when they operate at different power
supply potentials. In a typical configuration, the positive
power supply of the first, bottom device is connected
to the negative power supply of the second, top device,
as shown in Figure 1. When devices are stacked in this
manner, they can be daisy chained by connecting the high
side port of the bottom device to the low side port of the
top device. With this arrangement, the master writes to
or reads from the cascaded devices as if they formed one
long shift register. The LTC6803-1/LTC6803-3 translate the
voltage level of the signals between the low side and high
side ports to pass data up and down the battery stack.
Physical Layer
On the LTC6803-1/LTC6803-3, seven pins comprise the
low side and high side ports. The low side pins are CSBI,
SCKI, SDI and SDO. The high side pins are CSBO, SCKO
and SDOI. CSBI and SCKI are always inputs, driven by the
master or by the next lower device in a stack. CSBO and
SCKO are always outputs that can drive the next higher
device in a stack. SDI is a data input when writing to a
stack of devices. For devices not at the bottom of a stack,
SDI is a data output when reading from the stack. SDOI
is a data output when writing to and a data input when
reading from a stack of devices. SDO is an open-drain
output that is only used on the bottom device of a stack,
where it may be tied with SDI, if desired, to form a single,
bi-directional port. The SDO pin on the bottom device of
a stack requires a pull-up resistor. For devices up in the
stack, SDO should be tied to the local V– or left floating.
To communicate between daisy-chained devices, the high
side port pins of a lower device (CSBO, SCKO and SDOI)
should be connected through high voltage diodes to the
respective low side port pins of the next higher device
(CSBI, SCKI and SDI). In this configuration, the devices
communicate using current rather than voltage. To signal
a logic high from the lower device to the higher device,
the lower device sinks a smaller current from the higher
device pin. To signal a logic low, the lower device sinks
a larger current. Likewise, to signal a logic high from
the higher device to the lower device, the higher device
sources a larger current to the lower device pin. To signal
a logic low, the higher device sources a smaller current.
See Figure 2. Since CSBO, SCKO and SDOI voltages are
close to the V– of high side device, the V– of the high side
device must be at least 5V higher than that of the low side
device to guarantee current flows of the current mode
interface. It is recommended that high voltage diodes be
placed in series with the SPI daisy-chain signals as shown
if Figure 1. These diodes prevent reverse voltage stress
on the IC if a battery group bus bar is removed. See Battery Interconnection Integrity for additional information.
Standby current consumed in the current mode serial interface is minimized when CSBI, SCKI and SDI are all high.
The voltage mode pin (VMODE) determines whether the low
side serial port is configured as voltage mode or current
mode. For the bottom device in a daisy-chain stack, this
pin must be pulled high (tied to VREG). The other devices
in the daisy chain must have this pin pulled low (tied to V–)
to designate current mode communication. To designate
the top-of-stack device for polling commands, the TOS
VSENSE
(WRITE)
+
–
LOW SIDE PORT
ON HIGHER DEVICE
READ 1
WRITE
HIGH SIDE PORT
ON LOWER DEVICE
VSENSE
(READ)
+
–
680313 F02
Figure 2. Current Mode Interface
680313fa
16
LTC6803-1/LTC6803-3
OPERATION
pin on the top device of a daisy chain must be tied high.
The other devices in the stack must have TOS tied low.
See Figure 1.
Data Link Layer
Clock Phase And Polarity: The LTC6803 SPI compatible
interface is configured to operate in a system using CPHA
= 1 and CPOL = 1. Consequently, data on SDI must be
stable during the rising edge of SCKI.
Data Transfers: Every byte consists of 8 bits. Bytes are
transferred with the most significant bit (MSB) first. On a
write, the data value on SDI is latched into the device on
the rising edge of SCKI (Figure 3). Similarly, on a read, the
data value output on SDO is valid during the rising edge of
SCKI and transitions on the falling edge of SCKI (Figure 4).
CSBI must remain low for the entire duration of a command sequence, including between a command byte and
subsequent data. On a write command, data is latched in
on the rising edge of CSBI.
Network Layer
PEC Byte: The packet error code (PEC) byte is a cyclic
redundancy check (CRC) value calculated for all of the
bits in a register group in the order they are passed, using
the initial PEC value of 01000001 (0x41) and the following
characteristic polynomial:
x8 + x2 + x + 1
To calculate the 8-bit PEC value, a simple procedure can
be established:
1. Initialize the PEC to 0100 0001.
2. For each bit DIN coming into the register group, set
IN0 = DIN XOR PEC[7], then IN1=PEC[0] XOR IN0,
IN2 = PEC[1] XOR IN0.
3. Update the 8-bit PEC as PEC[7] = PEC[6],
PEC[6] = PEC[5],……PEC[3] = PEC[2], PEC[2] = IN2,
PEC[1] = IN1, PEC[0] = IN0.
4. Go back to step 2 until all data are shifted. The 8-bit
result is the final PEC byte.
CSBI
SCKI
SDI
MSB (CMD) BIT 6 (CMD)
LSB (PEC) MSB (DATA)
LSB (PEC)
680313 F03
Figure 3. Transmission Format (Write)
CSBI
SCKI
SDI
SDO
MSB (CMD) BIT 6 (CMD)
LSB (PEC)
MSB (DATA)
LSB (PEC)
680313 F04
Figure 4. Transmission Format (Read)
680313fa
17
LTC6803-1/LTC6803-3
OPERATION
An example to calculate the PEC is listed in Table 1 and
Figure 5. The PEC of the 1 byte data 0x01 is computed as
0xC7 after the last bit of the byte clocked in. For multiple
byte data, the PEC is valid at the end (LSB) of the last byte.
device address. See the Bus Protocols and Commands
sections.
In daisy-chained configurations, all devices in the chain
receive the command bytes simultaneously. For example,
to initiate ADC conversions in a stack of devices, a single
STCVAD command is sent, and all devices will start conversions at the same time. For read and write commands,
a single command is sent, and then the stacked devices
effectively turn into a cascaded shift register, in which
data is shifted through each device to the next higher (on
a write) or the next lower (on a read) device in the stack.
See the Serial Command Examples section.
LTC6803 calculates PEC byte for any command or data
received and compares it with the PEC byte following the
command or data. The command or data is regarded as
valid only if the PEC bytes match. LTC6803 also attaches
the calculated PEC byte at the end of the data it shifts out.
For daisy-chained LTC6803-1/LTC6803-3, each device
computes the PEC byte based on the data it sends out
or receives for itself. The data passing through for other
devices do affect its PEC. On a read command, each device
shifts its data out with, and then shifts out the PEC byte it
computed, MSB first. For example, when reading the flag
registers from two stacked devices (bottom device A and
top device B), the data will be output in the following order:
Polling Methods: For ADC conversions, three methods can
be used to determine ADC completion. First, a controller
can start an ADC conversion and wait for the specified
conversion time to pass before reading the results. The
second method is to hold CSBI low after an ADC start
command has been sent. The ADC conversion status will
be output on SDO (Figure 6). A problem with the second
method is that the controller is not free to do other serial
communication while waiting for ADC conversions to
complete. The third method overcomes this limitation.
The controller can send an ADC start command, perform
other tasks, and then send a poll ADC converter status
(PLADC) command to determine the status of the ADC
conversions (Figure 7). For OV/UV interrupt status, the poll
interrupt status (PLINT) command can be used to quickly
determine whether any cell in a stack is in an overvoltage
or undervoltage condition (Figure 7).
FLGR0(A), FLGR1(A), FLGR2(A), PEC(A), FLGR0(B),
FLGR1(B), FLGR2(B), PEC(B )
On a write command, each device receives its data and
then the PEC byte, MSB first. For example, when writing
configuration registers to two stacked devices (bottom
device A and top device B), the data will be input in the
following order:
CFGRR0(B), CFGR1(B),……, CFGR5(B), PEC(B),
CFGR0(A), CFGR1(A),……, CFGR5(A), PEC(A)
Broadcast Commands: A broadcast command is one to
which all devices on the bus will respond, regardless of
Table 1. Procedure to Calculate PEC Byte
CLOCK
CYCLE
DIN
IN0
IN1
IN2
PEC[7]
PEC[6]
PEC[5]
PEC[4]
PEC[3]
PEC[2]
PEC[1]
PEC[0]
0
0
0
1
0
0
1
0
0
0
0
0
1
1
0
1
1
0
1
0
0
0
0
0
1
0
2
0
0
1
1
0
0
0
0
0
0
1
1
3
0
0
0
1
0
0
0
0
0
1
1
0
4
0
0
0
0
0
0
0
0
1
1
0
0
5
0
0
0
0
0
0
0
1
1
0
0
0
6
0
0
0
0
0
0
1
1
0
0
0
0
7
1
1
1
1
0
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
8
680313fa
18
1
IN0
DTFF
END
INO = DATAIN XOR PEC[7];
PEC1 = PEC[0] XOR IN0;
PEC2 = PEC[1] XOR IN0;
PEC[7:0] = {PEC[6:2], PEC2, PEC1, IN0};
2
3
4
2
1
BEGIN PEC[7:0] = 0x41
CLK Q
Q
PEC[0]
D
PEC Hardware and Software Example
CLOCK
BEGIN PEC[7:0] = 0x41
INO = DATAIN XOR PEC[7];
DATAIN
XOR
PEC[0]
INO
XOR
PEC1
Q
DTFF
CLK Q
D
PEC[1]
PEC1 = PEC[0] XOR IN0;
XOR
PEC2
Q
PEC[2]
Figure 5
DTFF
CLK Q
D
PEC[2]
PEC2 = PEC[1] XOR IN0;
PEC[1]
IN0
3
Q
DTFF
CLK Q
D
PEC[3]
PEC[3]
4
CLK Q
DTFF
Q
DTFF
CLK Q
D
PEC[5]
PEC[5]
Q
DTFF
CLK Q
D
PEC[6]
PEC[7:0] = {PEC[6:2], PEC2, PEC1, IN0};
END
PEC[4]
PEC[4]
D
Q
PEC[6]
Q
680313 F05
DTFF
CLK Q
D
PEC[7]
PEC[7]
OPERATION
PEC[7]
LTC6803-1/LTC6803-3
680313fa
19
LTC6803-1/LTC6803-3
OPERATION
tCYCLE
CSBI
SCKI
SDI
MSB (CMD) BIT6 (CMD)
LSB (PEC)
SDO
TOGGLE OR LEVEL POLL
680313 F06
Figure 6. Transmission Format (ADC Conversion and Poll)
CSBI
SCKI
SDI
MSB (CMD) BIT6 (CMD)
SDO
LSB (PEC)
TOGGLE OR LEVEL POLL
680313 F07
Figure 7. Transmission Format (PLADC Conversion or PLINT)
Toggle Polling: Toggle polling allows a robust determination both of device states and of the integrity of the connections between the devices in a stack. Toggle polling is
enabled when the LVLPL bit is low. After entering a polling
command, the data out line will be driven by the slave
devices based on their status. When polling for the ADC
converter status, data out will be low when any device is
busy performing an ADC conversion and will toggle at
1kHz when no device is busy. Similarly, when polling for
interrupt status, the output will be low when any device
has an interrupt condition and will toggle at 1kHz when
none has an interrupt condition.
Toggle Polling—Daisy-Chained Broadcast Polling: The
SDO pin (bottom device) or SDI pin (stacked devices) will
be low if a device is busy/in interrupt. If it is not busy/not
in interrupt, the device will pass the signal from the SDOI
input to data out (if not the top-of-stack device) or toggle
the data out line at 1kHz (if the top-of-stack device). The
master pulls CSBI high to exit polling.
Level Polling: Level polling is enabled when the LVLPL
bit is high. After entering a polling command, the data
out line will be driven by the slave devices based on their
status. When polling for the ADC converter status, data
out will be low when any device is busy performing an
ADC conversion and will be high when no device is busy.
Similarly, when polling for interrupt status, the output will
be low when any device has an interrupt condition and will
be high when none has an interrupt condition.
Level Polling—Daisy-Chained Broadcast Polling: The SDO
pin (bottom device) or SDI pin (stacked devices) will be
low if a device is busy/in interrupt. If it is not busy/not
in interrupt, the device will pass the level from the SDOI
input to data out (if not the top-of-stack device) or hold the
data out line high (if the top-of-stack device). Therefore,
if any device in the chain is busy or in interrupt, the SDO
signal at the bottom of the stack will be low. If all devices
are not busy/not in interrupt, the SDO signal at the bottom of the stack will be high. The master pulls CSBI high
to exit polling.
680313fa
20
LTC6803-1/LTC6803-3
OPERATION
Table 2. Protocol Key
PEC
Packet Error Code
Master-to-Slave
N
Number of Bits
Slave-to-Master
...
Continuation of Protocol
Complete Byte of
Data
Table 3. Broadcast Poll Command
8
8
Command
PEC
Revision Code: The diagnostic register group contains a
2-bit revision code. If software detection of device revision
is necessary, then contact the factory for details. Otherwise,
the code can be ignored. In all cases, however, the values
of all bits must be used when calculating the packet error
code (PEC) byte on data reads.
Bus Protocols: There are 3 different protocol formats,
depicted in Table 3 through Table 5. Table 2 is the key for
reading the protocol diagrams.
Poll Data
Table 4. Broadcast Read
8
8
8
…
8
8
8
…
8
Command
PEC
Data Byte Low
…
Data Byte High
PEC
Shift Byte 1
…
Shift Byte N
Table 5. Broadcast Write
8
8
8
…
8
8
8
…
8
Command
PEC
Data Byte Low
…
Data Byte High
PEC
Shift Byte 1
…
Shift Byte N
See Serial Command examples.
Table 6. Command Codes and PEC Bytes
COMMAND DESCRIPTION
NAME
CODE
PEC
Write Configuration Register Group
WRCFG
01
C7
Read Configuration Register Group
RDCFG
02
CE
Read All Cell Voltage Group
RDCV
04
DC
Read Cell Voltages 1-4
RDCVA
06
D2
Read Cell Voltages 5-8
RDCVB
08
F8
Read Cell Voltages 9-12
RDCVC
0A
F6
Read Flag Register Group
RDFLG
0C
E4
Read Temperature Register Group
RDTMP
0E
EA
Start Cell Voltage ADC Conversions and Poll Status
STCVAD
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
B0
B7
BE
B9
AC
AB
A2
A5
88
8F
86
81
94
93
9A
9D
All
Cell 1
Cell 2
Cell 3
Cell 4
Cell 5
Cell 6
Cell 7
Cell 8
Cell 9
Cell 10
Cell 11
Cell 12
Clear (FF)
Self Test1
Self Test2
680313fa
21
LTC6803-1/LTC6803-3
OPERATION
Table 6. Command Codes and PEC Bytes (continued)
COMMAND DESCRIPTION
NAME
CODE
PEC
Start Open-Wire ADC Conversions and Poll Status
STOWAD
All
Cell 1
Cell 2
Cell 3
Cell 4
Cell 5
Cell 6
Cell 7
Cell 8
Cell 9
Cell 10
Cell 11
Cell 12
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
27
2E
29
3C
3B
32
35
18
1F
16
11
04
Start Temperature ADC Conversions and Poll Status
STTMPAD
All
External1
External2
Internal
Self Test 1
Self Test 2
30
31
32
33
3E
3F
50
57
5E
59
7A
7D
Poll ADC Converter Status
Poll Interrupt Status
PLADC
40
07
PLINT
50
77
Start Diagnose and Poll Status
DAGN
52
79
Read Diagnostic Register
RDDGNR
54
6B
Start Cell Voltage ADC Conversions and Poll Status,
with Discharge Permitted
STCVDC
All
Cell 1
Cell 2
Cell 3
Cell 4
Cell 5
Cell 6
Cell 7
Cell 8
Cell 9
Cell 10
Cell 11
Cell 12
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
E7
E0
E9
EE
FB
FC
F5
F2
DF
D8
D1
D6
C3
Start Open-Wire ADC Conversions and Poll Status,
with Discharge Permitted
STOWDC
All
Cell 1
Cell 2
Cell 3
Cell 4
Cell 5
Cell 6
Cell 7
Cell 8
Cell 9
Cell 10
Cell 11
Cell 12
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
97
90
99
9E
8B
8C
85
82
AF
A8
A1
A6
B3
680313fa
22
LTC6803-1/LTC6803-3
OPERATION
Table 7. Configuration (CFG) Register Group
REGISTER
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CFGR0
RD/WR
WDT
GPIO2
GPIO1
LVLPL
CELL10
CDC[2]
CDC[1]
CDC[0]
CFGR1
RD/WR
DCC8
DCC7
DCC6
DCC5
DCC4
DCC3
DCC2
DCC1
CFGR2
RD/WR
MC4I
MC3I
MC2I
MC1I
DCC12
DCC11
DCC10
DCC9
CFGR3
RD/WR
MC12I
MC11I
MC10I
MC9I
MC8I
MC7I
MC6I
MC5I
CFGR4
RD/WR
VUV[7]
VUV[6]
VUV[5]
VUV[4]
VUV[3]
VUV[2]
VUV[1]
VUV[0]
CFGR5
RD/WR
VOV[7]
VOV[6]
VOV[5]
VOV[4]
VOV[3]
VOV[2]
VOV[1]
VOV[0]
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Table 8. Cell Voltage (CV) Register Group
REGISTER
RD/WR
BIT 7
BIT 6
CVR00
RD
C1V[7]
C1V[6]
C1V[5]
C1V[4]
C1V[3]
C1V[2]
C1V[1]
C1V[0]
CVR01
RD
C2V[3]
C2V[2]
C2V[1]
C2V[0]
C1V[11]
C1V[10]
C1V[9]
C1V[8]
CVR02
RD
C2V[11]
C2V[10]
C2V[9]
C2V[8]
C2V[7]
C2V[6]
C2V[5]
C2V[4]
CVR03
RD
C3V[7]
C3V[6]
C3V[5]
C3V[4]
C3V[3]
C3V[2]
C3V[1]
C3V[0]
CVR04
RD
C4V[3]
C4V[2]
C4V[1]
C4V[0]
C3V[11]
C3V[10]
C3V[9]
C3V[8]
CVR05
RD
C4V[11]
C4V[10]
C4V[9]
C4V[8]
C4V[7]
C4V[6]
C4V[5]
C4V[4]
CVR06
RD
C5V[7]
C5V[6]
C5V[5]
C5V[4]
C5V[3]
C5V[2]
C5V[1]
C5V[0]
CVR07
RD
C6V[3]
C6V[2]
C6V[1]
C6V[0]
C5V[11]
C5V[10]
C5V[9]
C5V[8]
CVR08
RD
C6V[11]
C6V[10]
C6V[9]
C6V[8]
C6V[7]
C6V[6]
C6V[5]
C6V[4]
CVR09
RD
C7V[7]
C7V[6]
C7V[5]
C7V[4]
C7V[3]
C7V[2]
C7V[1]
C7V[0]
CVR10
RD
C8V[3]
C8V[2]
C8V[1]
C8V[0]
C7V[11]
C7V[10]
C7V[9]
C7V[8]
CVR11
RD
C8V[11]
C8V[10]
C8V[9]
C8V[8]
C8V[7]
C8V[6]
C8V[5]
C8V[4]
CVR12
RD
C9V[7]
C9V[6]
C9V[5]
C9V[4]
C9V[3]
C9V[2]
C9V[1]
C9V[0]
CVR13
RD
C10V[3]
C10V[2]
C10V[1]
C10V[0]
C9V[11]
C9V[10]
C9V[9]
C9V[8]
CVR14
RD
C10V[11]
C10V[10]
C10V[9]
C10V[8]
C10V[7]
C10V[6]
C10V[5]
C10V[4]
CVR15*
RD
C11V[7]
C11V[6]
C11V[5]
C11V[4]
C11V[3]
C11V[2]
C11V[1]
C11V[0]
CVR16*
RD
C12V[3]
C12V[2]
C12V[1]
C12V[0]
C11V[11]
C11V[10]
C11V[9]
C11V[8]
CVR17*
RD
C12V[11]
C12V[10]
C12V[9]
C12V[8]
C12V[7]
C12V[6]
C12V[5]
C12V[4]
*Registers CVR15, CVR16, and CVR17 can only be read if the CELL10 bit in register CFGR0 is low
Table 9. Flag (FLG) Register Group
REGISTER
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FLGR0
RD
C4OV
C4UV
C3OV
C3UV
C2OV
C2UV
C1OV
C1UV
FLGR1
RD
C8OV
C8UV
C7OV
C7UV
C6OV
C6UV
C5OV
C5UV
FLGR2
RD
C12OV*
C12UV*
C11OV*
C11UV*
C10OV
C10UV
C9OV
C9UV
* Bits C11UV, C12UV, C11OV and C12OV are always low if the CELL10 bit in register CFGR0 is high
680313fa
23
LTC6803-1/LTC6803-3
OPERATION
Table 10. Temperature (TMP) Register Group
REGISTER
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TMPR0
RD
ETMP1[7]
ETMP1[6]
ETMP1[5]
ETMP1[4]
TMPR1
RD
ETMP2[3]
ETMP2[2]
ETMP2[1]
ETMP2[0]
ETMP1[3]
ETMP1[2]
ETMP1[1]
ETMP1[0]
ETMP1[11]
ETMP1[10]
ETMP1[9]
ETMP1[8]
TMPR2
RD
ETMP2[11]
ETMP2[10]
ETMP2[9]
ETMP2[8]
ETMP2[7]
ETMP2[6]
ETMP2[5]
ETMP2[4]
TMPR3
RD
ITMP[7]
ITMP[6]
ITMP[5]
ITMP[4]
TMPR4
RD
NA
NA
NA
THSD
ITMP[3]
ITMP[2]
ITMP[1]
ITMP[0]
ITMP[11]
ITMP[10]
ITMP[9]
ITMP[8]
Table 11. Packet Error Code (PEC)
REGISTER
PEC
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RD
PEC[7]
PEC[6]
PEC[5]
PEC[4]
PEC[3]
PEC[2]
PEC[1]
PEC[0]
Table 12. Diagnostic Register Group
REGISTER
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DGNR0
RD
REF[7]
REF[6]
REF[5]
REF[4]
REF[3]
REF[2]
REF[1]
REF[0]
DGNR1
RD
REV[1]
REV[0]
MUXFAIL
NA
REF[11]
REF[10]
REF[9]
REF[8]
Table 13. Memory Bit Descriptions
NAME
CDC
DESCRIPTION
Comparator Duty Cycle
VALUES
CDC
UV/OV COMPARATOR
PERIOD
VREF POWERED DOWN
BETWEEN MEASUREMENTS
CELL VOLTAGE
MEASUREMENT TIME
0
(default)
N/A (Comparator Off)
Standby Mode
Yes
N/A
1
N/A (Comparator Off)
No
13ms
2
13ms
No
13ms
3
130ms
No
13ms
4
500ms
No
13ms
5
130ms
Yes
21ms
6
500ms
Yes
21ms
7
2000ms
Yes
21ms
CELL10
10-Cell Mode
0 = 12-cell mode (default); 1 = 10-cell mode
LVLPL
Level Polling Mode
0 = toggle polling (default); 1 = level polling
GPIO1
GPIO1 Pin Control
Write: 0 = GPIO1 pin pull-down on; 1 = GPIO1 pin pull-down off (default)
Read: 0 = GPIO1 pin at logic ‘0’; 1 = GPIO1 pin at logic ‘1’
GPIO2
GPIO2 Pin Control
Write: 0 = GPIO2 pin pull-down on; 1 = GPIO2 pin pull-down off (default)
Read: 0 = GPIO2 pin at logic ‘0’; 1 = GPIO2 pin at logic ‘1’
WDT
Watchdog Timer
Read: 0 = WDT pin at logic ‘0’; 1 = WDT pin at logic ‘1’
DCCx
Discharge Cell x
x = 1..12 0 = turn off shorting switch for cell ‘x’ (default); 1 = turn on shorting switch
VUV
Undervoltage Comparison Voltage*
Comparison voltage = (VUV – 31) • 16 • 1.5mV
VOV
Overvoltage Comparison Voltage*
Comparison voltage = (VOV – 32) • 16 • 1.5mV
MUXFAIL
Multiplexer Self Test Result
Read: 0 = test passed; 1 = test failed
680313fa
24
LTC6803-1/LTC6803-3
OPERATION
Table 13. Memory Bit Descriptions (continued)
NAME
DESCRIPTION
VALUES
MCxI
Mask Cell x Interrupts
x = 1..12 0 = enable interrupts for cell ‘x’ (default)
1 = turn off interrupts and clear flags for cell ‘x’
CxV
Cell x Voltage*
x = 1..12 12-bit ADC measurement value for cell ‘x’
cell voltage for cell ‘x’ = (CxV – 512) • 1.5mV
reads as 0xFFF while A/D conversion in progress
CxUV
Cell x Undervoltage Flag
x = 1..12 cell voltage compared to VUV comparison voltage
0 = cell ‘x’ not flagged for undervoltage condition; 1 = cell ‘x’ flagged
CxOV
Cell x Overvoltage Flag
x = 1..12 cell voltage compared to VOV comparison voltage
0 = cell ‘x’ not flagged for overvoltage condition; 1 = cell ‘x’ flagged
ETMPx
External Temperature Measurement*
Temperature measurement voltage = (ETMPx – 512) • 1.5mV
0 = thermal shutdown has not occurred; 1 = thermal shutdown has occurred
THSD
Thermal Shutdown Status
REV
Revision Code
Device revision code
ITMP
Internal Temperature Measurement*
Temperature measurement voltage = (ITMP – 512) • 1.5mV = 8mV * T(°K)
Status cleared to ‘0’ on read of Thermal Register Group
PEC
Packet Error Code
Cyclic redundancy check (CRC) value
REF
Reference Voltage for Diagnostics
This reference voltage = (REF – 512) • 1.5mV. Normal range is within 2.1V to 2.9V
*Voltage equations use the decimal value of the registers, 0 to 4095 for 12-bit and 0 to 255 for 8-bit registers
SERIAL COMMAND EXAMPLES
Examples below use a configuration of three stacked
LTC6803-1 or LTC6803-3 devices: bottom (B), middle
(M), and top (T)
Write Configuration Registers (Figure 8)
1. Pull CSBI low
2. Send WRCFG command and its PEC byte
3. Send CFGR0 byte for top device, then CFGR1 (T), …CFGR5 (T), PEC of CFGR0(T) to CFGR5(T)
4. Send CFGR0 byte for middle device, then CFGR1 (M) … CFGR5 (M) ), PEC of CFGR0(M) to CFGR5(M)
5. Send CFGR0 byte for bottom device, then CFGR1 (B), … CFGR5 (B) ), PEC of CFGR0(B) to CFGR5(B)
6. Pull CSBI high; data latched into all devices on rising edge of CSBI. S pins respond as data latched.
Calculation of serial interface time for sequence above:
Number of devices in stack = N
Number of bytes in sequence = B = 2 command byte and 7 data bytes per device = 2 + 7 • N
Serial port frequency per bit = F
Time = (1/F) • B • 8 bits/byte = (1/F) • (2 + 7 • N) • 8
Time for 3-cell example above, with 1MHz serial port = (1/1000000) • (2 + 7 • 3) • 8 = 184µs
680313fa
25
LTC6803-1/LTC6803-3
OPERATION
CSBI
SCKI
SDI
WRCFG + CFGR + PEC
td
Sn
(n = 1 TO 12)
td < 2µs IF Sn IS UNLOADED
Sn, DISCHARGE PIN STATE
680313 F08
Figure 8. S Pin Action and SPI Transmission
Read Cell Voltage Registers (12 Cell Mode)
1. Pull CSBI low
2. Send RDCV command and PEC
3. Read CVR00 byte of bottom device, then CVR01 (B), CVR02 (B), … CVR17 (B), and then PEC (B)
4. Read CVR00 byte of middle device, then CVR01 (M), CVR02 (M), … CVR17 (M), and then PEC (M)
5. Read CVR00 byte for top device, then CVR01 (T), CVR02 (T), … CVR17 (T), and then PEC (T)
6. Pull CSBI high
Calculation of serial interface time for sequence above:
Number of devices in stack = N
Number of bytes in sequence = B = 2 command byte, and 18 data bytes plus 1 PEC byte per device = 2 + 19 • N
Serial port frequency per bit = F
Time = (1/F) • B • 8 bits/byte = (1/F) • (2 + 19 • N) • 8
Time for 3-cell example above, with 1MHz serial port = (1/1000000) • (2 + 19 • 3) • 8 = 472µs
Start Cell Voltage ADC Conversions and Poll Status (Toggle Polling)
1. Pull CSBI low
2. Send STCVAD command byte and PEC (all devices in stack start ADC conversions simultaneously)
3. SDO output from bottom device pulled low for approximately 12ms
4. SDO output toggles at 1kHz rate, indicating conversions complete for all devices in daisy chain
5. Pull CSBI high to exit polling
Start Cell Voltage ADC Conversions and Poll Status (Broadcast Command with Toggle Polling)
1. Pull CSBI low
2. Send STCVAD command and PEC (all devices in stack start ADC conversions simultaneously)
3. SDO output of all devices in parallel pulled low for approximately 12ms
4. SDO output toggles at 1kHz rate, indicating conversions complete for all devices in the daisy chain
5. Pull CSBI high to exit polling
Poll Interrupt Status (Level Polling)
1. Pull CSBI low
2. Send PLINT command and PEC
3. SDO output from bottom device pulled low if any device has an interrupt condition; otherwise, SDO high
4. Pull CSBI high to exit polling
26
680313fa
LTC6803-1/LTC6803-3
APPLICATIONS INFORMATION
DIFFERENCE BETWEEN THE LTC6803-1 AND LTC6803‑3
The only difference between the LTC6803-1 and the
LTC6803-3 is the bonding of the V– and C0 pins. The
V– and C0 are separate signals on every LTC6803 die.
In the LTC6803-1 package, the V– and C0 signals are
shorted together by bonding these signals to the same
pin. In the LTC6803‑3 package, V– and C0 are separate
pins. Therefore, the LTC6803-1 is pin compatible with the
LTC6802-1. For new designs the LTC6803-3 pinout allows
a Kelvin connection to C0 (Figure 24).
Larger series resistors and shunt capacitors can be used
to lower the filter bandwidth. The measurement error due
to the larger component values is a complex function of
the component values. The error also depends on how
often measurements are made. Table 14 is an example.
In each example a 3.6V cell is being measured and the
error is displayed in millivolts. There is a RC filter in series
with inputs C1 through C12 for the LTC6803-1. There is
an RC filter in series with inputs C0 through C12 for the
LTC6803-3.
Table 14. Cell Measurement Errors vs Input RC Values
CELL VOLTAGE FILTERING
The LTC6803 employs a sampling system to perform its
analog-to-digital conversions and provides a conversion
result that is essentially an average over the 0.5ms conversion window, provided there isn’t noise aliasing with
respect to the delta-sigma modulator rate of 512kHz. This
indicates that a lowpass filter with 30dB attenuation at
500kHz may be beneficial. Since the delta-sigma integration bandwidth is about 1kHz, the filter corner need not
be lower than this to assure accurate conversions.
Series resistors of 100Ω may be inserted in the input
paths without introducing meaningful measurement error. Shunt capacitors may be added from the cell inputs
to V–, creating RC filtering as shown in Figure 9. The cell
balancing MOSFET in Figure 12 can cause a small transient
when it switches on and off. Keeping the cutoff frequency
of the RC filter relatively high will allow adequate settling
prior to the actual conversion. A delay of about 500µs is
provided in the ADC timing, so a 16kHz LPF is optimal
(100Ω, 0.1µF) and offers 30dB of noise rejection.
100Ω
Cn
100nF
+
7.5V
100Ω
100nF
680313 F09
C(n – 1)
Figure 9. Adding RC Filtering to the Cell Inputs
(One Cell Connection Shown)
R = 100Ω, R = 1k,
C = 0.1µF C = 0.1µF
Cell 1 Error
(mV, LTC6803-1)
0.5
4.5
Cell 2 to Cell 12 (mV)
1
9
R = 1k,
C = 1µF
R = 10k,
C = 3.3µF
1.5
1.5
3
0.5
For the LTC6803-1, no resistor should be placed in series
with the V– pin. Because the supply current flows from
the V– pin, any resistance on this pin could generate a
significant conversion error for cell 1, and the error of
cell 1 caused by the RC filter differs from errors of cell 2
to cell 12.
OPEN CONNECTION DETECTION
When a cell input (C pin) is open, it affects two cell measurements. Figure 10 shows an open connection to C3,
in an application without external filtering between the C
pins and the cells. During normal ADC conversions (that
is, using the STCVAD command), the LTC6803 will give
near zero readings for B3 and B4 when C3 is open. The
zero reading for B3 occurs because during the measurement of B3, the ADC input resistance will pull C3 to the
C2 potential. Similarly, during the measurement of B4, the
ADC input resistance pulls C3 to the C4 potential.
Figure 11 shows an open connection at the same point in
the cell stack as Figure 10, but this time there is an external
filtering network still connected to C3. Depending on the
value of the capacitor remaining on C3, a normal measurement of B3 and B4 may not give near-zero readings, since
the C3 pin is not truly open. In fact, with a large external
capacitance on C3, the C3 voltage will be charged midway
680313fa
27
LTC6803-1/LTC6803-3
APPLICATIONS INFORMATION
+
B4
B3
+
21
+
23
+
25
27
+
29
in the value of battery connected between inputs C3 and
C4 (battery B4).
LTC6803-1
C4
The following algorithm can be used to detect an open
connection to cell pin Cn:
C3
C2
1. Issue a STOWAD command (with 100µA sources
connected).
MUX
C1
V–
2. Issue a RDCV command and store all cell measurements
into array CELLA(n).
100µA
3. Issue the 2nd STOWAD command (with 100µA sources
connected).
680313 F10
Figure 10. Open Connection
4. Issue the 2nd RDCV command and store all cell measurements into array CELLB(n).
+
B4
B3
+
+
21
CF4
23
CF3
+
25
+
27
29
C4
LTC6803-1
C3
C2
MUX
C1
V–
100µA
680313 F11
Figure 11. Open Connection with RC Filtering
between C2 and C4 after several cycles of measuring cells
B3 and B4. Thus the measurements for B3 and B4 may
indicate a valid cell voltage when in fact the exact state of
B3 and B4 is unknown.
To reliably detect an open connection, the command
STOWAD is provided. With this command, two 100µA
current sources are connected to the ADC inputs and
turned on during all cell conversions. Referring again to
Figure 11, with the STOWAD command, the C3 pin will be
pulled down by the 100µA current source during the B3
cell measurement and during the B4 cell measurement.
This will tend to decrease the B3 measurement result and
increase the B4 measurement result relative to the normal
STCVAD command. The biggest change is observed in the
B4 measurement when C3 is open. So, the best method to
detect an open wire at input C3 is to look for an increase
5. For battery cells, if CELLA(1) < 0 or CELLB(1) < 0, V–
must be open.
If CELLA(12) < 0 or CELLB(12) < 0, C12 must be open.
For n = 2 to 11, if CELLB(n+1) – CELLA(n+1) > 200mV,
or CELLB(n+1) reaches the full scale of 5.375V, then
Cn is open.
The 200mV threshold is chosen to provide tolerance for
measurement errors. For a system with the capacitor connected to Cn larger than 0.5µF, repeating step 3 several
times will discharge the external capacitor enough to meet
the criteria.
If the top C pin is open yet V+ is still connected, then the
best way to detect an open connection to the top C pin
is by comparing the sum of all cell measurements using
the STCVAD command to an auxiliary measurement of
the sum of all the cells, using a method similar to that
shown in Figure 21. A significantly lower result for the
sum of all 12 cells suggests an open connection to the
top C pin, provided it was already determined that no
other C pin is open.
USING THE S PINS AS DIGITAL OUTPUTS OR
GATE DRIVERS
The S outputs include an internal pull-up PMOS. Therefore
the S pins will behave as a digital output when loaded with
a high impedance, e.g., the gate of an external MOSFET.
For applications requiring high battery discharge currents,
connect a discrete PMOS switch device and suitable
680313fa
28
LTC6803-1/LTC6803-3
APPLICATIONS INFORMATION
discharge resistor to the cell, and the gate terminal to the
S output pin, as illustrated in Figure 12.
C (n)
Si2351DS
+
3.3k
S (n)
33Ω
1W
C (n – 1)
680313 F12
Figure 12. External Discharge FET Connection (One Cell Shown)
POWER DISSIPATION AND THERMAL SHUTDOWN
The MOSFETs connected to the pins S1 through S12 can be
used to discharge battery cells. An external resistor should
be used to limit the power dissipated by the MOSFETs. The
maximum power dissipation in the MOSFETs is limited by
the amount of heat that can be tolerated by the LTC6803.
Excessive heat results in elevated die temperatures. The
electrical characteristics for the LTC6803 I-grade are
guaranteed for die temperatures up to 85°C. Little or no
degradation will be observed in the measurement accuracy
for die temperatures up to 105°C. Damage may occur
above 150°C, therefore the recommended maximum die
temperature is 125°C.
To protect the LTC6803 from damage due to overheating,
a thermal shutdown circuit is included. Overheating of the
device can occur when dissipating significant power in the
cell discharge switches. The problem is exacerbated when
the thermal conductivity of the system is poor.
The thermal shutdown circuit is enabled whenever the
device is not in standby mode (see Modes of Operation).
It will also be enabled when any current mode input or
output is sinking or sourcing current. If the temperature
detected on the device goes above approximately 145°C,
the configuration registers will be reset to default states,
turning off all discharge switches and disabling ADC
conversions. When a thermal shutdown has occurred, the
THSD bit in the temperature register group will go high.
The bit is cleared by performing a read of the temperature
registers (RDTMP command).
Since thermal shutdown interrupts normal operation, the
internal temperature monitor should be used to determine
when the device temperature is approaching unacceptable
levels.
USING THE LTC6803 WITH LESS THAN 12 CELLS
If the LTC6803 is powered by the stacked cells, the minimum
number of cells is governed by the supply voltage requirements of the LTC6803. The sum of the cell voltages must be
10V to guarantee that all electrical specifications are met.
Figure 13 shows an example of the LTC6803 when used to
monitor seven cells. The lowest C inputs connect to theseven cells and the upper C inputs connect to C12. Other
configurations, e.g., 9 cells, would be configured in the
same way: the lowest C inputs connected to the battery
cells and the unused C inputs connected to C12. The unused
inputs will result in a reading of 0V for those channels.
The ADC can also be commanded to measure a stack of
10 or 12 cells, depending on the state of the CELL10 bit
in the control register. The ADC can also be commanded
to measure any individual cell voltage.
FAULT PROTECTION
Care should always be taken when using high energy
sources such as batteries. There are numerous ways
that systems can be misconfigured when considering
the assembly and service procedures that might affect a
battery system during its useful lifespan. Table 15 shows
the various situations that should be considered when planning protection circuitry. The first five scenarios are to be
anticipated during production and appropriate protection
is included within the LTC6803-1/LTC6803-3 device itself.
BATTERY INTERCONNECTION INTEGRITY
The FMEA scenarios involving a break in the stack of battery
cells are potentially the most damaging. In the case where
the battery stack has a discontinuity between groupings
of cells monitored by LTC6803 ICs, any load will force a
large reverse potential on the daisy-chain connection. This
680313fa
29
LTC6803-1/LTC6803-3
APPLICATIONS INFORMATION
NEXT HIGHER GROUP
OF 7 CELLS
100
+
+
+
+
+
+
+
NEXT HIGHER GROUP
OF 7 CELLS
100
V+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7 LTC6803-1
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
V–
NEXT LOWER GROUP
OF 7 CELLS
+
+
+
+
+
+
+
V+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7 LTC6803-3
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
C0
V–
NEXT LOWER GROUP
OF 7 CELLS
680313 F13
Figure 13. Monitoring 7 Cells with the LTC6803-1/LTC6803-3
Table 15. LTC6803-1/LTC6803-3 Failure Mechanism Effect Analysis
SCENARIO
Cell input open-circuit (random).
EFFECT
Power-up sequence at IC inputs.
Cell input open-circuit (random).
Differential input voltage overstress.
Disconnection of a harness
Loss of supply connection to the IC.
between a group of battery cells
and the IC (in a system of stacked
groups).
Data link disconnection between
Break of "daisy-chain" communication (no stress to
stacked LTC6803 units.
ICs). Communication will be lost to devices above the
disconnection. The devices below the disconnection
are still able to communicate and perform all functions,
however, the polling feature is disabled.
Cell-pack integrity, break between Daisy-chain voltage reversal up to full stack potential
stacked units.
during pack discharge.
Cell-pack integrity, break between
stacked units.
Cell-pack integrity, break within
stacked unit.
Daisy-chain positive overstress during charging.
Cell-pack integrity, break within
stacked unit.
Cell input positive overstress during charge.
Cell input reverse overstress during discharge.
DESIGN MITIGATION
Clamp diodes at each pin to V+ and V– (within IC) provide
alternate power path.
Zener diodes across each cell voltage input pair (within IC)
limits stress.
Separate power may be supplied by a local supply.
All units above the disconnection will enter standby mode
within 2 seconds of disconnect. Discharge switches are
disabled in standby mode.
Use series protection diodes with top-port I/O connections
(RS07J for up to 600V). Use isolated data link at bottommost data port.
Add redundant current path link. See Figure 14.
Add parallel Schottky diodes across each cell for loadpath redundancy. Diode and connections must handle full
operating current of stack, will limit stress on IC.
Add SCR across each cell for charge-path redundancy. SCR
and connections must handle full charging current of stack,
will limit stress on IC by selection of trigger Zener.
680313fa
30
LTC6803-1/LTC6803-3
APPLICATIONS INFORMATION
situation might occur in a modular battery system during
initial installation or a service procedure. The daisy-chain
ports are protected from the reverse potential in this scenario by external series high voltage diodes required in
the upper port data connections as shown in Figure 14.
During the charging phase of operation, this fault would
lead to forward biasing of daisy-chain ESD clamps that
would also lead to part damage. An alternative connection
to carry current during this scenario will avoid this stress
from being applied (Figure 14).
4
5
6
7
8
9
10
11
12
13
14
+
V–
PROTECT
AGAINST
BREAK
HERE
+
LTC6803-1
(NEXT HIGHER IN STACK)
16
SDO
OPTIONAL
REDUNDANT
CURRENT
PATH
15
SDI
SCKI
17
CSBI
RSO7J
×3
SDOI
V
SCKO
CSBO
+
18
19
20
21
LTC6803-1
(NEXT LOWER IN STACK)
22
860313 F14
Figure 14. Reverse-Voltage Protection for
the Daisy Chain (One Link Connection Shown)
23
24
25
26
Internal Protection Diodes
Each pin of the LTC6803 has protection diodes to help
prevent damage to the internal device structures caused
by external application of voltages beyond the supply rails
as shown in Figure 15. The diodes shown are conventional
silicon diodes with a forward breakdown voltage of 0.5V.
The unlabeled Zener diode structures have a reversebreakdown characteristic which initially breaks down at
12V then snaps back to a 7V clamping potential. The Zener
diodes labeled ZCLAMP are higher voltage devices with an
initial reverse breakdown of 30V snapping back to 25V.
The forward voltage drop of all Zeners is 0.5V. Refer to
Figure 15 in the event of unpredictable voltage clamping
or current flow. Limiting the current flow at any pin to
±10mA will prevent damage to the IC.
27
28
29
LTC6803-3
V+
C12
SCKO
3
S12
C11
SDOI
2
S11
C10
CSBO
ZCLAMP
1
S10
C9
S9
C8
S8
ZCLAMP
ZCLAMP
ZCLAMP
ZCLAMP
ZCLAMP
ZCLAMP
C7
VREG
S7
VREF
C6
ZCLAMP
VTEMP2
S6
VTEMP1
C5
35
34
33
32
S5
C4
CSBI
S4
SDO
C3
SDI
S3
SCKI
C2
VMODE
S2
GPIO2
ZCLAMP
C1
GPIO1
S1
WDTB
C0
TOS
V–
30
44
43
42
41
40
39
38
37
36
680313 F15
NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 30
Figure 15. Internal Protection Diodes
READING EXTERNAL TEMPERATURE PROBES
The LTC6803 includes two channels of ADC input, VTEMP1
and VTEMP2, that are intended to monitor thermistors
(tempco about –4%/°C generally) or diodes (–2.2mV/°C
typical) located within the cell array. Sensors can be
powered directly from VREF as shown in Figure 16 (up to
60µA total).
680313fa
31
LTC6803-1/LTC6803-3
APPLICATIONS INFORMATION
For sensors that require higher drive currents, a buffer
op amp may be used as shown in Figure 17. Power for
the sensor is actually sourced indirectly from the VREG
pin in this case. Probe loads up to about 1mA maximum
are supported in this configuration. Since VREF is shutdown during the LTC6803 idle and shutdown modes, the
thermistor drive is also shut off and thus power dissipation
minimized. Since VREG remains always on, the buffer op
amp (LT6000 shown) is selected for its ultralow power
consumption (12µA).
Expanding Probe Count
+
LT6000
–
LTC6803-1
VREG
VREF
VTEMP2
VTEMP1
NC
V–
10k
10k
NTC
10k
NTC
680313 F17
Figure 17. Buffering VREF for Higher Current Sensors
As shown Figure 18, a dual 4:1 multiplexer is used to expand the general purpose VTEMP1 and VTEMP2 ADC inputs
to accept 8 different probe signals. The channel is selected
by setting the general purpose digital outputs GPIO1 and
GPIO2 and the resultant signals are buffered by sections
of the LT6004 micropower dual operational amplifier. The
probe excitation circuitry will vary with probe type and is
not shown here.
100k
100k
PROBE8
PROBE7
PROBE6
PROBE5
6
4
5
+ –
Another method of multiple sensor support is possible
without the use of any GPIO pins. If the sensors are PN
diodes and several used in parallel, then the hottest diode
will produce the lowest forward voltage and effectively
establish the input signal to the VTEMP input(s). The hottest
diode will therefore dominate the readout from the VTEMP
inputs that the diodes are connected to. In this scenario,
the specific location or distribution of heat is not known,
but such information may not be important in practice.
Figure 19 shows the basic concept. In any of the sensor
configurations shown, a full-scale cold readout would be
an indication of a failed open-sensor connection to the
LTC6803.
LTC6803-1
VREG
VREF
VTEMP2
VTEMP1
NC
V–
10k
7
8
1/2 LT6004
1
2
3
4
5
6
7
8
Y0
VCC
X2
Y2
X1
Y
X
Y3
74HC4052
X0
Y1
X3
INH
A
VEE
GND
B
16
15
14
13
12
11
10
9
PROBE4
PROBE3
PROBE2
PROBE1
CPO2
GPO1
VREG
VTEMP2
VTEMP1
1/2 LT6004 8
+ 3
1
2
4
–
680313 F18
1µF
V–
Figure 18. Expanding Sensor Count with Multiplexing
LTC6803-1
VREG
VREF
VTEMP2
VTEMP1
NC
V–
200k
200k
680313 F19
1µF
1µF
100k
NTC
100k
NTC
Figure 19. Using Diode Sensors as Hot Spot Detectors
680313 F16
Figure 16. Driving Thermistors Directly from VREF
680313fa
32
LTC6803-1/LTC6803-3
APPLICATIONS INFORMATION
ADDING CALIBRATION AND FULL-STACK
MEASUREMENTS
thermal loading to the LTC6803 if powered from VREG, an
external high voltage NPN pass transistor is used to form
a local 4.4V (Vbe below VREG) from the battery stack. The
GPIO1 signal controls a PMOS FET switch to activate the
reference when calibration is to be performed. Since GPIO
signals default to logic high in shutdown, the reference
will automatically turn off during idle periods.
The general purpose VTEMP ADC inputs may be used to digitize any signals from 0V to 4V with accuracy corresponding
closely with that of the cell 1 ADC input. One useful signal
to provide is a high accuracy voltage reference, such as
3.300V from an LTC6655-3.3. From periodic readings of
this signal, the host software can provide correction of
the LTC6803 readings to improve the accuracy over that
of the internal LTC6803 reference and/or validate ADC
operation. Figure 20 shows a means of selectively powering an LTC6655-3.3 from the battery stack, under the
control of the GPIO1 output of the LTC6803-1. Since the
operational power of the reference IC would add significant
Another useful signal is a measure of the total stack potential. This provides a redundant operational measurement
of the cells in the event of a malfunction in the normal
acquisition process, or as a faster means of monitoring
the entire stack potential. Figure 21 shows how a resistive divider is used to derive a scaled representation of a
full cell group potential. A MOSFET is used to disconnect
TOP CELL POTETNTIAL
CZT5551
LTC6803-1
38
GPIO1
VREG
VTEMP1
V–
1M
Si2351DS
100nF
LTC6655-3.3
8
GND
SHDN
7
2
VOUT_F
VIN
6
3
GND VOUT_S
5
4
GND
GND
34
1
31
29
1µF
10µF
680313 F20
Figure 20. Providing Measurement of Calibration Reference
499k
CELL GROUP+
1M
2N7002K
WDTB
2
VREG
8
VTEMP1
1
+
1/2 LT6004
–
V–
CELL GROUP–
3
2
1
3
1µF
10nF
4
31.6k
680313 F21
Figure 21. Using a VTEMP Input for Full-Stack Readings
680313fa
33
LTC6803-1/LTC6803-3
APPLICATIONS INFORMATION
the resistive loading on the cell group when the IC enters
standby mode (i.e., when WDTB goes low). An LT6004
micropower operational amplifier section is shown for
buffering the divider signal to preserve accuracy. This
circuit has the virtue that it can be converted about four
times more frequently than the entire battery array, thus
offering a higher sample rate option at the expense of
some precision/accuracy, reserving the high resolution
cell readings for calibration and balancing data.
PROVIDING HIGH SPEED ISOLATION OF THE SPI DATA
PORT
Isolation techniques that are capable of supporting the
1Mbps data rate of the LTC6803 require more power on
the isolated (battery) side than can be furnished by the
VREG output of the LTC6803. To keep battery drain minimal,
this means that a DC/DC function must be implemented
along with a suitable data isolation circuit, such as shown
in Figure 22. A quad (3 + 1) data isolator Si8441AB-C-IS
is used to provide non-galvanic SPI signal connections
between a host microprocessor and an LTC6803. An
inexpensive isolated DC/DC converter provides power-
1
5V_HOST
2
SPI_CLOCK
SPI_CHIPSELECT
SPI_MASTEROUT
SPI_MASTERIN
100Ω
3
100Ω
4
100Ω
5
100Ω
6
1µF
GND_HOST
7
8
1µF
Si8441AB-C-IS
QUAD ISOLATOR
VDD1
VDD2
GND1
GND2
A1
B1
A2
B2
A3
B3
A4
B4
EN1
EN2
GND1
GND2
ing of the isolator function completely from the host 5V
power supply. A quad three-state buffer is used to allow
SPI inputs at the LTC6803 to rise to logic high level when
the isolator circuitry powers down, assuring the lowest
power consumption in the standby condition. The pullups to VREG are selected to match the internal loading on
VREG by ICs operating with a current mode SPI interface,
thus balancing the current in all cells during operation.
The additional pull-up on the SDO line (1k resistor and
Schottky diode) is to improve rise time, in lower data-rate
applications this may not be needed.
SUPPLY DECOUPLING IF BATTERY-STACK POWERED
As shown in Figure 23, the LTC6803-3 can have filtering
on both V+ and V–, so differential bypassing to the cell
group potentials is recommended. The Zener suppresses
overvoltages from reaching the IC supply pins. A small
ferrite-bead inductor provides protection for the Zener, particularly from energetic ESD strikes. Since the LTC6803-1
cannot have a series resistance to V–, additional Schottky
diodes are needed to prevent ESD-induced reverse-supply
(substrate) currents to flow.
CMDSH2-3
16
15
14
13
12
4.22k
11
1/4 74ABT126
13
12
1
2
11
10
1k
4.22k
3
1/4 74ABT126
1µF
9
CSB1
4
5
4.22k
6
1/4 74ABT126
4.22k
10
8
470pF
20.0k
33nF
PE-68386
1•
•6
3
4
BAT54S
74ABT126 SUPPLY SHARED WITH
ISOLATOR VDD2 and GND2
SCI
SDO
9
1/4 74ABT126
1 LTC1693-2 8
IN1
VCC1
2
7
GND1 OUT1
3
6
IN2
VCC2
4
5
GND2 OUT2
VREG
SCKI
680313 F22
V–
10.0k
Figure 22. Providing an Isolated High Speed Data Interface
680313fa
34
LTC6803-1/LTC6803-3
APPLICATIONS INFORMATION
CELLGROUP+
BLM31PG330SN1L
100Ω
CMHZ5265B
V+
100nF
BAT46W
CELLGROUP–
V–
680313 F23
LTC6803-1 Configuration
V+
TP0610K
DZ1
15V
LTC6803-3
IC #3
C0
CELLGROUP+
BLM31PG330SN1L
CMHZ5265B
CELLGROUP–
100Ω
100Ω
V+
V
V–
V+
The V– trace resistance can cause an observable voltage
drop between the negative end of the bottom battery
cell and V– pin of LTC6803. This voltage drop will add
to the measurement error of the bottom cell voltage for
LTC6803‑1. The LTC6803-3 separates C0 from V–, allowing Kelvin connection on C0 as shown in Figure 24. Any
voltage drop on V– trace will not affect the bottom cell
voltage measurement. The Kelvin connection will also
allow RC filtering on V– as shown in Figure 23.
LTC6803-1
+
+
BATTERY
STACK
+
LTC6803-3
C1
+
C1
R
V–
ISUPPLY
C0
R
ISUPPLY
DZ2
15V
LTC6803-3
IC #2
ADVANTAGES OF KELVIN CONNECTION ON C0
BATTERY
STACK
+
TP0610K
C12
Figure 23. Supply Decoupling
+
+
D1
–
100nF
LTC6803-3 Configuration
+
+
1M
+
+
C12
V–
680313 F24
Figure 24. Kelvin Connection on C0 Improving
Bottom Cell Voltage Measurement Accuracy
HARDWARE SHUTDOWN
To completely shut down the LTC6803 a PMOS switch can
be connected to V+, or V+ can be driven from an isolated
power supply. Figure 25 shows an example of a switched
1M
D2
C0
+
+
+
V–
V+
C12
LTC6803-3
IC #1
C0
TP0610K
DZ3
15V
1M
SHDN
DZ4
1.8V
50k
V–
+
+
+
680313 F25
DZ1, DZ2, DZ3: MMSZ5245B
DZ4: MMSZ4678T1
ALL NPN: MMBTA42
ALL PN: RS07J
Figure 25. Hardware Shutdown Circuit Reduces Total Supply
Current of LTC6803 to Less Than 1nA
V+. The breakdown voltage of DZ4 is about 1.8V. If SHDN <
1.8V, no current will flow through the stacked MMBTA42s
and the 1M resistors. TP0610Ks will be completely shut
off. If SHDN > 2.5V, M7 will be turned on and all TP0610Ks
will be turned on.
Figure 26 is an example of isolated power supply. This
circuit provides power for two LTC6803s used to monitor
24 series connected battery cells. When 5V is removed, the
LTC6803s will draw 1nA from the battery cells. Note that
use of an external V+ supply will not protect daisy-chain
SPI operation at low total stack potentials (below 5V).
680313fa
35
LTC6803-1/LTC6803-3
APPLICATIONS INFORMATION
1µF
10k
10µF
1
16
2
15
3
14
1µF
BAT54S
1µF
11
7
10
8
9
BAT54S
1µF
1µF
1µF
6
1µF
1µF
100k
BAT54S IMC1210ER
BAT54S
1µF
1µF
1µF
1µF
100V
EACH OUTPUT
61V TYP
+V1
CMHZ5265B
COM1
1µF
1
5V
LTC1693-2
8
VCC1
IN1
2
7
GND1 OUT1
3
6
IN2
VCC2
4
5
GND2 OUT2
INPUT
5V
90mA TYP
220pF
33.2k
1µF
GND
EPF8119S
BAT54S
1µF
BAT54S
1µF
100k
BAT54S IMC1210ER
BAT54S
1µF
1µF
1µF
100V
+V2
CMHZ5265B
680313 F26
COM2
Figure 26. LTC6803 Powered by Isolated Power Supplies
PCB LAYOUT CONSIDERATIONS
The VREG and VREF pins should be bypassed with a 1µF
capacitor for best performance. The LTC6803 is capable of
operation with as much as 55V between V+ and V–. Care
should be taken on the PCB layout to maintain physical
separation of traces at different potentials. The pinout of
the LTC6803-1 and LTC6803-3 were chosen to facilitate
this physical separation. There is no more than 5.5V
between any two adjacent pins. The package body is used
to separate the highest voltage (e. g., 43.2V) from the lowest voltage (0V). As an example, Figure 27 shows the DC
voltage on each pin with respect to V– when twelve 3.6V
battery cells are connected to the LTC6803-3.
ADVANTAGES OF DELTA-SIGMA ADCS
The LTC6803 employs a delta-sigma analog-to-digital
converter for voltage measurement. The architecture of
delta sigma converters can vary considerably, but the
common characteristic is that the input is sampled many
times over the course of a conversion and then filtered or
averaged to produce the digital output code. In contrast,
a SAR converter takes a single snapshot of the input
voltage and then performs the conversion on this single
sample. For measurements in a noisy environment, a
delta sigma converter provides distinct advantages over
a SAR converter.
42.5V
42.5V
42.5V
43.2V
43.2V
43.2V
39.6V
39.6V
36V
36V
32.4V
32.4V
28.8V
28.8V
25.2V
25.2V
21.6
21.6
18V
18V
14.4V
14.4V
CSBI
CSBO
SDO
SDOI
SDI
SCKO
SCKI
V+
VMODE
C12
GPIO2
S12
GPIO1
C11
WDTB
S11
C10 LTC6803-3 TOS
VREG
S10
VREF
C9
VTEMP2
S9
VTEMP1
C8
NC
S8
V–
C7
C0
S7
S1
C6
C1
S6
S2
C5
C2
S5
S3
C4
C3
S4
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
5V
3.1V
1.5V
1.5V
0V
0V
0V
3.6V
3.6V
7.2V
7.2V
10.8V
10.8V
680313 F27
Figure 27. Typical Pin Voltages for Twelve 3.6V Cells
While SAR converters can have high sample rates, the fullpower bandwidth of a SAR converter is often greater than
1MHz, which means the converter is sensitive to noise out
to this frequency. And many SAR converters have much
higher bandwidths—up to 50MHz and beyond. It is possible to filter the input, but if the converter is multiplexed
to measure several input channels a separate filter will be
680313fa
36
LTC6803-1/LTC6803-3
APPLICATIONS INFORMATION
For a given sample rate, a delta-sigma converter can
achieve excellent noise rejection while settling completely
in a single conversion—something that a filtered SAR converter cannot do. Noise rejection is particularly important
in high voltage switching controllers, where switching
noise will invariably be present in the measured voltage.
Other advantages of delta-sigma converters are that they
are inherently monotonic, meaning they have no missing
codes, and they have excellent DC specifications.
Converter Details
The LTC6803’s ADC has a second order delta-sigma
modulator followed by a SINC2, finite impulse response
(FIR) digital filter. The front-end sample rate is 512ksps,
which greatly reduces input filtering requirements. A
simple 16kHz, 1-pole filter composed of a 100Ω resistor
and a 0.1µF capacitor at each input will provide adequate
filtering for most applications. These component values
will not degrade the DC accuracy of the ADC.
Each conversion consists of two phases—an autozero
phase and a measurement phase. The ADC is autozeroed
at each conversion, greatly improving CMRR. The second
half of the conversion is the actual measurement.
Noise Rejection
Figure 28 shows the frequency response of the ADC. The
roll-off follows a SINC2 response, with the first notch at
4kHz. Also shown is the response of a 1-pole, 850Hz filter
(187µs time constant) which has the same integrated
response to wideband noise as the LTC6803’s ADC, which
10
0
FILTER GAIN (dB)
required for each channel. A low frequency filter cannot
reside between a multiplexer and an ADC and achieve a
high scan rate across multiple channels. Another consequence of filtering a SAR ADC is that any noise reduction
gained by filtering the input cancels the benefit of having
a high sample rate in the first place, since the filter will
take many conversion cycles to settle.
–10
–20
–30
–40
–50
–60
10
100
1k
10k
FREQUENCY (Hz)
100k
680313 F28
Figure 28. Noise Filtering of the LTC6803 ADC
is about 1350Hz. This means that if wideband noise is
applied to the LTC6803 input, the increase in noise seen
at the digital output will be the same as an ADC with a
wide bandwidth (such as a SAR) preceded by a perfect
1350Hz brick wall lowpass filter.
Thus if an analog filter is placed in front of a SAR converter
to achieve the same noise rejection as the LTC6803 ADC,
the SAR will have a slower response to input signals. For
example, a step input applied to the input of the 850Hz
filter will take 1.55ms to settle to 12 bits of precision, while
the LTC6803 ADC settles in a single 1ms conversion cycle.
This also means that very high sample rates do not provide
any additional information because the analog filter limits
the frequency response.
While higher order active filters may provide some improvement, their complexity makes them impractical for
high channel count measurements as a single filter would
be required for each input.
Also note that the SINC2 response has a 2nd order rolloff envelope, providing an additional benefit over a single
pole analog filter.
680313fa
37
LTC6803-1/LTC6803-3
PACKAGE DESCRIPTION
G Package
44-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1754 Rev Ø)
12.50 – 13.10*
(.492 – .516)
1.25 ±0.12
7.8 – 8.2
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
5.3 – 5.7
0.25 ±0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 – 5.60*
(.197 – .221)
PARTING
LINE
0.10 – 0.25
(.004 – .010)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
2.0
(.079)
MAX
1.65 – 1.85
(.065 – .073)
0° – 8°
0.55 – 0.95**
(.022 – .037)
1.25
(.0492)
REF
NOTE:
1.DRAWING IS NOT A JEDEC OUTLINE
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSIONS ARE IN
0.50
BSC
7.40 – 8.20
(.291 – .323)
MILLIMETERS
(INCHES)
4. DRAWING NOT TO SCALE
5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE
0.50
(.01968)
BSC
SEATING
PLANE
0.20 – 0.30†
(.008 – .012)
TYP
0.05
(.002)
MIN
G44 SSOP 0607 REV Ø
*DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS,
BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT
THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE
**LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE
†THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE
680313fa
38
LTC6803-1/LTC6803-3
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
08/12
Clarification to UV/OV Operation
Correction to 12-Cell Li-Ion Application Circuit
14, 15
40
680313fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
39
LTC6803-1/LTC6803-3
TYPICAL APPLICATION
Cascadable 12-Cell Li-Ion Battery Monitor
CELL12
IMC1210ER100K
MM5Z5265B
BAT46W
1M
BAT46W
CASCADED SPI PORT
TO NEXT LTC6803-1
100Ω
100nF
CSBI
SDI
SCKI
2
3
4
5
C12FILTER
6
DC12
7
C11FILTER
8
DC11
9
C10FILTER
10
DC10
11
C9FILTER
REPEAT INPUT
CIRCUITS FOR
CELL3 TO CELL12
1
12
DC9
13
C8FILTER
14
DC8
15
C7FILTER
16
DC7
17
C6FILTER
18
DC6
19
C5FILTER
20
DC5
21
C4FILTER
22
DC4
CSBO
CSBI
SDOI
SDO
SCKO
SDI
V+
SCKI
C12
VMODE
S12
GPIO2
C11
GPIO1
S11
WDTB
C10 LTC6803-1
NC
S10
TOS
C9
VREG
S9
VREF
C8
VTEMP2
S8
VTEMP1
C7
NC
C6
S6
C5
S5
C4
S4
CSBI
SDO* MAIN SPI PORT
TO HOST µP OR
SDI
NEXT LTC6803-1
SCKI
42
41
40
*REQUIRES 1k PULL-UP RESISTOR AT HOST DEVICE
(SIGNAL NOT USED FOR INTER-IC COMMUNCATION)
39 1M
1M
38
37 1M
36
35
34
33
32
31
10k
30
CELL2
100Ω
3
+
2
–
1µF
5
6
C2FILTER
100nF
RQJ0303PGDQA
CELL1
3.3k
475Ω
100Ω
RQJ0303PGDQA
8
100Ω
1
100nF
1/2 LT6004
+
4
8
1/2 LT6004
–
4
7
10k
NTC1
100Ω
100nF
PDZ7.5B
33Ω
NTC2
1µF
C3FILTER
DC3
1M
43
29
V–
28
S1
27
C1
26
S2
25
C2
24
S3
23
C3
S7
1M
44
680313 TA02
DC2
C1FILTER
100nF
PDZ7.5B
33Ω
3.3k
475Ω
DC1
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC6801
Independent Multicell Battery Stack Fault Monitor
Monitors Up to 12 Series-Connected Battery Cells for Undervoltage or
Overvoltage. Companion to LTC6802 and LTC6803 Family
LTC6802-1
Multicell Battery Stack Monitor with Parallel Addressed
Serial Interface
Functionally Equivalent to the LTC6803-1 and LTC6803-3, Pin Compatible with
the LTC6803-1
LTC6802-2
Multicell Battery Stack Monitor with an Individually
Addressable Serial Interface
Functionally Equivalent to LTC6803-2/LTC6803-4, Pin Compatible with the
LTC6803-2
LTC6803-2/
LTC6803-4
Multicell Battery Stack Monitor with an Individually
Addressable Serial Interface
Functionality Equivalent to LTC6803-1/LTC6803-3, Allows for Parallel
Communication Battery Stack Topologies
680313fa
40 Linear Technology Corporation
LT 0812 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2011
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