LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Low Phase Noise, Dual
Output Buffer/Driver/
Logic Converter
DESCRIPTION
FEATURES
Low Phase Noise Buffer/Driver
nn Optimized Conversion of Sine Wave Signals to
Logic Levels
nn Three Logic Output Types Available
nn LVPECL
nn LVDS
nn CMOS
nn Additive Jitter 45fs
RMS (LTC6957-1)
nn Frequency Range Up to 300MHz
nn 3.15V to 3.45V Supply Operation
nn Low Skew 3ps Typical
nn Fully Specified from –40°C to 125°C
nn 12-Lead MSOP and 3mm × 3mm DFN Packages
The LTC®6957-1/LTC6957-2/LTC6957-3/LTC6957-4 is a
family of very low phase noise, dual output AC signal
buffer/driver/logic level translators. The input signal can
be a sine wave or any logic level (≤2VP-P). There are four
members of the family that differ in their output logic
signal type as follows:
nn
LTC6957-1: LVPECL Logic Outputs
LTC6957-2: LVDS Logic Outputs
LTC6957-3: CMOS Logic, In-Phase Outputs
LTC6957-4: CMOS Logic, Complementary Outputs
The LTC6957 will buffer and distribute any logic signal
with minimal additive noise, however, the part really
excels at translating sine wave signals to logic levels. The
early amplifier stages have selectable lowpass filtering
to minimize the noise while still amplifying the signal to
increase its slew rate. This input stage filtering/noise limiting is especially helpful in delivering the lowest possible
phase noise signal with slow slewing input signals such
as a typical 10MHz sine wave system reference.
APPLICATIONS
System Reference Frequency Distribution
High Speed ADC, DAC, DDS Clock Driver
nn Military and Secure Radio
nn Low Noise Timing Trigger
nn Broadband Wireless Transceiver
nn High Speed Data Acquisition
nn Medical Imaging
nn Test and Measurement
nn
nn
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents 7969189 and 8319551.
TYPICAL APPLICATION
3.3V
0.1µF
Additive Phase Noise at 100MHz
–140
OCXO
100MHz
+7dBm
SINE WAVE
V+
SD1
FILTB
10nF
–145
OUT1
IN+
TO PLL CHIPS
OR SYSTEM
SAMPLING CLOCKS
–
IN
50Ω
10nF
OUT2
GND
SD2
6957 TA01a
PHASE NOISE (dBc/Hz)
FILTA
SINGLE-ENDED SINE WAVE INPUT
AT +7dBm (500mVRMS)
FILTA = FILTB = GND
LTC6957-2 (LVDS)
–150
LTC6957-4 (CMOS)
–155
–160
LTC6957-3
(CMOS)
–165
100
LTC6957-1 (LVPECL)
1k
10k
100k
OFFSET FREQUENCY (Hz)
1M
69571234 TA01b
6957fb
For more information www.linear.com/LTC6957-1
1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage (V+ or VDD) to GND...........................3.6V
Input Current (IN+, IN–, FILTA, FILTB, SD1, SD2)
(Note 2)........................................................... ±10mA
LTC6957-1 Output Current ......................... 1mA, –30mA
LTC6957-2 Output Current .................................. ±10mA
LTC6957-3, LTC6957-4 Output Current (Note 3)... ±30mA
Specified Temperature Range
LTC6957I..............................................–40°C to 85°C
LTC6957H........................................... –40°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (for MSOP Soldering, 10sec).... 300°C
PIN CONFIGURATION
LTC6957-1, LTC6957-2
LTC6957-3, LTC6957-4
TOP VIEW
TOP VIEW
FILTA
1
12 SD1
FILTA
1
V+
2
11 OUT1+
V+
2
IN+
3
10 OUT1–
IN+
3
IN–
4
9 OUT2–
IN–
4
OUT2+
GND
5
FILTB
6
13
GND
GND
5
8
FILTB
6
7 SD2
13
GND
11 V DD
10 OUT1
9 OUT2
8 GNDOUT
7 SD2
DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 58°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 58°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
LTC6957-1, LTC6957-2
LTC6957-3, LTC6957-4
TOP VIEW
FILTA
V+
IN+
IN–
GND
FILTB
2
12 SD1
1
2
3
4
5
6
TOP VIEW
12
11
10
9
8
7
SD1
OUT1+
OUT1–
OUT2–
OUT2+
SD2
FILTA
V+
IN+
IN–
GND
FILTB
1
2
3
4
5
6
12
11
10
9
8
7
MS PACKAGE
12-LEAD PLASTIC MSOP
MS PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 145°C/W
TJMAX = 150°C, θJA = 145°C/W
SD1
V DD
OUT1
OUT2
GNDOUT
SD2
6957fb
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ORDER INFORMATION
http://www.linear.com/product/LTC6957-1#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6957IDD-1#PBF
LTC6957IDD-1#TRPBF
LFQJ
12-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6957IDD-2#PBF
LTC6957IDD-2#TRPBF
LFQK
12-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6957IDD-3#PBF
LTC6957IDD-3#TRPBF
LFQM
12-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6957IDD-4#PBF
LTC6957IDD-4#TRPBF
LFQN
12-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6957IMS-1#PBF
LTC6957IMS-1#TRPBF
69571
12-Lead Plastic MSOP
–40°C to 85°C
LTC6957HMS-1#PBF
LTC6957HMS-1#TRPBF
69571
12-Lead Plastic MSOP
–40°C to 125°C
LTC6957IMS-2#PBF
LTC6957IMS-2#TRPBF
69572
12-Lead Plastic MSOP
–40°C to 85°C
LTC6957HMS-2#PBF
LTC6957HMS-2#TRPBF
69572
12-Lead Plastic MSOP
–40°C to 125°C
LTC6957IMS-3#PBF
LTC6957IMS-3#TRPBF
69573
12-Lead Plastic MSOP
–40°C to 85°C
LTC6957HMS-3#PBF
LTC6957HMS-3#TRPBF
69573
12-Lead Plastic MSOP
–40°C to 125°C
LTC6957IMS-4#PBF
LTC6957IMS-4#TRPBF
69574
12-Lead Plastic MSOP
–40°C to 85°C
LTC6957HMS-4#PBF
LTC6957HMS-4#TRPBF
69574
12-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
6957fb
For more information www.linear.com/LTC6957-1
3
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS
LTC6957-1
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 50Ω connected to 1.3V, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
300
MHz
0.8
2
VP-P
0.8
2
VP-P
Inputs (IN–, IN+)
fIN
Input Frequency Range
l
VINSE
Input Signal Level Range, Single-Ended
l
0.2
VINDIFF
Input Signal Level Range, Differential
l
0.2
tMIN
Minimum Input Pulse Width
VINCM
Self-Bias Voltage, IN+, IN–
l
1.8
2.06
2.3
V
RIN
Input Resistance, Differential
l
1.5
2
2.5
kΩ
CIN
Input Capacitance, Differential
BWIN
Input Section Small Signal Bandwidth (–3dB)
High or Low
0.5
ns
0.5
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
pF
1200
500
160
50
MHz
MHz
MHz
MHz
Outputs (LVPECL)
VOH
Output High Voltage
LTC6957I
LTC6957H
l
l
V+ – 1.22 V+ – 0.98 V+ – 0.93
V+ – 1.22 V+ – 0.98 V+ – 0.87
V
V
VOL
Output Low Voltage
LTC6957I
LTC6957H
l
l
V+ – 2.1
V+ – 2.1
V+ – 1.8
V+ – 1.8
V+ – 1.67
V+ – 1.62
V
V
VOD
Output Differential Voltage
l
±660
±810
±965
tr
Output Rise Time
180
ps
tf
Output Fall Time
160
ps
t PD
Propagation Delay
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
l
l
l
l
∆tPD /∆T
Propagation Delay Variation Over Temperature
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
l
l
l
l
0.1
0.1
0.11
0.15
∆tPD/∆V
Propagation Delay Variation vs Supply Voltage
FILTB = L, FILTA = L
l
4
50
ps/V
tSKEW
Output Skew, Differential, CH1 to CH2
l
3
30
ps
tMATCH
Output Matching (OUTx + to OUTx–)
See Timing Diagram
l
2.5
30
ps
V+
V+ Operating Supply Voltage Range
RLOAD = 50Ω to (V+– 2V)
l
3.3
3.45
V
IS
Supply Current
Both Outputs Enabled (SD1 = SD2 = L)
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L)
Both Outputs Disabled (SD1 = SD2 = H)
Including Output Loads
No Output Loads
No Output Loads
No Output Loads
RLOAD = 50Ω to (V+– 2V), ×4
l
l
l
l
18
15
0.7
58
22
19
1.2
72
mA
mA
mA
mA
0.35
0.5
0.6
1.1
3.2
0.7
0.8
1.3
4
mV
ns
ns
ns
ns
ps/°C
ps/°C
ps/°C
ps/°C
Power
3.15
tENABLE
Output Enable Time, Other SDx = L
40
µs
tWAKEUP
Output Enable Time, Other SDx = H
120
µs
tDISABLE
Output Disable Time, Other SDx = L
20
µs
tSLEEP
Output Disable Time, Other SDx = H
20
µs
4
6957fb
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS
LTC6957-1
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 50Ω connected to 1.3V, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Logic Inputs
VIH
High Level SD or FILT Input Voltage
l
VIL
Low Level SD or FILT Input Voltage
l
IIN_DIG
Input Current SD or FILT Pins
l
V+ – 0.4
V
0.1
0.4
V
±10
µA
Additive Phase Noise and Jitter
fIN = 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
at 10Hz Offset
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
–130
–140
–150
–157
–157.5
–157.5
123
45
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
fIN = 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
at 10Hz Offset
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
–137
–146
–154.6
–157
–157.2
–157.2
200
114
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
fIN = 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
at 10Hz Offset
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
–138
–148.1
–156.8
–160.6
–161
–161
142
90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
6957fb
For more information www.linear.com/LTC6957-1
5
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS
LTC6957-2
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 110Ω differential, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
300
MHz
Inputs (IN–, IN+)
fIN
Input Frequency Range
l
VINSE
Input Signal Level Range, Single-Ended
l
0.2
0.8
2
VP-P
VINDIFF
Input Signal Level Range, Differential
l
0.2
0.8
2
VP-P
tMIN
Minimum Input Pulse Width
VINCM
Self-Bias Voltage, IN+, IN–
l
1.8
2
2.3
V
RIN
Input Resistance, Differential
l
1.5
2
2.5
kΩ
CIN
Input Capacitance, Differential
BWIN
Input Section Small Signal Bandwidth
High or Low
0.5
ns
0.5
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
pF
1200
500
160
50
MHz
MHz
MHz
MHz
Outputs (LVDS)
VOD
Output Differential Voltage
l
∆VOD
Delta VOD
l
VOS
Output Offset Voltage
l
∆VOS
Delta VOS
l
ISC
Short-Circuit Current
l
tr
Output Rise Time
170
ps
tf
Output Fall Time
170
ps
t PD
Propagation Delay
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
l
l
l
l
∆tPD /∆T
Propagation Delay Variation Over Temperature
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
l
l
l
l
0.5
0.6
0.7
1.8
∆tPD /∆V Propagation Delay Variation vs Supply Voltage
FILTB = L, FILTA = L
l
5
60
ps/V
Output Skew, Differential, CH1 to CH2
l
3
50
ps
V+
V+ Operating Supply Voltage Range
l
3.3
3.45
V
IS
Supply Current
Both Outputs Enabled (SD1 = SD2 = L)
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L)
Both Outputs Disabled (SD1 = SD2 = H)
l
l
l
38
26
0.7
45
30
1.2
mA
mA
mA
tSKEW
250
1.125
0.65
360
450
mV
0.2
50
mV
1.25
1.375
1.5
50
mV
3.9
6
mA
0.84
0.9
1.35
3.5
1.15
1.3
1.8
4.4
V
ns
ns
ns
ns
ps/°C
ps/°C
ps/°C
ps/°C
Power
3.15
tENABLE
Output Enable Time, Other SDx = L
300
ns
tWAKEUP
Output Enable Time, Other SDx = H
400
ns
tDISABLE
Output Disable Time, Other SDx = L
40
ns
tSLEEP
Output Disable Time, Other SDx = H
50
ns
6
6957fb
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS
LTC6957-2
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 110Ω differential, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Logic Inputs
VIH
High Level SD or FILT Input Voltage
l
VIL
Low Level SD or FILT Input Voltage
l
IIN_DIG
Input Current SD or FILT Pins
l
V+ – 0.4
V
0.1
0.4
V
±10
µA
Additive Phase Noise and Jitter
fIN = 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
–124
–134
–143.5
–151.3
–154
–154
183
67
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
fIN = 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
–132.5
–142.5
–150.7
–156
–157
–157
203
116
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
fIN = 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
–132
–142
–151
–157.5
–159.5
–159.5
169
107
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
6957fb
For more information www.linear.com/LTC6957-1
7
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS
LTC6957-3/LTC6957-4
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD /2, unless otherwise specified. All voltages are with
respect to ground.
SYMBOL PARAMETER
CONDITIONS
Inputs (IN–, IN+)
Input Frequency Range
fIN
Input Signal Level Range, Single-Ended
VINSE
VINDIFF Input Signal Level Range, Differential
tMIN
Minimum Input Pulse Width
Self-Bias Voltage, IN+, IN–
VINCM
Input Resistance, Differential
RIN
Input Capacitance, Differential
CIN
Input Section Small Signal Bandwidth
BWIN
l
l
0.2
0.2
0.8
0.8
0.6
2
2
0.5
1200
500
160
50
High or Low
l
1.8
1.5
l
l
VDD – 0.1
VDD – 0.2
l
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
No Load
–3mA Load
No Load
3mA Load
VOL
Output Low Voltage
tr
tf
tPD
Output Rise Time
Output Fall Time
Propagation Delay
∆tPD/∆T
Propagation Delay Variation Over Temperature
∆tPD/∆V
Propagation Delay Variation vs Supply Voltage
tSKEW
Output Skew, CH1 to CH2
LTC6957-3
LTC6957-4
IDD
V+ Operating Supply Voltage Range
VDD Operating Supply Voltage Range
Supply Current, Pin 2
Both Outputs Enabled (SD1 = SD2 = L)
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L)
Both Outputs Disabled (SD1 = SD2 = H)
Supply Current, Pin 11, No Load
tENABLE
tWAKEUP
tDISABLE
tSLEEP
Output Enable Time, Other SDx = L
Output Enable Time, Other SDx = H
Output Disable Time, Other SDx = L
Output Disable Time, Other SDx = H
8
TYP
l
Outputs (CMOS)
Output High Voltage
VOH
Power
V+
VDD
IS
MIN
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
FILTB = FILTA = L, V+ = VDD
300
2
2
MHz
VP-P
VP-P
ns
V
kΩ
pF
MHz
MHz
MHz
MHz
2.3
2.5
l
320
300
0.95
1
1.5
3.6
1.7
1.7
2
3
100
200
l
l
5
120
35
250
ps
ps
3.3
3.3
3.45
3.45
V
V
24
24
0.7
0.001
0.056
200
300
20
20
27.5
27.5
1.2
0.01
0.07
mA
mA
mA
mA
mA/MHz
ns
ns
ns
ns
0.1
0.2
l
l
l
l
l
l
0.8
l
l
l
l
l
l
l
l
Static
Dynamic, per Output
UNITS
V
V
V
V
ps
ps
ns
ns
ns
ns
ps/°C
ps/°C
ps/°C
ps/°C
ps/V
l
VDD Must Be ≤V +
MAX
l
l
3.15
2.4
1.6
1.8
2.4
4.8
6957fb
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
ELECTRICAL CHARACTERISTICS
LTC6957-3/LTC6957-4
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD /2, unless otherwise specified. All voltages are with
respect to ground.
SYMBOL PARAMETER
CONDITIONS
Digital Logic Inputs
VIH
High Level SD or Filt Input Voltage
Low Level SD or Filt Input Voltage
VIL
Input Current SD or Filt Pins
IIN_DIG
MIN
l
TYP
MAX
UNITS
0.1
0.4
±10
V
V
µA
V+ – 0.4
l
l
Additive Phase Noise and Jitter
fIN = 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
fIN = 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
fIN = 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Input pins IN+, IN–, FILTA, FILTB, SD1 and SD2 are protected by
steering diodes to either supply. If the inputs go beyond either supply rail,
the input current should be limited to less than 10mA. If pushing current
into FILTB, the Pin 6 voltage must be limited to 4V. On the logic pins
(FILTA, FILTB, SD1 and SD2) the Absolute Maximum input current applies
–123
–133
–143
–152
–156
–156
146
53
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
–132
–142
–150.6
–156.5
–157.4
–157.4
192
109
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
–135
–145
–153
–159.8
–161
–161
142
90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
only at the maximum operating supply voltage of 3.45V; 10mA of input
current with the absolute maximum supply voltage of 3.6V may create
permanent damage from voltage stress.
Note 3: With 3.6V Absolute Maximum supply voltage, the LTC6957-3/
LTC6957-4 CMOS outputs can sink 30mA while low, and source 30mA
while high without damage. However, if overdriven or subject to an
inductive load kick outside the supply rails, 30mA can create damaging
voltage stress and is not guaranteed unless VDD is limited to 3.15V.
6957fb
For more information www.linear.com/LTC6957-1
9
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
20
V+ = 3.45V
16
2.10
SUPPLY CURRENT (mA)
INPUT VOLTAGE (V)
NO OUTPUT LOADS
18
2.15
V+ = 3.3V
2.05
2.00
V+ = 3.15V
18.4
12
TA = –55°C
TA = 25°C
10
8
6
5 25 45 65 85 105 125
TEMPERATURE (°C)
17.2
16.8
0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
SUPPLY VOLTAGE (V)
2.45
Supply Current vs Temperature
58
V+ = 3.3V
50Ω LOADS TO 1.3V
1.55
VOL
SUPPLY CURRENT (mA)
OUTPUT VOLTAGE (V)
1.60
V+ = 3.45V
56
VOH
2.30
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G03
Output Voltage vs Temperature
2.50
1.50
17.4
16.6
–55 –35 –15
2.4
VOH
V+ = 3.15V
17.8
2
Output Voltage vs Load Current
1.45
18.0
69571234 G02
2.55
2.35
V+ = 3.3V
0
69571234 G01
2.40
V+ = 3.45V
18.2
17.0
4
1.90
–55 –35 –15
NO OUTPUT LOADS
18.8
TA = 125°C
14
1.95
OUTPUT VOLTAGE (V)
Supply Current vs Temperature
18.6
SUPPLY CURRENT (mA)
2.20
LTC6957-1
2.2
1.6
VOL
54
V+ = 3.3V
52
V+ = 3.15V
50
48
50Ω “Y” LOAD TO GROUND
ON BOTH CHANNELS
1.40
–8
–2
–6
–4
LOAD CURRENT (mA)
1.4
–55 –35 –15
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
Enable and Wakeup
WAKE-UP:
OUTPUTS WITH
OTHER CHANNEL OFF
80
NUMBER OF UNITS
2.5V
2.0V
1.5V
ENABLE: OUTPUTS WITH
OTHER CHANNEL ON
3.0V
0V
SD
Differential Output vs Frequency
60
1.8
OUT1+ TO OUT2+ RISING EDGE
TYPICAL OF ALL OUTPUT EDGES/PAIRS
1.6
2 LOTS, 400
UNITS EACH,
3 TEMPERATURES
= 125°C
= 25°C
= –55°C
40
20
69571234 G07
20ns/DIV
MULTIPLE EXPOSURES, PERSISTENCE MODE
CLOCK I/O = 120MHz
SD DRIVE ~ 140kHz, ASYNCHRONOUS
1.4
1.2
125°C
1.0
0.8
25°C
0.6
0.4
–55°C
0.2
0
–10 –8 –6 –4 –2 0 2
tSKEW (ps)
4
6
8
10
69571234 G08
PRODUCTION DATA,
1ps RESOLUTION, ~1-2ps UNCERTAINTY
10
69571234 G06
Typical Distribution of Skew
100
2.5V
1.5V
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G05
69571234 G04
2.0V
46
–55 –35 –15
DIFFERENTIAL OUTPUT (VP-P)
1.35
–10
0
0dBm INPUT
0
250 500 750 1000 1250 1500 1750 2000
FREQUENCY (MHz)
69571234 G09
6957fb
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
Additive Phase Noise
vs Input Frequency
300MHz
153.6MHz
–155
–160
–140
–10dBm, FILTA = L, FILTB = H
–145
0dBm, FILTA = H, FILTB = L
–150
–155
–165
100
1M
1k
10k
100k
OFFSET FREQUENCY (Hz)
69571234 G10
PHASE NOISE (dBc/Hz)
–150
3.45V
3.3V
–160
–145
0dBm, FILTA = H, FILTB = L
–150
–155
7dBm, FILTA = FILTB = L
–165
1k
10k
100k
100
OFFSET FREQUENCY (Hz)
1M
0.550
3.5
FILTA = FILTB = H
69571234 G16
tPD (ns)
tPD (ns)
125°C
0.56
V+ = 3.0V, 50Ω LOADS TO 1.3V
0.54
V+ = 3.3V, 50Ω LOADS TO 1.3V
0.450
–55 –35 –15
50Ω LOADS TO V+ –2V
0.52
0.50
50Ω LOADS TO FIXED 1.3V
0.475
5 25 45 65 85 105 125
TEMPERATURE (°C)
25°C
–3
tPD vs Supply Voltage and
Termination Voltage
0.500
FILTA = H, FILTB = L
0
–55 –35 –15
–1
–2
tPD vs Temperature
0.525
FILTA = FILTB = L
–55°C
0
69571234 G15
V+ = 3.6V, 50Ω LOADS TO 1.9V
3.0
0.5
2
1
69571234 G14
tPD vs Temperature
1.0
3
–4
EACH CURVE NORMALIZED TO 0° AT 0dBm
–5
–10 –8 –6 –4 –2 0 2 4 6 8 10
INPUT AMPLITUDE (dBm)
1M
69571234 G13
FILTA = L, FILTB = H
fIN = 300MHz
V+ = 3.3V
4
–140
1M
AM to PM Conversion
5
–160
3.15V
1k
10k
100k
OFFSET FREQUENCY (Hz)
1k
10k
100k
OFFSET FREQUENCY (Hz)
69571234 G12
tPD (ns)
PHASE NOISE (dBc/Hz)
1M
SINGLE-ENDED SINE WAVE INPUT
–145
125°C
–55°C
–165
100
–135
–140
25°C
–155
–130
SINGLE-ENDED SINE WAVE INPUT,
100MHz at 7dBm (500mVRMS)
FILTA = FILTB = L
–165
100
–150
Additive Phase Noise at 122.88MHz
–130
–155
–145
69571234 G11
Additive Phase Noise
vs Supply Voltage
–135
–140
–160
+10dBm, FILTA = FILTB = L
1k
10k
100k
OFFSET FREQUENCY (Hz)
SINGLE-ENDED SINE WAVE INPUT,
100MHz at 7dBm (500mVRMS)
FILTA = FILTB = L
–135
–160
100MHz
–165
100
–130
SINGLE-ENDED 100MHz SINE WAVE INPUT
SEE APPLICATIONS INFORMATION
PHASE NOISE (dBc/Hz)
–145
–150
–135
PHASE NOISE (dBc/Hz)
–140
Additive Phase Noise
vs Temperature
–130
SINGLE-ENDED SINE WAVE INPUT
AT 7dBm (500mVRMS)
FILTA = FILTB = L
–135
PHASE NOISE (dBc/Hz)
Additive Phase Noise
vs Amplitude
NORMALIZED PHASE (DEG)
–130
LTC6957-1
0.48
FILTA = FILTB = L
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G17
0.46
FILTA = FILTB = L
3
3.1
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
3.5
3.6
69571234 G18
6957fb
For more information www.linear.com/LTC6957-1
11
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
V+ = 3.45V
40
V+ = 3.3V
2.05
2.00
V+ = 3.15V
40.5
35
SUPPLY CURRENT (mA)
30
TA = 125°C
25
20
TA = 25°C
15
TA = –55°C
10
1.95
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
DC DATA,
IN+ > (IN– + 50mV)
VOH, VOL AND VOS (V)
1.0
0
50
410
1.2
VOD (CALCULATED)
400
250
1.0
–55 –35 –15
1.0V
1.5V
3.0V
0V
SD
ENABLE: OUTPUTS WITH
OTHER CHANNEL ON
69571234 G25
20ns/DIV
MULTIPLE EXPOSURES, PERSISTENCE MODE
CLOCK I/O = 120MHz
SD DRIVE ~ 140kHz, ASYNCHRONOUS
380
5 25 45 65 85 105 125
TEMPERATURE (°C)
1
LOAD STRESS PER TIA/EIA-644-A FIGURE 4
0.6
1.2
1.8
VTEST LOAD VOLTAGE (V)
0
69571234 G23
3.95
2.4
69571234 G24
Differential Output vs Frequency
900
V+ = 3.3V
3.90
V+ = 3.15V
3.85
3.80
3.75
–55 –35 –15
–55°C
800
V+ = 3.45V
ANY ONE (1) OUTPUT
SHORTED TO GROUND
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G26
12
OUT–
1.1
4.00
2.0V
1.0V
1.2
Output Short-Circuit Current
vs Temperature
WAKE-UP:
OUTPUTS WITH
OTHER
CHANNEL OFF
125°C
25°C
–55°C
OUT+
1.3
390
69571234 G22
SHORT-CIRCUIT CURRENT (mA)
1.5V
1.4
VOS (CALCULATED)
Enable and Wakeup
2.0V
420
VOL (MEASURED)
150
100
200
LOAD RESISTOR (Ω)
USE OF RLOAD > 150Ω
NOT RECOMMENDED
fIN MAY BE COMPROMISED
1.5
1.3
1.1
V+ = 3.6V
V+ = 3.3V
V+ = 3V
Output Voltages vs Loading
430
DIFFERENTIAL OUTPUT (mVP-P)
OUTPUT VOLTAGE (V)
OUT –
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G21
VOD (mV)
1.2
0.8
VOH (MEASURED)
1.4
1.4
V+ = 3.15V
38.5
Output Voltages vs Temperature
1.5
OUT +
39.0
69571234 G20
Output Voltages vs Load Resistor
1.6
39.5
37.5
–55 –35 –15
0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6
SUPPLY VOLTAGE (V)
69571234 G19
1.8
V+ = 3.3V
38.0
5
1.90
–55 –35 –15
V+ = 3.45V
40.0
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2.15
2.10
Supply Current vs Temperature
41.0
45
SUPPLY CURRENT (mA)
2.20
LTC6957-2
700
25°C
600
500
125°C
400
300
200
10dBm INPUT
FILTA = FILTB = L
RLOAD = 100Ω
100
0
0
200
400
600
800
FREQUENCY (MHz)
1000
1200
69571234 G27
6957fb
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
–140
–145
153.6MHz
–150
300MHz
–155
–160
–135
PHASE NOISE (dBc/Hz)
–135
PHASE NOISE (dBc/Hz)
–130
SINGLE-ENDED SINE WAVE INPUT
AT 7dBm (500mVRMS)
FILTA = FILTB = L
–165
100
–10dBm, FILTA = L, FILTB = H
–145
0dBm, FILTA = H, FILTB = L
–150
1k
10k
100k
OFFSET FREQUENCY (Hz)
–155
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
3.45V
–150
3.3V
–155
3.15V
1k
10k
100k
OFFSET FREQUENCY (Hz)
1M
1k
10k
100k
OFFSET FREQUENCY (Hz)
AM to PM Conversion
5
–145
–150
0dBm, FILTA = H, FILTB = L
–155
3
2
1
–55°C
0
–1 25°C
–2
–3
125°C
–4
7dBm, FILTA = FILTB = L
1k
10k
100k
OFFSET FREQUENCY (Hz)
69571234 G31
fIN = 300MHz
V+ = 3.3V
4
–140
EACH CURVE NORMALIZED TO 0° AT 0dBm
–5
–10 –8 –6 –4 –2 0 2 4 6
INPUT AMPLITUDE (dBm)
1M
69571234 G32
tPD vs Temperature
0.96
0.950
FILTA = FILTB = H
V+ = 3.0V
10
tPD vs Supply Voltage
125°C
0.94
0.925
3.0
8
69571234 G33
tPD vs Temperature
4.0
1M
69571234 G30
SINGLE-ENDED SINE WAVE INPUT
–165
100
1M
125°C
–55°C
–165
100
–160
–160
1k
10k
100k
OFFSET FREQUENCY (Hz)
25°C
–155
–135
–140
–165
100
–150
Additive Phase Noise at 122.88MHz
–130
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT 7dBm (500mVRMS)
FILTA = FILTB = L
–145
–145
69571234 G29
Additive Phase Noise
vs Supply Voltage
–135
–140
10dBm, FILTA = FILTB = L
69571234 G28
–130
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT 7dBm (500mVRMS)
FILTA = FILTB = L
–160
–165
100
1M
Additive Phase Noise
vs Temperature
–135
–140
–160
100MHz
–130
SINGLE-ENDED 100MHz SINE WAVE INPUT
SEE APPLICATIONS INFORMATION
NORMALIZED PHASE (DEG)
–130
Additive Phase Noise
vs Amplitude
PHASE NOISE (dBc/Hz)
Additive Phase Noise
vs Input Frequency
LTC6957-2
FILTA = FILTB = L
100Ω LOAD
1.0
FILTA = L, FILTB = H
V+ = 3.6V
tPD (ns)
1.5
tPD (ns)
tPD (ns)
0.92
0.900
V+ = 3.3V
0.875
0.88
FILTA = H, FILTB = L
0.850
FILTA = FILTB = L
0.5
–55 –35 –15
100Ω LOAD
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G34
0.825
–55 –35 –15
25°C
0.90
FILTA = FILTB = L
100Ω LOAD
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G35
0.86
0.84
–55°C
3
3.1
3.4
3.2
3.3
SUPPLY VOLTAGE (V)
3.5
3.6
69571234 G36
6957fb
For more information www.linear.com/LTC6957-1
13
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
V+ = 3.45V
V+ SUPPLY CURRENT (mA)
V+ = 3.3V
2.05
2.00
V+ = 3.15V
20
15
25°C
10
125°C
5
1.95
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
0.6
0
2.4
1.2
1.8
V+ VOLTAGE (V)
3
69571234 G37
V+ = 3.15V
20.0
0.25
0
5
10
15
LOAD CURRENT (mA)
125°C
VDD – 0.75
VDD = 3.3V
0.50
OUTPUT LOW,
SINKING CURRENT
0.25
0
20
125°C
–55°C
0
21
V DD SUPPLY CURRENT (mA)
125°C
0
0.6
25°C –55°C
2.4
1.2
1.8
VDD VOLTAGE (V)
3
3.6
69571234 G43
14
2.7V
–155
3.0V
3.3V
–165
100
20
1k
10k
100k
OFFSET FREQUENCY (Hz)
V+ = VDD = 3.3V
20
69571234 G42
3.0
100
10
DYNAMIC, ONE (1)
OUTPUT ACTIVE AT 312.5MHz,
13pF LOAD, LEFT AXIS
19 OTHER OUTPUT DISABLED
1
18
0.1
17
–55 –35 –15
1M
Output Voltage Swing
vs Frequency
STATIC, NO DC LOAD,
RIGHT (LOGARITHMIC)
AXIS
VDD SUPPLY CURRENT (µA)
1
2.4V
–150
Supply Current vs Temperature
5
2
–145
69571234 G41
Supply Current vs Supply Voltage
3
SINGLE-ENDED SINE WAVE INPUT,
at 7dBm (500mVRMS)
–135 100MHz
V+ = 3.3V, VDD AS SHOWN
FILTA = FILTB = L
–140
–160
25°C
5
10
15
LOAD CURRENT (mA)
69571234 G40
4
25°C
OUTPUT HIGH,
SOURCING CURRENT
VDD – 0.5
OUTPUT LOW,
SINKING CURRENT
0
–55°C
PHASE NOISE (dBc/Hz)
0.50
Additive Phase Noise
vs Supply Voltage
–130
VDD – 0.25
VDD = 3.6V
VDD = 3.3V
VDD = 3V
VDD = 2.7V
VDD = 2.4V
VDD – 0.75
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G39
VDD
OUTPUT HIGH,
SOURCING CURRENT
VDD – 0.5
19.5
–55 –35 –15
3.6
Output Voltages vs Load Current
Output Voltages vs Load Current
VDD – 0.25
OUTPUT VOLTAGE (V)
V+ = 3.3V
69571234 G38
OUTPUT VOLTAGE (V)
VDD
VDD CURRENT (mA)
20.5
–55°C
1.90
–55 –35 –15
0
V+ = 3.45V
21.0
0.01
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G44
OUTPUT SWING (VP-P)
INPUT VOLTAGE (V)
2.15
2.10
Supply Current vs Temperature
21.5
25
V + SUPPLY CURRENT (mA)
2.20
LTC6957-3/LTC6957-4
2.5
–55°C
25°C
125°C
2.0
1.5
1
10dBm INPUT
FILTA = FILTB = L
IN DC1766A
RLOAD = 133Ω AC-COUPLED
CAUTION: AT VERY
HIGH FREQUENCIES,
THE CMOS OUTPUTS
MAY NOT TOGGLE
AT ALL DEPENDING
ON INPUT FREQUENCY, AMPLITUDE,
SUPPLY VOLTAGE,
OR TEMPERATURE
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
69571234 G45
6957fb
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TYPICAL PERFORMANCE CHARACTERISTICS
–140
300MHz
–145
153.6MHz
–150
–155
–135
PHASE NOISE (dBc/Hz)
–135
PHASE NOISE (dBc/Hz)
–130
SINGLE-ENDED SINE WAVE INPUT
AT 7dBm (500mVRMS)
FILTA = FILTB = L
100MHz
–10dBm, FILTA = L, FILTB = H
–145
0dBm, FILTA = H, FILTB = L
–150
–155
–165
100
–165
100
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT 7dBm (500mVRMS)
V+ = VDD
FILTA = FILTB = L
3.15V
3.45V
–155
–160
10dBm, FILTA = FILTB = L
1k
10k
100k
OFFSET FREQUENCY (Hz)
1k
10k
100k
OFFSET FREQUENCY (Hz)
1M
–150
0dBm, FILTA = H, FILTB = L
–155
–165
100
1k
10k
100k
OFFSET FREQUENCY (Hz)
3.0
1M
RISING EDGE
tPD (ns)
tPD (ns)
tPD (ns)
69571234 G52
–55°C
–2
–3
0.75
–55 –35 –15
8
10
tPD vs Supply Voltage
V+ = 3.45V
1.02
1.00
V+ = VDD
0.98
FALLING EDGE
0.96
0.80
FALLING EDGE
0
–1
1.04
0.90
5 25 45 65 85 105 125
TEMPERATURE (°C)
1
1.06
0.95
0.85
0.5
–55 –35 –15
2
69571234 G51
1.00
FILTA = H, FILTB = L
3
EACH CURVE NORMALIZED TO 0° AT 0dBm
fIN = 300MHz
V+= VDD = 3.3V
25°C
–4
125°C
–5
–10 –8 –6 –4 –2 0 2 4 6
INPUT AMPLITUDE (dBm)
tPD vs Temperature
1.05
1M
AM to PM Conversion
1.10
1.0
1k
10k
100k
OFFSET FREQUENCY (Hz)
69571234 G50
1.15
FILTA = L, FILTB = H
–55°C
69571234 G48
4
–145
tPD vs Temperature
FILTA = FILTB = L
125°C
5
–140
FILTA = FILTB = H
1.5
–155
SINGLE-ENDED SINE WAVE INPUT
69571234 G49
4.0
1M
7dBm, FILTA = FILTB = L
3.3V
25°C
–165
100
–160
–165
100
–150
–135
–145
–150
–145
Additive Phase Noise at 122.88MHz
–130
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–140
–140
69571234 G47
Additive Phase Noise
vs Supply Voltage
–135
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT 7dBm (500mVRMS)
FILTA = FILTB = L
–160
69571234 G46
–130
–135
–140
–160
1M
–130
SINGLE-ENDED 100MHz SINE WAVE INPUT
SEE APPLICATIONS INFORMATION
–160
1k
10k
100k
OFFSET FREQUENCY (Hz)
Additive Phase Noise
vs Temperature
NORMALIZED PHASE (DEG)
–130
Additive Phase Noise
vs Amplitude
PHASE NOISE (dBc/Hz)
Additive Phase Noise
vs Input Frequency
LTC6957-3/LTC6957-4
FILTA = FILTB = L
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G53
RISING EDGE
0.94
2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6
VDD SUPPLY VOLTAGE (V)
69571234 G54
6957fb
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15
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
PIN FUNCTIONS
FILTA, FILTB (Pin 1, Pin 6): Input Bandwidth Limiting
Control. These CMOS logic inputs control the bandwidth
of the early amplifier stages. For slow slewing signals
substantially lower phase noise is achieved by using this
feature. See the Applications Information section for more
details.
V+ (Pin 2): Supply Voltage (3.15V to 3.45V). This supply must be kept free from noise and ripple. It should be
bypassed directly to GND (Pin 5) with a 0.1µF capacitor.
IN+,
IN–
(Pin 3, Pin 4): Input Signal Pins. These inputs
are differential, but can also interface with single-ended
signals. The input can be a sine wave signal or a CML,
LVPECL, TTL or CMOS logic signal. See the Applications
Information section for more details.
GND (Pin 5): Ground. Connect to a low inductance ground
plane for best performance. The connection to the bypass
capacitor for V+ (Pin 2) should be through a direct, low
inductance path.
SD1, SD2 (Pin 12, Pin 7): Output Enable Control. These
CMOS logic inputs control the enabling and disabling of
their respective OUT1 and OUT2 outputs. When both outputs are disabled, the LTC6957 is placed in a low power
shutdown state.
LTC6957-1 Only
OUT1–, OUT1+ (Pin 10, Pin 11): LVPECL Outputs. Differential
logic outputs typically terminated by 50Ω connected to a
supply 2V below the V+ supply. Refer to the Applications
Information section for more details.
OUT2–, OUT2+ (Pin 9, Pin 8): LVPECL Outputs. Differential
logic outputs typically terminated by 50Ω connected to a
supply 2V below the V+ supply. Refer to the Applications
Information section for more details.
16
LTC6957-2 Only
OUT1–, OUT1+ (Pin 10, Pin 11): LVDS Outputs, Mostly
TIA/EIA-644-A Compliant. Refer to the Applications
Information section for more details.
OUT2–, OUT2+ (Pin 9, Pin 8): LVDS Outputs, Mostly
TIA/EIA-644-A Compliant. Refer to the Applications
Information section for more details.
LTC6957-3/LTC6957-4 Only
OUT1, OUT2 (Pin 10, Pin 9): CMOS Outputs. Refer to the
Applications Information section for more details.
VDD (Pin 11): Output Supply Voltage (2.4V to 3.45V). For
best performance connect this to the same supply as V+
(Pin 2). If the output needs to be a lower logic rail, this
supply can be separately connected, but this voltage must
be less than or equal to that on Pin 2 for proper operation.
This supply must also be kept free from noise and ripple.
It should be bypassed directly to the GNDOUT pin (Pin 8)
with a 0.1µF capacitor.
GNDOUT (Pin 8): Output Logic Ground. Tie to a low
inductance ground plane for best performance. The connection to the bypass capacitor for VDD (Pin 11) should
be through a direct, low inductance path.
LTC6957-xDD Only
Exposed Pad (Pin 13): Always tie the underlying DFN
exposed pad to GND (Pin 5). To achieve the rated θJA of
the DD package, there should be good thermal contact
to the PCB.
6957fb
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
BLOCK DIAGRAMS
1
6
3
4
FILTA
2
12
V+
SD1
OUT1+
FILTB
OUT1–
IN+
11
10
IN–
OUT2–
OUT2+
5
GND
9
8
SD2
7
LTC6957-1 and LTC6957-2
1
6
3
4
FILTA
2
V+
12
SD1
FILTB
V DD
OUT1
11
10
IN+
IN–
OUT2
9
GNDOUT 8
5
GND
7
SD2
6957 BD
LTC6957-3 and LTC6957-4
6957fb
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17
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TIMING DIAGRAM
SD1
SD2
INPUT
*
OUT1+/OUT1
OUT1–
*
*
OUT2+/OUT2
OUT2–
*
tDISABLE
tSLEEP
tWAKEUP
tENABLE
* SEE APPLICATIONS INFORMATION FOR
LOGIC BEHAVIOR DURING SHUTDOWN
SPECIFIC TO LVPECL/LVDS/CMOS OUTPUTS.
LTC6957-1 SHOWN HERE FOR REFERENCE.
EACH OUTPUT TYPE BEHAVES DIFFERENTLY
DURING SHUTDOWN.
DETAIL
INPUT
tPD
50%
OUT1+/OUT1
OUT1–
50%
tMATCH
90%
OUT2+/OUT2
OUT2–
10%
tRISE
90%
10%
tFALL
18
tSKEW
6957 TD1
6957fb
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
General Considerations
The LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 are
low noise, dual output clock buffers that are designed
for demanding, low phase noise applications. Properly
applied, they can preserve phase noise performance in
situations where alternative solutions would degrade the
phase noise significantly. They are also useful as logic
converters.
However, no buffer device is capable of removing or
reducing phase noise present on an input signal. As with
most low phase noise circuits, improper application of
the LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 can
result in an increase in the phase noise through a variety
of mechanisms. The information below will, hopefully,
allow a designer to avoid such an outcome.
The LTC6957 is designed to be used with high performance clock signals destined for driving the encode
inputs of ADCs or mixer inputs. Such clocks should not
be treated as digital signals. The beauty of digital logic is
that there is noise margin both in the voltage and the timing, before any deleterious effects are noticed. In contrast,
high performance clock signals have no margin for error
in the timing before the system performance is degraded.
Users are encouraged to keep this distinction in mind
while designing the entire clocking signal chain before,
during, and after the LTC6957.
Input Interfacing
The input stage is the same for all versions of the LTC6957
and is designed for low noise and ease of interfacing to
sine-wave and small amplitude signals. Other logic types
can interface directly, or with little effort since they present a smaller challenge for noise preservation.
Figure 1 shows a simplified schematic of the LTC6957
input stage. The diodes are all for protection, both during
ESD events and to protect the low noise NPN devices from
being damaged by input overdrive.
The resistors are to bias the input stage at an optimal
DC level, but they are too large to leave floating without
increasing the noise. Therefore, for low noise use, always
connect both inputs to a low AC impedance. A capacitor to
ground/return is imperative on the unused input in singleended applications.
2
1
6
3
4
V+
FILTA
FILTERS
FILTB
+
1.8k
1.2k
IN
IN–
1.2k
2mA
3.2k
5
GND
6957 F01
Figure 1
6957fb
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19
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
Figure 2a shows how to interface single-ended LVPECL
logic to the LTC6957, while Figure 2b shows how to drive
the LTC6957 with differential LVPECL signals. The capacitors shown are 10nF and can be inexpensive ceramics,
preferably in small SMT cases. For use above 100MHz,
lower value capacitors may be desired to avoid series
resonance, which could increase the noise in Figure 2a
even though the capacitor is just on the DC input. This
comment applies to all capacitors hooked to the inputs
throughout this data sheet.
In Figure 2a, the RTERM implementation is up to the user
and is to terminate the transmission line. If it is connected
to a VTT that is passively generated and heavily bypassed
to ground, the 10nF to ground shown on the inverting
LTC6957 input is the appropriate connection to use.
However, if the termination goes to an actively generated
VTT voltage, lower noise may be achieved by connecting
the capacitor on the inverting input to that VTT rather than
ground.
In Figure 2b, both inputs to the LTC6957 are driven,
increasing the differential input signal size and minimizing noise from any common mode source such as VTT,
both of which improve the achievable phase noise.
A variety of termination techniques can be used, and
as long as the two sides use the same termination, the
configuration used won't matter much. In Figure 2b, the
RTERMs are shown in a "Y" configuration that creates a passive VTT at the common point. Most 3.3V LVPECL devices
have differential outputs and can be terminated with three
50Ω resistors as shown.
Figure 3 shows a 50Ω RF signal source interface to the
LTC6957. For a pure tone (sine wave) input, Figure 3 can
handle up to 10dBm maximum. A broadband 50Ω match
as shown should suffice for most applications, though
for small amplitude input signals a narrow band reactive
matching network may offer incremental improvements
in performance.
3.3V
10nF
50Ω
+
LTC6957
50Ω
–
+
SOURCE
LTC6957
RTERM
10nF
6957 F03
–
10nF
6957 F02a
Figure 3. Single-Ended 50Ω Input Source
Figure 2a. Single-Ended LVPECL Input
3.3V
+
LTC6957
–
6957 F02b
3×
RTERM
Figure 2b. Differential LVPECL Input
Figure 2
20
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LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
Figure 4b shows a single-ended CML signal driving the
LTC6957. This is not commonly used because of noise
and immunity weaknesses compared to the differential CML case. Because the signal is created by a current pulled through the termination resistor, the signal
is inherently referenced to the supply voltage to which
RTERM is tied. For that reason, the other LTC6957 should
be AC-referenced to that supply voltage as shown.
Figure 4 shows the interface between current mode logic
(CML) signals and the LTC6957 inputs. The specifics of
terminating will be dependent on the particular CML driver
used; Figure 4 shows terminations only at the load end
of the line, but the same LTC6957 interface is appropriate for applications with the source end of the line also
terminated. In Figure 4a, a differential signal interface to
the LTC6957 is shown, which must be AC-coupled due to
the DC input levels required at the LTC6957.
RTERM
The polarity change shown here is for graphic clarity only,
and can be reversed by swapping the LTC6957 input
terminals.
RTERM
10nF
+
LTC6957
10nF
–
6957 F04a
Figure 4a. Differential CML Input
10nF
+
RTERM
LTC6957
10nF
–
6957 F04b
Figure 4b. Single-Ended CML Input
Figure 4
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21
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
Figure 5 shows the LTC6957 being driven by an LVDS
(EIA-644-A) signal pair. This is simply a matter of differentially terminating the pair and AC-coupling as shown
into the LTC6957 whose DC common mode voltage is
incompatible with the LVDS standard.
10nF
+
110Ω
LTC6957
10nF
–
6957 F05
Figure 5. LVDS Input
The choice of 110Ω versus 100Ω termination is arbitrary
(the EIA-644-A standard allows 90Ω to 132Ω) and should
be made to match the differential impedance of the trace
pair. The termination and AC-coupling elements should be
located as close as possible to the LTC6957.
If DC-coupling is desired, for example to control the
LTC6957 output phasing during times the LVDS input
clocks will be halted, a pair of 3k resistors can parallel
the two capacitors in Figure 5. An EIA/TIA-644-A compliant driver can drive this load, which is less load stress
than specification 4.1.1. The differential voltage into the
LTC6957 when clocked (>100kHz) will be full LVDS levels.
When the clocks stop, the DC differential voltage created
by the resistors and the 1.2k internal resistors (Figure
1) will be 100mV, still sufficient to assure the desired
LTC6957 output polarity. Choosing the smallest capacitors needed for phase noise performance will minimize
the settling transients when the clocks restart.
Interfacing with CMOS Logic
The logic families discussed and illustrated to this point
are generally a better choice for routing and distributing
low phase-noise reference/clock signals than is CMOS
logic. All of the logic types shown so far are well suited
for use with low impedance terminations. Most of the time
there is a differential signal when using LVPECL or CML,
and LVDS always has a differential signal. Differential
signals provide lots of margin for error when it comes
to picking up noise and interference that can corrupt a
reference clock.
22
CMOS on the other hand cannot drive 50Ω loads, is usually routed single-ended, and by its nature is coupled to
the potentially noisy supply voltage half the time.
The LTC6957-3/LTC6957-4 provide CMOS outputs, so it
may seem surprising to read herein that CMOS is a poor
choice for low phase noise applications. However, these
devices should prove useful for designers that recognize
the challenges and limitations of using CMOS signals for
low phase noise applications. See the CMOS Outputs of
the LTC6957-3/LTC6957-4 section for further information.
The best method for driving the LTC6957 with CMOS signals would be to provide differential drive, but if that is not
available, there are few ways to create a differential CMOS
signal without running the risk of corrupting the skew or
creating other problems. Therefore, single-ended CMOS
signals are the norm and care must be taken when using
this to drive the LTC6957.
The primary concern is that all routing should be terminated to minimize reflections. With CMOS logic there is
usually plenty of signal (more than the LTC6957 can handle without attenuation) and the amplitude of the LTC6957
input signal will generally be of secondary importance
compared to avoiding the deleterious effects of signal
reflections. The primary concern about terminations is
that the input waveform presented to the LTC6957 should
have full speed slewing at the all important transitions.
If a rising edge is slowed by the destructive addition of
the ringing/settling of a prior edge reflection, or even the
start of the current edge, the phase noise performance will
suffer. This is true for all logic types, but is particularly
problematic when using CMOS because of the fast slew
rates and because it does not naturally lend itself to clean
terminations.
Point-to-point routing is best, and care should be taken
to avoid daisy-chain routing, because the terminated
end may be the only point along the line that sees clean
transitions. Earlier loads may even see a dwell in the
transition region which will greatly degrade phase noise
performance.
6957fb
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LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION
Figure 6 shows a suggested CMOS to LTC6957 interface.
The transmission line shown is the PCB trace and the
component values are for a characteristic impedance of
50Ω, though they could be scaled up or down for other
values of Z0. The R1/R2 divider at the CMOS output cuts
the Thevenin voltage in half when the ZOUT of the driver is
included. More importantly, it drives the transmission line
with a Thevenin driving resistance of 50Ω, matching the
Z0 of the line. On the other end of the line, a 50Ω load is
presented, minimizing reflections. This results in a second
2:1 attenuation in voltage, so the LTC6957 input will be
approximately 800mVP-P with 3V CMOS; 1.25VP-P with 5V
and 600mVP-P with 2.5V. All of these levels are less than
the maximum input swing of 2VP-P yet with clean edges
and fast slew rates should be able to realize the full phase
noise performance of the LTC6957.
CMOS
R1
75Ω
ROUT ≈ 25Ω
R2
100Ω
50Ω
Input Resistors
The LTC6957 input resistors, seen in Figure 1, are present
at all times, including during shutdown. Although they
constitute a large portion of the shutdown current, this
behavior prevents the shutdown and wake-up cycling of
the LTC6957 from “kicking back” into prior stages, which
could create large transients that could take a while to
settle. Particularly in the common case of AC-coupling
where the coupling cap charge is preserved.
Input Filtering
The LTC6957 includes input filtering with three narrowband settings in addition to the full bandwidth limitation
of the circuit design.
Table 1
+
Z0 = 50Ω
phase noise spectrum related to the other signals processed in the driver.
LTC6957
–
6957 F06
Figure 6. CMOS Input
The various capacitors are for AC-coupling and should
have Z
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