LTC690/LTC691
LTC694/LTC695
Microprocessor
Supervisory Circuits
Features
Description
Guaranteed Reset Assertion at VCC = 1V
n 1.5mA Maximum Supply Current
n Fast (35ns Max) Onboard Gating of RAM Chip
Enable Signals
n SO-8 and S16 Packaging
n 4.65V Precision Voltage Monitor
n Power OK/Reset Time Delay: 50ms, 200ms
or Adjustable
n Minimum External Component Count
n 1µA Maximum Standby Current
n Voltage Monitor for Power-Fail
or Low Battery Warning
n Thermal Limiting
n Performance Specified Over Temperature
n Superior Upgrade for MAX690 Family
The LTC®690 family, LTC690/LTC691/LTC694/LTC695,
provides complete power supply monitoring and battery
control functions for microprocessor reset, battery backup, CMOS RAM write protection, power failure warning
and watchdog timing. A precise internal voltage reference
and comparator circuit monitor the power supply line.
When an out-of-tolerance condition occurs, the reset
outputs are forced to active states and the chip enable
output unconditionally write-protects external memory.
In addition, the RESET output is guaranteed to remain
logic low even with VCC as low as 1V.
n
The LTC690 family powers the active CMOS RAMs with a
charge pumped NMOS power switch to achieve low drop
out and low supply current. When primary power is lost,
auxiliary power, connected to the battery input pin, powers
the RAMs in standby through an efficient PMOS switch.
Applications
n
n
n
n
For an early warning of impending power failure, the LTC690
family provides an internal comparator with a user-defined
threshold. An internal watchdog timer is also available, which
forces the reset pins to active states when the watchdog
input is not toggled prior to a preset timeout period.
Critical µP Power Monitoring
Intelligent Instruments
Battery-Powered Computers and Controllers
Automotive Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
+
VIN
10µF
VOUT
ADJ
5
5V
+
100µF
0.1µF
3V
VCC
VOUT
LTC690/LTC691
LTC694/LTC695
VBATT
POWER TO
µP
0.1µF CMOS RAM POWER
µP
SYSTEM
µP RESET
RESET
51k
µP NMI
PFO
PFI
I/O LINE
GND WDI
10k
0.1µF
100Ω
MICROPROCESSOR RESET, BATTERY BACK-UP, POWER FAILURE
WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR MICROPROCESSOR SYSTEMS
690 TA01
RESET OUTPUT VOLTAGE (V)
LT®1086-5
VIN ≥ 7.5V
RESET Output Voltage
vs Supply Voltage
TA = 25°C
EXTERNAL PULL-UP = 10µA
VBATT = 0V
4
3
2
1
0
0
1
3
4
2
SUPPLY VOLTAGE (V)
5
690 TA02
690ff
For more information www.linear.com/690
1
LTC690/LTC691
LTC694/LTC695
Absolute Maximum Ratings
(Notes 1 and 2)
Terminal Voltage
VCC...................................................... – 0.3V to 6.0V
VBATT................................................... –0.3V to 6.0V
All Other Inputs.....................– 0.3V to (VOUT + 0.3V)
Input Current
VCC.................................................................200mA
VBATT................................................................50mA
GND..................................................................20mA
VOUT Output Current....................Short-Circuit Protected
Power Dissipation................................................500mW
Operating Temperature Range
LTC690/91/94/95C ................................. 0°C to 70°C
LTC690/91/94/95I ..............................– 40°C to 85°C
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec.).................. 300°C
Pin Configuration
TOP VIEW
TOP VIEW
VBATT
VOUT
1
2
16 RESET
VBATT 1
16 RESET
15 RESET
VOUT 2
15 RESET
VCC 3
14 WDO
GND 4
13 CE IN
VCC
3
14 WDO
GND
4
13 CE IN
BATT ON
5
12
LOWLINE
6
11 WDI
OSC IN
7
10 PFO
OSC SEL
8
9
12 CE OUT
BATT ON 5
CE OUT
LOWLINE 6
11 WDI
OSC IN 7
10 PFO
9 PFI
OSC SEL 8
PFI
SW PACKAGE
16-LEAD WIDE PLASTIC SO
N PACKAGE
16-LEAD PDIP
TJMAX = 110°C, θJA = 130°C/W
TJMAX = 110°C, θJA = 130°C/W CONDITIONS: PCB MOUNT ON
FR4 MATERIAL, STILL AIR AT 25°C, COPPER TRACE
TOP VIEW
TOP VIEW
VOUT
1
8
VBATT
VOUT
1
8
VBATT
VCC
2
7
RESET
VCC
2
7
RESET
GND
3
6
WDI
GND
3
6
WDI
PFI 4
5
PFO
PFI
4
5
PFO
S8 PACKAGE
8-LEAD PLASTIC SO
J8 PACKAGE
N8 PACKAGE
8-LEAD CERDIP 8-LEAD PDIP
TJMAX = 110°C, θJA = 130°C/W (N8)
TJMAX = 110°C, θJA = 180°C/W CONDITIONS; PCB MOUNT ON
FR4 MATERIAL, STILL AIR AT 25°C, COPPER TRACE
690ff
2
For more information www.linear.com/690
LTC690/LTC691
LTC694/LTC695
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC691CN#PBF
LTC691CN#PBF
LTC691CN
16-Lead PDIP
0°C to 70°C
LTC691IN#PBF
LTC691IN#PBF
LTC691IN
16-Lead PDIP
–40°C to 85°C
LTC695CN#PBF
LTC695CN#PBF
LTC695CN
16-Lead PDIP
0°C to 70°C
LTC695IN#PBF
LTC695IN#PBF
LTC695IN
16-Lead PDIP
–40°C to 85°C
LTC691CSW#PBF
LTC691CSW#PBF
LTC691CSW
16-Lead Wide Plastic SO
0°C to 70°C
LTC691ISW#PBF
LTC691ISW#PBF
LTC691ISW
16-Lead Wide Plastic SO
–40°C to 85°C
LTC695CSW#PBF
LTC695CSW#PBF
LTC695CSW
16-Lead Wide Plastic SO
0°C to 70°C
LTC695ISW#PBF
LTC695ISW#PBF
LTC695ISW
16-Lead Wide Plastic SO
–40°C to 85°C
LTC690CN8#PBF
LTC690CN8#PBF
LTC690CN8
8-Lead PDIP
0°C to 70°C
LTC690IN8#PBF
LTC690IN8#PBF
LTC690IN8
8-Lead PDIP
–40°C to 85°C
LTC694CN8#PBF
LTC694CN8#PBF
LTC694CN8
8-Lead PDIP
0°C to 70°C
LTC694IN8#PBF
LTC694IN8#PBF
LTC694IN8
8-Lead PDIP
–40°C to 85°C
LTC690CS8#PBF
LTC690CS8#PBF
690
8-Lead Plastic SO
0°C to 70°C
LTC690IS8#PBF
LTC690IS8#PBF
690
8-Lead Plastic SO
–40°C to 85°C
LTC694CS8#PBF
LTC694CS8#PBF
694
8-Lead Plastic SO
0°C to 70°C
LTC694IS8#PBF
LTC694IS8#PBF
694
8-Lead Plastic SO
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Product Selection Guide
PINS
RESET
WATCHDOG
TIMER
BATTERY
BACK-UP
POWER-FAIL
WARNING
LTC690
8
X
X
X
X
LTC691
16
X
X
X
X
LTC694
8
X
X
X
X
LTC695
16
X
X
X
X
LTC699
8
X
X
LTC1232
8
X
X
LTC1235
16
X
X
RAM WRITE
PROTECT
PUSHBUTTON
RESET
CONDITIONAL
BATTERY
BACK-UP
X
X
X
X
X
X
X
X
690ff
For more information www.linear.com/690
3
LTC690/LTC691
LTC694/LTC695
Electrical
Characteristics
The l denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
Operating Voltage Range
VCC
VBATT
4.75
2.00
VOUT Output Voltage
IOUT = 1mA
TYP
MAX
UNITS
5.50
4.25
V
V
Battery Back-Up Switching
l
VCC – 0.05 VCC – 0.005
VCC – 0.10 VCC – 0.005
V
V
l
IOUT = 50mA
VCC – 0.50 VCC – 0.250
V
VOUT in Battery Back-Up Mode
IOUT = 250µA, VCC < VBATT
V
Supply Current (Exclude IOUT)
IOUT = 50mA
VBATT – 0.1 VBATT – 0.2
0.6
0.6
Supply Current in Battery Back-Up Mode
VCC = 0V, VBATT = 2.8V
0.04
0.04
l
Battery Standby Current (+ = Discharge, – = Charge)
5.5 > VCC > VBATT + 0.2V
l
Battery Switchover Threshold, VCC – VBATT
–0.1
–0.1
Power Up
Power Down
1.5
2.5
mA
mA
1
5
µA
µA
+0.02
+0.10
µA
µA
70
50
Battery Switchover Hysteresis
mV
mV
20
BATT ON Output Voltage (Note 4)
ISINK = 3.2mA
BATT ON Output Short-Circuit Current (Note 4)
BATT ON = VOUT Sink Current
mV
0.4
35
BATT ON = 0V Source Current
V
m
0.5
1
25
4.5
4.65
4.75
µA
Reset and Watchdog Timer
Reset Voltage Threshold
l
Reset Threshold Hysteresis
Reset Active Time (LTC690/91) (Note 5)
Reset Active Time (LTC694/95) (Note 5)
Watchdog Timeout Period, Internal Oscillator
40
OSC SEL HIGH, VCC = 5V
l
40
35
50
50
60
70
ms
ms
l
160
140
200
200
240
280
ms
ms
l
1.2
1
1.6
1.6
2.00
2.25
sec
sec
l
80
70
100
100
120
140
ms
ms
4097
1025
Clock
Cycles
OSC SEL HIGH, VCC = 5V
Long Period, VCC = 5V
Short Period, VCC = 5V
Watchdog Timeout Period, External Clock (Note 6)
V
mV
Long Period
Short Period
4032
960
Reset Active Time PSRR
Watchdog Timeout Period PSRR, Internal OSC
Minimum WDI Input Pulse Width
VIL = 0.4V, VIH = 3.5V
RESET Output Voltage at VCC = 1V
ISINK = 10µA, VCC = 1V
RESET and LOWLINE Output Voltage (Note 4)
ISINK = 1.6mA, VCC = 4.25V
ISOURCE = 1µA, VCC = 5V
3.5
RESET and WDO Output Voltage (Note 4)
ISINK = 1.6mA, VCC = 5V
ISOURCE = 1µA, VCC = 4.25V
3.5
l
1
ms/V
1
ms/V
200
ns
4
200
mV
0.4
V
V
0.4
V
V
690ff
4
For more information www.linear.com/690
LTC690/LTC691
LTC694/LTC695
Electrical
Characteristics
The l denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
CONDITIONS
RESET, RESET, WDO, LOWLINE
Output Short-Circuit Current (Note 4)
Output Sink Current
MIN
Output Source Current
1
TYP
MAX
3
25
25
WDI Input Threshold
Logic Low
Logic high
WDI Input Current
WDI = VOUT
WDI = 0V
l
l
–50
VCC = 5V
l
1.25
UNITS
µA
mA
0.8
V
4
–8
50
µA
1.3
1.35
3.5
Power-Fail Detector
PFI Input Threshold
PFI Input Threshold PSRR
0.3
PFI Input Current
±0.01
PFO Output Voltage (Note 4)
ISINK = 3.2mA
ISOURCE = 1µA
PFO Short-Circuit Source Current (Note 4)
PFI = HIGH, PFO = 0V
3.5
1
3
±25
nA
0.4
V
25
25
PFI = LOW, PFO = VOUT
V
mV/V
µA
mA
PFI Comparator Response Time (Falling)
∆VIN = –20mV, VOD = 15mV
2
µs
PFI Comparator Response Time (Rising) (Note 4)
∆VIN = 20mV, VOD = 15mV
with 10kΩ Pull-Up
40
8
µs
Chip Enable Gating
CE IN Threshold
VIL
VIH
CE IN Pull-Up Current (Note 7)
3
CE OUT Output Voltage
ISINK = 3.2mA
ISOURCE = 3.0mA
ISOURCE = 1µA, VCC = 0V
CE Propagation Delay
VCC = 5V, CL = 20pF
VOUT – 1.50
VOUT – 0.05
20
20
l
CE OUT Output Short-Circuit Current
0.8
2
Output Source Current
Output Sink Current
V
µA
0.4
V
35
45
ns
30
35
mA
OSC IN Input Current (Note 7)
±2
µA
OSC SEL Input Pull-Up Current (Note 7)
5
µA
Oscillator
OSC IN Frequency Range
OSC SEL = 0V
OSC IN Frequency with External Capacitor
OSC SEL = 0V, COSC = 47pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: For military temperature range parts or for the LTC692 and
LTC693, consult the factory.
Note 4: The output pins of BATT ON, LOWLINE, PFO, WDO, RESET and
RESET have weak internal pull-ups of typically 3µA. However, external
pull-up resistors may be used when higher speed is required.
l
0
250
4
kHz
kHz
Note 5: The LTC690 and LTC691 have minimum reset active time of 35ms
(50ms typically) while the LTC694 and LTC695 have longer minimum
reset active time of 140ms (200ms typically). The reset active time of
the LTC691 and LTC695 can be adjusted (see Table 2 in Applications
Information section).
Note 6: The external clock feeding into the circuit passes through the
oscillator before clocking the watchdog timer (See Block Diagram).
Variation in the timeout period is caused by phase errors which occur
when the oscillator divides the external clock by 64. The resulting variation
in the timeout period is 64 clocks plus one clock of jitter.
Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pull-ups which pull to the supply when the input pins are floating.
690ff
For more information www.linear.com/690
5
LTC690/LTC691
LTC694/LTC695
Block Diagram
M2
VBATT
VOUT
M1
VCC
CHARGE
PUMP
–
+
BATT ON
C2
LOWLINE
+
C1
–
CE OUT
1.3V
CE IN
GND
–
+
PFI
OSC IN
OSC SEL
WDI
OSC
TRANSITION
DETECTOR
C3
PFO
RESET PULSE
GENERATOR
WATCHDOG
TIMER
RESET
RESET
WDO
690 BD
Pin Functions
VCC: 5V Supply Input. The VCC pin should be bypassed
with a 0.1µF capacitor.
VOUT: Voltage Output for Backed Up Memory. Bypass with
a capacitor of 0.1µF or greater. During normal operation,
VOUT obtains power from VCC through an NMOS power
switch, M1, which can deliver up to 50mA and has a typical
on resistance of 5Ω. When VCC is lower than VBATT, VOUT
is internally switched to VBATT. If VOUT and VBATT are not
used, connect VOUT to VCC.
VBATT: Back-Up Battery Input. When VCC falls below VBATT,
auxiliary power, connected to VBATT, is delivered to VOUT
through PMOS switch, M2. If back-up battery or auxiliary
power is not used, VBATT should be connected to GND.
GND: Ground pin.
BATT ON: Battery On Logic Output from Comparator C2.
BATT ON goes low when VOUT is internally connected to
VCC. The output typically sinks 35mA and can provide
base drive for an external PNP transistor to increase the
output current above the 50mA rating of VOUT. BATT ON
goes high when VOUT is internally switched to VBATT.
PFI: Power Failure Input. PFI is the noninverting input
to the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes
low when PFI is below 1.3V. Connect PFI to GND or VOUT
when C3 is not used.
690ff
6
For more information www.linear.com/690
LTC690/LTC691
LTC694/LTC695
Pin Functions
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When VCC is lower than VBATT, C3 is shut down and
PFO is forced low.
RESET: Logic Output for µP Reset Control. Whenever
VCC falls below either the reset voltage threshold (4.65V,
typically) or VBATT, RESET goes active low. After VCC returns
to 5V, reset pulse generator forces RESET to remain active
low for a minimum of 35ms for the LTC690 /LTC691 (140ms
for the LTC694/LTC695). When the watchdog timer is
enabled but not serviced prior to a preset timeout period,
reset pulse generator also forces RESET to active low for
a minimum of 35ms for the LTC690/LTC691 (140ms for
the LTC694/5) for every preset timeout period (see Figure
11). The reset active time is adjustable on the LTC691/
LTC695. An external pushbutton reset can be used in
connection with the RESET output. See Pushbutton Reset
in Applications Information section.
RESET: RESET is an active high logic output. It is the
inverse of RESET.
LOW�LINE: Logic Output from Comparator C1. LOWLINE
indicates a low line condition at the VCC input. When VCC
falls below the reset voltage threshold (4.65V typically),
LOWLINE goes low. As soon as VCC rises above the reset
voltage threshold, LOWLINE returns high (see Figure 1).
LOWLINE goes low when VCC drops below VBATT (see
Table 1).
WDI: Watchdog Input, WDI, is a three level input. Driving
WDI either high or low for longer than the watchdog timeout
period, forces both RESET and WDO low. Floating WDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).
WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
timeout period, WDO goes low. WDO is set high whenever
there is a transition on the WDI pin, or LOWLINE goes
low. The watchdog timer can be disabled by floating WDI
(see Figure 11).
CE IN: Logic input to the ChipEnable gating circuit. CE IN
can be derived from microprocessor’s address line and/
or decoder output. See Applications Information section
and Figure 5 for additional information.
CE OUT: Logic Output on the ChipEnable Gating Circuit.
When VCC is above the reset voltage threshold, CE OUT is
a buffered replica of CE IN. When VCC is below the reset
voltage threshold CE OUT is forced high (see Figure 5).
OSC SEL: Oscillator Selection Input. When OSC SEL is
high or floating, the internal oscillator sets the reset active
time and watchdog timeout period. Forcing OSC SEL low,
allows OSC IN be driven from an external clock signal or
external capacitor be connected between OSC IN and GND.
OSC IN: Oscillator Input. OSC IN can be driven by an external
clock signal or external capacitor can be connected between
OSC IN and GND when OSC SEL is forced low. In this
configuration the nominal reset active time and watchdog
timeout period are determined by the number of clocks or
set by the formula (see Applications Information section).
When OSC SEL is high or floating, the internal oscillator is
enabled and the reset active time is fixed at 50ms typical
for the LTC691 and 200ms typical for the LTC695. OSC
IN selects between the 1.6 seconds and 100ms typical
watchdog timeout periods. In both cases, the timeout
period immediately after a reset is 1.6 seconds typical.
690ff
For more information www.linear.com/690
7
LTC690/LTC691
LTC694/LTC695
Typical Performance Characteristics
4.90
SLOPE = 5Ω
4.85
4.80
2.78
2.76
2.74
10
0
30
40
20
LOAD CURRENT (mA)
2.72
50
1.302
1.300
1.298
100
0
300
400
200
LOAD CURRENT (µA)
500
RESET ACTIVE TIME
50
216
208
200
192
48
50
25
75
0
TEMPERATURE (°C)
100
125
184
–50 –25
50
25
75
0
TEMPERATURE (°C)
4
2
1.3V
+
PFO
–
30pF
1
0
1.305V
0
1
2
5
3 4
TIME (µs)
6
5
4.63
4.62
4.61
4.60
–50 –25
4
3
2
VPFI
1
1.3V
7
8
690 G07
+
PFO
–
30pF
0
100
0
20 40
125
690 G06
6
5
VCC = 5V
TA = 25˚C
4
3
2
5V
1
0
1.315V
VPFI = 20mV STEP
1.295V
6
50
25
75
0
TEMPERATURE (°C)
Power-Fail Comparator Response
Time with Pull-Up Resistor
VCC = 5V
TA = 25°C
1.315V
VPFI = 20mV STEP
1.285V
PFO OUTPUT VOLTAGE (V)
VCC = 5V
TA = 25°C
5
VPFI
125
4.64
Power-Fail Comparator
Response Time
6
3
100
4.65
690 G05
690 G04
Power-Fail Comparator
Response Time
125
4.66
VCC = 5V
224
52
100
Reset Voltage Threshold
vs Temperature
RESET VOLTAGE THRESHOLD (V)
232
54
50
25
75
0
TEMPERATURE (°C)
690 G03
Reset Active Time
vs Temperature LTC694-5
VCC = 5V
46
–50 –25
1.294
–50 –25
690 G02
56
RESET ACTIVE TIME
1.304
1.296
Reset Active Time
vs Temperature LTC690-1
PFO OUTPUT VOLTAGE (V)
VCC = 5V
1.306
SLOPE = 125Ω
690 G01
58
1.308
VCC = 0V
VBATT = 2.8V
TA = 25°C
PFO OUTPUT VOLTAGE (V)
4.75
Power Failure Input Threshold
vs Temperature
VOUT vs IOUT
PFI INPUT THRESHOLD (V)
4.95
OUTPUT VOLTAGE (V)
2.80
VCC = 5V
VBATT = 2.8V
TA = 25°C
OUTPUT VOLTAGE (V)
5.00
VOUT vs IOUT
690 G08
+
1.3V
–
10k
PFO
30pF
VPFI = 20mV STEP
1.295V
60 80 100 120 140 160 180
TIME (µs)
VPFI
0
2
4
8 10 12 14 16 18
TIME (µs)
6
690 G09
690ff
8
For more information www.linear.com/690
LTC690/LTC691
LTC694/LTC695
Applications Information
Microprocessor Reset
The LTC690 family uses a bandgap voltage reference
and a precision voltage comparator C1 to monitor the
5V supply input on VCC (see Block Diagram). When VCC
falls below the reset voltage threshold, the RESET output
is forced to active low state. The reset voltage threshold
accounts for a 5% variation on VCC, so the RESET output
becomes active low when VCC falls below 4.75V (4.65V
typical). On power-up, the RESET signal is held active low
for a minimum of 35ms for the LTC690/LTC691 (140ms
for the LTC694/LTC695) after reset voltage threshold is
reached to allow the power supply and microprocessor to
stabilize. The reset active time is adjustable on the LTC691/
LTC695. On power-down, the RESET signal remains active
low even with VCC as low as 1V. This capability helps hold
the microprocessor in stable shutdown condition. Figure
1 shows the timing diagram of the RESET signal.
of the precision voltage comparator C1. When VCC falls
below the reset voltage threshold, LOWLINE goes low.
LOWLINE returns high as soon as VCC rises above the
reset voltage threshold.
Battery Switchover
The battery switchover circuit compares VCC to the VBATT
input, and connects VOUT to whichever is higher. When
VCC rises to 70mV above VBATT, the battery switchover
comparator, C2, connects VOUT to VCC through a charge
pumped NMOS power switch, M1. When VCC falls to
50mV above VBATT, C2 connects VOUT to VBATT through a
PMOS switch, M2. C2 has typically 20mV of hysteresis to
prevent spurious switching when VCC remains nearly equal
to VBATT. The response time of C2 is approximately 20µs.
The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at VCC pin do
not activate the RESET output. Response time is typically
10µs. To help prevent mistriggering due to transient loads,
VCC pin should be bypassed with a 0.1µF capacitor with
the leads trimmed as short as possible.
During normal operation, the LTC690 family uses a charge
pumped NMOS power switch to achieve low dropout and
low supply current. This power switch can deliver up to
50mA to VOUT from VCC and has a typical on resistance
of 5Ω. The VOUT pin should be bypassed with a capacitor of 0.1µF or greater to ensure stability. Use of a larger
bypass capacitor is advantageous for supplying current
to heavy transient loads.
The LTC691 and LTC695 have two additional outputs:
RESET and LOWLINE. RESET is an active high output
and is the inverse of RESET. LOWLINE is the output
When operating currents larger than 50mA are required
from VOUT, or a lower dropout (VCC-VOUT voltage differential)
is desired, the LTC691 and LTC695 should be used.
VCC
RESET
V2
V1
t1
V2
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
V1
t1
t1 = RESET ACTIVE TIME
LOW LINE
690 F01
Figure 1. Reset Active Time
690ff
For more information www.linear.com/690
9
LTC690/LTC691
LTC694/LTC695
Applications Information
These products provide BATT ON output to drive the base
of external PNP transistor (Figure 2). If higher currents
are needed with the LTC690 and LTC694, a high current
Schottky diode can be connected from the VCC pin to the
VOUT pin to supply the extra current.
ANY PNP POWER TRANSISTOR
farad-size double layer capacitors, can be used for short
term memory back-up instead of a battery. The charging
resistor for both capacitors and rechargeable batteries
should be connected to VOUT since this eliminates the
discharge path that exists when the resistor is connected
to VCC (Figure 3).
I=
5
3
5V
0.1µF
1
3V
BATT ON
2
VOUT
VCC
LTC691
LTC695
VOUT – VBATT
R
R
5V
0.1µF
VCC
0.1µF
VBATT
GND
4
VOUT
LTC690
LTC691
LTC694
LTC695
690 F02
3V
VBATT
GND
Figure 2. Using BATT ON to Drive External PNP Transistor
The LTC690 family is protected for safe area operation
with short-circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for long
period of time, thermal shutdown turns the power switch
off until the device cools down. The threshold temperature
for thermal shutdown is approximately 155°C with about
10°C of hysteresis which prevents the device from oscillating in and out of shutdown.
The PNP switch used in competitive devices was not chosen
for the internal power switch because it injects unwanted
current into the substrate. This current is collected by the
VBATT pin in competitive devices and adds to the charging
current of the battery which can damage lithium batteries.
The LTC690 family uses a charge pumped NMOS power
switch to eliminate unwanted charging current while
achieving low dropout and low supply current. Since no
current goes to the substrate, the current collected by
VBATT pin is strictly junction leakage.
A 125Ω PMOS switch connects the VBATT input to VOUT
in battery back-up mode. The switch is designed for very
low dropout voltage (input-to-output differential). This
feature is advantageous for low current applications such
as battery back-up in CMOS RAM and other low power
CMOS circuitry. The supply current in battery back-up
mode is 1µA maximum.
The operating voltage at the VBATT pin ranges from 2.0V
to 4.25V. High value capacitors, such as electrolytic or
0.1µF
690 F03
Figure 3. Charging External Battery Through VOUT
Replacing the Back-Up Battery
When changing the back-up battery with system power
on, spurious resets can occur while battery is removed
due to battery standby current. Although battery standby
current is only a tiny leakage current, it can still charge
up the stray capacitance on the VBATT pin. The oscillation
cycle is as follows: When VBATT reaches within 50mV of
VCC, the LTC690 switches to battery back-up. VOUT pulls
VBATT low and the device goes back to normal operation.
The leakage current then charges up the VBATT pin again
and the cycle repeats.
If spurious resets during battery replacement pose no
problems, then no action is required. Otherwise, a resistor
from VBATT to GND will hold the pin low while changing
the battery. For example, the battery standby current is
1µA maximum over temperature and the external resistor
required to hold VBATT below VCC is:
R≤
VCC − 50mV
1µA
With VCC = 4.5V, a 4.3M resistor will work. With a 3V battery, this resistor will draw only 0.7µA from the battery,
which is negligible in most cases.
690ff
10
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LTC690/LTC691
LTC694/LTC695
Applications Information
input of battery-backed up CMOS RAM. CE OUT can also
be used to drive the Store or Write input of an EEPROM,
EAROM or NOVRAM to achieve similar protection. Figure
5 shows the timing diagram of CE IN and CE OUT.
If battery connections are made through long wires, a
10Ω to 100Ω series resistor and a 0.1µF capacitor are
recommended to prevent any overshoot beyond VCC due
to the lead inductance (Figure 4).
10Ω
CE IN can be derived from the microprocessor’s address
decoder output. Figure 6 shows a typical nonvolatile CMOS
RAM application.
VBATT
4.3M
0.1µF
LTC690
LTC691
LTC694
LTC695
Memory protection can also be achieved with the LTC690
and LTC694 by using RESET as shown in Figure 7.
GND
Table 1. Input and Output Status in Battery Back-Up Mode
690 F04
Figure 4. 10Ω/0.1µF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement
Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
VBATT to GND and VOUT to VCC .
Memory Protection
The LTC691 and LTC695 include memory protection circuitry that ensures the integrity of the data in memory by
preventing write operations when VCC is at invalid level.
Two additional pins, CE IN and CE OUT, control the Chip
Enable or Write inputs of CMOS RAM. When VCC is 5V,
CE OUT follows CE IN with a typical propagation delay of
20ns. When VCC falls below the reset voltage threshold or
VBATT, CE OUT is forced high, independent of CE IN. CE
OUT is an alternative signal to drive the CE, CS, or Write
VCC
STATUS
VCC
C2 monitors VCC for active switchover.
VOUT
VOUT is connected to VBATT through an internal PMOS switch.
VBATT
The supply current is 1µA maximum.
BATT ON
Logic high. The open-circuit output voltage is equal to VOUT .
PFI
Power failure input is ignored.
PFO
Logic low
RESET
Logic low
RESET
Logic high. The open-circuit output voltage is equal to VOUT.
LOWLINE Logic low
V2
V1
SIGNAL
WDI
Watchdog input is ignored.
WDO
Logic high. The open-circuit output voltage is equal to VOUT.
CE IN
ChipEnable Input is ignored.
CE OUT
Logic high. The open-circuit output voltage is equal to VOUT.
OSC IN
OSC IN is ignored.
OSC SEL
OSC SEL is ignored.
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
CE IN
VOUT = VBATT
CE OUT
VOUT = VBATT
690 F05
Figure 5. Timing Diagram for CE IN and CE OUT
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11
LTC690/LTC691
LTC694/LTC695
Applications Information
5V
0.1µF
VCC
VOUT
+
LTC691
LTC695
CE OUT
VBATT
3V
GND
10µF
62512
RAM
CS
20ns PROPAGATION DELAY
CE IN
RESET
Power-Fail Warning
VCC
0.1µF
GND
FROM DECODER
RESET
TO µP
690 F06
Figure 6. A Typical Nonvolatile CMOS RAM Application
5V
VCC
0.1µF
VOUT
+
LTC690
LTC694
VCC
62128
RAM
CS1
0.1µF
10µF
CS
VBATT
RESET
GND
3V
CS2
GND
690 F07
Figure 7. Write Protect for RAM with LTC690 or LTC694
VIN ≥ 7.5V
10µF
+
LT1086-5
VIN
VOUT
ADJ
+
5V
100µF
R3
300k
R1
51k
LTC690/LTC691
LTC694/LTC695
PFO
PFI
R2
10k
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower
trip points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the summing junction at the PFI pin.
VCC
0.1µF
R4
10k
The LTC690 family generates a Power Failure Output (PFO)
for early warning of failure in the microprocessor’s power
supply. This is accomplished by comparing the Power
Failure Input (PFI) with an internal 1.3V reference. PFO
goes low when the voltage at the PFI pin is less than 1.3V.
Typically PFI is driven by an external voltage divider (R1 and
R2 in Figures 8 and 9) which senses either an unregulated
DC input or a regulated 5V output. The voltage divider ratio
can be chosen such that the voltage at the PFI pin falls
below 1.3V several milliseconds before the 5V supply falls
below the maximum reset voltage threshold 4.75V. PFO is
normally used to interrupt the microprocessor to execute
shutdown procedure between PFO and RESET or RESET.
GND
690 F08
TO µP
R1 R1
VH = 1.3V 1+
+
R2 R3
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
R1 (5V − 1.3V) R1
VL = 1.3V 1+
−
R2 1.3V (R3 + R4)
Figure 8. Monitoring Unregulated DC Supply
with the LTC690’s Power-Fail Comparator
VIN ≥ 6.5V
+
10µF
LT1086-5
VIN VOUT
ADJ
+
5V
10µF
R1
27k
R4
10k
R3
2.7M
R2
8.2k
R5
3.3k
0.1µF
VCC
LTC690/LTC691
LTC694/LTC695
PFO
PFI GND
TO µP
Figure 9. Monitoring Regulated DC Supply
with the LTC690’s Power-Fail Comparator
1690 F09
Assuming R4
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