LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TimerBlox:
Voltage-Controlled Pulse
Width Modulator (PWM)
Description
Features
Pulse Width Modulation (PWM) Controlled by
Simple 0V to 1V Analog Input
n Four Available Options Define Duty Cycle Limits
– Minimum Duty Cycle at 0% or 5%
– Maximum Duty Cycle at 95% or 100%
n Frequency Range: 3.81Hz to 1MHz
n Configured with 1 to 3 Resistors
n 0.8 • VSET
±3.0
l
l
Duty Cycle Settling Time (Note 6)
%
%
%
LTC6992-1/LTC6992-4, POL = 0, VMOD = 1V l
100
LTC6992-2/LTC6992-3, POL = 0, VMOD = 1V l
90.5
95
99
0
%
1
5
9.5
%
LTC6992-1/LTC6992-3, POL = 0, VMOD = 0V
tMASTER = tOUT/NDIV
%
l
LTC6992-2/LTC6992-4, POL = 0, VMOD = 0V l
tS,PWM
±3.7
±4.5
±4.9
8•tMASTER
%
µs
69921234fc
3
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET,
DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
V+
IS
Operating Supply Voltage Range
l
Power-On Reset Voltage
l
Supply Current
RL = ∞, RSET = 50k,
NDIV = 1
RL = ∞, RSET = 50k,
NDIV = 4
RL = ∞, RSET = 50k,
NDIV ≥ 16
RL = ∞, RSET = 800k,
NDIV = 1 to 16,384
2.25
5.5
V
1.95
V
V+ = 5.5V
l
365
450
µA
V+ = 2.25V
l
225
285
µA
V+ = 5.5V
l
350
420
µA
V+ = 2.25V
l
225
280
µA
V+ = 5.5V
l
325
390
µA
V+ = 2.25V
l
215
265
µA
V+ = 5.5V
l
120
170
µA
V+ = 2.25V
l
105
150
µA
1.00
1.03
V
Analog Inputs
VSET
Voltage at SET Pin
l
∆VSET/∆T
VSET Drift Over Temperature
l
RSET
Frequency-Setting Resistor
l
0.97
±75
50
MOD Pin Input Capacitance
µV/°C
800
2.5
MOD Pin Input Current
l
VMOD,HI
VMOD Voltage for Maximum
Duty Cycle
LTC6992-1/LTC6992-4, POL = 0, D = 100%
LTC6992-2/LTC6992-3, POL = 0, D = 95%
l
VMOD,LO
VMOD Voltage for Minimum
Duty Cycle
LTC6992-1/LTC6992-3, POL = 0, D = 0%
LTC6992-2/LTC6992-4, POL = 0, D = 5%
l 0.064 • VSET
VDIV
DIV Pin Voltage
∆VDIV/∆V+
DIV Pin Valid Code Range (Note 5)
DIV Pin Input Current
0.10 • VSET
0.14 • VSET
pF
±10
nA
0.936•VSET
V
V
V
V
V+
V
l
±1.5
%
l
±10nA
l
Deviation from Ideal
VDIV/V+ = (DIVCODE + 0.5)/16
0.90 • VSET
0.86 • VSET
kΩ
0
Digital Output
IOUT(MAX)
Output Current
V+ = 2.7V to 5.5V
±20
mA
VOH
High Level Output Voltage (Note 7)
V+ = 5.5V
IOUT = –1mA
IOUT = –16mA
l
l
5.45
4.84
5.48
5.15
V
V
IOUT = –1mA
V+ = 3.3V
IOUT = –10mA
l
l
3.24
2.75
3.27
2.99
V
V
IOUT = –1mA
V+ = 2.25V
IOUT = -8mA
l
l
2.17
1.58
2.21
1.88
V
V
V+ = 5.5V
IOUT = 1mA
IOUT = 16mA
l
l
0.02
0.26
0.04
0.54
V
V
IOUT = 1mA
V+ = 3.3V
IOUT = 10mA
l
l
0.03
0.22
0.05
0.46
V
V
IOUT = 1mA
V+ = 2.25V
IOUT = 8mA
l
l
0.03
0.26
0.07
0.54
V
V
VOL
Low Level Output Voltage (Note 7)
tr
Output Rise Time (Note 8)
V+ = 5.5V, RLOAD = ∞
V+ = 3.3V, RLOAD = ∞
V+ = 2.25V, RLOAD = ∞
1.1
1.7
2.7
ns
ns
ns
tf
Output Fall Time (Note 8)
V+ = 5.5V, RLOAD = ∞
V+ = 3.3V, RLOAD = ∞
V+ = 2.25V, RLOAD = ∞
1.0
1.6
2.4
ns
ns
ns
69921234fc
4
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Electrical Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6992C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 3: The LTC6992C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6992C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6992I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6992H is guaranteed
to meet specified performance from –40°C to 125°C. The LTC6992MP is
guaranteed to meet specified performance from –55°C to 125°C.
Note 4: Frequency accuracy is defined as the deviation from the fOUT
equation, assuming RSET is used to program the frequency.
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
Note 6: Duty cycle settling time is the amount of time required for the
output to settle within ±1% of the final duty cycle after a ±10% change in
the setting (±80mV step in VMOD).
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Jitter is the ratio of the peak-to-peak deviation of the period to the
mean of the period. This specification is based on characterization and is
not 100% tested.
Note 10: Long-term drift of silicon oscillators is primarily due to the
movement of ions and impurities within the silicon and is tested at 30°C
under otherwise nominal operating conditions. Long-term drift is specified
as ppm/√kHr due to the typically nonlinear nature of the drift. To calculate
drift for a set time period, translate that time into thousands of hours, take
the square root and multiply by the typical drift number. For instance, a
year is 8.77kHr and would yield a drift of 266ppm at 90ppm/√kHr. Drift
without power applied to the device may be approximated as 1/10th of the
drift with power, or 9ppm/√kHr for a 90ppm/√kHr device.
Typical Performance Characteristics
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
otherwise noted.
Frequency Error vs Temperature
2
Frequency Error vs Temperature
3
GUARANTEED MAX OVER TEMPERATURE
2
RSET = 50k
3 PARTS
ERROR (%)
ERROR (%)
GUARANTEED MAX OVER TEMPERATURE
2
RSET = 200k
3 PARTS
1
1
0
–1
–2
–2
GUARANTEED MIN OVER TEMPERATURE
–25
75
0
25
50
TEMPERATURE (°C)
100
125
6992 G01
–3
–50
GUARANTEED MAX OVER TEMPERATURE
RSET = 800k
3 PARTS
1
0
–1
–3
–50
Frequency Error vs Temperature
3
ERROR (%)
3
0
–1
–2
GUARANTEED MIN OVER TEMPERATURE
–25
75
0
25
50
TEMPERATURE (°C)
100
125
6992 G02
–3
–50
GUARANTEED MIN OVER TEMPERATURE
–25
75
0
25
50
TEMPERATURE (°C)
100
125
6992 G03
69921234fc
5
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical Performance Characteristics
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
otherwise noted.
Frequency Error vs RSET
Frequency Drift vs Supply Voltage
GUARANTEED MAX OVER TEMPERATURE
2
0.3
200
0.2
DRIFT (%)
1
ERROR (%)
250
0.4
3 PARTS
0
–1
RSET = 50k
0.1
0
–0.1
–0.2
RSET = 200k
–0.3
–2
–0.4
GUARANTEED MIN OVER TEMPERATURE
–3
50
100
200
RSET (k)
400
–0.5
800
RSET = 800k
REFERENCED TO V+ = 4.5V
2
100
0
0.98
6
4
5
3
SUPPLY VOLTAGE (V)
VSET Drift vs Supply
0.8
0.8
1.015
0.6
0.6
0.4
0.4
0.2
0.2
–0.6
–0.6
–0.8
–1.0
REFERENCED TO ISET = 10µA
0
5
10
ISET (µA)
20
15
VSET (V)
1.005
0
–0.4
0.990
2
3
4
SUPPLY (V)
5
0.980
–50
NDIV = 1 Duty Cycle Error vs RSET
1
1
ERROR (%)
1
0
–1
0
–1
–2
–2
–2
–3
–3
–3
–4
–4
–4
–5
–5
–5
100
200
RSET (k)
400
800
6992 G10
50
100
200
RSET (k)
125
VMOD/VSET = 0.8 (87.5%)
4 DIVCODE = 0
3 PARTS
3
2
50
100
NDIV = 1 Duty Cycle Error vs RSET
2
–1
75
0
25
50
TEMPERATURE (°C)
5
2
0
–25
6992 G09
VMOD/VSET = 0.5 (50%)
4 DIVCODE = 0
3 PARTS
3
VMOD/VSET = 0.2 (12.5%)
DIVCODE = 0
3 PARTS
ERROR (%)
ERROR (%)
3
6
5
6992 G08
NDIV = 1 Duty Cycle Error vs RSET
4
0.985
REFERENCED TO V+ = 4V
6992 G07
5
1.000
0.995
–0.8
–1.0
3 PARTS
1.010
–0.2
–0.4
1.02
1.012
VSET vs Temperature
1.020
0
0.996
1.004
VSET (V)
0.988
6992 G06
1.0
DRIFT (mV)
VSET (mV)
150
6992 G05
VSET Drift vs ISET
–0.2
2 LOTS
DFN AND SOT-23
1274 UNITS
50
6992 G04
1.0
Typical VSET Distribution
0.5
NUMBER OF UNITS
3
400
800
6992 G11
50
100
200
RSET (k)
400
800
6992 G12
69921234fc
6
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical Performance Characteristics
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
otherwise noted.
5
NDIV > 1 Duty Cycle Error vs RSET
NDIV > 1 Duty Cycle Error vs RSET
5
2
2
2
1
1
1
VMOD/VSET = 0.8 (87.5%)
4 DIVCODE = 4
3 PARTS
3
0
–1
ERROR (%)
VMOD/VSET = 0.5 (50%)
4 DIVCODE = 4
3 PARTS
3
ERROR (%)
0
–1
–2
–2
–3
–3
–3
–4
–4
–4
–5
–5
–5
50
100
200
RSET (k)
400
800
50
100
200
RSET (k)
400
6992 G13
93
ERROR (%)
7
3
LTC6992-2/LTC6992-3
VMOD = VSET
92
8
LTC6992-2/LTC6992-4
VMOD = VSET
7
LTC6992-2/LTC6992-4
VMOD = VSET
6
4
94
LTC6992-2/LTC6992-3
VMOD = VSET
8
6
2
0
–1
–2
–3
4
4
–4
3
3
–5
–50
200
RSET (k)
400
800
100
50
200
RSET (k)
400
GUARANTEED MAX
4
VMOD/VSET = 0.8 (87.5%)
DIVCODE = 0
2 3 PARTS
3
1
1
1
0
–1
–3
–3
–4
–5
–50
GUARANTEED MIN
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6992 G19
ERROR (%)
3
ERROR (%)
VMOD/VSET = 0.5 (50%)
DIVCODE = 0
2 3 PARTS
–2
GUARANTEED MAX
0
–1
–2
–3
–4
–5
–50
125
VMOD/VSET = 0.2 (12.5%)
DIVCODE = 4
2 3 PARTS
3
–2
100
5
4
GUARANTEED MAX
–1
0
25
50
75
TEMPERATURE (°C)
NDIV > 1 Duty Cycle Error
vs Temperature
5
0
–25
6992 G18
NDIV = 1 Duty Cycle Error
vs Temperature
5
4
800
GUARANTEED MIN
6992 G17
6992 G16
NDIV = 1 Duty Cycle Error
vs Temperature
800
1
5
100
400
GUARANTEED MAX
VMOD/VSET = 0.2 (12.5%)
DIVCODE = 0
3 PARTS
5
50
200
RSET (k)
5
DIVCODE = 4
96 3 PARTS
95
92
100
NDIV = 1 Duty Cycle Error
vs Temperature
97
DIVCODE = 0
96 3 PARTS
95
93
50
6992 G15
NDIV > 1 Duty Cycle Error vs RSET
97
94
800
6992 G14
NDIV = 1 Duty Cycle Clamps
vs RSET
ERROR (%)
0
–1
–2
ERROR (%)
ERROR (%)
VMOD/VSET = 0.2 (12.5%)
4 DIVCODE = 4
3 PARTS
3
ERROR (%)
NDIV > 1 Duty Cycle Error vs RSET
5
GUARANTEED MIN
–25
75
0
25
50
TEMPERATURE (°C)
100
125
6992 G20
–4
–5
–50
GUARANTEED MIN
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6992 G21
69921234fc
7
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical Performance Characteristics
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
otherwise noted.
NDIV > 1 Duty Cycle Error
vs Temperature
NDIV > 1 Duty Cycle Error
vs Temperature
97
5
5
4
GUARANTEED MAX
VMOD/VSET = 0.8 (87.5%)
DIVCODE = 4
2 3 PARTS
VMOD/VSET = 0.5 (50%)
DIVCODE = 4
2 3 PARTS
3
1
1
ERROR (%)
3
0
–1
–3
–3
–5
–50
100
0
25
50
75
TEMPERATURE (°C)
–25
100
0
25
50
75
TEMPERATURE (°C)
–25
5
3
3
2
2
1
1
VMOD /VSET = 0.5 (50%)
4 3 PARTS
0
–1
0
–1
–2
–2
–3
–3
4
–4
–4
3
–50
–5
5
–25
75
0
25
50
TEMPERATURE (°C)
100
125
0
2
4
6
8
10
DIVCODE
12
6992 G25
DIVCODE = 0
90 3 PARTS
VMOD / VSET = 0.8 (87.5%)
4 3 PARTS
80
2
70
DUTY CYCLE (%)
3
–1
–2
12
14
6992 G28
LTC6992-2/
LTC6992-4
30
10
6
8
10
DIVCODE
12
0
14
LTC6992-1/
LTC6992-4
80
LTC6992-2/
LTC6992-3
40
20
4
DIVCODE = 4
90 3 PARTS
50
–4
2
6
8
10
DIVCODE
NDIV > 1 Duty Cycle vs VMOD/ VSET
LTC6992-1/
LTC6992-4
60
–3
0
4
100
100
0
2
6992 G27
NDIV = 1 Duty Cycle vs VMOD/ VSET
Duty Cycle Error vs DIVCODE
1
0
6992 G26
5
–5
–5
14
DUTY CYCLE (%)
6
125
Duty Cycle Error vs DIVCODE
5
ERROR (%)
LTC6992-2/LTC6992-4
VMOD = GND
ERROR (%)
DUTY CYCLE (%)
8
100
75
0
25
50
TEMPERATURE (°C)
–25
6992 G24
VMOD /VSET = 0.2 (12.5%)
4 3 PARTS
94
ERROR (%)
3
–50
125
Duty Cycle Error vs DIVCODE
DIVCODE = 4
96 3 PARTS
95
7
4
6992 G23
97
LTC6992-2/LTC6992-3
VMOD = VSET
LTC6992-2/LTC6992-4
VMOD = GND
5
GUARANTEED MIN
–5
–50
NDIV > 1 Duty Cycle Clamps
vs Temperature
92
8
6
6992 G22
93
92
7
–4
125
LTC6992-2/LTC6992-3
VMOD = VSET
93
–1
–2
GUARANTEED MIN
94
0
–2
–4
DIVCODE = 0
96 3 PARTS
95
GUARANTEED MAX
ERROR (%)
4
ERROR (%)
NDIV = 1 Duty Cycle Clamps
vs Temperature
LTC6992-2/
LTC6992-3
70
60
50
40
LTC6992-2/
LTC6992-4
30
20
10
LTC6992-1/LTC6992-3
0
0.2
0.4
0.6
VMOD/VSET (V/V)
1
0.8
6992 G29
0
LTC6992-1/LTC6992-3
0
0.2
0.4
0.6
VMOD/VSET (V/V)
1
0.8
6992 G30
69921234fc
8
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical Performance Characteristics
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
otherwise noted.
NDIV > 1 Duty Cycle vs VMOD/ VSET
80
3
3
70 LTC6992-2/
LTC6992-4
60
2
LTC6992-2/
LTC6992-3
2
PART C
1
PART B
0
–1
PART A
1
–1
–2
20
–3
–3
LTC6992-1/
10 DIVCODE = 11
LTC6992-4
3 PARTS
0
0
0.2
0.4
0.6
VMOD/VSET (V/V)
–4
–4
–5
1
0.8
0
100
97
97
96
96
0
PART B
–1
–2
DIVCODE = 4
99 LTC6992-2/LTC6992-3
98 3 PARTS
DUTY CYCLE (%)
PART A
1
95
94
93
92
95
94
93
92
91
91
90
90
–4
89
89
–5
88
0.804
–3
0
25
50
75
IDEAL DUTY CYCLE (%)
100
0.868
0.836
VMOD/VSET (V/V)
DIVCODE = 4
71 3 PARTS
12
9
9
8
8
DIVCODE = 4
11 LTC6992-2/LTC6992-4
10 3 PARTS
DUTY CYCLE (%)
66
65
64
63
0.628
0.644
VMOD/VSET (V/V)
0.66
0.676
6992 G37
DUTY CYCLE (%)
70
0.612
Linearity Near 5% Duty Cycle
12
DIVCODE = 4
11 LTC6992-1/LTC6992-3
10 3 PARTS
67
0.9
6992 G36
Linearity Near 0% Duty Cycle
Linearity Near 67% Duty Cycle
68
0.868
0.836
VMOD/VSET (V/V)
6992 G35
72
62
0.596
88
0.804
0.9
6992 G34
69
100
Linearity Near 95% Duty Cycle
100
DIVCODE = 4
99 LTC6992-1/LTC6992-4
98 3 PARTS
DUTY CYCLE (%)
PART C
25
50
75
IDEAL DUTY CYCLE (%)
6992 G33
Linearity Near 100% Duty Cycle
DIVCODE = 11
4 3 PARTS
2
0
6992 G32
NDIV > 1 Duty Cycle Error vs Ideal
3
PART A
–5
100
25
50
75
IDEAL DUTY CYCLE (%)
PART C
PART B
0
–2
30
5
ERROR (%)
ERROR (%)
ERROR (%)
50
40
DIVCODE = 4
4 3 PARTS
DIVCODE = 0
4 3 PARTS
LTC6992-1/LTC6992-3
6992 G31
DUTY CYCLE (%)
NDIV > 1 Duty Cycle Error vs Ideal
5
90
DUTY CYCLE (%)
NDIV = 1 Duty Cycle Error vs Ideal
5
100
7
6
5
4
7
6
5
4
3
3
2
2
1
1
0
0.084
0
0.084
0.116
0.148
VMOD/VSET (V/V)
0.18
6992 G38
0.116
0.148
VMOD/VSET (V/V)
0.18
6992 G39
69921234fc
9
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical Performance Characteristics
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
otherwise noted.
0.5
36
34
0.3
33
0.2
32
0.1
31
30
28
–0.3
27
–0.4
26
0.308
–0.5
0.34
0.356
VMOD/VSET (V/V)
0.388
0.372
0.2
95% CLAMP
5% CLAMP
VMOD/VSET = 0.8
VMOD/VSET = 0.2
VMOD/VSET = 0.5
3
4
SUPPLY (V)
POWER SUPPLY CURRENT (µA)
POWER SUPPLY CURRENT (µA)
RSET = 100k, ÷4
150
100
RSET = 800k, ÷1
50
0
0
0.2
0.4
0.6
VMOD (V)
RSET = 50k, ÷16
250
200
RSET = 100k, ÷1
150
100
RSET = 800k, ÷1
50
2
3
Jitter vs Frequency
÷1, V+ = 2.5V
1.0
0.8
÷4, V+ = 5V
÷4, V+ = 2.5V
0.6
0.4
0.2
0
0.01
÷64
0.1
200
150
÷16
1
10
FREQUENCY (kHz)
100
1000
6992 G46
5.0V, RSET = 800k, ÷1
100
2.5V, RSET = 800k, ÷1
50
–25
75
0
25
50
TEMPERATURE (°C)
÷16,384
200
÷1
100
50
0
0.001
0.01
10
0.1
1
FREQUENCY (kHz)
100
V+ = 2.5V
350
÷4
150
125
Supply Current vs Frequency, 2.5V
400
300
250
100
6992 G45
V+ = 5V
350
POWER SUPPLY CURRENT (µA)
JITTER (%P-P)
1.2
2.5V, RSET = 50k, ÷1
250
Supply Current vs Frequency, 5V
400
6
5
5.0V, RSET = 50k, ÷16
300
6992 G44
2.0
÷1, V+ = 5V
4
SUPPLY (V)
5.0V, RSET = 50k, ÷1
0
–50
6
4
5
SUPPLY VOLTAGE (V)
6992 G43
PEAK-TO-PEAK PERIOD
1.8 DEVIATION MEASURED
OVER 30s INTERVALS
1.6
VMOD/VSET = 0.5
1.4
3
350
RSET = 50k, ÷4
300
0
1
0.8
2
Supply Current vs Temperature
RSET = 50k, ÷1
350
200
REFERENCED TO V+ = 4V
400
POWER SUPPLY CURRENT (µA)
LTC6992-2
RSET = 50k, ÷16
VMOD/VSET = 0.8
6992 G42
Supply Current vs Supply Voltage
350
250
–0.5
400
RSET = 50k, ÷1
VMOD/VSET = 0.5
6992 G41
Supply Current vs VMOD
300
–0.1
–0.4
6
5
6992 G40
400
95% CLAMP
0
–0.3
REFERENCED TO V+ = 4V
2
VMOD/VSET = 0.2
0.1
–0.2
POWER SUPPLY CURRENT (µA)
0.324
5% CLAMP
0.3
–0.1
–0.2
DIVCODE = 4
0.4
0
29
0.5
DIVCODE = 0
0.4
DRIFT (%)
DUTY CYCLE (%)
DIVCODE = 4
35 3 PARTS
NDIV > 1 Duty Cycle Drift
vs Supply
NDIV = 1 Duty Cycle Drift vs Supply
DRIFT (%)
Linearity Near 31% Duty Cycle
1000
6992 G47
300
250
÷4
÷16,384
200
150
÷1
100
50
0
0.001
0.01
10
0.1
1
FREQUENCY (kHz)
100
1000
6992 G48
69921234fc
10
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical Performance Characteristics
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
otherwise noted.
150
OUTPUT RESISTANCE (Ω)
50
0
–50
–100
–150
–200
3.0
CLOAD = 5pF
45
100
2.5
40
35
OUTPUT SOURCING CURRENT
30
25
20
OUTPUT SINKING CURRENT
15
10
2.0
tRISE
1.5
tFALL
1.0
0.5
5
0
400
800 1200 1600 2000 2400 2800
TIME (h)
0
2
3
4
5
SUPPLY VOLTAGE (V)
6
Typical ISET Current Limit vs V+
1000
0
2
3
4
5
SUPPLY VOLTAGE (V)
6992 G50
6992 G48a
6
6992 G51
Typical Start-Up, POL = 0
SET PIN SHORTED TO GND
800
ISET (µA)
DELTA FREQUENCY (ppm)
50
65 UNITS
SOT-23 AND DFN PARTS
TA = 30°C
RISE/FALL TIME (ns)
200
Rise and Fall Time
vs Supply Voltage
Output Resistance
vs Supply Voltage
Typical Frequency Error vs
Time (Long-Term Drift)
V+
1V/DIV
600
OUT
1V/DIV
400
200
0
2
3
4
5
SUPPLY VOLTAGE (V)
500µs
100µs/DIV
V+ = 2.5V
DIVCODE = 3 (÷64)
RSET = 50k
VMOD = 0.3V (~25% DUTY CYCLE)
6
6992 G53
6992 G52
Typical Start-Up, POL = 1
125kHz Full Modulation
LTC6992-1
VMOD
0.5V/DIV
V+
1V/DIV
OUT
1V/DIV
OUT
1V/DIV
500µs
100µs/DIV
V+ = 2.5V
DIVCODE = 12 (÷64, POL = 1)
RSET = 50k
VMOD = 0.2V (~87.5% DUTY CYCLE)
6992 G54
V+ = 3.3V
DIVCODE = 1
RSET = 100k
50µs/DIV
6992 G55
69921234fc
11
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Pin Functions
(DCB/S6)
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1μF capacitor.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. The DIV pin voltage (VDIV) is internally converted
into a 4-bit result (DIVCODE). VDIV may be generated by
a resistor divider between V+ and GND. Use 1% resistors
to ensure an accurate result. The DIV pin and resistors
should be shielded from the OUT pin or any other traces
that have fast edges. Limit the capacitance on the DIV pin
to less than 100pF so that VDIV settles quickly. The MSB of
DIVCODE (POL) determines if the PWM signal is inverted
before driving the output. When POL = 1 the transfer function is inverted (duty cycle decreasing as VMOD increases).
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (VSET) is regulated to 1V above GND. The
amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current
range is 1.25μA to 20μA. The output oscillation will stop
if ISET drops below approximately 500nA. A resistor connected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
50ppm/°C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor
may be used.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the VSET voltage.
V+
MOD
OUT
LTC6992
GND
SET
RSET
V+
V+
C1
0.1µF
R1
DIV
6992 PF
R2
MOD (Pin 4/Pin 1): Pulse-Width Modulation Input. The
voltage on the MOD pin controls the output duty cycle. The
linear control range is between 0.1 • VSET and 0.9 • VSET
(approximately 100mV to 900mV). Beyond those limits,
the output will either clamp at 5% or 95%, or stop oscillating (0% or 100% duty cycle), depending on the version.
GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground
plane for best performance.
OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
from GND to V+ with an output resistance of approximately
30Ω. The duty cycle is determined by the voltage on the
MOD pin. When driving an LED or other low-impedance
load a series output resistor should be used to limit the
source/sink current to 20mA.
69921234fc
12
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Block Diagram
V+
R1 DIV
4
(S6 Package Pin Numbers Shown)
5
4-BIT A/D
CONVERTER
POL
DIGITAL
FILTER
R2
OUTPUT
POLARITY
MASTER OSCILLATOR
ISET
fOSC = 1MHz • 50kΩ •
VSET
MCLK
PULSE WIDTH MODULATOR
PROGRAMMABLE DIVIDER
÷1, 4, 16, 64, 256, 1024, 4096, 16384
DUTY CYCLE =
VMOD(LIM) – 0.1•VSET
tON
0.8•VSET
OUT
6
tOUT
DISABLE OUTPUT
UNTIL SETTLED
HALT OSCILLATOR
IF ISET < 500nA
D=
VMOD(LIM)
+
–
VSET = 1V
3
ISET
POR
+
–
VREF
1V
2
SET
GND
tON
tOUT
VOLTAGE LIMITER
VMOD
1
MOD
6992 BD
RSET
69921234fc
13
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Operation
The LTC6992 is built around a master oscillator with a
1MHz maximum frequency. The oscillator is controlled
by the SET pin current (ISET) and voltage (VSET), with a
1MHz • 50k conversion factor that is accurate to ±0.8%
under typical conditions.
I
1
fMASTER =
= 1MHz • 50k • SET
tMASTER
VSET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the output frequency.
The simplest way to generate ISET is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET.
The master oscillator equation reduces to:
1
1MHz • 50k
fMASTER =
=
tMASTER
RSET
From this equation, it is clear that VSET drift will not affect
the output frequency when using a single program resistor
(RSET). Error sources are limited to RSET tolerance and
the inherent frequency accuracy ΔfOUT of the LTC6992.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25μA and 20μA).
DIVCODE
The DIV pin connects to an internal, V+ referenced 4-bit A/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6992:
1. DIVCODE determines the output frequency divider setting, NDIV.
2. DIVCODE determines the output polarity, via the POL
bit.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
2.25V TO 5.5V
V+
LTC6992
R1
DIV
R2
GND
6992 F01
Figure 1. Simple Technique for Setting DIVCODE
The LTC6992 includes a programmable frequency divider
which can further divide the frequency by 1, 4, 16, 64,
256, 1024, 4096 or 16384 before driving the OUT pin.
The divider ratio NDIV is set by a resistor divider attached
to the DIV pin.
1
1MHz • 50k ISET
fOUT =
=
•
tOUT
NDIV
VSET
With RSET in place of VSET/ISET the equation reduces to:
fOUT =
1
tOUT
=
1MHz • 50k
NDIV • RSET
69921234fc
14
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Operation
Table 1. DIVCODE Programming
DIVCODE
POL
NDIV
RECOMMENDED fOUT
R1 (kΩ)
R2 (kΩ)
VDIV /V+
0
0
1
62.5kHz to 1MHz
Open
Short
≤0.03125 ±0.015
1
0
4
15.63kHz to 250kHz
976
102
0.09375 ±0.015
2
0
16
3.906kHz to 62.5kHz
976
182
0.15625 ±0.015
3
0
64
976.6Hz to 15.63kHz
1000
280
0.21875 ±0.015
4
0
256
244.1Hz to 3.906kHz
1000
392
0.28125 ±0.015
5
0
1024
61.04Hz to 976.6Hz
1000
523
0.34375 ±0.015
6
0
4096
15.26Hz to 244.1Hz
1000
681
0.40625 ±0.015
7
0
16384
3.815Hz to 61.04Hz
1000
887
0.46875 ±0.015
8
1
16384
3.815Hz to 61.04Hz
887
1000
0.53125 ±0.015
9
1
4096
15.26Hz to 244.1Hz
681
1000
0.59375 ±0.015
10
1
1024
61.04Hz to 976.6Hz
523
1000
0.65625 ±0.015
11
1
256
244.1Hz to 3.906kHz
392
1000
0.71875 ±0.015
12
1
64
976.6Hz to 15.63kHz
280
1000
0.78125 ±0.015
13
1
16
3.906kHz to 62.5kHz
182
976
0.84375 ±0.015
14
1
4
15.63kHz to 250kHz
102
976
0.90625 ±0.015
15
1
1
62.5kHz to 1MHz
Short
Open
≥0.96875 ±0.015
Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the
corresponding NDIV and POL values for the recommended
resistor pairs. Other values may be used as long as:
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
VDIV
Figure 2 illustrates the information in Table 1, showing
that NDIV is symmetric around the DIVCODE midpoint.
If the voltage is generated by other means (i.e. the output
of a DAC) it must track the V+ supply voltage. The last
POL BIT = 0
1000
POL BIT = 1
15
0
100
fOUT (kHz)
DIVCODE + 0.5
±1.5%
16
For example, if the supply is 3.3V and the desired DIVCODE
is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.
2. The driving impedance (R1||R2) does not exceed 500kΩ.
1
14
2
10
13
3
1
12
11
4
10
5
0.1
9
6
7
0.01
0.001
V+
1. The VDIV/V+ ratio is accurate to ±1.5% (including resistor tolerances and temperature effects).
=
0V
8
0.5•V+
V+
INCREASING VDIV
6992 F02
Figure 2. Frequency Range and POL Bit vs DIVCODE
69921234fc
15
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Operation
Pulse Width (Duty Cycle) Modulation
Output Polarity (POL Bit)
The MOD pin is a high impedance analog input providing
direct control of the output duty cycle. The duty cycle is
proportional to the voltage applied to the MOD pin, VMOD.
VMOD
1
Duty Cycle = D =
−
0.8 • VSET 8
The duty cycle equation describes a proportional transfer
function, where duty cycle increases as VMOD increases.
The LTC6992 includes a POL bit (determined by the
DIVCODE as described earlier) that inverts the output
signal. This makes the duty cycle gain negative, reducing
duty cycle as VMOD increases.
The PWM duty cycle accuracy ΔD specifies that the above
equation is valid to within ±4.5% for VMOD between 0.2 •
VSET and 0.8 • VSET (12.5% to 87.5% duty cycle).
Since VSET = 1V ±30mV, the duty cycle equation may be
approximated by the following equation.
Duty Cycle = D ≅
POL = 0
D•tOUT
Duty Cycle Limits
The only difference between the four versions of the
LTC6992 is the limits, or clamps, placed on the output
duty cycle. The LTC6992-1 generates output duty cycles
ranging from 0% to 100%. At 0% or 100% the output
will stop oscillating and rest at GND or V+, respectively.
VMOD
1
−
0.8 • VSET 8
OUT
VMOD − 100mV
800mV
The VMOD control range is approximately 0.1V to 0.9V.
Driving VMOD beyond that range (towards GND or V+) will
have no further affect on the duty cycle.
D=
tOUT
POL = 1
D•tOUT
VMOD
1
D = 1−
−
0.8 • VSET 8
OUT
tOUT
6992 F03
Figure 3. POL Bit Functionality
The LTC6992-2 will never stop oscillating, regardless of
the VMOD level. Internal clamping circuits limit its duty
cycle to a 5% to 95% range (1% to 99% guaranteed).
Therefore, its VMOD control range is 0.14 • VSET to 0.86 •
VSET (approximately 0.14V to 0.86V).
The LTC6992-3 and LTC6992-4 complete the family by
providing one-sided clamping. The LTC6992-3 allows
0% to 95% duty cycle, and the LTC6992-4 allows 5% to
100% duty cycle.
69921234fc
16
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Operation
POL = 1 forces a simple logic inversion, so it changes the
duty cycle range of the LTC6992-3 (making it 100% to 5%)
and LTC6992-4 (making it 95% to 0%). These transfer
functions are detailed in Figure 4.
100
Table 2. Duty Cycle Ranges
DUTY CYCLE RANGE vs VMOD = 0V → 1V
PART NUMBER
POL = 0
POL = 1
LTC6992-1
0% to 100%
100% to 0%
LTC6992-2
5% to 95%
95% to 5%
LTC6992-3
0% to 95%
100% to 5%
LTC6992-4
5% to 100%
95% to 0%
100
VMOD /VSET = 0.1
90
90
70
POL = 0
POL = 1
60
50
40
30
20
70
50
40
30
0
VMOD /VSET = 0.86
10
VMOD /VSET = 0.9
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VMOD/VSET (V/V)
0
1
0
6992 F04a
1
LTC6992-2
100
100
90
90
VMOD /VSET = 0.1
VMOD /VSET = 0.14
80
70
POL = 0
POL = 1
60
DUTY CYCLE (%)
80
DUTY CYCLE (%)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VMOD/VSET (V/V)
6992 F04b
LTC6992-1
50
40
30
70
POL = 1
60
POL = 0
50
40
30
20
20
VMOD /VSET = 0.86
10
0
POL = 0
POL = 1
60
20
10
0
VMOD /VSET = 0.14
80
DUTY CYCLE (%)
DUTY CYCLE (%)
80
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VMOD/VSET (V/V)
1
6992 F02c
LTC6992-3
VMOD /VSET = 0.9
10
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
VMOD/VSET (V/V)
1
6992 F02d
LTC6992-4
Figure 4. PWM Transfer Functions for All LTC6992 Family Parts
69921234fc
17
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Operation
Changing DIVCODE After Start-Up
Start-Up Time
Following start-up, the A/D converter will continue
monitoring VDIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6992 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, tSTART. The OUT pin
is held low during this time. The typical value for tSTART
ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV):
tDIVCODE = 16 • (∆DIVCODE + 6) • tMASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes.
A digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
DIV
0.5V/DIV
512µs
tSTART(TYP) = 500 • tMASTER
The output will begin oscillating after tSTART. If POL = 0
the first pulse has the correct width. If POL = 1 (DIVCODE
≥ 8), the first pulse width can be shorter or longer than
expected, depending on the duty cycle setting, and will
never be less than 25% of tOUT.
During start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the output is enabled. The
start-up time may increase if the supply or DIV pin voltages are not stable. For this reason, it is recommended to
minimize the capacitance on the DIV pin so it will properly
track V+. Less than 100pF will not affect performance.
V+
OUT
1V/DIV
V+ = 3.3V
RSET = 200k
VMOD = 0.3V
100µs/DIV
6992 F05
Figure 5. DIVCODE Change from 3 to 1
DIV
STABLE VDIV
tDIVCODE
tSTART
OUT
6992 F06
1ST PULSE WIDTH MAY BE INACCURATE
Figure 6. Start-Up Timing Diagram
69921234fc
18
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Applications Information
Basic Operation
The simplest and most accurate method to program the
LTC6992 is to use a single resistor, RSET, between the
SET and GND pins. The design procedure is a four step
process. After choosing the proper LTC6992 version and
POL bit setting, select the NDIV value and then calculate
the value for the RSET resistor.
Alternatively, Linear Technology offers the easy to use
TimerBlox Designer tool to quickly design any LTC6992
based circuit. Download the free TimerBlox Designer
software at www.linear.com/timerblox.
Step 1: Selecting the POL Bit Setting
Most applications will use POL = 0, resulting in a positive
transfer function. However, some applications may require
a negative transfer function, where increasing VMOD reduces the output duty cycle. For example, if the LTC6992
is used in a feedback loop, POL = 1 may be required to
achieve negative feedback.
To minimize supply current, choose the lowest NDIV value
(generally recommended). For faster start-up or decreased
jitter, choose a higher NDIV setting. Alternatively, use Table 1
as a guide to select the best NDIV value for the given application.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or VDIV/V+ ratio to apply to the DIV pin.
Step 4: Calculate and Select RSET
The final step is to calculate the correct value for RSET
using the following equation.
RSET =
1MHz • 50k
NDIV • fOUT
Select the standard resistor value closest to the calculated
value.
Example: Design a PWM circuit that satisfies the following
requirements:
Step 2: Selecting the LTC6992 Version
• fOUT = 20kHz
The difference between the LTC6992 versions is observed at
the endpoints of the duty cycle control range. Applications
that require the output to never stop oscillating should use
the LTC6992-2. On the other hand, if the output should be
allowed to rest at GND or V+ (0% or 100% duty cycle),
select the LTC6992-1.
• Positive VMOD to duty cycle response
• Minimum power consumption
The LTC6992-3 and LTC6992-4 clamp the duty cycle at
only one end of the control range, allowing the output to
stop oscillating at the other extreme. If POL = 1 the clamp
will swap from low duty cycle to high, or vice-versa. Refer
to Table 2 and Figure 4 for assistance in selecting the
proper version.
Step 2: Selecting the LTC6992 Version
Step 3: Selecting the NDIV Frequency Divider Value
(1b)
• Output can reach 100% duty cycle, but not 0%
Step 1: Selecting the POL Bit Setting
For positive transfer function (duty cycle increases with
VMOD), choose POL = 0.
To limit the minimum duty cycle, but allow the maximum
duty cycle to reach 100%, choose LTC6992-4. (Note that
if POL = 1 the LTC6992-3 would be the correct choice.)
Step 3: Selecting the NDIV Frequency Divider Value
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
NDIV value. For a given output frequency, NDIV should be
selected to be within the following range.
Choose an NDIV value that meets the requirements of
Equation (1a).
1MHz
62.5kHz
≤ NDIV ≤
fOUT
fOUT
Potential settings for NDIV include 4 and 16. NDIV = 4 is
the best choice, as it minimizes supply current by us-
(1a)
3.125 ≤ NDIV ≤ 50
69921234fc
19
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
applications information
Step 4: Select RSET
Calculate the correct value for RSET using Equation (1b).
RSET =
1MHz • 50k
= 625k
4 • 20kHz
Since 625k is not available as a standard 1% resistor,
substitute 619k if a 0.97% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
The completed design is shown in Figure 7.
VMOD
MOD
OUT
LTC6992-4
RSET
625k
GND
V+
SET
DIV
6992 F07
2.25V TO 5.5V
R1
976k
DIVCODE = 1
R2
102k
Figure 7. 20kHz PWM Oscillator
Figure 8 demonstrates the worst-case impact of this variation (if VSET is at its 0.97V or 1.03V limits).
This error is in addition to the inherent PWM duty cycle
accuracy spec ΔD (±4.5%), so care should be taken if
accuracy at high duty cycles (VMOD near 0.9V) is critical.
Sensitivity to ΔVSET can be eliminated by making VMOD
proportional to VSET. For example, Figure 9 shows a simple
circuit for generating an arbitrary duty cycle. The equation
for duty cycle does not depend on VSET at all.
100
90
∆VSET = –30mV
80
DUTY CYCLE (%)
ing a large RSET resistor. POL = 0 and NDIV = 4 requires
DIVCODE = 1. Using Table 1, choose the R1 and R2 values
to program DIVCODE = 1.
70
60
∆VSET = 0mV
50
∆VSET = 30mV
40
30
20
10
0
0
0.4
0.6
VMOD (V)
0.2
0.8
1
6992 F08
Figure 8. Duty Cycle Variation Due to ∆VSET
Duty Cycle Sensitivity to ΔVSET
The output duty cycle is proportional to the ratio of VMOD/
VSET. Since VSET can vary up to ±30mV from 1V it can
effectively gain or attenuate VMOD, as shown below when
ΔVSET is added to the equation.
VMOD
1
D=
−
0.8 • ( VSET + ∆VSET ) 8
For many designs, the absolute VMOD to duty cycle accuracy
is not critical. For others, making the simplifying assumption of ΔVSET = 0V creates the potential for additional
duty cycle error, which increases with VMOD, reaching a
maximum of 3.4% if ΔVSET = –30mV.
V
∆V
1 ∆V
∆D ≅ − MOD • SET ≅ − DIDEAL + • SET
800mV VSET
8 VSET
MOD
OUT
LTC6992-X
GND
2.25V TO 5.5V
V+
R1
SET
RSET1
RSET2
DIV
6992 F09
D=
R2
RSET2
5
1
•
−
4 RSET1 + RSET2 8
Figure 9. Fixed-Frequency, Arbitrary Duty Cycle Oscillator
69921234fc
20
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Applications Information
ISET Extremes (Master Oscillator Frequency Extremes)
Pulse Width Modulation Bandwidth and Settling Time
When operating with ISET outside of the recommended
1.25μA to 20μA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
The LTC6992 has a wide PWM bandwith, making it suitable
for a variety of feedback applications. Figure 10 shows that
the frequency response is flat for modulation frequencies
up to nearly 1/10 of the output frequency. Beyond that
point, some peaking may occur (depending on NDIV and
average duty cycle setting).
The oscillator will still function with reduced accuracy for
ISET < 1.25µA. At approximately 500nA, the oscillator output
will be frozen in its current state. The output could halt in
a high or low state. This avoids introducing short pulses
while frequency modulating a very low frequency output.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Duty cycle settling time depends on the master oscillator
frequency. Following a ±80mV step change in VMOD, the
duty cycle takes approximately eight master clock cycles
(8 • tMASTER) to settle to within 1% of the final value.
Examples are shown in Figures 11a and 11b.
10
÷4, 50%
∆D(fMOD)/∆D(0Hz) (dB)
5
÷16
÷1, 50%
0
÷1, 80%
–5
÷4, 15%
–10
–15
–20
0.001
0.01
0.1
fMOD /fOUT (Hz/Hz)
1
6992 F10
Figure 10. PWM Frequency Response
VMOD
0.1V/DIV
VMOD
0.1V/DIV
OUT
2V/DIV
OUT
2V/DIV
DUTY CYCLE
5% DIV
DUTY CYCLE
5% DIV
10µs/DIV
V+ = 3.3V
DIVCODE = 0
RSET = 200k
VMOD = 0.3V ±40mV
6992 F11a
Figure 11a. PWM Settling Time, 25% Duty Cycle
10µs/DIV
V+ = 3.3V
DIVCODE = 0
RSET = 200k
VMOD = 0.5V ±40mV
6992 F11b
Figure 11b. PWM Settling Time, 50% Duty Cycle
69921234fc
21
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
applications information
Power Supply Current
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under any
condition using the following equation:
If N DIV = 1 (DIVCODE = 0 or 15):
IS(TYP) ≈ V + • fOUT • ( 39pF + CLOAD )
+
V+
V + • Duty Cycle
+
+ 2.2 •ISET + 85µA
320kΩ
RLOAD
If N DIV > 1 (DIVCODE = 1 or 14):
IS(TYP) ≈ V + • NDIV • fOUT • 27pF
+ V + • fOUT • ( 28pF + CLOAD )
+
V+
V + • Duty Cycle
+
+ 2.6 •ISET + 90µA
320kΩ
RLOAD
Supply Bypassing and PCB Layout Guidelines
The LTC6992 is a 2.4% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Figure 14 shows example PCB layouts for both the TSOT-23
and DFN packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6992. These layouts are
a guide and need not be followed exactly.
1. Connect the bypass capacitor, C1, directly to the V+ and
GND pins using a low inductance path. The connection
from C1 to the V+ pin is easily done directly on the top
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1μF ceramic capacitor.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place RSET as close as possible to the SET pin and
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
4. Connect RSET directly to the GND pin. Using a long path
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
69921234fc
22
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
applications information
MOD
OUT
LTC6992
V+
GND
SET
C1
0.1µF
V+
R1
DIV
RSET
R2
V+
R1
R2
V+
C1
C1
V+
OUT
MOD
OUT
DIV
GND
GND
V+
SET
MOD
SET
DIV
R1
RSET
RSET
DFN PACKAGE
R2
TSOT-23 PACKAGE
6992 F14
Figure 14. Supply Bypassing and PCB Layout
Typical Applications
Constant On-Time Modulator
VMOD
VIN
0V TO 2V
RIN*
11.8k
VCTRL
RM1
1.05k
MOD
RM2
9.31k
GND
RSET
44.2k
VSET
OUT
OUT
VCC
LTC6992-1
SET
V+
C1
0.1µF
DIV
6992 TA02
R1
182k
DIVCODE = 2
(÷16, POL = 1)
R2
976k
*OPTIONAL RESISTOR ADJUSTS FOR DESIRED VIN RANGE.
IF
R
RM2
= 0.9 THEN tON = NDIV • 1.125µs • SET
RM1 +RM2
50k
AS VIN INCREASES, tOUT INCREASES AND DUTY CYCLE
DECREASES (BECAUSE POL = 1) TO MAINTAIN A CONSTANT tON.
FOR CONSTANT OFF-TIME, JUST CHANGE DIVCODE SO POL = 0.
69921234fc
23
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
typical applications
Digitally Controlled Duty Cycle with Internal VREF Reference Variation Eliminated
MOD
OUT
V+
LTC6992-X
0.1µF
V+
+
1/2
LTC6078
GND
V+
SET
DIV
RSET
C1
0.1µF
R1
R2
6992 TA03
–
V+
VCC
DIN
REF
VOUT
LTC1659
GND
0.1µF
µP
CLK
CS/LD
Programming NDIV Using an 8-Bit DAC
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
MOD
OUT
LTC6992-X
RSET
GND
V+
SET
DIV
2.25V TO 5.5V
C1
0.1µF
C2
0.1µF
VCC
SDI
VOUT LTC2630-LZ8 SCK
CS/LD
GND
µP
DIVCODE
DAC CODE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
24
40
56
72
88
104
120
136
152
168
184
200
216
232
255
6992 TA04
69921234fc
24
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
typical applications
Changing Between Two Frequencies
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
MOD
LTC6992-X
V+
GND
V+
fMAX
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
OUT
0.1µF
RVCO
fMIN
SET
MOD
V+
GND
V+
V+
0.1µF
R1
SET
DIV
RSET
OUT
LTC6992-X
V+
R2
RSET2
R1
DIV
RSET1
R2
fMIN
‘HC04
fMAX
2N7002
‘HC04
6992 TA05
NOTES
1. WHEN THE NMOSFET IS OFF, THE FREQUENCY IS SET BY RSET = RSET1.
2. WHEN THE NMOSFET IS ON, THE FREQUENCY IS SET BY RSET = RSET1 || RSET2.
3. V+ SUPPLY VARIATION IS NOT A FACTOR AS THE SWITCHING RESISTOR IS
EITHER FLOATING OR CONNECTED TO GROUND.
NOTES
WHILE THIS CIRCUIT IS SIMPLER THAN THE CIRCUIT TO THE RIGHT,
ITS FREQUENCY ACCURACY IS WORSE DUE TO THE EFFECT OF
V+ SUPPLY VARIATION FROM SYSTEM TO SYSTEM AND OVER TEMPERATURE.
Simple Diode Temperature Sensor
R8
84.5k
5V
R6
R7
45.3k 16.9k
D1
1N458
5V
5V 0.1µF
–
+
+10mV/C
MOD
LT6003
R9
365Ω
D3
LTC6992-2
GND
SET
R1
130k
R2
50k
R3
130k
DIV
6992 TA06
Q1
5V
R4
1000k
ADJUST FOR 50% DUTY CYCLE AT 25°C
MOC207M
OUT
V+
0.1µF
R5
186k
0.1µF
OUTPUT
R11
422Ω
C1
1µF
NDIV = 16
f = 10kHz
PWM OUTPUT FOR ISOLATED MEASUREMENT
+1% DUTY CYCLE CHANGE PER DEGREE C
–10°C TO 65°C RANGE WITH OPTO-ISOLATOR (DC: 15% TO 95%)
69921234fc
25
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
typical applications
Motor Speed/Direction Control for Full H-Bridge (Locked Anti-Phase Drive)
VS
12V
2.6kHz, 5% TO 95% PWM
5% DC = CLOCKWISE
50% DC = STOPPED
95% DC = COUNTER CLOCKWISE
INPUT 0V TO 1V
MOD
A1
CW CURRENT
FLOW
MOTOR
OUT
LTC6992-2
GND
V+
V+
R1
1000k
SET
A2
0.1µF
POWER H-BRIDGE
HIGH = SWITCH ON
DIV
R3
300k
R2
280k
6992 TA07
Motor Speed/Direction Control for Full H-Bridge (Sign/Magnitude Drive)
VS
12V
A5
A4
2.6kHz, 5% TO 95% PWM
5% DC = SLOW
95% DC = FAST
INPUT 0V TO 1V
MOD
CW CURRENT
FLOW
MOTOR
OUT
LTC6992-2
GND
V+
V+
R4
1000k
SET
R3
300k
0.1µF
POWER H-BRIDGE
HIGH = SWITCH ON
DIV
R5
280k
A3
DIRECTION
H = CCW, L = CW
6992 TA08
69921234fc
26
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
typical applications
Ratiometric Sensor to Pulse Width, Non-Inverting Response
R6
9.09k
VS
R4
90.9k
VS = 2.5V TO 5.5V
R3
K=1
10k
RSENSOR
K • VS
K=0
R5
10M
–
+
C2
0.22µF
0.1µF
C1
0.15µF
MOD
LT1490
OUT
LTC6992-1
OUTPUT
DUTY CYCLE = K • 100%
V+
GND
R1
1000k
SET
RSET
316k
VS
0.1µF
DIV
6992 TA09
NDIV = 16
fOUT = 10kHz
R2
186k
Ratiometric Sensor to Pulse Width, Inverting Response
R6
9.09k
VS
VS = 2.5V TO 5.5V
R3
100k
K=1
RSENSOR
R6
90.9k
–
+
K • VS
K=0
VS
R4
10k
C2
0.22µF
0.1µF
C1
0.15µF
MOD
LT1490
OUT
LTC6992-1
R5
10k
GND
OUTPUT
DUTY CYCLE = (1–K) • 100%
V+
R1
1000k
SET
RSET
316k
VS
0.1µF
DIV
6992 TA10
NDIV = 16
fOUT = 10kHz
R2
186k
69921234fc
27
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
typical applications
Radio Control Servo Pulse Generator
R6
9.09k
C1
1µF
R6
90.9k
VS
VS = 2.5V TO 5.5V
R5
130k
–
+
R6
8.66k
SERVO
CONTROL
POT
10k
C2
0.22µF
0.1µF
MOD
LT1490
OUTPUT
1ms TO 2ms PULSE EVERY 16ms
OUT
LTC6992-1
GND
V+
VS
R1
1000k
2ms
SET
1ms
DIV
R2
681k
6992 TA11
RSET
196k
0.1µF
NDIV = 4096
fOUT = 62.5Hz, 16ms PERIOD
Direct Voltage Controlled PWM Dimming (0 to 15000 Cd/m2 Intensity)
R3
90.9Ω
VDIMMING
MOD
OUT
LTC6992-1
V+
GND
5V
R1
1M
SET
RSET
105k
C1
0.1µF
D1
HIGH INTENSITY LED
SSL-LX5093XUWC
DIV
6992 TA12
R2
280k
f = 7.5kHz
NDIV = 64
69921234fc
28
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
typical applications
Wide Range LED Dimming (0 to 85000 Cd/m2 Brightness)
R2
7.5k
VFAST
–
+
5V
R1
10k
LT6004
5V 0.1µF
FAST PWM
CONTROLS 6000 TO 85000
Cd/m2 BRIGHTNESS
–
+
MOD
LT6004
R4
7.5k
OUT
LTC6992-4
V+
GND
R3
10k
RDIV1
1M
VREF
SET
RSET1
61.9k
5V
C4
0.1µF
DIV
RDIV2
280k
5–100%
NDIV = 64
f = 12.6kHz
3.3V
5V
3.3VIN
PVIN
LED+
A1
D1
PWM
LT3518UF
D2
VDIMMING
0V TO 1.65V
VSLOW
SLOW PWM
CONTROLS 0 TO 6000
Cd/m2 BRIGHTNESS
MOD
OUT
LUMILEDS LXHL-BW02
LTC6992-1
GND
V+
RDIV3
1M
SET
RSET2
124k
5V
C1
0.1µF
DIV
0–100%
NDIV = 4096
fOUT = 100Hz
RDIV4
681k
6992 TA13
69921234fc
29
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
typical applications
Isolated PWM (5% to 95%) Controller
R14
10k
1kHz
SOURCE
PWM
–
+
0.1µF
LT1011
R2
100k
C1
1µF
R15
10k
R1
10k
MOD
R9 ISOLATION
20k BARRIER
T1
LTC6992-2
GND
•
L1
•
L2
V+
R16
100k
R5
20k
R3
1k
R4
10k
LT1011
R10 100kHz
499k INTERMEDIATE PWM
R8
10k
R18
100k
C4
1µF
OUT
ISOPWM
LTC6992-2
GND
V+
ISOV+
R12
1M
SET
R11
787k
C3
1000pF
LT1636
MOD
C2
0.1µF
R17
10k
DIV
+
–
CONCEPT DESIGN USING SIMPLE R-C FILTERING FOR PWM CONTROL.
NOT OPTIMIZED FOR OFFSETS.
–
+
R7
1k
0.1µF
SET
0.1µF V+
OUT
R6
4.99k
ISOV+
0.1µF
0.1µF
DIV
1kHz
ISOLATED PWM
R13
280k
6992 TA14
ISOV+
+
–
V+
0.1µF
LT1636
T1: PCA EPF8119S ETHERNET TRANSFORMER
69921234fc
30
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
0.70 ±0.05
3.55 ±0.05
1.65 ±0.05
(2 SIDES)
2.15 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
R = 0.05
TYP
2.00 ±0.10
(2 SIDES)
3.00 ±0.10
(2 SIDES)
0.40 ± 0.10
4
6
1.65 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
3
0.200 REF
0.75 ±0.05
1
(DCB6) DFN 0405
0.25 ± 0.05
0.50 BSC
1.35 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
69921234fc
31
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636 Rev B)
0.62
MAX
2.90 BSC
(NOTE 4)
0.95
REF
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
1.90 BSC
S6 TSOT-23 0302 REV B
69921234fc
32
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Revision History
REV
DATE
DESCRIPTION
A
01/11
Revised θJA value for TSOT package in the Pin Configuration.
B
C
07/11
01/12
PAGE NUMBER
2
Added Note 7 for VOH and VOL in the Electrical Characteristics table.
4
Minor edit to the Block Diagram.
12
Minor edit to the equation in the “Duty Cycle Sensitivity to ∆VSET” section.
19
Revised Typical Applications drawings.
25
Revised Description and Order Information sections
1 to 3
Added additional information to ∆fOUT/∆V+ and included Note 11 in Electrical Characteristics section
3, 4
Added Typical Frequency Error vs Time curve to Typical Performance Characteristics section
11
Added text to Basic Operation paragraph in Applications Information section
19
Corrected fOUT value in Typical Applications drawing 6692 TA13
29
Added MP-Grade
1, 2, 3, 5
69921234fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical Application
PWM Controller for LED Driver
L1
6.8µH
VIN
8V TO 16V
SHDN VIN
D1
SW
FB
R2
124k
LT3517
ANALOG PWM
DUTY CYCLE
CONTROL
(0V TO 1V)
MOD
LTC6992-1
GND
PWM
OUT
5V
V+
0.1µF
SET
TGEN
C1
2.2µF
1M
DIV
102k
ISP
VREF
CTRL
ISN
SYNC
TG
VC
681k
C4
0.1µF
RT
6.04k
2MHz
RT
C1
0.22µF
R1
3.92M
300mA
RSENSE
330mΩ
C2
4.7µF
SS GND
C3
0.1µF
6992 TA15
C1: KEMET C0806C225K4RAC
C2: KEMET C1206C475K3RAC
C3, C4: MURATA GRM21BR71H104KA01B
C5: MURATA GRM21BR71H224KA01B
D1: DIODE DFLS160
L1: TOKO B992AS-6R8N
LEDS: LUXEON I (WHITE)
M1: ZETEX ZXMP6A13FTA
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC1799
1MHz to 33MHz ThinSOT Silicon Oscillator
Wide Frequency Range
LTC6900
1MHz to 20MHz ThinSOT Silicon Oscillator
Low Power, Wide Frequency Range
LTC6906/LTC6907
10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator
Micropower, ISUPPLY = 35µA at 400kHz
LTC6930
Fixed Frequency Oscillator, 32.768kHz to 8.192MHz
0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
LTC6990
TimerBlox, Voltage Controlled Oscillator
Frequency from 488Hz to 1MHz, No Caps, 2.2% Accurate
LTC6991
TimerBlox, Very Low Frequency Clock with Reset
Cycle Time from 2ms to 9.5 Hours, No Caps, 2.2% Accurate
LTC6993
TimerBlox, Monostable Pulse Generator
Resistor Set Pulse Width from 1µs to 34sec, No Caps, 3% Accurate
LTC6994
TimerBlox, Delay Block/Debouncer
Resistor Set Delay from 1µs to 34sec, No Caps Required, 3% Accurate
69921234fc
34 Linear Technology Corporation
LT 0112 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
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