LTM2894
Isolated USB Data
Transceiver
FEATURES
DESCRIPTION
Isolated USB Transceiver: 7500VRMS for 1 Minute
nn CSA (IEC/UL) Approved, File #255632
nn Reinforced Insulation
nn USB 2.0 Full Speed and Low Speed Compatible
nn Auto-Configuration of Bus Speed
nn 4.4V to 36V V
BUS and VBUS2 Operating Range
nn 3.3V LDO Output Supply Signal References V
LO and
VLO2
nn 50kV/μs Common Mode Transient Immunity
nn ±20kV HBM ESD on USB Interface Pins
nn 1414V
PEAK Maximum Continuous Working Voltage
nn 17.4mm Creepage Distance
nn 22mm × 6.25mm Surface Mount BGA
The LTM®2894 is a complete galvanically-isolated USB 2.0
compatible μModule® (micromodule) transceiver.
nn
APPLICATIONS
Isolated USB Interfaces
Host, Hub, or Device Isolation
nn Industrial/Medical Data Acquisition
nn
The LTM2894 is ideal for isolation in host, hub, bus splitter or peripheral device applications. It is compatible with
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps)
operation. Automatic speed selection configures integrated
pull-up resistors on the upstream port to match those
sensed on the downstream device.
The isolator µModule technology uses coupled inductors
to provide 7500VRMS of isolation and 17.4mm of creepage
between the upstream and downstream USB interface.
This device is ideal for systems requiring isolated ground
returns or large common mode voltage variations. Uninterrupted communication is guaranteed for common mode
transients greater than 50kV/μs.
Enhanced ESD protection allows this part to withstand
up to ±20kV (human body model) on the USB transceiver
interface pins to local supplies and ±20kV through the
isolation barrier to supplies without latchup or damage.
nn
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
Isolated V2.0 Full Speed Hub Port
5VISO
Full Speed Data
5V
3.3V
VBUS2
VBUS
VLO2
ON
ON2
ISOLATION BARRIER
VLO
D1+
HUB
µC
D2+
15k
120µF
USB PORT
D2–
0.5V/DIV
D1–
15k
D2+
0.5V/DIV
LTM2894
D2–
GND
500ns/DIV
2894 TA01b
GND2
2894 TA01
Rev A
Document Feedback
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1
LTM2894
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Supply Voltages
VBUS to GND........................................... –0.3V to 45V
VBUS2 to GND2....................................... –0.3V to 45V
VLO to GND................................................... –0.3V to 4V
VLO2 to GND2................................................ –0.3V to 4V
ON to GND....................................... –0.3V to (VLO + 0.3)
ON2 to GND2................................. –0.3V to (VLO2 + 0.3)
D1+, D1– to GND ........................................ –0.3V to 5.3V
D2+, D2– to GND2 ..................................... –0.3V to 5.3V
Operating Temperature Range
LTM2894C (Notes 1, 3)................................. 0 to 70°C
LTM2894I (Notes 1, 3)..............................–40 to 85°C
LTM2894H (Notes 1, 3).......................... –40 to 125°C
Storage Temperature Range....................... –40 to 125°C
Maximum Internal Operating Temperature............. 125°C
Lead Temperature (Soldering, 10 sec).................... 260°C
1
2
3
4
5
6
D1– D1+ ON VLO GND VBUS
A
B
GND
C
D
E
F
G
H
J
K
L
M
N
P
R
S
T
U
V
GND2
W
X
VBUS2
D2– D2+ ON2 VLO2
GND2
BGA PACKAGE
24-LEAD (22mm × 6.25mm × 2.06mm)
TJMAX = 125°C, θJA = 49.6°C/W, θJB = 33.7°C/W, θJCTOP = 26°CW, θJCBOT = 34°C/W,
WEIGHT = 0.5g
ORDER INFORMATION
PART NUMBER
PACKAGE
TYPE
PART MARKING
BALL FINISH
DEVICE
FINISH CODE
MSL
RATING
LTM2894CY#PBF
LTM2894IY#PBF
TEMPERATURE RANGE
0°C to 70°C
BGA
SAC305 (RoHS)
LTM2894Y
e1
LTM2894HY#PBF
• BGA Package and Tray Drawings
–40°C to 85°C
–40°C to 125°C
• Device temperature grade is indicated by a label on the shipping container.
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
3
• This product is not recommended for second side reflow.
This product is moisture sensitive. For more information, go to
Recommended BGA PCB Assembly and Manufacturing Procedures.
Rev A
2
For more information www.analog.com
LTM2894
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VBUS2 = 5V, GND = GND2 = 0V, ON = 3.3V, ON2 = 3.3V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
4.4
UNITS
Power Supply
VBUS
Operating Supply Range (USB Bus Power Input)
5
36
V
IBUSPOFF
VBUS Supply Current Power Off
ON = 0V
l
1
20
µA
IBUS
VBUS Supply Current Power On
Figure 1, VBUS = 5V, IVLO = 0mA
l
5
9
mA
IBUSSPND
VBUS Supply Current Suspend Mode
VBUS = 5V, USB Suspend Timeout
l
1.5
2.0
mA
VBUS2
Operating Supply Range (Isolated Power Input)
5
36
V
IBUS2POFF
VBUS2 Supply Current Power Off
ON2 = 0V
l
1
10
µA
IBUS2
VBUS2 Supply Current Power On
Figure 1, VBUS2 = 5V, IVLO2 = 0mA
l
5
9
mA
IBUS2SPND
VBUS2 Supply Current Suspend Mode
VBUS2 = 5V, USB Suspend Timeout
l
5
9
mA
VLO
3.3
3.55
VLO2
l
l
VLO Regulated Output Voltage Signal Reference
Figure 1, IVLO = 0mA
l
VLO Output Voltage Maximum Current Source
Figure 1
l
VLO2 Regulated Output Voltage Signal Reference
Figure 1, IVLO2 = 0mA
l
VLO2 Output Voltage Maximum Current Source
Figure 1
l
4.4
3.05
10
3.05
3.3
3.55
V
mA
V
10
mA
0.8
V
USB Input Levels (D1+, D1–, D2+, D2–)
Single-Ended Input High Voltage
l
Single-Ended Input Low Voltage
l
Single-Ended Input Hysteresis
2.0
V
200
l
Differential Input Sensitivity
|(D1+ – D1–)| or |(D2+ – D2–)|
l
0.2
Common Mode Voltage Range
(D1+ + D1–)/2 or (D2+ + D2–)/2
l
0.8
Logic Input High Voltage
l
2.0
Logic Input Low Voltage
l
Logic Input Current
l
mV
V
2.5
V
Logic Input Levels (ON, ON2)
V
0.8
±1
Logic Input Hysteresis
200
V
µA
mV
USB Output Levels (D1+, D1–, D2+, D2–)
Output Low Voltage
RPU = 1.5kΩ to 3.6V, Figure 2
l
0
0.3
V
Output High Voltage
RPD = 15kΩ to 0V
l
2.8
3.6
V
l
1.3
2.0
V
Differential Output Signal Cross-Point Voltage
Terminations
RPU
RPD
ZDRV
Bus Pull-Up Resistance on Upstream Facing Port
D2+ or D2– Pull-Up 1.5kΩ to 3.3V
l
1.425
1.575
kΩ
Bus Pull-Down Resistance on Downstream Facing
Port (D2+ and D2–)
D2+ and D2– Pull-Down to GND2
l
14.25
15.75
kΩ
l
28
USB Driver Output Resistance
USB Transceiver Pad Capacitance to GND
(Note 2)
44
10
Ω
pF
Rev A
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3
LTM2894
SWITCHING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VBUS2 = 5V, GND = GND2 = 0V, ON = 3.3V, ON2 = 3.3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tLDR
Low Speed Data Rate
CL = 50pF to 450pF (Note 4)
tLR
Rise Time
Figure 2, CL = 50pF to 600pF
l
75
300
ns
tLF
Fall Time
Figure 2, CL = 50pF to 600pF
l
75
300
ns
l
Low Speed USB
tLPRR,tLPFF
1.5
200
Mbps
Propagation Delay
Figure 2, CL = 50pF to 600pF
300
ns
Differential Jitter
To Next Transition (Note 8)
±45
ns
Differential Jitter
To Paired Transitions (Note 8)
±15
ns
tFDR
Full Speed Data Rate
CL = 50pF (Note 4)
tFR
Rise Time
Figure 3, CL = 50pF
l
tFF
Fall Time
Figure 3, CL = 50pF
l
4
tFPRR, tFPFF
Propagation Delay
Figure 3, CL = 50pF
l
60
Differential Jitter
To Next Transition (Note 8)
2
ns
Differential Jitter
To Paired Transitions (Note 8)
1
ns
Wake Up from Suspend Mode
Resume Signal
Full Speed USB
12
4
Mbps
20
80
ns
20
ns
115
ns
Suspend
l
0.25
10
µs
ESD HBM (Note 8)
Isolation Barrier
GND to GND2
±20
kV
D1+, D1–, D2+, D2–
D1+/D1– to GND, VBUS, or VLO
D2+/D2– to GND2, VBUS2, or VLO2
±20
±20
kV
kV
±4
kV
ON or ON2
Rev A
4
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LTM2894
ISOLATION CHARACTERISTICS
SYMBOL
Specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
1 Minute (Derived from 1 Second Test)
7500
1 Second (Note 5)
9000
TYP
MAX
UNITS
Isolation Barrier: GND to GND2
VISO
VIORM
Rated Dielectric Insulation Voltage (Notes 6, 7)
Common Mode Transient Immunity
(Note 2)
50
Maximum Working Insulation Voltage
(Note 2)
1414
Partial Discharge
VPR = 2650 VPEAK (Note 5)
Comparative Tracking Index
IEC 60112 (Note 2)
Depth of Erosion
IEC 60112 (Note 2)
Distance Through Insulation
(Note 2)
VRMS
VRMS
75
kV/µs
VPEAK, VDC
1000
CTI
DTI
VRMS
5
600
1
pC
VRMS
0.017
mm
0.2
mm
Input to Output Resistance
(Notes 2, 5)
5
TΩ
Input to Output Capacitance
(Notes 2, 5)
2
pF
Creepage Distance
(Notes 2, 5)
18.1
mm
CSA (Note 9)
CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1 +A2:
Basic Insulation at 910VRMS
Reinforced Insulation at 455VRMS
CSA 62368-1-14 and IEC 62368-1-14:2014, second edition:
Basic Insulation at 600VRMS
Reinforced Insulation at 455VRMS
CSA 60601-1:14 and IEC 60601-1, third edition, +A1:
Two means of patient protection (2 MOPP) at 287.5VRMS
UL 1577-2015:
Single Protection, 6000VRMS Isolation Voltage
File 255632
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Guaranteed by design and not subject to test.
Note 3: This µModule transceiver includes overtemperature protection that
is intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above specified maximum operating
junction temperature may result in device degradation or failure.
Note 4: Maximum data rate is guaranteed by other measured parameters
and is not directly tested.
Note 5: Device considered a 2-terminal device. Measurement between
groups of pins A1 through B6 shorted together and pins W1 through X6
shorted together.
Note 6: The rated dielectric insulation voltage should not be interpreted as
a continuous voltage rating.
Note 7: In accordance with UL1577, each device is proof tested at the
7500VRMS rating by applying an acceleration factor of 1.2, 9000VRMS, for
one second.
Note 8: Evaluated by design, not production tested.
Note 9: Ratings are for pollution degree 2, material group 3 and
overvoltage category II where applicable. Ratings for other environmental
and electrical conditions to be determined from the appropriate safety
standard.
Rev A
For more information www.analog.com
5
LTM2894
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted. VBUS = 5V,
VBUS2 = 5V, GND = GND2 = 0V, ON = 3.3V, ON2 = 3.3V.
Full Speed Propagation Delay vs
Temperature
100
Low Speed Propagation Delay vs
Temperature
250
CLOAD = 120pF
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
95
90
85
80
75
Full Speed Differential Jitter
CLOAD = 120pF
D1–
240
D1+
230
1V/DIV
D2+
220
D2–
JITTER 1.4nsP-P
210
2894 G03
10ns/DIV
70
–50
–25
0
50
25
75
TEMPERATURE (°C)
100
200
–50
125
–25
25
75
0
50
TEMPERATURE (°C)
100
2894 G01
2894 G02
Low Speed Differential Jitter
Full Speed Eye Diagram
1V/DIV
D2–
JITTER 7.5nsP-P
2894 G04
50ns/DIV
Low Speed Eye Diagram
3.6
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
3.1
D+, D– SIGNALS (V)
D1–
D+, D– SIGNALS (V)
D1+
D2+
125
2.6
2.1
1.6
1.1
0.6
0.1
0
10
20
30
40 50
TIME (ns)
60
70
80
0
100
200
300 400
TIME (ns)
2894 G05
40
Thermal Derating for
Operating Temperature Range vs
VBUS or VBUS2
600
2894 G06
Low Speed Data
D2–
0.5V/DIV
35
VBUS OR VBUS2 (V)
500
30
25
20
15
D2+
0.5V/DIV
10
5
H-GRADE
I-GRADE
C-GRADE
5µs/DIV
2894 G09
0
–60 –40 –20 0 20 40 60 80 100 120 140
AMBIENT TEMPERATURE (°C)
LIMITED BY JUNCTION
TEMPERATURE RISE PER GRADE
θJA = 49.6°C/W
6
2894 G08
Rev A
For more information www.analog.com
LTM2894
PIN FUNCTIONS
Upstream Side
Downstream Side
D1– (A1): USB Data Bus Upstream Facing Negative
Transceiver Pin. A 1.5k pull-up resistor is automatically
configured to indicate the idle condition of the D1– pin.
GND2 (W1 - W6, X5): Downstream Circuit Ground.
D1+ (A2): USB Data Bus Upstream Facing Positive
Transceiver Pin. A 1.5k pull-up resistor is automatically
configured to indicate the idle condition of the D1+ pin.
ON (A3): Enable. Enables data communication through
the isolation barrier. If ON is high, the upstream side is
enabled. If ON is low, the upstream side is held in reset.
The ON pin is referenced between VLO and GND.
VLO (A4): Voltage Supply Output from the Upstream Side
3.3V LDO. The VLO pin is used as a positive reference for
the ON pin and can support up to 10mA of surplus current
to controlling devices. This pin contains internal ceramic
bypass capacitance of 4.4µF.
GND (A5, B1 - B6): Upstream Circuit Ground.
VBUS (A6): Voltage Supply Input for Upstream USB
Transceiver. Recommended operating range is 4.4V to 36V.
Connect to the USB VBUS supply or an external source. This
pin contains internal ceramic bypass capacitance of 0.3µF.
D2– (X1): USB Data Bus Downstream Facing Negative
Transceiver Pin. The pin has a 15k pull-down resistor to
GND2.
D2+ (X2): USB Data Bus Downstream Facing Positive
Transceiver Pin. The pin has a 15k pull-down resistor to
GND2.
ON2 (X3): Enable. Enables data communication through
the isolation barrier. If ON2 is high, the downstream side
is enabled. If ON2 is low, the downstream side is held in
reset. The ON2 pin is referenced between VLO2 and GND2.
VLO2 (X4): Voltage Supply Output from the Downstream
Side 3.3V LDO. The VLO2 pin can support up to 10mA of
surplus current for low voltage devices. This pin contains
internal ceramic bypass capacitance of 4.4µF.
VBUS2 (X6): Voltage Supply Input for the Isolated Downstream USB Transceiver. Recommended operating range
is 4.4V to 36V referenced to GND2. This pin contains
internal ceramic bypass capacitance of 0.3µF.
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Rev A
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7
LTM2894
BLOCK DIAGRAM
VBUS
0.3µF
3.3V
REG
VBUS2
3.3V
REG
0.3µF
VLO
VLO2
4.4µF
4.4µF
ON
ON2
ISOLATED
COMMUNICATION
INTERFACE
1.5k
D1+
ISOLATED
COMMUNICATION
INTERFACE
1.5k
D2+
D1–
D2–
15k
GND
GND
GND
GND
GND
GND
15k
GND2 GND2 GND2 GND2 GND2 GND2 GND2
GND
2894 BD
TEST CIRCUITS
IBUS
IBUS2
LTM2894
VBUS2
VLO
+
–
VBUS
IVLO
GND
ISOLATION BARRIER
VBUS
VLO2
IVLO2
+
–
VBUS2
GND2
2894 F01
Figure 1. Power Supply Loads
Rev A
8
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LTM2894
TEST CIRCUITS
D2+ OR D1+
D1+ OR D2+
+
3.3V
0V
3.6V
D2– OR D1–
D1– OR D2–
+
D1– OR D2–
CL
3.3V
1.5k
0V
tLPRR
D1+ OR D2+
tLPFF
D2– OR D1–
90%
D2+ OR D1+
90%
10%
10%
2894 F02
CL
tLR
tLF
Figure 2. Low Speed Timing Measurements
D2+ OR D1+
D1+ OR D2+
+
3.3V
0V
3.3V
D2– OR D1–
D1– OR D2–
+
D1+ OR D2+
CL
0V
tFPFF
D1– OR D2–
tFPRR
D2+ OR D1+
90%
D2– OR D1–
90%
10%
10%
2894 F03
CL
tFR
tFF
Figure 3. Full Speed Timing Measurements
FUNCTIONAL TABLE
USB Transceiver Functional Table
Mode
D1+
D1–
Pull-Up Connection
D2+
D2–
Full Speed (Idle)
1.5kΩ Pull-Up
Host Pull-Down
D1+
Peripheral Pull-Up
15kΩ Pull-Down
1.5kΩ Pull-Up
D1–
15kΩ Pull-Down
Peripheral Pull-Up
Low Speed (Idle)
Host Pull-Down
Disconnected (Idle)
Host Pull-Down
Host Pull-Down
None
15kΩ Pull-Down
15kΩ Pull-Down
Suspend (Idle > 3ms)
Set During Idle Time
Set During Idle Time
Set During Idle Time
Peripheral or 15kΩ
Peripheral or 15kΩ
D1 to D2 data
IN+
IN–
Set During Idle Time
OUT+
OUT–
D2 to D1 data
OUT+
OUT–
Set During Idle Time
IN+
IN–
Rev A
For more information www.analog.com
9
LTM2894
OPERATION
The LTM2894 µModule transceiver provides a galvanically
isolated robust USB interface, complete with decoupling
capacitors. An automatically configured pull up resistor is
included to represent the condition of the isolated downstream USB bus to the upstream USB bus. The LTM2894
is ideal for use in USB connections where grounds between
upstream hub/host and downstream devices can take on
different voltages. Isolation in the LTM2894 blocks high
voltage differences and eliminates ground loops and is
extremely tolerant of common mode transients between
ground potentials. Error free operation is maintained
though common mode events exceeding 50kV/µs providing excellent noise isolation.
The integrated USB transceiver on both sides of the isolation barrier supports full and low speed modes defined in
the USB 2.0 Specification. The communication through the
isolation barrier for USB is bidirectional and as such the
LTM2894 determines data flow direction based on which
side a start of packet (SOP) begins first. The direction of
data is maintained until an end of packet (EOP) pattern is
observed or a timeout occurs due to a lack of activity. The
USB interface maintains a small consistent propagation
delay representative of a single connection or hub delay
and transfers all bus state and data information.
Pull-up resistors integrated in the upstream interface
automatically indicate device connections and disconnections. A downstream device connection automatically
selects the proper pull-up resistor at the upstream facing
port after sensing the idle state of the downstream device at connection time. Disconnection of a downstream
device automatically releases the pull-up resistor on the
upstream facing port allowing the upstream 15k pull-down
resistors to pull the bus signals to a disconnect condition.
This function makes the LTM2894 ideal for host, hub, bus
splitter, or peripheral device integration.
µModule Technology
The LTM2894 utilizes isolator µModule technology to
translate signals across an isolation barrier. Signals on
either side of the barrier are encoded into pulses and
translated across the isolation boundary using coreless
transformers formed in the µModule substrate. This
system, complete with data refresh, error checking, safe
shutdown on fail, and extremely high common mode immunity, provides a robust solution for bidirectional signal
isolation. The µModule technology provides the means to
combine the isolated signaling with our USB transceiver
in one small package.
USB Transceiver Pin Protection
The LTM2894 USB transceiver pins D1+, D1–, D2+, and
D2– have protection from ESD and short-circuit faults.
The transceiver pins withstand ±20KV HBM ESD events.
Overcurrent circuitry on the transceiver pins monitor fault
conditions from D1+ and D1– to GND, VLO, or VBUS (5.3V
MAX) and from D2+ and D2– to GND2, VLO2, or VBUS2 (5.3V
MAX). A current detection circuit disables the transceiver
pin if the pin sinks about 40mA for greater than 600ns.
The VLO and VLO2 output supplies protect the USB transceiver pins from shorts to GND or GND2 respectively with
a 40mA current limit.
APPLICATIONS INFORMATION
USB Connectivity
The LTM2894 µModule transceiver connects directly to
USB ports on the upstream side and the downstream side
without the addition of external components. The transceiver passes through all data and does not act as a hub
or intelligent device. The bus lines are monitored for idle
conditions, start of packet, and end of packet conditions
to properly maintain bus speed and data direction. The
series resistance, pull-up, and pull-down resistors are
built into the LTM2894. The upstream facing USB port
contains automatically configured 1.5k pull-up resistors
which are switched in or out based on the downstream
side peripheral device configuration. This implementation
allows upstream reporting of the downstream bus speed
and connection/disconnection conditions. Built-in 15k pulldown resistors are included from the D2+ and D2– signals
to GND2 supporting the downstream bus configuration.
Rev A
10
For more information www.analog.com
LTM2894
APPLICATIONS INFORMATION
Monitoring the USB data pins, the LTM2894 detects a
K-state to begin a data packet and set the data direction.
The data is monitored for an end of packet signature and
a finishing J-state before the bus is released. The data pay
load between the K-state and J-state is transferred through
the LTM2894 isolator with a delay of approximately 80ns.
Idle State Communication
The LTM2894 μModule transceiver maintains the conditions of the USB bus idle state by monitoring the downstream side bus idle condition and refreshing the state
across the isolation barrier at a consistent rate. Furthermore, the LTM2894 monitors the speed of the downstream
peripheral once connected and sets its own operation to
match. Figure 4 shows the abbreviated circuitry of the
automatic monitoring and reporting of the bus speeds.
The D2+ or D2– signals are monitored for a connection to
pull-ups on D2+ or D2– and the result is processed as full
speed or low speed, otherwise disconnect. The idle state
is communicated to the upstream side through a refresh
transmission. The switches SW1 or SW2 are controlled
based on the received information. SW1 is closed if D2+
is detected to have a pull-up and D2– was open. SW2 is
closed if D2– is detected to have a pull-up and D2+ was
open. Both SW1 and SW2 are opened if the downstream
USB bus is disconnected. During a USB suspend, the pullup resistor will maintain the condition prior to detecting
the suspend command.
UPSTREAM CONNECTION
DOWNSTREAM CONNECTION
LTM2894
VLO
D1+
D1–
RPU
1.5k
SW2
RPU
1.5k
ISOLATION BARRIER
SW1
3.3V
REFRESH
D2+
3.3V
FULL
SPEED
LOW
SPEED
1.5k
1.5k
D2– OR
RPD
15k
RPD
15k
OR DISCONNECTED
2894 F04
Figure 4. Idle State Automatic Resistor Setting
Suspend Mode
When the upstream USB bus is idle for greater than 3ms
the LTM2894 will enter suspend mode. Once the part enters
suspend the VBUS supply current reduces below 2mA.
The LTM2894 wakes up from suspend due to disconnects,
reconnects, and downstream initiated resume signaling
when the LTM2894 is in a hub, host, or peripheral device.
The upstream transceiver maintains observation and reports downstream transceiver disconnects and reconnects.
Recovery from suspend mode occurs when a data state
change is detected and may take up to 10µs.
During suspend mode, DC current drawn from VLO into
external circuits will be supplied from VBUS and may exceed
the limits set in the USB specification.
VBUS2 current does not reduce in suspend mode.
VLO and VLO2 Supplies
The VLO and VLO2 output supply pins are available for use
as a low current 3.3V supply on both sides of the isolation
barrier. They also serve as supplies for the USB interface
circuitry. An internal linear regulator maintains 3.3 volts on
VLO from the VBUS input supply. A separate linear regulator maintains 3.3V on VLO2 from VBUS2. The current is
limited to 10mA for external applications. Exceeding this
limit may cause degradation in the VLO or VLO2 supplies
and undesirable operation from the USB isolator. Connection of signals ON to VLO or ON2 to VLO2 will not cause a
significant change in the available current. These supplies
are available to support interface logic to the isolated USB
port. In order to meet the suspend mode current limit,
minimize the DC current of external applications on the
VLO output supply. VLO and VLO2 are protected from over
current and over temperature conditions.
Supply Current
Loading on the multiple output supply pins of the LTM2894
affect the supply current consumption on VBUS. The
VBUS input supplies current to the upstream side of the
transceiver and to the VLO pin. The VBUS2 input supplies
power to the downstream side of the transceiver and to
the VLO2 pin.
Rev A
For more information www.analog.com
11
LTM2894
APPLICATIONS INFORMATION
Supply Current Equations (Typical)
PC Board Layout
The high integration of the LTM2894 makes PCB layout simple. However, to optimize its electrical isolation
characteristics, and EMI, some layout considerations are
necessary. The PCB layout in Figure 5 is a recommended
configuration for a low EMI USB application. The following
considerations optimize the performance of the LTM2894.
Operating :
IBUS = 6mA + I VLO
IBUS2 = 6mA + I VLO2
Suspend:
IBUSSPND = 1.5mA + I VLO
• Do not place copper between the inner columns of
pads on the top or bottom on the PCB. This area must
remain open to withstand the rated isolation voltage
and maintain the creepage distance.
IBUS2SPND = 6mA + I VLO2
Off :
IBUSPOFF = 10µA
• Route D1– and D1+ and D2– and D2+ as differential
pairs with 90Ω impedance, matching the USB cable
impedance.
IBUS2POFF = 10µA
USB 2.0 Compatibility
The LTM2894 µModule transceiver is compatible with the
USB 2.0 specification of full and low speed operation. Some
characteristics of the LTM2894 µModule transceiver may
not support full compliance with the USB 2.0 specification.
The propagation delay for full speed data of 80ns exceeds
the specification for a single hub of 44ns plus the attached cable delay of 26ns. This results from driving the
data signal to the 3.3V rail prior to a K-state transition to
maintain balanced crossover voltages equivalent to the
cross over voltages of the successive data transitions.
USB ports commonly drive the idle state bus to the 3.3V
rail prior to the K-state start of packet transition. Further,
the LTM2894 does not re-time the data transitions, and
will propagate the edges as received, with the potential to
add additional jitter or pulse width distortion.
RF, Magnetic Field Immunity
The isolator µModule technology used within the LTM2894
has been independently evaluated, and successfully passed
the RF and magnetic field immunity testing requirements
per European Standard EN 55024, in accordance with the
following test standards:
EN 61000-4-3 Radiated, Radio-Frequency, Electromagnetic Field Immunity
EN 61000-4-8 Power Frequency Magnetic Field Immunity
EN 61000-4-9 Pulsed Magnetic Field Immunity
Tests were performed using an unshielded test card designed per the data sheet PCB layout recommendations.
Specific limits per test are detailed in Table 2.
Table 2. Test Frequency Field Strength
Hot Plug Protection
The VBUS and VBUS2 inputs are bypassed with low ESR
ceramic capacitors. During a hot-plug event, the supply
inputs can overshoot the supplied voltage due to cable
inductance. When using external power supply sources
greater than 24V that can be hot-plugged, add an additional
2.2µF tantalum capacitor with greater than 1Ω of ESR, or
a ceramic capacitor with a series 1Ω resistor to the VBUS
or VBUS2 input to reduce the possibility of exceeding absolute maximum ratings. Refer to Application Note AN88,
Ceramic Capacitors Can Cause Overvoltage Transients, for
a detailed discussion of this problem.
EN 61000-4-3, Annex D, 80MHz to 1GHz
1.4MHz to 2GHz
2GHz to 2.7GHz
10V/m
3V/m
1V/m
EN 61000-4-8, Level 4 50Hz and 60Hz
30A/m
EN 61000-4-8, Level 5 60Hz
100A/m*
EN 61000-4-9, Level 5 Pulse
1000A/m
*Non-IEC Method
Rev A
12
For more information www.analog.com
LTM2894
APPLICATIONS INFORMATION
EMI
Figure 7 EMI Plot was achieved with the layout structure
in Figure 6. Results are corrected per IEC 61000-4-20.
Radiated emissions have been measured for the LTM2894
using a gigahertz transverse electromagnetic (GTEM) cell
without a USB cable attached. The performance shown in
R1
49.9k
R2
464k
5
4
3
2
1
OVLO/DC UVLO VIN RBIAS SWA
LT3999
R1
100k
R5
39Ω
0805
11 GND
RT SYNC
7
8
C2
180pF
SWB
10
6
1
TR2
1:1.7
6
2
5
2
5
3
4
3
4
1
C3
4.7µF
1210
50V
TR1
1:1.1
D3
MBR0580S1
D4
MBR0580S1
R3, 28k
PINS NOT USED IN LT3999
CIRCUIT: ILIM/SS, RDC
D1
MBR0580S1
JP1
VCC
5V TO 36V
C10
4.7µF
2312
50V
VLO
D2
MBR0580S1
JP2
GND
J1
VIN
R6
100k
R7
100k
ON
4
GND
3
D+
2
D–
1
VBUS
B6
A6
B5
A5
B4
A4
B3
A3
B2
A2
B1
A1
C6
4.7µF
1210
D1+ D1–
10
9
8
7
6
11
C8
1nF
C9
10nF
VBUS2
C10
10µF
0805
C7
22nF
TR1: WURTH ELEKTRONIK 760390012
TR2: WURTH ELEKTRONIK 750313769
GND2
VBUS2
GND2
GND2
GND2
VLO2
GND2
ON2
GND2
D2+
GND2
D2–
W6
X6
W5
X5
W4
X4
W3
X3
W2
X2
W1
X1
VCC2
JP3
VCC2
INPUT = 6V TO 36V
OUTPUT = ~6V, 200mA
JP4
GND2
VLO2
VBUS2
VBUS
LT3065-5
IN
OUT
IN
OUT
SHDN
SENSE
PWRGD
ADJ
IMAX GND BYP
R10
1.5k
LTM2894
GND
VBUS
GND
GND
GND
VLO
GND
ON
GND
D1+
GND
D1–
1
2
3
4
5
L1
V
10µH CC2
R9
C5
249Ω 47pF
0805
ISOLATION BARRIER
VIN
R8
C4
249Ω 47pF
0805
4
GND
3
D+
2
D–
1
VBUS
J2
D2– D2+
2894 F05
Figure 5. Low Noise, Low EMI, 5kVRMS, Reinforced USB Isolator Demo Circuit
Rev A
For more information www.analog.com
13
LTM2894
APPLICATIONS INFORMATION
Top Layer
Bottom Layer
Figure 6. PC Board Layout
60
50
CISPR 22 CLASS B LIMIT
AMPLITUDE (dBµV/m)
40
30
20
10
DC2438A
0
DETECTOR = PEAK–HOLD
RBW = 120kHz, VBW = 300kHz
SWEEP TIME = 680ms
# OF SWEEPS ≥10
# OF POINTS = 501
–10
–20
–30
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
DC2894 F07
Figure 7. EMI Plot
TYPICAL APPLICATIONS
5VISO
5VISO
VBUS2
VBUS
LTM2894
VLO2
ON
ON2
ISOLATION BARRIER
VLO
D1+
USB PORT
D1–
GND
D2+
120µF
USB PORT
D2–
GND2
2894 F08
Figure 8. Bus Splitter
14
For more information www.analog.com
Rev A
LTM2894
TYPICAL APPLICATIONS
3.3V
5V
5VISO
VBUS
VBUS2
ON
ON2
ISOLATION BARRIER
VLO2
D1–
15k
LTM2894
VLO
D1+
HOST
µC
5VISO
15k
GND
120µF
D2+
USB PORT
D2–
GND2
2894 F09
Figure 9. USB Host Integration
5VISO
VBUS
5VISO
VBUS2
LTM2894
VLO2
ON
ON2
ISOLATION BARRIER
VLO
D1+
USB PORT
D1–
GND
1.5k
D2+
PERIPHERAL
FULL SPEED
D2–
GND2
2894 F10
Figure 10. Powered Peripheral Device
3.3VISO
VBUS
VBUS2
LTM2894
VLO2
ON
ON2
ISOLATION BARRIER
VLO
D1+
USB PORT
D1–
GND
3.3VISO
D2+
1.5k
PERIPHERAL
FULL SPEED
D2–
GND2
2894 F11
Figure 11. Peripheral Powered with 3.3V Only
Rev A
For more information www.analog.com
15
LTM2894
PACKAGE DESCRIPTION
BGA Package
24-Lead (22mm × 6.25mm × 2.06mm)
(Reference LTC DWG# 05-08-1991 Rev Ø)
A
aaa Z
E
Y
Z
SEE NOTES
DETAIL A
A2
X
SEE NOTES
6
5
4
3
2
7
1
PIN 1
3
A
PIN “A1”
CORNER
4
B
b
A1
C
ccc Z
D
E
F
b1
MOLD
CAP
G
SUBSTRATE
J
K
Z
// bbb Z
D
H
H1
H2
DETAIL B
L
F
M
N
Øb (24 PLACES)
P
ddd M Z X Y
eee M Z
R
S
T
U
V
DETAIL A
W
e
X
aaa Z
e
G
DETAIL B
PACKAGE SIDE VIEW
PACKAGE BOTTOM VIEW
2.50
1.50
0.00
0.50
0.50
2.20
1.50
2.50
2.80
PACKAGE TOP VIEW
b
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
10.375
2. ALL DIMENSIONS ARE IN MILLIMETERS
9.375
0.60 ±0.025 Ø 24x
DIMENSIONS
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
0.00
MIN
1.81
0.40
1.41
0.55
0.45
0.46
0.95
NOM
2.06
0.50
1.56
0.60
0.50
22.0
6.25
1.0
20.75
5.0
0.56
1.00
MAX
2.31
0.60
1.71
0.65
0.55
NOTES
0.66
1.05
0.15
0.10
0.15
0.15
0.08
TOTAL NUMBER OF BALLS: 24
9.375
10.375
3
BALL DESIGNATION PER JESD MS-028 AND JEP95
4
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
7
COMPONENT
PIN “A1”
TRAY PIN 1
BEVEL
10.075
10.675
!
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
LTMXXXXXX
µModule
PACKAGE IN TRAY LOADING ORIENTATION
BGA 24 1014 REV Ø
SUGGESTED PCB LAYOUT
TOP VIEW
Rev A
16
For more information www.analog.com
LTM2894
REVISION HISTORY
REV
DATE
DESCRIPTION
A
06/18
Added UL/CSA Certifications
Increased Typical Creepage Distance
PAGE NUMBER
1, 5
5
Rev A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
more by
information
www.analog.com
17
LTM2894
TYPICAL APPLICATION
3.3VISO
3.3VISO
VCC
51k
OVRCUR1
PWRON1
5VISO
LTC1154
STATUS
VS
EN
DS
SD
GATE
IN
GND
0.14Ω
120µF
SN74LVC04
27Ω
51k
VBUS
VBUS2
OVRCUR2
LTM2894
VLO2
ON2
ISOLATION BARRIER
VLO
ON
+
D1
USB PORT
+
D2
15k
PWRON2
LTC1154
STATUS
VS
EN
DS
SD
GATE
IN
GND
0.14Ω
5VISO
120µF
SN74LVC04
1.5k
27Ω
DP0
USB PORT B
27Ω
DP2
DM2
27Ω
15k
15k
3.3VISO
D1–
27Ω
D2–
GND
15k
3.3VISO
TUSB2046B
3.3VISO
USB PORT A
27Ω
DP1
DM1
51k
DM0
OVRCUR3
GND2
PWRON3
LTC1154
STATUS
VS
EN
DS
SD
GATE
IN
GND
0.14Ω
5VISO
120µF
SN74LVC04
3.3VISO
6MHz CLOCK
SIGNAL
EXTMEM
XTAL1
USB PORT C
27Ω
DP3
DM3
27Ω
XTAL2
15k
15k
3.3VISO
SUSPND
POWER ON
RESET
51k
RESET
OVRCUR4
TSTPLL
TSTMODE
BUSPWR
GANGED
PWRON4
LTC1154
STATUS
VS
EN
DS
SD
GATE
IN
GND
0.14Ω
5VISO
120µF
SN74LVC04
DP4
DM4
GND
USB PORT D
27Ω
27Ω
15k
15k
2894 F12
Figure 12. V1.1 USB Hub Isolation
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM2884
Complete Isolated USB µModule Transceiver + Power
2500VRMS Isolation in Surface Mount BGA
LTM2881
Complete Isolated RS485/RS422 µModule Transceiver + Power
2500VRMS Isolation in Surface Mount BGA or LGA
LTM2882
Dual Isolated RS232 µModule Transceiver with Integrated DC/DC Converter
2500VRMS Isolation in Surface Mount BGA or LGA
LTM2883
SPI or I2C µModule Isolator with Adjustable ±12.5V and 5V Regulated Power
2500VRMS Isolation in Surface Mount BGA
LTM2892
SPI or I2C µModule Isolator
3500VRMS Isolation in Surface Mount BGA
LTM2886
SPI or I2C µModule Isolator with Adjustable 5V and ±5V Regulated Power
2500VRMS Isolation in Surface Mount BGA
LTM2889
Complete 4Mbps CAN FD µModule Isolator + Power
2500VRMS Isolation in Surface Mount BGA
LTM2893
Complete 100MHz SPI ADC µModule Isolator
6000VRMS Isolation in Surface Mount BGA
Rev A
18
D17019-0-6/18(A)
For more information www.analog.com
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